Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34517 )
Change subject: soc/intel/{cnl,icl}: Enable support to configure interrupt overrides
......................................................................
soc/intel/{cnl,icl}: Enable support to configure interrupt overrides
This implementation selects SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE
config. It would enable support from SOC to dynamically populate the
PCI IRQ routing table based on the devices enabled from the mainboard.
And pass the same to FSP to configure the IRQ entries in ITSS PIRx
register. The same table can be used to generate the ACPI PIRQ mapping
table.
Change-Id: I8464d5797cb4ff85406c06e1ecb92c7207380acd
Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com>
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/icelake/Kconfig
2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/34517/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index f859cd5..0283f2c 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -97,6 +97,7 @@
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
+ select SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 5dca44b..79a19ee 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -51,6 +51,7 @@
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
+ select SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_RESET
select SSE2
--
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Gerrit-Change-Id: I8464d5797cb4ff85406c06e1ecb92c7207380acd
Gerrit-Change-Number: 34517
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Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com>
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Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34348 )
Change subject: src/soc/intel/*/include: Get list of devices that needs IRQ programming
......................................................................
src/soc/intel/*/include: Get list of devices that needs IRQ programming
This implementation adds SOC function that returns list of PCI devices
that needs IRQ programming. This list can be further used to program
IRQ for these devices.
Change-Id: I3482172f6cb549dece23e2b8b09b8b79578b83b7
Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com>
---
M src/soc/intel/cannonlake/Makefile.inc
A src/soc/intel/cannonlake/irq.c
M src/soc/intel/icelake/Makefile.inc
A src/soc/intel/icelake/irq.c
4 files changed, 150 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/34348/1
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 8a4a8b7..ed0d09c 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -41,6 +41,7 @@
ramstage-y += graphics.c
ramstage-y += gspi.c
ramstage-y += i2c.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) += irq.c
ramstage-y += lockdown.c
ramstage-y += lpc.c
ramstage-y += me.c
diff --git a/src/soc/intel/cannonlake/irq.c b/src/soc/intel/cannonlake/irq.c
new file mode 100644
index 0000000..ce0e539
--- /dev/null
+++ b/src/soc/intel/cannonlake/irq.c
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/irq.h>
+#include <soc/pci_devs.h>
+#include <stdint.h>
+
+static const int irq_devices[] = {
+ PCH_DEVFN_HDA,
+ PCH_DEVFN_SMBUS,
+ PCH_DEVFN_GBE,
+ PCH_DEVFN_TRACEHUB,
+ PCH_DEVFN_PCIE9,
+ PCH_DEVFN_PCIE10,
+ PCH_DEVFN_PCIE11,
+ PCH_DEVFN_PCIE12,
+ PCH_DEVFN_PCIE13,
+ PCH_DEVFN_PCIE14,
+ PCH_DEVFN_PCIE15,
+ PCH_DEVFN_PCIE16,
+ PCH_DEVFN_PCIE1,
+ PCH_DEVFN_PCIE2,
+ PCH_DEVFN_PCIE3,
+ PCH_DEVFN_PCIE4,
+ PCH_DEVFN_PCIE5,
+ PCH_DEVFN_PCIE6,
+ PCH_DEVFN_PCIE7,
+ PCH_DEVFN_PCIE8,
+ PCH_DEVFN_EMMC,
+ PCH_DEVFN_SATA,
+ PCH_DEVFN_CSE,
+ PCH_DEVFN_CSE_2,
+ PCH_DEVFN_CSE_IDER,
+ PCH_DEVFN_CSE_KT,
+ PCH_DEVFN_CSE_3,
+ PCH_DEVFN_CSE_4,
+ PCH_DEVFN_XHCI,
+ PCH_DEVFN_USBOTG,
+ PCH_DEVFN_CNViWIFI,
+ PCH_DEVFN_SDCARD,
+ PCH_DEVFN_ISH,
+ PCH_DEVFN_THERMAL,
+ PCH_DEVFN_UFS,
+ PCH_DEVFN_UART0,
+ PCH_DEVFN_UART1,
+ PCH_DEVFN_GSPI0,
+ PCH_DEVFN_GSPI1,
+ PCH_DEVFN_UART2,
+ PCH_DEVFN_I2C5,
+ PCH_DEVFN_I2C4,
+ PCH_DEVFN_I2C0,
+ PCH_DEVFN_I2C1,
+ PCH_DEVFN_I2C2,
+ PCH_DEVFN_I2C3,
+ PCH_DEVFN_GSPI2,
+};
+
+const int *get_soc_irq_devices(size_t *size)
+{
+ *size = ARRAY_SIZE(irq_devices);
+ return irq_devices;
+}
diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc
index cd02934..2973e15 100644
--- a/src/soc/intel/icelake/Makefile.inc
+++ b/src/soc/intel/icelake/Makefile.inc
@@ -43,6 +43,7 @@
ramstage-y += graphics.c
ramstage-y += gspi.c
ramstage-y += i2c.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) += irq.c
ramstage-y += lockdown.c
ramstage-y += memmap.c
ramstage-y += p2sb.c
diff --git a/src/soc/intel/icelake/irq.c b/src/soc/intel/icelake/irq.c
new file mode 100644
index 0000000..ce0e539
--- /dev/null
+++ b/src/soc/intel/icelake/irq.c
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/irq.h>
+#include <soc/pci_devs.h>
+#include <stdint.h>
+
+static const int irq_devices[] = {
+ PCH_DEVFN_HDA,
+ PCH_DEVFN_SMBUS,
+ PCH_DEVFN_GBE,
+ PCH_DEVFN_TRACEHUB,
+ PCH_DEVFN_PCIE9,
+ PCH_DEVFN_PCIE10,
+ PCH_DEVFN_PCIE11,
+ PCH_DEVFN_PCIE12,
+ PCH_DEVFN_PCIE13,
+ PCH_DEVFN_PCIE14,
+ PCH_DEVFN_PCIE15,
+ PCH_DEVFN_PCIE16,
+ PCH_DEVFN_PCIE1,
+ PCH_DEVFN_PCIE2,
+ PCH_DEVFN_PCIE3,
+ PCH_DEVFN_PCIE4,
+ PCH_DEVFN_PCIE5,
+ PCH_DEVFN_PCIE6,
+ PCH_DEVFN_PCIE7,
+ PCH_DEVFN_PCIE8,
+ PCH_DEVFN_EMMC,
+ PCH_DEVFN_SATA,
+ PCH_DEVFN_CSE,
+ PCH_DEVFN_CSE_2,
+ PCH_DEVFN_CSE_IDER,
+ PCH_DEVFN_CSE_KT,
+ PCH_DEVFN_CSE_3,
+ PCH_DEVFN_CSE_4,
+ PCH_DEVFN_XHCI,
+ PCH_DEVFN_USBOTG,
+ PCH_DEVFN_CNViWIFI,
+ PCH_DEVFN_SDCARD,
+ PCH_DEVFN_ISH,
+ PCH_DEVFN_THERMAL,
+ PCH_DEVFN_UFS,
+ PCH_DEVFN_UART0,
+ PCH_DEVFN_UART1,
+ PCH_DEVFN_GSPI0,
+ PCH_DEVFN_GSPI1,
+ PCH_DEVFN_UART2,
+ PCH_DEVFN_I2C5,
+ PCH_DEVFN_I2C4,
+ PCH_DEVFN_I2C0,
+ PCH_DEVFN_I2C1,
+ PCH_DEVFN_I2C2,
+ PCH_DEVFN_I2C3,
+ PCH_DEVFN_GSPI2,
+};
+
+const int *get_soc_irq_devices(size_t *size)
+{
+ *size = ARRAY_SIZE(irq_devices);
+ return irq_devices;
+}
--
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Hello Iru Cai,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/45577
to review the following change.
Change subject: Documentation: Introduce HP Sure Start and the method to bypass it
......................................................................
Documentation: Introduce HP Sure Start and the method to bypass it
Change-Id: Id198afdaa13b4c361e1b77a56d5a2436ed1c4c86
Signed-off-by: Iru Cai <mytbk920423(a)gmail.com>
---
A Documentation/mainboard/hp/hp_sure_start.md
M Documentation/mainboard/index.md
2 files changed, 58 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/45577/1
diff --git a/Documentation/mainboard/hp/hp_sure_start.md b/Documentation/mainboard/hp/hp_sure_start.md
new file mode 100644
index 0000000..d1f3f67
--- /dev/null
+++ b/Documentation/mainboard/hp/hp_sure_start.md
@@ -0,0 +1,57 @@
+# HP Sure Start
+
+According to the [HP Sure Start Technical Whitepaper], HP Sure Start is a chipset
+and processor independent firmware intrusion detection and automatic repair system.
+It is implemented in HP notebooks since 2013, and desktops since 2015.
+
+This document talks about some mechanism of HP Sure Start on some machines, and
+the method to bypass it.
+
+## Laptops with SMSC MEC1322 embedded controller
+
+Haswell EliteBook, ZBook and ProBook 600 series use SMSC MEC1322 embedded controller.
+The EC firmware implements HP Sure Start. A Haswell EliteBook has two flash chips.
+According to the strings in the EC firmware, the 16MB flash chip that stores the
+BIOS firmware is called the *system flash*, and the 2MB flash chip that stores part
+of the system flash content is called the *private flash*.
+
+The private flash is connected to the EC, and is not accessible by the OS.
+It contains the following:
+
+- HP Sure Start policy header (starting with the string "POLI")
+- A copy of the Intel Flash Descriptor
+- A copy of the GbE firmware
+- Machine Unique Data (MUD)
+- Hashes of the IFD, GbE firmware and MUD, the hash algorithm is unknown
+- A copy of the bootblock, UEFI PEI stage, and microcode
+
+If the IFD of the system flash does not match the hash in the private flash, for example,
+modifying the IFD with ``ifdtool -u`` or ``me_cleaner -S``, the EC will recover the IFD.
+
+If the content of the private flash is lost. The EC firmware will still copy the IFD,
+bootblock and PEI to the private flash. However, the IFD is not protected after that.
+
+HP Sure Start also verifies bootblock, PEI, and microcode without using the private flash.
+EC firmware reads them from an absolute address of the system flash chip, which is
+hardcoded in the EC firmware. It looks like this verification is done with a digital
+signature. If the PEI volume is modified, EC firmware will recover it using the copy
+in the private flash. If the private flash has no valid copies of the PEI volume, and
+the PEI volume is modified, the machine will refuse to boot with the CapsLock LED blinking.
+
+## Bypassing HP Sure Start
+
+First search the mainboard for the flash chips. If there are two flash chips,
+the smaller one may be the private flash.
+
+For Intel boards, try to modify the IFD with ``ifdtool -u``, power on and shut down
+the machine, then read the flash again. If the IFD is not modified, it is likely to
+be recovered from the private flash. Find the private flash and erase it, then the IFD
+can be modified.
+
+To bypass the bootblock and PEI verification, we can modify the IFD to make the
+BIOS region not overlap with the protected region. Since the EC firmware is usually
+located at the high address of the flash chip (and in the protected region),
+we can leave it untouched, and do not need to extract the EC firmware to put it in
+the coreboot image.
+
+[HP Sure Start Technical Whitepaper]: http://h10032.www1.hp.com/ctg/Manual/c05163901
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 0eefee8..335eae2 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -61,6 +61,7 @@
### EliteBook series
- [HP Laptops with KBC1126 EC](hp/hp_kbc1126_laptops.md)
+- [HP Sure Start](hp/hp_sure_start.md)
- [EliteBook 2560p](hp/2560p.md)
- [EliteBook 8760w](hp/8760w.md)
--
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Gerrit-Change-Number: 45577
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Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45814 )
Change subject: mb/emulation/q35: Define pm_acpi_smi_cmd_port
......................................................................
mb/emulation/q35: Define pm_acpi_smi_cmd_port
The X86 Qemu targets use the AMD64 SMM save state, but unlike
most AMD CPU's the PM ACPI SMI port is not configurable and uses
the Intel default APM_CNT, 0xb2 port.
This will be used by the common save state handler.
Change-Id: Ifee9476f628a2df710fb4340ce6a19b008df1033
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/emulation/qemu-q35/Makefile.inc
A src/mainboard/emulation/qemu-q35/smi.c
2 files changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/45814/1
diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc
index e142d4d..59c61c4 100644
--- a/src/mainboard/emulation/qemu-q35/Makefile.inc
+++ b/src/mainboard/emulation/qemu-q35/Makefile.inc
@@ -14,3 +14,5 @@
verstage-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
\ No newline at end of file
diff --git a/src/mainboard/emulation/qemu-q35/smi.c b/src/mainboard/emulation/qemu-q35/smi.c
new file mode 100644
index 0000000..5d8d482
--- /dev/null
+++ b/src/mainboard/emulation/qemu-q35/smi.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+
+/* The X86 qemu target uses AMD64 save states but the APM port is not configurable. */
+uint16_t pm_acpi_smi_cmd_port(void)
+{
+ return APM_CNT;
+}
--
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