coreboot-gerrit September 2020

coreboot-gerrit@coreboot.org

1 participants
2629 discussions

Change in coreboot[master]: cbfstool: Use cbfs_serialized.h and standard vboot helpers
by Julius Werner (Code Review) 03 Dec '20

03 Dec '20

Hello Patrick Georgi, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41117 to review the following change. Change subject: cbfstool: Use cbfs_serialized.h and standard vboot helpers ...................................................................... cbfstool: Use cbfs_serialized.h and standard vboot helpers This patch reduces some code duplication in cbfstool by switching it to use the CBFS data structure definitions in commonlib rather than its own private copy. In addition, replace a few custom helpers related to hash algorithms with the official vboot APIs of the same purpose. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I22eae1bcd76d85fff17749617cfe4f1de55603f4 --- M src/commonlib/bsd/cbfs_mcache.c M src/commonlib/bsd/cbfs_private.c M src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h M src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h M src/commonlib/cbfs.c M src/mainboard/facebook/fbg1701/board_mboot.h M util/cbfstool/Makefile.inc M util/cbfstool/cbfs-mkpayload.c M util/cbfstool/cbfs-mkstage.c M util/cbfstool/cbfs-payload-linux.c M util/cbfstool/cbfs.h M util/cbfstool/cbfs_image.c M util/cbfstool/cbfs_image.h M util/cbfstool/cbfscomptool.c M util/cbfstool/cbfstool.c M util/cbfstool/common.h M util/cbfstool/compress.c 17 files changed, 201 insertions(+), 409 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/41117/1 diff --git a/src/commonlib/bsd/cbfs_mcache.c b/src/commonlib/bsd/cbfs_mcache.c index 5a967dd..45255c5 100644 --- a/src/commonlib/bsd/cbfs_mcache.c +++ b/src/commonlib/bsd/cbfs_mcache.c @@ -108,8 +108,8 @@ const uint32_t data_offset = be32toh(entry->file.h.offset); const uint32_t data_length = be32toh(entry->file.h.len); - if (namesize <= data_offset - offsetof(union cbfs_mdata, filename) && - memcmp(name, entry->file.filename, namesize) == 0) { + if (namesize <= data_offset - offsetof(union cbfs_mdata, h.filename) && + memcmp(name, entry->file.h.filename, namesize) == 0) { LOG("Found '%s' @%#x size %#x in mcache @%p\n", name, entry->offset, data_length, current); *data_offset_out = entry->offset + data_offset; diff --git a/src/commonlib/bsd/cbfs_private.c b/src/commonlib/bsd/cbfs_private.c index 0b6b888..e575cd3 100644 --- a/src/commonlib/bsd/cbfs_private.c +++ b/src/commonlib/bsd/cbfs_private.c @@ -46,7 +46,7 @@ const uint32_t data_offset = be32toh(mdata.h.offset); const uint32_t data_length = be32toh(mdata.h.len); const uint32_t type = be32toh(mdata.h.type); - const bool empty = (type == CBFS_TYPE_DELETED || type == CBFS_TYPE_DELETED2); + const bool empty = (type == CBFS_TYPE_DELETED || type == CBFS_TYPE_NULL); DEBUG("Found CBFS header @%#zx (type %d, attr +%#x, data +%#x, length %#x)\n", offset, be32toh(mdata.h.type), attr_offset, data_offset, data_length); @@ -74,7 +74,7 @@ if (cbfs_dev_read(dev, mdata.raw + sizeof(mdata.h), offset + sizeof(mdata.h), todo) != todo) return CB_CBFS_IO; - DEBUG("File name: '%s'\n", mdata.filename); + DEBUG("File name: '%s'\n", mdata.h.filename); if (do_hash && !empty && vb2_digest_extend(&dc, mdata.raw, data_offset)) return CB_ERR; @@ -132,8 +132,8 @@ size_t already_read, void *arg) { struct cbfs_lookup_args *args = arg; - if (args->namesize > already_read - offsetof(union cbfs_mdata, filename) || - memcmp(args->name, mdata->filename, args->namesize) != 0) + if (args->namesize > already_read - offsetof(union cbfs_mdata, h.filename) || + memcmp(args->name, mdata->h.filename, args->namesize) != 0) return CB_CBFS_NOT_FOUND; LOG("Found '%s' @%#zx size %#x\n", args->name, offset, be32toh(mdata->h.len)); diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h index ac7b1b1..39e4e10 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h @@ -31,12 +31,8 @@ #include <cbfs_glue.h> /* Helper structure to allocate space for a blob of metadata on the stack. */ -#define CBFS_METADATA_MAX_SIZE 256 union cbfs_mdata { - struct { - struct cbfs_file h; - char filename[]; - }; + struct cbfs_file h; uint8_t raw[CBFS_METADATA_MAX_SIZE]; }; diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h index 556c8e4..334c9f6 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h @@ -6,44 +6,40 @@ #include <stdint.h> #include <vb2_sha.h> -/** These are standard values for the known compression - algorithms that coreboot knows about for stages and - payloads. Of course, other CBFS users can use whatever - values they want, as long as they understand them. */ +enum cbfs_compression { + CBFS_COMPRESS_NONE = 0, + CBFS_COMPRESS_LZMA = 1, + CBFS_COMPRESS_LZ4 = 2, +}; -#define CBFS_COMPRESS_NONE 0 -#define CBFS_COMPRESS_LZMA 1 -#define CBFS_COMPRESS_LZ4 2 +enum cbfs_type { + CBFS_TYPE_DELETED = 0x00000000, + CBFS_TYPE_NULL = 0xffffffff, + CBFS_TYPE_BOOTBLOCK = 0x01, + CBFS_TYPE_CBFSHEADER = 0x02, + CBFS_TYPE_STAGE = 0x10, + CBFS_TYPE_SELF = 0x20, + CBFS_TYPE_FIT = 0x21, + CBFS_TYPE_OPTIONROM = 0x30, + CBFS_TYPE_BOOTSPLASH = 0x40, + CBFS_TYPE_RAW = 0x50, + CBFS_TYPE_VSA = 0x51, + CBFS_TYPE_MBI = 0x52, + CBFS_TYPE_MICROCODE = 0x53, + CBFS_TYPE_FSP = 0x60, + CBFS_TYPE_MRC = 0x61, + CBFS_TYPE_MMA = 0x62, + CBFS_TYPE_EFI = 0x63, + CBFS_TYPE_STRUCT = 0x70, + CBFS_TYPE_CMOS_DEFAULT = 0xaa, + CBFS_TYPE_SPD = 0xab, + CBFS_TYPE_MRC_CACHE = 0xac, + CBFS_TYPE_CMOS_LAYOUT = 0x01aa, +}; -/** These are standard component types for well known - components (i.e - those that coreboot needs to consume. - Users are welcome to use any other value for their - components */ - -#define CBFS_TYPE_DELETED 0x00000000 -#define CBFS_TYPE_DELETED2 0xffffffff -#define CBFS_TYPE_STAGE 0x10 -#define CBFS_TYPE_SELF 0x20 -#define CBFS_TYPE_FIT 0x21 -#define CBFS_TYPE_OPTIONROM 0x30 -#define CBFS_TYPE_BOOTSPLASH 0x40 -#define CBFS_TYPE_RAW 0x50 -#define CBFS_TYPE_VSA 0x51 -#define CBFS_TYPE_MBI 0x52 -#define CBFS_TYPE_MICROCODE 0x53 -#define CBFS_TYPE_FSP 0x60 -#define CBFS_TYPE_MRC 0x61 -#define CBFS_TYPE_MMA 0x62 -#define CBFS_TYPE_EFI 0x63 -#define CBFS_TYPE_STRUCT 0x70 -#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa -#define CBFS_TYPE_SPD 0xab -#define CBFS_TYPE_MRC_CACHE 0xac -#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa - -#define CBFS_HEADER_MAGIC 0x4F524243 -#define CBFS_HEADER_VERSION1 0x31313131 -#define CBFS_HEADER_VERSION2 0x31313132 +#define CBFS_HEADER_MAGIC 0x4F524243 /* BE: 'ORBC' */ +#define CBFS_HEADER_VERSION1 0x31313131 /* BE: '1111' */ +#define CBFS_HEADER_VERSION2 0x31313132 /* BE: '1112' */ #define CBFS_HEADER_VERSION CBFS_HEADER_VERSION2 /* this is the master cbfs header - it must be located somewhere available @@ -67,9 +63,15 @@ /* "Unknown" refers to CBFS headers version 1, * before the architecture was defined (i.e., x86 only). */ -#define CBFS_ARCHITECTURE_UNKNOWN 0xFFFFFFFF -#define CBFS_ARCHITECTURE_X86 0x00000001 -#define CBFS_ARCHITECTURE_ARM 0x00000010 +enum cbfs_architecture { + CBFS_ARCHITECTURE_UNKNOWN = 0xFFFFFFFF, + CBFS_ARCHITECTURE_X86 = 0x00000001, + CBFS_ARCHITECTURE_ARM = 0x00000010, + CBFS_ARCHITECTURE_AARCH64 = 0x0000aa64, + CBFS_ARCHITECTURE_MIPS = 0x00000100, /* deprecated */ + CBFS_ARCHITECTURE_RISCV = 0xc001d0de, + CBFS_ARCHITECTURE_PPC64 = 0x407570ff, +}; /** This is a component header - every entry in the CBFS will have this header. @@ -87,6 +89,7 @@ */ #define CBFS_FILE_MAGIC "LARCHIVE" +#define CBFS_METADATA_MAX_SIZE 256 struct cbfs_file { char magic[8]; @@ -94,8 +97,13 @@ uint32_t type; uint32_t attributes_offset; uint32_t offset; + char filename[0]; } __packed; +#if defined __GNUC__ && (__GNUC__ * 100 + __GNUC_MINOR__) >= 406 +_Static_assert(sizeof(struct cbfs_file) == 24, "cbfs_file size mismatch"); +#endif + /* The common fields of extended cbfs file attributes. Attributes are expected to start with tag/len, then append their specific fields. */ @@ -108,13 +116,16 @@ /* Depending on how the header was initialized, it may be backed with 0x00 or * 0xff. Support both. */ -#define CBFS_FILE_ATTR_TAG_UNUSED 0 -#define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff -#define CBFS_FILE_ATTR_TAG_COMPRESSION 0x42435a4c -#define CBFS_FILE_ATTR_TAG_HASH 0x68736148 -#define CBFS_FILE_ATTR_TAG_POSITION 0x42435350 /* PSCB */ -#define CBFS_FILE_ATTR_TAG_ALIGNMENT 0x42434c41 /* ALCB */ -#define CBFS_FILE_ATTR_TAG_IBB 0x32494242 /* Initial BootBlock */ +enum cbfs_file_attr_tag { + CBFS_FILE_ATTR_TAG_UNUSED = 0, + CBFS_FILE_ATTR_TAG_UNUSED2 = 0xffffffff, + CBFS_FILE_ATTR_TAG_COMPRESSION = 0x42435a4c, /* BE: 'BCZL' */ + CBFS_FILE_ATTR_TAG_HASH = 0x68736148, /* BE: 'hsaH' */ + CBFS_FILE_ATTR_TAG_POSITION = 0x42435350, /* BE: 'BCSP' */ + CBFS_FILE_ATTR_TAG_ALIGNMENT = 0x42434c41, /* BE: 'BCLA' */ + CBFS_FILE_ATTR_TAG_IBB = 0x32494242, /* BE: '2IBB' */ + CBFS_FILE_ATTR_TAG_PADDING = 0x47444150, /* BE: 'GNDP' */ +}; struct cbfs_file_attr_compression { uint32_t tag; @@ -176,11 +187,13 @@ struct cbfs_payload_segment segments; }; -#define PAYLOAD_SEGMENT_CODE 0x434F4445 -#define PAYLOAD_SEGMENT_DATA 0x44415441 -#define PAYLOAD_SEGMENT_BSS 0x42535320 -#define PAYLOAD_SEGMENT_PARAMS 0x50415241 -#define PAYLOAD_SEGMENT_ENTRY 0x454E5452 +enum cbfs_payload_segment_type { + PAYLOAD_SEGMENT_CODE = 0x434F4445, /* BE: 'CODE' */ + PAYLOAD_SEGMENT_DATA = 0x44415441, /* BE: 'DATA' */ + PAYLOAD_SEGMENT_BSS = 0x42535320, /* BE: 'BSS ' */ + PAYLOAD_SEGMENT_PARAMS = 0x50415241, /* BE: 'PARA' */ + PAYLOAD_SEGMENT_ENTRY = 0x454E5452, /* BE: 'ENTR' */ +}; struct cbfs_optionrom { uint32_t compression; diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c index caa81ea..a4cdc60 100644 --- a/src/commonlib/cbfs.c +++ b/src/commonlib/cbfs.c @@ -351,7 +351,7 @@ if (cbfsf_file_type(fh, &ftype)) return VB2_ERROR_UNKNOWN; - if (ftype == CBFS_TYPE_DELETED || ftype == CBFS_TYPE_DELETED2) + if (ftype == CBFS_TYPE_DELETED || ftype == CBFS_TYPE_NULL) continue; rv = cbfs_extend_hash_with_offset(&ctx, cbfs, &fh->data); diff --git a/src/mainboard/facebook/fbg1701/board_mboot.h b/src/mainboard/facebook/fbg1701/board_mboot.h index 5864d4b..1b93162 100644 --- a/src/mainboard/facebook/fbg1701/board_mboot.h +++ b/src/mainboard/facebook/fbg1701/board_mboot.h @@ -7,7 +7,7 @@ const mboot_measure_item_t mb_log_list[] = { { "config", CBFS_TYPE_RAW, MBOOT_PCR_INDEX_0, EV_NO_ACTION, NULL }, { "revision", CBFS_TYPE_RAW, MBOOT_PCR_INDEX_0, EV_NO_ACTION, NULL }, - { "cmos_layout.bin", CBFS_COMPONENT_CMOS_LAYOUT, MBOOT_PCR_INDEX_0, + { "cmos_layout.bin", CBFS_TYPE_CMOS_LAYOUT, MBOOT_PCR_INDEX_0, EV_NO_ACTION, NULL }, #if CONFIG(VENDORCODE_ELTAN_VBOOT) { "oemmanifest.bin", CBFS_TYPE_RAW, MBOOT_PCR_INDEX_7, EV_NO_ACTION, diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index f38c825..000ceb2 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -108,6 +108,7 @@ TOOLCPPFLAGS += -include $(top)/src/commonlib/bsd/include/commonlib/bsd/compiler.h TOOLCPPFLAGS += -I$(VBOOT_SOURCE)/firmware/include TOOLCPPFLAGS += -I$(VBOOT_SOURCE)/firmware/2lib/include +TOOLCPPFLAGS += -I$(VBOOT_SOURCE)/host/include # UEFI header file support. It's not pretty, but that's what we currently # have right now. TOOLCPPFLAGS += -I$(top)/src diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c index 830fe16..da8fdee 100644 --- a/util/cbfstool/cbfs-mkpayload.c +++ b/util/cbfstool/cbfs-mkpayload.c @@ -66,7 +66,7 @@ } int parse_elf_to_payload(const struct buffer *input, struct buffer *output, - enum comp_algo algo) + enum cbfs_compression algo) { Elf64_Phdr *phdr; Elf64_Ehdr ehdr; @@ -247,7 +247,7 @@ struct buffer *output, uint32_t loadaddress, uint32_t entrypoint, - enum comp_algo algo) + enum cbfs_compression algo) { comp_func_ptr compress; struct cbfs_payload_segment segs[2] = { {0} }; @@ -292,7 +292,7 @@ } int parse_fv_to_payload(const struct buffer *input, struct buffer *output, - enum comp_algo algo) + enum cbfs_compression algo) { comp_func_ptr compress; struct cbfs_payload_segment segs[2] = { {0} }; @@ -420,7 +420,7 @@ } int parse_fit_to_payload(const struct buffer *input, struct buffer *output, - enum comp_algo algo) + enum cbfs_compression algo) { struct fdt_header *fdt_h; diff --git a/util/cbfstool/cbfs-mkstage.c b/util/cbfstool/cbfs-mkstage.c index be920b4..cfa820b 100644 --- a/util/cbfstool/cbfs-mkstage.c +++ b/util/cbfstool/cbfs-mkstage.c @@ -89,7 +89,7 @@ return NULL; } -static void fill_cbfs_stage(struct buffer *outheader, enum comp_algo algo, +static void fill_cbfs_stage(struct buffer *outheader, enum cbfs_compression algo, uint64_t entry, uint64_t loadaddr, uint32_t filesize, uint32_t memsize) { @@ -109,7 +109,7 @@ * works for all elf files, not just the restricted set. */ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, - enum comp_algo algo, uint32_t *location, + enum cbfs_compression algo, uint32_t *location, const char *ignore_section) { struct parsed_elf pelf; diff --git a/util/cbfstool/cbfs-payload-linux.c b/util/cbfstool/cbfs-payload-linux.c index 6b4bf27..b9e56ea 100644 --- a/util/cbfstool/cbfs-payload-linux.c +++ b/util/cbfstool/cbfs-payload-linux.c @@ -47,14 +47,14 @@ struct buffer cmdline; struct buffer initrd; /* Output variables. */ - enum comp_algo algo; + enum cbfs_compression algo; comp_func_ptr compress; struct buffer output; size_t offset; struct cbfs_payload_segment *out_seg; }; -static int bzp_init(struct bzpayload *bzp, enum comp_algo algo) +static int bzp_init(struct bzpayload *bzp, enum cbfs_compression algo) { memset(bzp, 0, sizeof(*bzp)); @@ -199,7 +199,7 @@ */ int parse_bzImage_to_payload(const struct buffer *input, struct buffer *output, const char *initrd_name, - char *cmdline, enum comp_algo algo) + char *cmdline, enum cbfs_compression algo) { struct bzpayload bzp; unsigned int initrd_base = 64*1024*1024; diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index f0c215d..10b478c 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -17,234 +17,57 @@ #define __CBFS_H #include "common.h" -#include <stdint.h> - -#include <vb2_api.h> - -/* cbfstool will fail when trying to build a cbfs_file header that's larger - * than MAX_CBFS_FILE_HEADER_BUFFER. 1K should give plenty of room. */ -#define MAX_CBFS_FILE_HEADER_BUFFER 1024 - -/* create a magic number in host-byte order. - * b3 is the high order byte. - * in the coreboot tools, we go with the 32-bit - * magic number convention. - * This was an inline func but that breaks anything - * that uses it in a case statement. - */ - -#define makemagic(b3, b2, b1, b0)\ - (((b3)<<24) | ((b2) << 16) | ((b1) << 8) | (b0)) +#include <commonlib/bsd/cbfs_serialized.h> /* To make CBFS more friendly to ROM, fill -1 (0xFF) instead of zero. */ #define CBFS_CONTENT_DEFAULT_VALUE (-1) -// Alignment (in bytes) to be used when no master header is present -#define CBFS_ENTRY_ALIGNMENT 64 - -#define CBFS_HEADER_MAGIC 0x4F524243 #define CBFS_HEADPTR_ADDR_X86 0xFFFFFFFC -#define CBFS_HEADER_VERSION1 0x31313131 -#define CBFS_HEADER_VERSION2 0x31313132 -#define CBFS_HEADER_VERSION CBFS_HEADER_VERSION2 -#define CBFS_ALIGNMENT 64 - -struct cbfs_header { - uint32_t magic; - uint32_t version; - uint32_t romsize; - uint32_t bootblocksize; - uint32_t align; /* hard coded to 64 byte */ - uint32_t offset; - uint32_t architecture; /* Version 2 */ - uint32_t pad[1]; -} __packed; - -#define CBFS_ARCHITECTURE_UNKNOWN 0xFFFFFFFF -#define CBFS_ARCHITECTURE_X86 0x00000001 -#define CBFS_ARCHITECTURE_ARM 0x00000010 -#define CBFS_ARCHITECTURE_AARCH64 0x0000aa64 -#define CBFS_ARCHITECTURE_MIPS 0x00000100 /* deprecated */ -#define CBFS_ARCHITECTURE_RISCV 0xc001d0de -#define CBFS_ARCHITECTURE_PPC64 0x407570ff - -#define CBFS_FILE_MAGIC "LARCHIVE" - -struct cbfs_file { - uint8_t magic[8]; - /* length of file data */ - uint32_t len; +struct typedesc_t { uint32_t type; - /* offset to struct cbfs_file_attribute or 0 */ - uint32_t attributes_offset; - /* length of header incl. variable data */ - uint32_t offset; - char filename[]; -} __packed; + const char *name; +}; -#if defined __GNUC__ && (__GNUC__ * 100 + __GNUC_MINOR__) >= 406 -_Static_assert(sizeof(struct cbfs_file) == 24, "cbfs_file size mismatch"); -#endif - -/* The common fields of extended cbfs file attributes. - Attributes are expected to start with tag/len, then append their - specific fields. */ -struct cbfs_file_attribute { - uint32_t tag; - /* len covers the whole structure, incl. tag and len */ - uint32_t len; - uint8_t data[0]; -} __packed; - -/* Depending on how the header was initialized, it may be backed with 0x00 or - * 0xff. Support both. */ -#define CBFS_FILE_ATTR_TAG_UNUSED 0 -#define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff -#define CBFS_FILE_ATTR_TAG_COMPRESSION 0x42435a4c -#define CBFS_FILE_ATTR_TAG_HASH 0x68736148 -#define CBFS_FILE_ATTR_TAG_POSITION 0x42435350 /* PSCB */ -#define CBFS_FILE_ATTR_TAG_ALIGNMENT 0x42434c41 /* ALCB */ -#define CBFS_FILE_ATTR_TAG_PADDING 0x47444150 /* PDNG */ -#define CBFS_FILE_ATTR_TAG_IBB 0x32494242 /* Initial BootBlock */ - -struct cbfs_file_attr_compression { - uint32_t tag; - uint32_t len; - /* whole file compression format. 0 if no compression. */ - uint32_t compression; - uint32_t decompressed_size; -} __packed; - -struct cbfs_file_attr_hash { - uint32_t tag; - uint32_t len; - uint32_t hash_type; - /* hash_data is len - sizeof(struct) bytes */ - uint8_t hash_data[]; -} __packed; - -struct cbfs_file_attr_position { - uint32_t tag; - uint32_t len; - uint32_t position; -} __packed; - -struct cbfs_file_attr_align { - uint32_t tag; - uint32_t len; - uint32_t alignment; -} __packed; - -struct cbfs_stage { - uint32_t compression; - uint64_t entry; - uint64_t load; - uint32_t len; - uint32_t memlen; -} __packed; - -#define PAYLOAD_SEGMENT_CODE makemagic('C', 'O', 'D', 'E') -#define PAYLOAD_SEGMENT_DATA makemagic('D', 'A', 'T', 'A') -#define PAYLOAD_SEGMENT_BSS makemagic('B', 'S', 'S', ' ') -#define PAYLOAD_SEGMENT_PARAMS makemagic('P', 'A', 'R', 'A') -#define PAYLOAD_SEGMENT_ENTRY makemagic('E', 'N', 'T', 'R') - -struct cbfs_payload_segment { - uint32_t type; - uint32_t compression; - uint32_t offset; - uint64_t load_addr; - uint32_t len; - uint32_t mem_len; -} __packed; - -struct cbfs_payload { - struct cbfs_payload_segment segments; -} __packed; - -/** These are standard component types for well known - components (i.e - those that coreboot needs to consume. - Users are welcome to use any other value for their - components */ - -#define CBFS_COMPONENT_BOOTBLOCK 0x01 -#define CBFS_COMPONENT_CBFSHEADER 0x02 -#define CBFS_COMPONENT_STAGE 0x10 -#define CBFS_COMPONENT_SELF 0x20 -#define CBFS_COMPONENT_FIT 0x21 -#define CBFS_COMPONENT_OPTIONROM 0x30 -#define CBFS_COMPONENT_BOOTSPLASH 0x40 -#define CBFS_COMPONENT_RAW 0x50 -#define CBFS_COMPONENT_VSA 0x51 -#define CBFS_COMPONENT_MBI 0x52 -#define CBFS_COMPONENT_MICROCODE 0x53 -#define CBFS_COMPONENT_FSP 0x60 -#define CBFS_COMPONENT_MRC 0x61 -#define CBFS_COMPONENT_MMA 0x62 -#define CBFS_COMPONENT_EFI 0x63 -#define CBFS_COMPONENT_STRUCT 0x70 -#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa -#define CBFS_COMPONENT_SPD 0xab -#define CBFS_COMPONENT_MRC_CACHE 0xac -#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa - -/* The deleted type is chosen to be a value - * that can be written in a FLASH from all other - * values. - */ -#define CBFS_COMPONENT_DELETED 0 - -/* for all known FLASH, this value can be changed - * to all other values. This allows NULL files to be - * changed without a block erase - */ -#define CBFS_COMPONENT_NULL 0xFFFFFFFF +static const struct typedesc_t types_cbfs_compression[] = { + {CBFS_COMPRESS_NONE, "none"}, + {CBFS_COMPRESS_LZMA, "LZMA"}, + {CBFS_COMPRESS_LZ4, "LZ4"}, + {0, NULL}, +}; static struct typedesc_t filetypes[] unused = { - {CBFS_COMPONENT_BOOTBLOCK, "bootblock"}, - {CBFS_COMPONENT_CBFSHEADER, "cbfs header"}, - {CBFS_COMPONENT_STAGE, "stage"}, - {CBFS_COMPONENT_SELF, "simple elf"}, - {CBFS_COMPONENT_FIT, "fit"}, - {CBFS_COMPONENT_OPTIONROM, "optionrom"}, - {CBFS_COMPONENT_BOOTSPLASH, "bootsplash"}, - {CBFS_COMPONENT_RAW, "raw"}, - {CBFS_COMPONENT_VSA, "vsa"}, - {CBFS_COMPONENT_MBI, "mbi"}, - {CBFS_COMPONENT_MICROCODE, "microcode"}, - {CBFS_COMPONENT_FSP, "fsp"}, - {CBFS_COMPONENT_MRC, "mrc"}, - {CBFS_COMPONENT_CMOS_DEFAULT, "cmos_default"}, - {CBFS_COMPONENT_CMOS_LAYOUT, "cmos_layout"}, - {CBFS_COMPONENT_SPD, "spd"}, - {CBFS_COMPONENT_MRC_CACHE, "mrc_cache"}, - {CBFS_COMPONENT_MMA, "mma"}, - {CBFS_COMPONENT_EFI, "efi"}, - {CBFS_COMPONENT_STRUCT, "struct"}, - {CBFS_COMPONENT_DELETED, "deleted"}, - {CBFS_COMPONENT_NULL, "null"} + {CBFS_TYPE_BOOTBLOCK, "bootblock"}, + {CBFS_TYPE_CBFSHEADER, "cbfs header"}, + {CBFS_TYPE_STAGE, "stage"}, + {CBFS_TYPE_SELF, "simple elf"}, + {CBFS_TYPE_FIT, "fit"}, + {CBFS_TYPE_OPTIONROM, "optionrom"}, + {CBFS_TYPE_BOOTSPLASH, "bootsplash"}, + {CBFS_TYPE_RAW, "raw"}, + {CBFS_TYPE_VSA, "vsa"}, + {CBFS_TYPE_MBI, "mbi"}, + {CBFS_TYPE_MICROCODE, "microcode"}, + {CBFS_TYPE_FSP, "fsp"}, + {CBFS_TYPE_MRC, "mrc"}, + {CBFS_TYPE_CMOS_DEFAULT, "cmos_default"}, + {CBFS_TYPE_CMOS_LAYOUT, "cmos_layout"}, + {CBFS_TYPE_SPD, "spd"}, + {CBFS_TYPE_MRC_CACHE, "mrc_cache"}, + {CBFS_TYPE_MMA, "mma"}, + {CBFS_TYPE_EFI, "efi"}, + {CBFS_TYPE_STRUCT, "struct"}, + {CBFS_TYPE_DELETED, "deleted"}, + {CBFS_TYPE_NULL, "null"} }; -static const struct typedesc_t types_cbfs_hash[] unused = { - {VB2_HASH_INVALID, "none"}, - {VB2_HASH_SHA1, "sha1"}, - {VB2_HASH_SHA256, "sha256"}, - {VB2_HASH_SHA512, "sha512"}, - {0, NULL} -}; - -static size_t widths_cbfs_hash[] unused = { - [VB2_HASH_INVALID] = 0, - [VB2_HASH_SHA1] = 20, - [VB2_HASH_SHA256] = 32, - [VB2_HASH_SHA512] = 64, -}; - -#define CBFS_NUM_SUPPORTED_HASHES ARRAY_SIZE(widths_cbfs_hash) - #define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) ) +static inline size_t cbfs_file_attr_hash_size(enum vb2_hash_algorithm algo) { + return offsetof(struct cbfs_file_attr_hash, hash.raw) + + vb2_digest_size(algo); +} + /* cbfs_image.c */ uint32_t get_cbfs_entry_type(const char *name, uint32_t default_value); uint32_t get_cbfs_compression(const char *name, uint32_t unknown); diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 9bf3688..035b196 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -80,16 +80,6 @@ return lookup_type_by_name(types_cbfs_compression, name); } -static const char *get_hash_attr_name(uint16_t hash_type) -{ - return lookup_name_by_type(types_cbfs_hash, hash_type, "(invalid)"); -} - -int cbfs_parse_hash_algo(const char *name) -{ - return lookup_type_by_name(types_cbfs_hash, name); -} - /* CBFS image */ size_t cbfs_calculate_file_header_size(const char *name) @@ -227,7 +217,7 @@ size_t empty_header_len = cbfs_calculate_file_header_size(""); uint32_t entries_offset = 0; - uint32_t align = CBFS_ENTRY_ALIGNMENT; + uint32_t align = CBFS_ALIGNMENT; if (image->has_header) { entries_offset = image->header.offset; @@ -266,7 +256,7 @@ size_t capacity = entries_size - empty_header_len; LOG("Created CBFS (capacity = %zu bytes)\n", capacity); - return cbfs_create_empty_entry(entry_header, CBFS_COMPONENT_NULL, + return cbfs_create_empty_entry(entry_header, CBFS_TYPE_NULL, capacity, ""); } @@ -402,7 +392,7 @@ size_t copy_end = buffer_size(dst); - align = CBFS_ENTRY_ALIGNMENT; + align = CBFS_ALIGNMENT; dst_entry = (struct cbfs_file *)buffer_get(dst); @@ -412,9 +402,9 @@ src_entry = cbfs_find_next_entry(image, src_entry)) { size_t entry_size; - if ((src_entry->type == htonl(CBFS_COMPONENT_NULL)) || - (src_entry->type == htonl(CBFS_COMPONENT_CBFSHEADER)) || - (src_entry->type == htonl(CBFS_COMPONENT_DELETED))) + if ((src_entry->type == htonl(CBFS_TYPE_NULL)) || + (src_entry->type == htonl(CBFS_TYPE_CBFSHEADER)) || + (src_entry->type == htonl(CBFS_TYPE_DELETED))) continue; entry_size = htonl(src_entry->len) + htonl(src_entry->offset); @@ -440,7 +430,7 @@ if (last_entry_size < 0) WARN("No room to create the last entry!\n") else - cbfs_create_empty_entry(dst_entry, CBFS_COMPONENT_NULL, + cbfs_create_empty_entry(dst_entry, CBFS_TYPE_NULL, last_entry_size, ""); return 0; @@ -476,7 +466,7 @@ cbfs_calculate_file_header_size("") - sizeof(int32_t); if (last_entry_size > 0) { - cbfs_create_empty_entry(entry, CBFS_COMPONENT_NULL, + cbfs_create_empty_entry(entry, CBFS_TYPE_NULL, last_entry_size, ""); /* If the last entry was an empty file, merge them. */ cbfs_walk(&image, cbfs_merge_empty_entry, NULL); @@ -510,8 +500,8 @@ * maximum size. */ if ((strlen(trailer->filename) != 0) && - (trailer->type != htonl(CBFS_COMPONENT_NULL)) && - (trailer->type != htonl(CBFS_COMPONENT_DELETED))) { + (trailer->type != htonl(CBFS_TYPE_NULL)) && + (trailer->type != htonl(CBFS_TYPE_DELETED))) { /* nothing to truncate. Return de-facto CBFS size in case it * was already truncated. */ *size = (uint8_t *)entry - (uint8_t *)buffer_get(region); @@ -565,8 +555,8 @@ uint32_t type = htonl(cur->type); /* Current entry is empty. Kepp track of it. */ - if ((type == htonl(CBFS_COMPONENT_NULL)) || - (type == htonl(CBFS_COMPONENT_DELETED))) { + if ((type == htonl(CBFS_TYPE_NULL)) || + (type == htonl(CBFS_TYPE_DELETED))) { prev = cur; continue; } @@ -627,7 +617,7 @@ prev_size -= spill_size + empty_metadata_size; /* Create new empty file. */ - cbfs_create_empty_entry(cur, CBFS_COMPONENT_NULL, + cbfs_create_empty_entry(cur, CBFS_TYPE_NULL, prev_size, ""); /* Merge any potential empty entries together. */ @@ -667,7 +657,7 @@ uint32_t min_entry_size = cbfs_calculate_file_header_size(""); uint32_t len, header_offset; uint32_t align = image->has_header ? image->header.align : - CBFS_ENTRY_ALIGNMENT; + CBFS_ALIGNMENT; uint32_t header_size = ntohl(header->offset); header_offset = content_offset - header_size; @@ -682,7 +672,7 @@ if (header_offset - addr > min_entry_size) { DEBUG("|min|...|header|content|... <create new entry>\n"); len = header_offset - addr - min_entry_size; - cbfs_create_empty_entry(entry, CBFS_COMPONENT_NULL, len, ""); + cbfs_create_empty_entry(entry, CBFS_TYPE_NULL, len, ""); if (verbose > 1) cbfs_print_entry_info(image, entry, stderr); entry = cbfs_find_next_entry(image, entry); addr = cbfs_get_entry_addr(image, entry); @@ -741,7 +731,7 @@ buffer_size(&image->buffer) - sizeof(int32_t)) { len -= sizeof(int32_t); } - cbfs_create_empty_entry(entry, CBFS_COMPONENT_NULL, len, ""); + cbfs_create_empty_entry(entry, CBFS_TYPE_NULL, len, ""); if (verbose > 1) cbfs_print_entry_info(image, entry, stderr); return 0; } @@ -777,7 +767,7 @@ entry = cbfs_find_next_entry(image, entry)) { entry_type = ntohl(entry->type); - if (entry_type != CBFS_COMPONENT_NULL) + if (entry_type != CBFS_TYPE_NULL) continue; addr = cbfs_get_entry_addr(image, entry); @@ -1352,10 +1342,10 @@ if (do_processing) { int (*make_elf)(struct buffer *, uint32_t) = NULL; switch (ntohl(entry->type)) { - case CBFS_COMPONENT_STAGE: + case CBFS_TYPE_STAGE: make_elf = cbfs_stage_make_elf; break; - case CBFS_COMPONENT_SELF: + case CBFS_TYPE_SELF: make_elf = cbfs_payload_make_elf; break; } @@ -1389,7 +1379,7 @@ } DEBUG("cbfs_remove_entry: Removed %s @ 0x%x\n", entry->filename, cbfs_get_entry_addr(image, entry)); - entry->type = htonl(CBFS_COMPONENT_DELETED); + entry->type = htonl(CBFS_TYPE_DELETED); cbfs_walk(image, cbfs_merge_empty_entry, NULL); return 0; } @@ -1513,28 +1503,21 @@ decompressed_size ); - struct cbfs_file_attr_hash *hash = NULL; - while ((hash = cbfs_file_get_next_hash(entry, hash)) != NULL) { - unsigned int hash_type = ntohl(hash->hash_type); - if (hash_type >= CBFS_NUM_SUPPORTED_HASHES) { - fprintf(fp, "invalid hash type %d\n", hash_type); + struct cbfs_file_attr_hash *attr = NULL; + while ((attr = cbfs_file_get_next_hash(entry, attr)) != NULL) { + size_t hash_len = vb2_digest_size(attr->hash.algo); + if (!hash_len) { + fprintf(fp, "invalid/unsupported hash algorithm: %d\n", + attr->hash.algo); break; } - size_t hash_len = widths_cbfs_hash[hash_type]; - char *hash_str = bintohex(hash->hash_data, hash_len); - uint8_t local_hash[hash_len]; - if (vb2_digest_buffer(CBFS_SUBHEADER(entry), - ntohl(entry->len), hash_type, local_hash, - hash_len) != VB2_SUCCESS) { - fprintf(fp, "failed to hash '%s'\n", name); - free(hash_str); - break; - } - int valid = memcmp(local_hash, hash->hash_data, hash_len) == 0; + char *hash_str = bintohex(attr->hash.raw, hash_len); + int valid = vb2_hash_verify(CBFS_SUBHEADER(entry), + ntohl(entry->len), &attr->hash) == VB2_SUCCESS; const char *valid_str = valid ? "valid" : "invalid"; fprintf(fp, " hash %s:%s %s\n", - get_hash_attr_name(hash_type), + vb2_get_hash_algorithm_name(attr->hash.algo), hash_str, valid_str); free(hash_str); } @@ -1549,12 +1532,12 @@ /* note the components of the subheader may be in host order ... */ switch (ntohl(entry->type)) { - case CBFS_COMPONENT_STAGE: + case CBFS_TYPE_STAGE: cbfs_print_stage_info((struct cbfs_stage *) CBFS_SUBHEADER(entry), fp); break; - case CBFS_COMPONENT_SELF: + case CBFS_TYPE_SELF: payload = (struct cbfs_payload_segment *) CBFS_SUBHEADER(entry); while (payload) { @@ -1650,8 +1633,8 @@ /* Loop until non-empty entry is found, starting from the current entry. After the loop, next_addr points to the next non-empty entry. */ next = entry; - while (ntohl(next->type) == CBFS_COMPONENT_DELETED || - ntohl(next->type) == CBFS_COMPONENT_NULL) { + while (ntohl(next->type) == CBFS_TYPE_DELETED || + ntohl(next->type) == CBFS_TYPE_NULL) { next = cbfs_find_next_entry(image, next); if (!next) break; @@ -1672,7 +1655,7 @@ uint32_t addr = cbfs_get_entry_addr(image, entry); size_t len = next_addr - addr - cbfs_calculate_file_header_size(""); DEBUG("join_empty_entry: [0x%x, 0x%x) len=%zu\n", addr, next_addr, len); - cbfs_create_empty_entry(entry, CBFS_COMPONENT_NULL, len, ""); + cbfs_create_empty_entry(entry, CBFS_TYPE_NULL, len, ""); return 0; } @@ -1766,8 +1749,7 @@ struct cbfs_file *entry) { uint32_t addr = cbfs_get_entry_addr(image, entry); - int align = image->has_header ? image->header.align : - CBFS_ENTRY_ALIGNMENT; + int align = image->has_header ? image->header.align : CBFS_ALIGNMENT; assert(entry && cbfs_is_valid_entry(image, entry)); addr += ntohl(entry->offset) + ntohl(entry->len); addr = align_up(addr, align); @@ -1808,8 +1790,8 @@ struct cbfs_file *cbfs_create_file_header(int type, size_t len, const char *name) { - struct cbfs_file *entry = malloc(MAX_CBFS_FILE_HEADER_BUFFER); - memset(entry, CBFS_CONTENT_DEFAULT_VALUE, MAX_CBFS_FILE_HEADER_BUFFER); + struct cbfs_file *entry = malloc(CBFS_METADATA_MAX_SIZE); + memset(entry, CBFS_CONTENT_DEFAULT_VALUE, CBFS_METADATA_MAX_SIZE); memcpy(entry->magic, CBFS_FILE_MAGIC, sizeof(entry->magic)); entry->type = htonl(type); entry->len = htonl(len); @@ -1882,7 +1864,7 @@ next = cbfs_file_next_attr(header, attr); } while (next != NULL); uint32_t header_size = ntohl(header->offset) + size; - if (header_size > MAX_CBFS_FILE_HEADER_BUFFER) { + if (header_size > CBFS_METADATA_MAX_SIZE) { DEBUG("exceeding allocated space for cbfs_file headers"); return NULL; } @@ -1904,35 +1886,31 @@ ntohl(attr->len)); } header->offset = htonl(header_size); - memset(attr, CBFS_CONTENT_DEFAULT_VALUE, size); + /* Attributes are expected to be small (much smaller than a flash page) + and not really meant to be overwritten in-place. To avoid surprising + values in reserved fields of attribute structures, initialize them to + 0, not 0xff. */ + memset(attr, 0, size); attr->tag = htonl(tag); attr->len = htonl(size); return attr; } int cbfs_add_file_hash(struct cbfs_file *header, struct buffer *buffer, - enum vb2_hash_algorithm hash_type) + enum vb2_hash_algorithm alg) { - uint32_t hash_index = hash_type; - - if (hash_index >= CBFS_NUM_SUPPORTED_HASHES) + if (!vb2_digest_size(alg)) return -1; - unsigned hash_size = widths_cbfs_hash[hash_type]; - if (hash_size == 0) - return -1; - - struct cbfs_file_attr_hash *attrs = + struct cbfs_file_attr_hash *attr = (struct cbfs_file_attr_hash *)cbfs_add_file_attr(header, - CBFS_FILE_ATTR_TAG_HASH, - sizeof(struct cbfs_file_attr_hash) + hash_size); + CBFS_FILE_ATTR_TAG_HASH, cbfs_file_attr_hash_size(alg)); - if (attrs == NULL) + if (attr == NULL) return -1; - attrs->hash_type = htonl(hash_type); - if (vb2_digest_buffer(buffer_get(buffer), buffer_size(buffer), - hash_type, attrs->hash_data, hash_size) != VB2_SUCCESS) + if (vb2_hash_calculate(buffer_get(buffer), buffer_size(buffer), + alg, &attr->hash) != VB2_SUCCESS) return -1; return 0; @@ -1984,7 +1962,7 @@ size, page_size); size_t image_align = image->has_header ? image->header.align : - CBFS_ENTRY_ALIGNMENT; + CBFS_ALIGNMENT; if (page_size % image_align) WARN("%s: Page size (%#zx) not aligned with CBFS image (%#zx).\n", __func__, page_size, image_align); @@ -2020,7 +1998,7 @@ entry = cbfs_find_next_entry(image, entry)) { uint32_t type = ntohl(entry->type); - if (type != CBFS_COMPONENT_NULL) + if (type != CBFS_TYPE_NULL) continue; addr = cbfs_get_entry_addr(image, entry); diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 1bb3c68..6ff0746 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -54,7 +54,7 @@ /* Creates an empty CBFS image by given size, and description to its content * (bootblock, align, header location, starting offset of CBFS entries). * The output image will contain a valid cbfs_header, with one cbfs_file - * entry with type CBFS_COMPONENT_NULL, with max available size. + * entry with type CBFS_TYPE_NULL, with max available size. * Only call this if you want a legacy CBFS with a master header. * Returns 0 on success, otherwise nonzero. */ int cbfs_legacy_image_create(struct cbfs_image *image, diff --git a/util/cbfstool/cbfscomptool.c b/util/cbfstool/cbfscomptool.c index 028893c..a1245b5 100644 --- a/util/cbfstool/cbfscomptool.c +++ b/util/cbfstool/cbfscomptool.c @@ -19,6 +19,7 @@ #include <strings.h> #include <time.h> +#include "cbfs.h" #include "common.h" const char *usage_text = "cbfs-compression-tool benchmark\n" diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index f15c65b..f97745e 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -34,6 +34,7 @@ #include <commonlib/fsp.h> #include <commonlib/endian.h> #include <commonlib/helpers.h> +#include <vboot_host.h> #define SECTION_WITH_FIT_TABLE "BOOTBLOCK" @@ -86,7 +87,7 @@ bool machine_parseable; bool unprocessed; bool ibb; - enum comp_algo compression; + enum cbfs_compression compression; int precompression; enum vb2_hash_algorithm hash; /* For linux payloads */ @@ -198,7 +199,7 @@ /* Take care of the hash attribute if it is used */ if (param.hash != VB2_HASH_INVALID) - metadata_size += sizeof(struct cbfs_file_attr_hash); + metadata_size += cbfs_file_attr_hash_size(param.hash); int32_t address = cbfs_locate_entry(&image, data_size, param.pagesize, param.alignment, metadata_size); @@ -250,7 +251,7 @@ offset = convert_to_from_top_aligned(param.image_region, -offset); - header = cbfs_create_file_header(CBFS_COMPONENT_RAW, + header = cbfs_create_file_header(CBFS_TYPE_RAW, buffer.size, name); if (cbfs_add_entry(&image, &buffer, offset, header, 0) != 0) { ERROR("Failed to add %llu into ROM image as '%s'.\n", @@ -351,7 +352,7 @@ * image is at 4GB == 0. */ h->bootblocksize = htonl(4); - h->align = htonl(CBFS_ENTRY_ALIGNMENT); + h->align = htonl(CBFS_ALIGNMENT); /* The offset and romsize fields within the master header are absolute * values within the boot media. As such, romsize needs to relfect * the end 'offset' for a CBFS. To achieve that the current buffer @@ -365,7 +366,7 @@ h->offset = htonl(offset); h->architecture = htonl(CBFS_ARCHITECTURE_UNKNOWN); - header = cbfs_create_file_header(CBFS_COMPONENT_CBFSHEADER, + header = cbfs_create_file_header(CBFS_TYPE_CBFSHEADER, buffer_size(&buffer), name); if (cbfs_add_entry(&image, &buffer, 0, header, 0) != 0) { ERROR("Failed to add cbfs master header into ROM image.\n"); @@ -487,7 +488,7 @@ * Check if Intel CPU topswap is specified this will require a * second bootblock to be added. */ - if (type == CBFS_COMPONENT_BOOTBLOCK && param.topswap_size) + if (type == CBFS_TYPE_BOOTBLOCK && param.topswap_size) if (add_topswap_bootblock(&buffer, &offset)) return 1; @@ -522,10 +523,10 @@ /* care about the additional metadata that is added */ /* to the cbfs file and therefore set the position */ /* the real beginning of the data. */ - if (type == CBFS_COMPONENT_STAGE) + if (type == CBFS_TYPE_STAGE) attrs->position = htonl(offset + sizeof(struct cbfs_stage)); - else if (type == CBFS_COMPONENT_SELF) + else if (type == CBFS_TYPE_SELF) attrs->position = htonl(offset + sizeof(struct cbfs_payload)); else @@ -759,7 +760,7 @@ if (ret != 0) { ret = parse_fit_to_payload(buffer, &output, param.compression); if (ret == 0) - header->type = htonl(CBFS_COMPONENT_FIT); + header->type = htonl(CBFS_TYPE_FIT); } /* If it's not an FIT, see if it's a UEFI FV */ @@ -817,7 +818,7 @@ /* Set the alignment to 4KiB minimum for FSP blobs when no base address * is provided so that relocation can occur. */ - if (param.type == CBFS_COMPONENT_FSP) { + if (param.type == CBFS_TYPE_FSP) { if (!param.baseaddress_assigned) param.alignment = 4*1024; convert = cbfstool_convert_fsp; @@ -858,7 +859,7 @@ return cbfs_add_component(param.filename, param.name, - CBFS_COMPONENT_STAGE, + CBFS_TYPE_STAGE, param.baseaddress, param.headeroffset, cbfstool_convert_mkstage); @@ -868,7 +869,7 @@ { return cbfs_add_component(param.filename, param.name, - CBFS_COMPONENT_SELF, + CBFS_TYPE_SELF, param.baseaddress, param.headeroffset, cbfstool_convert_mkpayload); @@ -888,7 +889,7 @@ } return cbfs_add_component(param.filename, param.name, - CBFS_COMPONENT_SELF, + CBFS_TYPE_SELF, param.baseaddress, param.headeroffset, cbfstool_convert_mkflatpayload); @@ -1577,10 +1578,7 @@ break; } case 'A': { - int algo = cbfs_parse_hash_algo(optarg); - if (algo >= 0) - param.hash = algo; - else { + if (!vb2_lookup_hash_alg(optarg, &param.hash)) { ERROR("Unknown hash algorithm '%s'.\n", optarg); return 1; diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index f152104..8aac371 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -22,10 +22,10 @@ #include <string.h> #include <assert.h> +#include <commonlib/bsd/cbfs_serialized.h> #include <commonlib/helpers.h> #include <console/console.h> -/* Endianness */ #include "swab.h" #define IS_TOP_ALIGNED_ADDRESS(x) ((uint32_t)(x) > 0x80000000) @@ -160,47 +160,29 @@ typedef int (*decomp_func_ptr) (char *in, int in_len, char *out, int out_len, size_t *actual_size); -enum comp_algo { - CBFS_COMPRESS_NONE = 0, - CBFS_COMPRESS_LZMA = 1, - CBFS_COMPRESS_LZ4 = 2, -}; - -struct typedesc_t { - uint32_t type; - const char *name; -}; - -static const struct typedesc_t types_cbfs_compression[] = { - {CBFS_COMPRESS_NONE, "none"}, - {CBFS_COMPRESS_LZMA, "LZMA"}, - {CBFS_COMPRESS_LZ4, "LZ4"}, - {0, NULL}, -}; - -comp_func_ptr compression_function(enum comp_algo algo); -decomp_func_ptr decompression_function(enum comp_algo algo); +comp_func_ptr compression_function(enum cbfs_compression algo); +decomp_func_ptr decompression_function(enum cbfs_compression algo); uint64_t intfiletype(const char *name); /* cbfs-mkpayload.c */ int parse_elf_to_payload(const struct buffer *input, struct buffer *output, - enum comp_algo algo); + enum cbfs_compression algo); int parse_fv_to_payload(const struct buffer *input, struct buffer *output, - enum comp_algo algo); + enum cbfs_compression algo); int parse_fit_to_payload(const struct buffer *input, struct buffer *output, - enum comp_algo algo); + enum cbfs_compression algo); int parse_bzImage_to_payload(const struct buffer *input, struct buffer *output, const char *initrd, - char *cmdline, enum comp_algo algo); + char *cmdline, enum cbfs_compression algo); int parse_flat_binary_to_payload(const struct buffer *input, struct buffer *output, uint32_t loadaddress, uint32_t entrypoint, - enum comp_algo algo); + enum cbfs_compression algo); /* cbfs-mkstage.c */ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, - enum comp_algo algo, uint32_t *location, + enum cbfs_compression algo, uint32_t *location, const char *ignore_section); /* location is TOP aligned. */ int parse_elf_to_xip_stage(const struct buffer *input, struct buffer *output, diff --git a/util/cbfstool/compress.c b/util/cbfstool/compress.c index 9938094..52ae6df 100644 --- a/util/cbfstool/compress.c +++ b/util/cbfstool/compress.c @@ -83,7 +83,7 @@ return 0; } -comp_func_ptr compression_function(enum comp_algo algo) +comp_func_ptr compression_function(enum cbfs_compression algo) { comp_func_ptr compress; switch (algo) { @@ -103,7 +103,7 @@ return compress; } -decomp_func_ptr decompression_function(enum comp_algo algo) +decomp_func_ptr decompression_function(enum cbfs_compression algo) { decomp_func_ptr decompress; switch (algo) { -- To view, visit https://review.coreboot.org/c/coreboot/+/41117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22eae1bcd76d85fff17749617cfe4f1de55603f4 Gerrit-Change-Number: 41117 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

4 20

Change in coreboot[master]: lib/trace: Remove TRACE support
by Kyösti Mälkki (Code Review) 03 Dec '20

03 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45757 ) Change subject: lib/trace: Remove TRACE support ...................................................................... lib/trace: Remove TRACE support Looks like the option is generally not compatible with garbage collections. Nothing is inlined, is_smp_boot() no longer evaluates to constant false and thus the symbols from secondary.S would need to be present for the build to pass after we set SMP=n. Change-Id: I0b6f310e15e6f4992cd054d288903fea8390e5cf Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M Makefile.inc M src/Kconfig M src/console/printk.c M src/console/vsprintf.c M src/drivers/uart/uart8250io.c D src/include/trace.h M src/lib/Makefile.inc D src/lib/trace.c 8 files changed, 0 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/45757/1 diff --git a/Makefile.inc b/Makefile.inc index a43de5e..d2138a0 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -181,9 +181,6 @@ bootblock-generic-ccopts += -D__BOOTBLOCK__ romstage-generic-ccopts += -D__ROMSTAGE__ ramstage-generic-ccopts += -D__RAMSTAGE__ -ifeq ($(CONFIG_TRACE),y) -ramstage-c-ccopts += -finstrument-functions -endif ifeq ($(CONFIG_COVERAGE),y) ramstage-c-ccopts += -fprofile-arcs -ftest-coverage endif diff --git a/src/Kconfig b/src/Kconfig index e46a6e6..45d23ae 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1092,16 +1092,6 @@ is present on Intel 6-series chipsets. endif -config TRACE - bool "Trace function calls" - default n - help - If enabled, every function will print information to console once - the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd) - the 0xaaaabbbb is the actual function and 0xccccdddd is EIP - of calling function. Please note some printk related functions - are omitted from trace to have good looking console dumps. - config DEBUG_COVERAGE bool "Debug code coverage" default n diff --git a/src/console/printk.c b/src/console/printk.c index 4a3de47..85d9bfb 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -10,7 +10,6 @@ #include <console/vtxprintf.h> #include <smp/spinlock.h> #include <smp/node.h> -#include <trace.h> #include <timer.h> DECLARE_SPIN_LOCK(console_lock) @@ -81,7 +80,6 @@ if (log_this < CONSOLE_LOG_FAST) return 0; - DISABLE_TRACE; spin_lock(&console_lock); console_time_run(); @@ -96,7 +94,6 @@ console_time_stop(); spin_unlock(&console_lock); - ENABLE_TRACE; return i; } diff --git a/src/console/vsprintf.c b/src/console/vsprintf.c index d0c569b..06b9e49 100644 --- a/src/console/vsprintf.c +++ b/src/console/vsprintf.c @@ -2,7 +2,6 @@ #include <console/vtxprintf.h> #include <string.h> -#include <trace.h> struct vsnprintf_context { char *str_buf; @@ -24,16 +23,12 @@ int i; struct vsnprintf_context ctx; - DISABLE_TRACE; - ctx.str_buf = buf; ctx.buf_limit = size ? size - 1 : 0; i = vtxprintf(str_tx_byte, fmt, args, &ctx); if (size) *ctx.str_buf = '\0'; - ENABLE_TRACE; - return i; } diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index d0841de..aa8c969 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -3,7 +3,6 @@ #include <arch/io.h> #include <boot/coreboot_tables.h> #include <console/uart.h> -#include <trace.h> #include "uart8250reg.h" /* Should support 8250, 16450, 16550, 16550A type UARTs */ @@ -54,7 +53,6 @@ static void uart8250_init(unsigned int base_port, unsigned int divisor) { - DISABLE_TRACE; /* Disable interrupts */ outb(0x0, base_port + UART8250_IER); /* Enable FIFOs */ @@ -72,7 +70,6 @@ /* Set to 3 for 8N1 */ outb(CONFIG_TTYS0_LCS, base_port + UART8250_LCR); - ENABLE_TRACE; } static const unsigned int bases[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; diff --git a/src/include/trace.h b/src/include/trace.h deleted file mode 100644 index ece1b21..0000000 --- a/src/include/trace.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __TRACE_H -#define __TRACE_H - -#if !ENV_ROMSTAGE_OR_BEFORE && CONFIG(TRACE) - -void __cyg_profile_func_enter(void *, void *) - __attribute__((no_instrument_function)); - -void __cyg_profile_func_exit(void *, void *) - __attribute__((no_instrument_function)); - -extern volatile int trace_dis; - -#define DISABLE_TRACE do { trace_dis = 1; } while (0); -#define ENABLE_TRACE do { trace_dis = 0; } while (0); -#define DISABLE_TRACE_ON_FUNCTION __attribute__((no_instrument_function)); - -#else /* !CONFIG_TRACE */ - -#define DISABLE_TRACE -#define ENABLE_TRACE -#define DISABLE_TRACE_ON_FUNCTION - -#endif - -#endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 73077f7..f1653a1 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -139,8 +139,6 @@ ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_BOOTSPLASH) += bootsplash.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c -ramstage-$(CONFIG_TRACE) += trace.c -postcar-$(CONFIG_TRACE) += trace.c ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-$(CONFIG_COVERAGE) += libgcov.c ramstage-y += edid.c diff --git a/src/lib/trace.c b/src/lib/trace.c deleted file mode 100644 index a3db40b..0000000 --- a/src/lib/trace.c +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <trace.h> - -int volatile trace_dis = 0; - -void __cyg_profile_func_enter(void *func, void *callsite) -{ - - if (trace_dis) - return; - - DISABLE_TRACE - printk(BIOS_INFO, "~%p(%p)\n", func, callsite); - ENABLE_TRACE -} - -void __cyg_profile_func_exit(void *func, void *callsite) -{ -} -- To view, visit https://review.coreboot.org/c/coreboot/+/45757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b6f310e15e6f4992cd054d288903fea8390e5cf Gerrit-Change-Number: 45757 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: cbfs: Port cbfs_load() and cbfs_map() to new API
by Julius Werner (Code Review) 03 Dec '20

03 Dec '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39305 to review the following change. Change subject: cbfs: Port cbfs_load() and cbfs_map() to new API ...................................................................... cbfs: Port cbfs_load() and cbfs_map() to new API This patch adapts cbfs_load() and cbfs_map() to use the new CBFS API directly, rather than through cbfs_boot_locate(). For cbfs_load() this means that attribute metadata does not need to be read twice. Change-Id: I754cc34b1c1471129e15475aa0f1891e02439a02 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/commonlib/bsd/cbfs_private.c M src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h M src/lib/cbfs.c 3 files changed, 43 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/39305/1 diff --git a/src/commonlib/bsd/cbfs_private.c b/src/commonlib/bsd/cbfs_private.c index 85a75ab..7e309ec 100644 --- a/src/commonlib/bsd/cbfs_private.c +++ b/src/commonlib/bsd/cbfs_private.c @@ -155,3 +155,21 @@ }; return cbfs_walk(dev, lookup_walker, &args, master_hash, 0); } + +void *cbfs_find_attr(union cbfs_mdata *mdata, uint32_t attr_tag) +{ + uint32_t offset = be32toh(mdata->h.attributes_offset); + uint32_t end = be32toh(mdata->h.offset); + + if (!offset) + return NULL; + + while (offset < end) { + struct cbfs_file_attribute *attr = (void *)mdata + offset; + if (be32toh(attr->tag) == attr_tag) + return attr; + offset += be32toh(attr->len); + } + + return NULL; +} diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h index df97009..4962cef 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h @@ -112,4 +112,7 @@ /* Returns the amount of bytes actually used by the CBFS metadata cache in |mcache|. */ size_t cbfs_mcache_real_size(const void *mcache, size_t mcache_size); +/* Finds a CBFS attribute in a metadata block. Attribute returned as-is (still big-endian). */ +void *cbfs_find_attr(union cbfs_mdata *mdata, uint32_t attr_tag); + #endif /* _COMMONLIB_BSD_CBFS_PRIVATE_H_ */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index bece4d0..c3660aa 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -81,18 +81,19 @@ void *cbfs_map(const char *name, size_t *size) { - struct cbfsf fh; - size_t fsize; + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + union cbfs_mdata mdata; + size_t data_offset; - if (cbfs_boot_locate(&fh, name, NULL)) + if (cbfs_boot_lookup(cbd, name, &mdata, &data_offset)) return NULL; - fsize = region_device_sz(&fh.data); + size_t data_size = be32toh(mdata.h.len); if (size != NULL) - *size = fsize; + *size = data_size; - return rdev_mmap(&fh.data, 0, fsize); + return rdev_mmap(&cbd->rdev, data_offset, data_size); } int cbfs_unmap(void *mapping) @@ -216,21 +217,25 @@ size_t cbfs_load(const char *name, void *buf, size_t buf_size) { - struct cbfsf fh; - uint32_t compression_algo; - size_t decompressed_size; + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + union cbfs_mdata mdata; + size_t data_offset; - if (cbfs_boot_locate(&fh, name, NULL) < 0) + if (cbfs_boot_lookup(cbd, name, &mdata, &data_offset)) return 0; - if (cbfsf_decompression_info(&fh, &compression_algo, - &decompressed_size) - < 0 - || decompressed_size > buf_size) - return 0; + uint32_t compression = CBFS_COMPRESS_NONE; + struct cbfs_file_attr_compression *attr = + cbfs_find_attr(&mdata, CBFS_FILE_ATTR_TAG_COMPRESSION); + if (attr) { + compression = be32toh(attr->compression); + if (buf_size < be32toh(attr->decompressed_size)) + return 0; + } - return cbfs_load_and_decompress(&fh.data, 0, region_device_sz(&fh.data), - buf, buf_size, compression_algo); + return cbfs_load_and_decompress(&cbd->rdev, data_offset, + be32toh(mdata.h.len), buf, buf_size, + compression); } size_t cbfs_prog_stage_section(struct prog *pstage, uintptr_t *base) -- To view, visit https://review.coreboot.org/c/coreboot/+/39305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I754cc34b1c1471129e15475aa0f1891e02439a02 Gerrit-Change-Number: 39305 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: cbfs: Move more stuff into cbfs_boot_lookup()
by Julius Werner (Code Review) 03 Dec '20

03 Dec '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39327 to review the following change. Change subject: cbfs: Move more stuff into cbfs_boot_lookup() ...................................................................... cbfs: Move more stuff into cbfs_boot_lookup() cbfs_boot_locate() is supposed to be deprecated eventually, after slowly migrating all APIs to bypass it. That means common features (like RO-fallback or measurement) need to be moved to the new cbfs_boot_lookup(). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I4bc9b7cbc42a4211d806a3e3389abab7f589a25a --- M src/lib/cbfs.c M src/security/vboot/vboot_crtm.c M src/security/vboot/vboot_crtm.h 3 files changed, 34 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/39327/1 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 39db97a..ef29299 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -31,40 +31,47 @@ #include <security/vboot/vboot_crtm.h> #include <security/vboot/vboot_common.h> -static cb_err_t cbfs_boot_lookup(const struct cbfs_boot_device *cbd, - const char *name, union cbfs_mdata *mdata, size_t *data_offset) +static cb_err_t cbfs_boot_lookup(struct region_device *rdev, const char *name, + union cbfs_mdata *mdata, size_t *data_offset, bool force_ro) { + cb_err_t err; + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(force_ro); + if (!cbd || rdev_chain_full(rdev, &cbd->rdev)) + return CB_ERR; + if (CONFIG(NO_CBFS_MCACHE)) - return cbfs_lookup(&cbd->rdev, name, mdata, data_offset, NULL); + err = cbfs_lookup(rdev, name, mdata, data_offset, NULL); else - return cbfs_mcache_lookup(&cbd->rdev, - cbd->mcache, cbd->mcache_size, - name, mdata, data_offset, NULL); + err = cbfs_mcache_lookup(rdev, cbd->mcache, cbd->mcache_size, + name, mdata, data_offset, NULL); + + if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && !force_ro && + err == CB_CBFS_NOT_FOUND) { + printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n", + name); + return cbfs_boot_lookup(rdev, name, mdata, data_offset, true); + } + if (err) + return err; + + if (vboot_measure_cbfs_hook(rdev, name, be32toh(mdata->h.type))) + return CB_ERR; + + return CB_SUCCESS; } int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) { - const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); - if (!cbd) - return -1; - + struct region_device rdev; union cbfs_mdata mdata; size_t data_offset; - cb_err_t err = cbfs_boot_lookup(cbd, name, &mdata, &data_offset); - if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && err == CB_CBFS_NOT_FOUND) { - printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n", - name); - if (!(cbd = cbfs_get_boot_device(true))) - return -1; - err = cbfs_boot_lookup(cbd, name, &mdata, &data_offset); - } - if (err) + if (cbfs_boot_lookup(&rdev, name, &mdata, &data_offset, false)) return -1; size_t msize = be32toh(mdata.h.offset); - if (rdev_chain(&fh->metadata, &cbd->rdev, data_offset - msize, msize) || - rdev_chain(&fh->data, &cbd->rdev, data_offset, be32toh(mdata.h.len))) + if (rdev_chain(&fh->metadata, &rdev, data_offset - msize, msize) || + rdev_chain(&fh->data, &rdev, data_offset, be32toh(mdata.h.len))) return -1; if (type) { if (!*type) @@ -73,9 +80,6 @@ return -1; } - if (vboot_measure_cbfs_hook(fh, name)) - return -1; - return 0; } diff --git a/src/security/vboot/vboot_crtm.c b/src/security/vboot/vboot_crtm.c index f68ab0a4..75c5662 100644 --- a/src/security/vboot/vboot_crtm.c +++ b/src/security/vboot/vboot_crtm.c @@ -157,19 +157,16 @@ return false; } -uint32_t vboot_measure_cbfs_hook(struct cbfsf *fh, const char *name) +uint32_t vboot_measure_cbfs_hook(struct region_device *rdev, const char *name, + uint32_t cbfs_type) { uint32_t pcr_index; - uint32_t cbfs_type; struct region_device rdev; char tcpa_metadata[TCPA_PCR_HASH_NAME]; if (!vboot_logic_executed()) return 0; - cbfsf_file_type(fh, &cbfs_type); - cbfs_file_data(&rdev, fh); - switch (cbfs_type) { case CBFS_TYPE_MRC: case CBFS_TYPE_MRC_CACHE: diff --git a/src/security/vboot/vboot_crtm.h b/src/security/vboot/vboot_crtm.h index 64cb4f2..8e6c076 100644 --- a/src/security/vboot/vboot_crtm.h +++ b/src/security/vboot/vboot_crtm.h @@ -49,13 +49,14 @@ #if CONFIG(VBOOT_MEASURED_BOOT) /* * Measures cbfs data via hook (cbfs) - * fh is the cbfs file handle to measure + * rdev covers the file data (not metadata) * return 0 if successful, else an error */ -uint32_t vboot_measure_cbfs_hook(struct cbfsf *fh, const char *name); +uint32_t vboot_measure_cbfs_hook(struct region_device *rdev, const char *name, + uint32_t cbfs_type); #else -#define vboot_measure_cbfs_hook(fh, name) 0 +#define vboot_measure_cbfs_hook(rdev, name, cbfs_type) 0 #endif #endif /* __VBOOT_VBOOT_CRTM_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bc9b7cbc42a4211d806a3e3389abab7f589a25a Gerrit-Change-Number: 39327 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: AMD AGESA DDR3 XMP support: scripts for applying the not-merged-yet p...
by Mike Banon (Code Review) 03 Dec '20

03 Dec '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40495 ) Change subject: AMD AGESA DDR3 XMP support: scripts for applying the not-merged-yet patches ...................................................................... AMD AGESA DDR3 XMP support: scripts for applying the not-merged-yet patches These scripts will help you to securely and conveniently apply five changes CB:40484, CB:40485, CB:40490, CB:40488, CB:40489 to add the DDR3 XMP support. Save to ./coreboot/ then run ./get_xmp_patches.sh , ./check... and ./apply... Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ibcb04871e5d969eee1cfd49d21962ae4bbcc4e5d --- A apply_xmp_patches.sh A check_xmp_patches.sh A get_xmp_patches.sh A sha256sums_xmp_correct.txt 4 files changed, 85 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/40495/1 diff --git a/apply_xmp_patches.sh b/apply_xmp_patches.sh new file mode 100755 index 0000000..4320ee2 --- /dev/null +++ b/apply_xmp_patches.sh @@ -0,0 +1,27 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/40484 +### nb/amd/agesa: read 256 bytes to SPD buffer instead of 128 +### +patch -p1 < "./b8b7fb7.diff" +### +### https://review.coreboot.org/c/coreboot/+/40485 +### vc/amd/agesa/f15tn: add 933 MHz to GfxMemClockFrequencyDefinitionTable +### +patch -p1 < "./a81f3eb.diff" +### +### https://review.coreboot.org/c/coreboot/+/40490 +### vc/amd/agesa/f15tn: add DDR1866_FREQUENCY to DdrMaxRateTab table +### +patch -p1 < "./bf4bd85.diff" +### +### https://review.coreboot.org/c/coreboot/+/40488 +### vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles +### +patch -p1 < "./3b9288e.diff" +### +### https://review.coreboot.org/c/coreboot/+/40489 +### vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile +### +patch -p1 < "./413db53.diff" +### diff --git a/check_xmp_patches.sh b/check_xmp_patches.sh new file mode 100755 index 0000000..88a0375 --- /dev/null +++ b/check_xmp_patches.sh @@ -0,0 +1,16 @@ +#!/bin/sh +rm -f "./sha256sums_xmp_my.txt" +sha256sum "./b8b7fb7.diff" > "./sha256sums_xmp_my.txt" +sha256sum "./a81f3eb.diff" >> "./sha256sums_xmp_my.txt" +sha256sum "./bf4bd85.diff" >> "./sha256sums_xmp_my.txt" +sha256sum "./3b9288e.diff" >> "./sha256sums_xmp_my.txt" +sha256sum "./413db53.diff" >> "./sha256sums_xmp_my.txt" +if cmp -s "./sha256sums_xmp_my.txt" "./sha256sums_xmp_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_xmp_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_xmp_my.txt and ./sha256sums_xmp_correct.txt" + exit 1 +fi +# diff --git a/get_xmp_patches.sh b/get_xmp_patches.sh new file mode 100755 index 0000000..34eba96 --- /dev/null +++ b/get_xmp_patches.sh @@ -0,0 +1,37 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/40484 +### nb/amd/agesa: read 256 bytes to SPD buffer instead of 128 +### +rm -f "./b8b7fb7.diff" +wget "https://review.coreboot.org/changes/40484/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./b8b7fb7.diff" +### +### https://review.coreboot.org/c/coreboot/+/40485 +### vc/amd/agesa/f15tn: add 933 MHz to GfxMemClockFrequencyDefinitionTable +### +rm -f "./a81f3eb.diff" +wget "https://review.coreboot.org/changes/40485/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./a81f3eb.diff" +### +### https://review.coreboot.org/c/coreboot/+/40490 +### vc/amd/agesa/f15tn: add DDR1866_FREQUENCY to DdrMaxRateTab table +### +rm -f "./bf4bd85.diff" +wget "https://review.coreboot.org/changes/40490/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./bf4bd85.diff" +### +### https://review.coreboot.org/c/coreboot/+/40488 +### vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles +### +rm -f "./3b9288e.diff" +wget "https://review.coreboot.org/changes/40488/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./3b9288e.diff" +### +### https://review.coreboot.org/c/coreboot/+/40489 +### vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile +### +rm -f "./413db53.diff" +wget "https://review.coreboot.org/changes/40489/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./413db53.diff" +### diff --git a/sha256sums_xmp_correct.txt b/sha256sums_xmp_correct.txt new file mode 100644 index 0000000..e3ccb04 --- /dev/null +++ b/sha256sums_xmp_correct.txt @@ -0,0 +1,5 @@ +0b19e790c27cc4344f5427e2af62b3d8f5c729c49a528709689e4c1536e55daf ./b8b7fb7.diff +0f5816d40a56e5fe3201e539c2f6cae51a03ae606085731f3c70eb7f2a007bd5 ./a81f3eb.diff +6749bbe5a8a33b0a32d214e32ffba4b6d7df740c73fd674c344653041e5103aa ./bf4bd85.diff +4579e9a7f3454e4909789b56d2fd6422129e31185a363cf6cd13485907b82b1d ./3b9288e.diff +d5161276160d1cf4d77a5252cb7f9855d2ff5de00dedea28790627d9a144b556 ./413db53.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/40495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcb04871e5d969eee1cfd49d21962ae4bbcc4e5d Gerrit-Change-Number: 40495 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile
by Mike Banon (Code Review) 03 Dec '20

03 Dec '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40489 ) Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile ...................................................................... vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile The ability to set up a custom memory profile is useful if you don't like the XMP memory profiles (if they exist) of your RAM sticks, or want to try some overclocking. Read SPD data will be overriden by your custom values. Took Crucial BLT8G3D1869DT1TX0 XMP 1 (1866MHz 9-9-9-27) as an example. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I1238ff00ef0efd11ea807794827476c30ac98065 --- M src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 10 files changed, 337 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/40489/1 diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig index 817c4b3..461b04d 100644 --- a/src/vendorcode/amd/agesa/Kconfig +++ b/src/vendorcode/amd/agesa/Kconfig @@ -38,6 +38,119 @@ help XMP 2 memory profile. Check that it exists on ALL of your RAM sticks! +config CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM + bool "CUSTOM" + help + Custom memory profile. Use the XMP SPD values as the base, if available. + +if CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM + +config CUSTOM_SPD_DIVIDENT + int "[10]: Medium Timebase (MTB) Dividend" + default 1 + range 1 255 + +config CUSTOM_SPD_DIVISOR + int "[11]: Medium Timebase (MTB) Divisor" + default 14 + range 1 255 + +config CUSTOM_SPD_TCK + int "[12]: SDRAM Minimum Cycle Time, tCK" + default 15 + range 1 255 + +config CUSTOM_SPD_CASLO + int "[14]: CAS Latencies Supported, Lower Byte" + default 124 + range 0 255 + +config CUSTOM_SPD_CASHI + int "[15]: CAS Latencies Supported, Higher Byte" + default 0 + range 0 255 + +config CUSTOM_SPD_TAA + int "[16]: Min CAS Latency Time, tAA" + default 132 + range 1 255 + +config CUSTOM_SPD_TWR + int "[17]: Min Write Recovery Time, tWR" + default 210 + range 1 255 + +config CUSTOM_SPD_TRCD + int "[18]: Min RAS# to CAS# Delay Time, tRCD" + default 132 + range 1 255 + +config CUSTOM_SPD_TRRD + int "[19]: Min Row Active to Row Active Delay Time, tRRD" + default 84 + range 1 255 + +config CUSTOM_SPD_TRP + int "[20]: Min Row Precharge Delay Time, tRP" + default 132 + range 1 255 + +config CUSTOM_SPD_UPPER_TRC + int "[21][7:4]: Min Active to Active/Refresh Delay, UPPER tRC" + default 2 + range 0 16 + +config CUSTOM_SPD_UPPER_TRAS + int "[21][3:0]: Min Active to Precharge Delay Time, UPPER tRAS" + default 1 + range 0 16 + +config CUSTOM_SPD_TRAS + int "[22]: Min Active to Precharge Delay Time, LOWER tRAS" + default 138 + range 1 255 + +config CUSTOM_SPD_TRC + int "[23]: Min Active to Active/Refresh Delay, LOWER tRC" + default 181 + range 1 255 + +if CPU_AMD_AGESA_FAMILY16_KB + +config CUSTOM_SPD_TRFC_LO + int "[24]: Min Refresh Recovery Delay Time, LOWER tRFC" + default 56 + range 1 255 + +config CUSTOM_SPD_TRFC_HI + int "[25]: Min Refresh Recovery Delay Time, UPPER tRFC" + default 14 + range 0 255 + +endif + +config CUSTOM_SPD_TWTR + int "[26]: Min Internal Write to Read Command Delay, tWTR" + default 105 + range 1 255 + +config CUSTOM_SPD_TRTP + int "[27]: Min Internal Read to Precharge Command Delay, tRTP" + default 105 + range 1 255 + +config CUSTOM_SPD_UPPER_TFAW + int "[28][3:0]: Min Four Activate Window Delay, UPPER tFAW" + default 1 + range 0 16 + +config CUSTOM_SPD_TFAW + int "[29]: Min Four Activate Window Delay Time, tFAW" + default 164 + range 1 255 + +endif + endchoice endif diff --git a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h index 86fe800..e38e675 100644 --- a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h @@ -798,6 +798,11 @@ #define CFG_DQS_TRAINING_CONTROL TRUE #endif +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) + #undef BLDCFG_IGNORE_SPD_CHECKSUM + #define BLDCFG_IGNORE_SPD_CHECKSUM TRUE +#endif + #ifdef BLDCFG_IGNORE_SPD_CHECKSUM #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM #else diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c index 392b7fc..cf3942b 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c @@ -64,6 +64,7 @@ #include "mm.h" #include "mn.h" #include "mt.h" +#include "mtspd3.h" #include "mu.h" #include "heapManager.h" #include "Filecode.h" @@ -101,6 +102,16 @@ IN OUT MEM_DATA_STRUCT *MemPtr ); +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ); + +#endif + /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * @@ -293,6 +304,60 @@ return Retval; } +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function modifies a SPD buffer with the custom SPD values set up in coreboot's config. + * + * @param[in,out] *Buffer - Pointer to the UINT8 + * + */ + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ) +{ + UINT16 Offset; + // + // Modify a SPD buffer. + // + Buffer[SPD_DIVIDENT] = CONFIG_CUSTOM_SPD_DIVIDENT; + Buffer[SPD_DIVISOR] = CONFIG_CUSTOM_SPD_DIVISOR; + Buffer[SPD_TCK] = CONFIG_CUSTOM_SPD_TCK; + Buffer[SPD_CASLO] = CONFIG_CUSTOM_SPD_CASLO; + Buffer[SPD_CASHI] = CONFIG_CUSTOM_SPD_CASHI; + Buffer[SPD_TAA] = CONFIG_CUSTOM_SPD_TAA; + Buffer[SPD_TWR] = CONFIG_CUSTOM_SPD_TWR; + Buffer[SPD_TRCD] = CONFIG_CUSTOM_SPD_TRCD; + Buffer[SPD_TRRD] = CONFIG_CUSTOM_SPD_TRRD; + Buffer[SPD_TRP] = CONFIG_CUSTOM_SPD_TRP; + // + // SPD_UPPER_TRC and SPD_UPPER_TRAS are the same index but different bits: + // SPD_UPPER_TRC - [7:4], SPD_UPPER_TRAS - [3:0]. + // + Buffer[SPD_UPPER_TRAS] = (CONFIG_CUSTOM_SPD_UPPER_TRC << 4) + CONFIG_CUSTOM_SPD_UPPER_TRAS; + Buffer[SPD_TRAS] = CONFIG_CUSTOM_SPD_TRAS; + Buffer[SPD_TRC] = CONFIG_CUSTOM_SPD_TRC; + Buffer[SPD_TWTR] = CONFIG_CUSTOM_SPD_TWTR; + Buffer[SPD_TRTP] = CONFIG_CUSTOM_SPD_TRTP; + Buffer[SPD_UPPER_TFAW] = CONFIG_CUSTOM_SPD_UPPER_TFAW; + Buffer[SPD_TFAW] = CONFIG_CUSTOM_SPD_TFAW; + // + // Print a SPD buffer. + // + printk(BIOS_SPEW, "***** SPD BUFFER *****\n"); + for (Offset = 0; Offset < 256; Offset++) { + printk(BIOS_SPEW, "Buffer[%d] = 0x%02X\n", Offset, Buffer[Offset]); + } + printk(BIOS_SPEW, "**********************\n"); +} + +#endif /* -----------------------------------------------------------------------------*/ /** @@ -369,6 +434,9 @@ if (AgesaStatus == AGESA_SUCCESS) { DimmSPDPtr->DimmPresent = TRUE; IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer); + #if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + AgesaCustomMemoryProfileSPD(SpdParam.Buffer); + #endif } else { DimmSPDPtr->DimmPresent = FALSE; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h index c7f490d..2797f80 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,7 +95,7 @@ #define SPD_FTB 9 -#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) || CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 diff --git a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h index 70c2135..82ebab7 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h @@ -2027,6 +2027,11 @@ #define CFG_DQS_TRAINING_CONTROL TRUE #endif +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) + #undef BLDCFG_IGNORE_SPD_CHECKSUM + #define BLDCFG_IGNORE_SPD_CHECKSUM TRUE +#endif + #ifdef BLDCFG_IGNORE_SPD_CHECKSUM #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM #else diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c index f2e5848..1030d7a 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c @@ -62,6 +62,7 @@ #include "mm.h" #include "mn.h" #include "mt.h" +#include "mtspd3.h" #include "mu.h" #include "heapManager.h" #include "Filecode.h" @@ -99,6 +100,16 @@ IN OUT MEM_DATA_STRUCT *MemPtr ); +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ); + +#endif + /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * @@ -302,6 +313,60 @@ return Retval; } +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function modifies a SPD buffer with the custom SPD values set up in coreboot's config. + * + * @param[in,out] *Buffer - Pointer to the UINT8 + * + */ + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ) +{ + UINT16 Offset; + // + // Modify a SPD buffer. + // + Buffer[SPD_DIVIDENT] = CONFIG_CUSTOM_SPD_DIVIDENT; + Buffer[SPD_DIVISOR] = CONFIG_CUSTOM_SPD_DIVISOR; + Buffer[SPD_TCK] = CONFIG_CUSTOM_SPD_TCK; + Buffer[SPD_CASLO] = CONFIG_CUSTOM_SPD_CASLO; + Buffer[SPD_CASHI] = CONFIG_CUSTOM_SPD_CASHI; + Buffer[SPD_TAA] = CONFIG_CUSTOM_SPD_TAA; + Buffer[SPD_TWR] = CONFIG_CUSTOM_SPD_TWR; + Buffer[SPD_TRCD] = CONFIG_CUSTOM_SPD_TRCD; + Buffer[SPD_TRRD] = CONFIG_CUSTOM_SPD_TRRD; + Buffer[SPD_TRP] = CONFIG_CUSTOM_SPD_TRP; + // + // SPD_UPPER_TRC and SPD_UPPER_TRAS are the same index but different bits: + // SPD_UPPER_TRC - [7:4], SPD_UPPER_TRAS - [3:0]. + // + Buffer[SPD_UPPER_TRAS] = (CONFIG_CUSTOM_SPD_UPPER_TRC << 4) + CONFIG_CUSTOM_SPD_UPPER_TRAS; + Buffer[SPD_TRAS] = CONFIG_CUSTOM_SPD_TRAS; + Buffer[SPD_TRC] = CONFIG_CUSTOM_SPD_TRC; + Buffer[SPD_TWTR] = CONFIG_CUSTOM_SPD_TWTR; + Buffer[SPD_TRTP] = CONFIG_CUSTOM_SPD_TRTP; + Buffer[SPD_UPPER_TFAW] = CONFIG_CUSTOM_SPD_UPPER_TFAW; + Buffer[SPD_TFAW] = CONFIG_CUSTOM_SPD_TFAW; + // + // Print a SPD buffer. + // + printk(BIOS_SPEW, "***** SPD BUFFER *****\n"); + for (Offset = 0; Offset < 256; Offset++) { + printk(BIOS_SPEW, "Buffer[%d] = 0x%02X\n", Offset, Buffer[Offset]); + } + printk(BIOS_SPEW, "**********************\n"); +} + +#endif /* -----------------------------------------------------------------------------*/ /** @@ -378,6 +443,9 @@ if (AgesaStatus == AGESA_SUCCESS) { DimmSPDPtr->DimmPresent = TRUE; IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer); + #if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + AgesaCustomMemoryProfileSPD(SpdParam.Buffer); + #endif } else { DimmSPDPtr->DimmPresent = FALSE; } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h index bbe5c12..ede7067 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h @@ -94,7 +94,7 @@ #define SPD_FTB 9 -#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) || CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 diff --git a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h index 90c4e3f..4349e4e 100644 --- a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h @@ -996,6 +996,11 @@ #define CFG_DQS_TRAINING_CONTROL TRUE #endif +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) + #undef BLDCFG_IGNORE_SPD_CHECKSUM + #define BLDCFG_IGNORE_SPD_CHECKSUM TRUE +#endif + #ifdef BLDCFG_IGNORE_SPD_CHECKSUM #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM #else diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c index d497aec..dfc1e35 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c @@ -62,6 +62,7 @@ #include "mm.h" #include "mn.h" #include "mt.h" +#include "mtspd3.h" #include "mu.h" #include "heapManager.h" #include "Filecode.h" @@ -99,6 +100,16 @@ IN OUT MEM_DATA_STRUCT *MemPtr ); +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ); + +#endif + /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * @@ -314,6 +325,62 @@ return Retval; } +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function modifies a SPD buffer with the custom SPD values set up in coreboot's config. + * + * @param[in,out] *Buffer - Pointer to the UINT8 + * + */ + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ) +{ + UINT16 Offset; + // + // Modify a SPD buffer. + // + Buffer[SPD_DIVIDENT] = CONFIG_CUSTOM_SPD_DIVIDENT; + Buffer[SPD_DIVISOR] = CONFIG_CUSTOM_SPD_DIVISOR; + Buffer[SPD_TCK] = CONFIG_CUSTOM_SPD_TCK; + Buffer[SPD_CASLO] = CONFIG_CUSTOM_SPD_CASLO; + Buffer[SPD_CASHI] = CONFIG_CUSTOM_SPD_CASHI; + Buffer[SPD_TAA] = CONFIG_CUSTOM_SPD_TAA; + Buffer[SPD_TWR] = CONFIG_CUSTOM_SPD_TWR; + Buffer[SPD_TRCD] = CONFIG_CUSTOM_SPD_TRCD; + Buffer[SPD_TRRD] = CONFIG_CUSTOM_SPD_TRRD; + Buffer[SPD_TRP] = CONFIG_CUSTOM_SPD_TRP; + // + // SPD_UPPER_TRC and SPD_UPPER_TRAS are the same index but different bits: + // SPD_UPPER_TRC - [7:4], SPD_UPPER_TRAS - [3:0]. + // + Buffer[SPD_UPPER_TRAS] = (CONFIG_CUSTOM_SPD_UPPER_TRC << 4) + CONFIG_CUSTOM_SPD_UPPER_TRAS; + Buffer[SPD_TRAS] = CONFIG_CUSTOM_SPD_TRAS; + Buffer[SPD_TRC] = CONFIG_CUSTOM_SPD_TRC; + Buffer[SPD_TRFC_LO] = CONFIG_CUSTOM_SPD_TRFC_LO; + Buffer[SPD_TRFC_HI] = CONFIG_CUSTOM_SPD_TRFC_HI; + Buffer[SPD_TWTR] = CONFIG_CUSTOM_SPD_TWTR; + Buffer[SPD_TRTP] = CONFIG_CUSTOM_SPD_TRTP; + Buffer[SPD_UPPER_TFAW] = CONFIG_CUSTOM_SPD_UPPER_TFAW; + Buffer[SPD_TFAW] = CONFIG_CUSTOM_SPD_TFAW; + // + // Print a SPD buffer. + // + printk(BIOS_SPEW, "***** SPD BUFFER *****\n"); + for (Offset = 0; Offset < 256; Offset++) { + printk(BIOS_SPEW, "Buffer[%d] = 0x%02X\n", Offset, Buffer[Offset]); + } + printk(BIOS_SPEW, "**********************\n"); +} + +#endif /* -----------------------------------------------------------------------------*/ /** @@ -390,6 +457,9 @@ if (AgesaStatus == AGESA_SUCCESS) { DimmSPDPtr->DimmPresent = TRUE; IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer); + #if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + AgesaCustomMemoryProfileSPD(SpdParam.Buffer); + #endif } else { DimmSPDPtr->DimmPresent = FALSE; } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h index bc608a5..472add0 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,7 +95,7 @@ #define SPD_FTB 9 -#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) || CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 -- To view, visit https://review.coreboot.org/c/coreboot/+/40489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1238ff00ef0efd11ea807794827476c30ac98065 Gerrit-Change-Number: 40489 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
by Mike Banon (Code Review) 03 Dec '20

03 Dec '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40488 ) Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ...................................................................... vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles XMP memory profiles support which has been tested on f15tn (ASUS A88XM-E) and f16kb (ASUS AM1I-A) with Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf (whole PDFs) Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I584416e3376afdf377a11783e55c5e9ff41e6b0d --- M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 5 files changed, 245 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/40488/1 diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index 3e3a0e9..7f85852 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -42,6 +42,10 @@ endchoice +if CPU_AMD_AGESA_OPENSOURCE +source "src/vendorcode/amd/agesa/Kconfig" +endif + if CPU_AMD_AGESA_BINARY_PI source "src/vendorcode/amd/pi/Kconfig" endif diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig new file mode 100644 index 0000000..817c4b3 --- /dev/null +++ b/src/vendorcode/amd/agesa/Kconfig @@ -0,0 +1,43 @@ +# +# This file is part of the coreboot project. +# +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if CPU_AMD_AGESA_FAMILY14 || CPU_AMD_AGESA_FAMILY15_TN || CPU_AMD_AGESA_FAMILY16_KB + +choice + prompt "DDR3 memory profile" + default CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + help + Choose the DDR3 memory profile to use for your RAM sticks, i.e. XMP 1. + XMP support is experimental, and your PC will fail booting if you choose + a profile which does not exist on ANY of your RAM sticks! If in doubt, + check their SPD Data using a coreboot's great fork of memtest86+ 5.01. + +config CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + bool "JEDEC" + help + JEDEC memory profile, standard and stable. Is guaranteed to be working. + +config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 + bool "XMP 1" + help + XMP 1 memory profile. Check that it exists on ALL of your RAM sticks! + +config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 + bool "XMP 2" + help + XMP 2 memory profile. Check that it exists on ALL of your RAM sticks! + +endchoice + +endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h index 3b37429..c7f490d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,6 +95,8 @@ #define SPD_FTB 9 +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 @@ -103,18 +105,70 @@ #define SPD_CASHI 15 #define SPD_TAA 16 -#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 #define SPD_TWR 17 +#define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 +#define SPD_UPPER_TRC 21 /* bits 7:4 */ +#define SPD_UPPER_TRAS 21 /* bits 3:0 */ +#define SPD_TRAS 22 +#define SPD_TRC 23 #define SPD_TWTR 26 #define SPD_TRTP 27 -#define SPD_TRC 23 -#define SPD_UPPER_TRC 21 /* bit 7:4 */ -#define SPD_UPPER_TRAS 21 /* bit 3:0 */ +#define SPD_UPPER_TFAW 28 /* bits 3:0 */ #define SPD_TFAW 29 -#define SPD_UPPER_TFAW 28 /* bit 3:0 */ + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1) + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bits 7:4 */ +#define SPD_UPPER_TRAS 194 /* bits 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bits 3:0 */ +#define SPD_TFAW 204 + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2) + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bits 7:4 */ +#define SPD_UPPER_TRAS 229 /* bits 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bits 3:0 */ +#define SPD_TFAW 239 + +#endif #define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h index ab46e4a..bbe5c12 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h @@ -94,6 +94,8 @@ #define SPD_FTB 9 +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 @@ -102,18 +104,70 @@ #define SPD_CASHI 15 #define SPD_TAA 16 -#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 #define SPD_TWR 17 +#define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 +#define SPD_UPPER_TRC 21 /* bits 7:4 */ +#define SPD_UPPER_TRAS 21 /* bits 3:0 */ +#define SPD_TRAS 22 +#define SPD_TRC 23 #define SPD_TWTR 26 #define SPD_TRTP 27 -#define SPD_TRC 23 -#define SPD_UPPER_TRC 21 /* bit 7:4 */ -#define SPD_UPPER_TRAS 21 /* bit 3:0 */ +#define SPD_UPPER_TFAW 28 /* bits 3:0 */ #define SPD_TFAW 29 -#define SPD_UPPER_TFAW 28 /* bit 3:0 */ + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1) + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bits 7:4 */ +#define SPD_UPPER_TRAS 194 /* bits 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bits 3:0 */ +#define SPD_TFAW 204 + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2) + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bits 7:4 */ +#define SPD_UPPER_TRAS 229 /* bits 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bits 3:0 */ +#define SPD_TFAW 239 + +#endif #define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h index bf13c7f..bc608a5 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,6 +95,8 @@ #define SPD_FTB 9 +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 @@ -103,18 +105,82 @@ #define SPD_CASHI 15 #define SPD_TAA 16 -#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 #define SPD_TWR 17 +#define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 +#define SPD_UPPER_TRC 21 /* bits 7:4 */ +#define SPD_UPPER_TRAS 21 /* bits 3:0 */ +#define SPD_TRAS 22 +#define SPD_TRC 23 + +#define SPD_TRFC_LO 24 +#define SPD_TRFC_HI 25 + #define SPD_TWTR 26 #define SPD_TRTP 27 -#define SPD_TRC 23 -#define SPD_UPPER_TRC 21 /* bit 7:4 */ -#define SPD_UPPER_TRAS 21 /* bit 3:0 */ +#define SPD_UPPER_TFAW 28 /* bits 3:0 */ #define SPD_TFAW 29 -#define SPD_UPPER_TFAW 28 /* bit 3:0 */ + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1) + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bits 7:4 */ +#define SPD_UPPER_TRAS 194 /* bits 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 + +#define SPD_TRFC_LO 199 +#define SPD_TRFC_HI 200 + +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bits 3:0 */ +#define SPD_TFAW 204 + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2) + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bits 7:4 */ +#define SPD_UPPER_TRAS 229 /* bits 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 + +#define SPD_TRFC_LO 234 +#define SPD_TRFC_HI 235 + +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bits 3:0 */ +#define SPD_TFAW 239 + +#endif #define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 @@ -122,9 +188,6 @@ #define SPD_TRP_FTB 37 #define SPD_TRC_FTB 38 -#define SPD_TRFC_LO 24 -#define SPD_TRFC_HI 25 - /*----------------------------- * Jedec DDR II related equates *----------------------------- -- To view, visit https://review.coreboot.org/c/coreboot/+/40488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I584416e3376afdf377a11783e55c5e9ff41e6b0d Gerrit-Change-Number: 40488 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

6 14

Change in coreboot[master]: [WIP] soc/amd/picasso: add FSP binary location
by Felix Held (Code Review) 03 Dec '20

03 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42472 ) Change subject: [WIP] soc/amd/picasso: add FSP binary location ...................................................................... [WIP] soc/amd/picasso: add FSP binary location Since the blobs haven't landed yet, it is expected that this breaks the Jenkins build. Change-Id: Ib2241cc90c7113e0c3de4409e08b9ae1f4c2f51e Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/Kconfig 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/42472/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index dd5731d..bf809f8 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -60,6 +60,20 @@ string default "src/soc/amd/picasso/memlayout.ld" +config FSP_M_FILE + string "FSP-M (memory init) binary path and filename" + depends on ADD_FSP_BINARIES + default "3rdparty/amd_blobs/picasso/PICASSO_M.fd" + help + The path and filename of the FSP-M binary for this platform. + +config FSP_S_FILE + string "FSP-S (silicon init) binary path and filename" + depends on ADD_FSP_BINARIES + default "3rdparty/amd_blobs/picasso/PICASSO_S.fd" + help + The path and filename of the FSP-S binary for this platform. + config EARLY_RESERVED_DRAM_BASE hex default 0x2000000 -- To view, visit https://review.coreboot.org/c/coreboot/+/42472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2241cc90c7113e0c3de4409e08b9ae1f4c2f51e Gerrit-Change-Number: 42472 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/intel/elkhartlake: Update Kconfig
by Lean Sheng Tan (Code Review) 02 Dec '20

02 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45078 ) Change subject: soc/intel/elkhartlake: Update Kconfig ...................................................................... soc/intel/elkhartlake: Update Kconfig Update Kconfig: 1. use FSP2.1 instead of 2.2 2. remove HECI_DISABLE_USING_SMM config 3. update CAR related stack & ram size 4. update FSP heap size 5. set IED region size = 0 as it is not used 6. update SMM TSEG size 7. update RP & I2c max device #s 8. update UART base address Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I6a44d357d71be706f402a6b2a4f2d4e7c0eeb4a9 --- M src/soc/intel/elkhartlake/Kconfig 1 file changed, 11 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/45078/1 diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 166bda0..b5462ff 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -32,7 +32,7 @@ select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED - select PLATFORM_USES_FSP2_2 + select PLATFORM_USES_FSP2_1 select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK @@ -61,29 +61,27 @@ select UDELAY_TSC select UDK_202005_BINDING select DISPLAY_FSP_VERSION_INFO - select HECI_DISABLE_USING_SMM config DCACHE_RAM_BASE default 0xfef00000 config DCACHE_RAM_SIZE - default 0x80000 + default 0xc0000 help The size of the cache-as-ram region required during bootblock and/or romstage. config DCACHE_BSP_STACK_SIZE hex - default 0x30400 + default 0x30000 help The amount of anticipated stack usage in CAR by bootblock and - other stages. In the case of FSP_USES_CB_STACK default value - will be sum of FSP-M stack requirement(192 KiB) and CB romstage - stack requirement(~1KiB). + other stages. In the case of FSP_USES_CB_STACK default value will be + sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB). config FSP_TEMP_RAM_SIZE hex - default 0x20000 + default 0x40000 help The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know @@ -95,7 +93,7 @@ config IED_REGION_SIZE hex - default 0x400000 + default 0x0 config HEAP_SIZE hex @@ -103,7 +101,7 @@ config MAX_ROOT_PORTS int - default 8 + default 7 config MAX_PCIE_CLOCKS int @@ -111,7 +109,7 @@ config SMM_TSEG_SIZE hex - default 0x800000 + default 0x1000000 config SMM_RESERVED_SIZE hex @@ -145,7 +143,7 @@ config SOC_INTEL_I2C_DEV_MAX int - default 6 + default 8 config SOC_INTEL_UART_DEV_MAX int @@ -153,7 +151,7 @@ config CONSOLE_UART_BASE_ADDRESS hex - default 0xfe032000 + default 0xfe042000 depends on INTEL_LPSS_UART_FOR_CONSOLE # Clock divider parameters for 115200 baud rate -- To view, visit https://review.coreboot.org/c/coreboot/+/45078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a44d357d71be706f402a6b2a4f2d4e7c0eeb4a9 Gerrit-Change-Number: 45078 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: soc/intel/skylake: Map VBIOS IDs
by Paul Menzel (Code Review) 02 Dec '20

02 Dec '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43853 ) Change subject: soc/intel/skylake: Map VBIOS IDs ...................................................................... soc/intel/skylake: Map VBIOS IDs The extracted VBIOS Option ROM ships the same ID for several generations, not matching the ID on the hardware resulting in a mismatch, and coreboot does not run the Option ROM. PCI ROM image, vendor ID 8086, device ID 0406, ID mismatch: vendor ID 8086, device ID 5916 Add the appropriate mappings. TEST=coreboot runs the ROM on the TUXEDO Book BU1406. Change-Id: Ia167d91627a7ff1b329ea75f150b3ce95c0acccb Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/soc/intel/skylake/graphics.c 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/43853/1 diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index 4ecf67a..f95ca6c 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -3,11 +3,13 @@ #include <commonlib/helpers.h> #include <console/console.h> #include <device/mmio.h> +#include <device/pci_rom.h> #include <device/resource.h> #include <drivers/intel/gma/i915.h> #include <drivers/intel/gma/i915_reg.h> #include <intelblocks/graphics.h> #include <soc/ramstage.h> +#include <soc/systemagent.h> #include <types.h> void graphics_soc_init(struct device *dev) @@ -76,3 +78,21 @@ struct soc_intel_skylake_config *chip = device->chip_info; return &chip->gfx; } + +/* + * Some VGA option roms are used for several chipsets but they only have one PCI ID in their + * header. If we encounter such an option rom, we need to do the mapping ourselves. + */ +u32 map_oprom_vendev(u32 vendev) +{ + u32 new_vendev = vendev; + + switch (vendev) { + case 0x80865916: /* PCI_DEVICE_ID_INTEL_KBL_GT2_SULTM */ + case 0x80865917: /* PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR */ + new_vendev = SA_IGD_OPROM_VENDEV; + break; + } + + return new_vendev; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/43853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia167d91627a7ff1b329ea75f150b3ce95c0acccb Gerrit-Change-Number: 43853 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2020