coreboot-gerrit September 2020

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Change in coreboot[master]: [NOTFORMERGE]: drivers/pc80/tpm: Probe for tpm multiple times
by Patrick Rudolph (Code Review) 14 Dec '20

14 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42510 ) Change subject: [NOTFORMERGE]: drivers/pc80/tpm: Probe for tpm multiple times ...................................................................... [NOTFORMERGE]: drivers/pc80/tpm: Probe for tpm multiple times Change-Id: Icdd675c0978173755d9ee18c20d8c314c1537a7a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/pc80/tpm/tis.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/42510/1 diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 185df34..ef556fe 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -393,7 +393,11 @@ if (vendor_dev_id) return 0; /* Already probed. */ - didvid = tpm_read_did_vid(0); + for (i = 0; i < 10000; i++) { + didvid = tpm_read_did_vid(0); + if (didvid && didvid != 0xffffffff) + break; + } if (!didvid || (didvid == 0xffffffff)) { printf("%s: No TPM device found\n", __FUNCTION__); return TPM_DRIVER_ERR; -- To view, visit https://review.coreboot.org/c/coreboot/+/42510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdd675c0978173755d9ee18c20d8c314c1537a7a Gerrit-Change-Number: 42510 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/amd/common: Refactor ACPIMMIO posted writes
by Kyösti Mälkki (Code Review) 13 Dec '20

13 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42825 ) Change subject: soc/amd/common: Refactor ACPIMMIO posted writes ...................................................................... soc/amd/common: Refactor ACPIMMIO posted writes Change-Id: Ic1a5c17c789dd79fea8f348d1a9d32d4301ced88 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/picasso/i2c.c M src/soc/amd/stoneyridge/i2c.c 3 files changed, 8 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/42825/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 2775b52..8546da9 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -369,12 +369,6 @@ write32(gpio_ctrl_ptr(gpio_num), value); } -static inline void gpio_write32_rb(uint8_t gpio_num, uint32_t value) -{ - write32(gpio_ctrl_ptr(gpio_num), value); - read32(gpio_ctrl_ptr(gpio_num)); -} - /* GPIO bank 0 */ static inline uint8_t gpio0_read8(uint8_t reg) { diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 881278f..61a4f8a 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -161,9 +161,11 @@ static void restore_i2c_pin_registers(uint8_t gpio, struct soc_amd_i2c_save *save_table) { + /* Write and flush posted writes. */ iomux_write8(gpio, save_table->mux_value); - iomux_read8(gpio); - gpio_write32_rb(gpio, save_table->control_value); + iomux_read8(0); + gpio_write32(gpio, save_table->control_value); + gpio_read32(0); } /* Slaves to be reset are controlled by devicetree register i2c_scl_reset */ diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index 0327028..cd42cda 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -144,9 +144,11 @@ static void restore_i2c_pin_registers(uint8_t gpio, struct soc_amd_i2c_save *save_table) { + /* Write and flush posted writes. */ iomux_write8(gpio, save_table->mux_value); - iomux_read8(gpio); - gpio_write32_rb(gpio, save_table->control_value); + iomux_read8(0); + gpio_write32(gpio, save_table->control_value); + gpio_read32(0); } /* Slaves to be reset are controlled by devicetree register i2c_scl_reset */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42825 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1a5c17c789dd79fea8f348d1a9d32d4301ced88 Gerrit-Change-Number: 42825 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: [TESTONLY] Revert "src/amd/common: Exclude biosram from psp_verstage"
by Kyösti Mälkki (Code Review) 13 Dec '20

13 Dec '20

Hello build bot (Jenkins), Raul Rangel, Martin Roth, Patrick Georgi, Julius Werner, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43067 to review the following change. Change subject: [TESTONLY] Revert "src/amd/common: Exclude biosram from psp_verstage" ...................................................................... [TESTONLY] Revert "src/amd/common: Exclude biosram from psp_verstage" This reverts commit f38af663d2c2c854859715803da249e6c24032db. I just want to see where the build fails. Change-Id: I0a995301404b67224be6addbeebf984c4b5c47d5 --- M src/soc/amd/common/block/acpimmio/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/43067/1 diff --git a/src/soc/amd/common/block/acpimmio/Makefile.inc b/src/soc/amd/common/block/acpimmio/Makefile.inc index 553d9e2..69253b9 100644 --- a/src/soc/amd/common/block/acpimmio/Makefile.inc +++ b/src/soc/amd/common/block/acpimmio/Makefile.inc @@ -6,7 +6,7 @@ smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c -verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c +verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c -- To view, visit https://review.coreboot.org/c/coreboot/+/43067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a995301404b67224be6addbeebf984c4b5c47d5 Gerrit-Change-Number: 43067 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: cbfs: Introduce cbfs_ro_map() and cbfs_ro_load()
by Julius Werner (Code Review) 13 Dec '20

13 Dec '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39306 to review the following change. Change subject: cbfs: Introduce cbfs_ro_map() and cbfs_ro_load() ...................................................................... cbfs: Introduce cbfs_ro_map() and cbfs_ro_load() This patch introduces two new CBFS API functions which are equivalent to cbfs_map() and cbfs_load(), respectively, with the difference that they always operate on the read-only CBFS region ("COREBOOT" FMAP section). Use it to replace some of the simple cases that needed to use cbfs_locate_file_in_region(). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I9c55b022b6502a333a9805ab0e4891dd7b97ef7f --- M src/drivers/pc80/rtc/option.c M src/include/cbfs.h M src/lib/cbfs.c M src/northbridge/intel/haswell/raminit.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/quark/romstage/romstage.c 6 files changed, 60 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/39306/1 diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c index 4789b15..1f9abb5 100644 --- a/src/drivers/pc80/rtc/option.c +++ b/src/drivers/pc80/rtc/option.c @@ -60,36 +60,28 @@ return CB_SUCCESS; } -static enum cb_err locate_cmos_layout(struct region_device *rdev) +static struct cmos_option_table *get_cmos_layout(struct region_device *rdev) { - uint32_t cbfs_type = CBFS_COMPONENT_CMOS_LAYOUT; - MAYBE_STATIC_BSS struct cbfsf fh = {}; + MAYBE_STATIC_BSS struct cmos_option_table ct = NULL; /* * In case VBOOT is enabled and this function is called from SMM, * we have multiple CMOS layout files and to locate them we'd need to * include VBOOT into SMM... * - * Support only one CMOS layout in the 'COREBOOT' region for now. + * Support only one CMOS layout in the RO CBFS for now. */ - if (!region_device_sz(&(fh.data))) { - if (cbfs_locate_file_in_region(&fh, "COREBOOT", "cmos_layout.bin", - &cbfs_type)) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " - "Options are disabled\n"); - return CB_CMOS_LAYOUT_NOT_FOUND; - } - } - - cbfs_file_data(rdev, &fh); - - return CB_SUCCESS; + if (!ct) + ct = cbfs_ro_map("cmos_layout.bin", NULL); + if (!ct) + printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " + "Options are disabled\n"); + return ct; } enum cb_err cmos_get_option(void *dest, const char *name) { struct cmos_option_table *ct; - struct region_device rdev; struct cmos_entries *ce; size_t namelen; int found = 0; @@ -97,16 +89,9 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { + ct = get_cmos_layout(); + if (!ct) return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - return CB_CMOS_LAYOUT_NOT_FOUND; - } /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -119,19 +104,15 @@ } if (!found) { printk(BIOS_DEBUG, "No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); return CB_CMOS_OPTION_NOT_FOUND; } - if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) { - rdev_munmap(&rdev, ct); + if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) return CB_CMOS_CHECKSUM_INVALID; - } - if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); +} + if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } - rdev_munmap(&rdev, ct); +} return CB_SUCCESS; } @@ -179,7 +160,6 @@ enum cb_err cmos_set_option(const char *name, void *value) { struct cmos_option_table *ct; - struct region_device rdev; struct cmos_entries *ce; unsigned long length; size_t namelen; @@ -188,16 +168,9 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { + ct = get_cmos_layout(); + if (!ct) return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - return CB_CMOS_LAYOUT_NOT_FOUND; - } /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -210,7 +183,6 @@ } if (!found) { printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); return CB_CMOS_OPTION_NOT_FOUND; } @@ -219,18 +191,13 @@ length = MAX(strlen((const char *)value) * 8, ce->length - 8); /* make sure the string is null terminated */ if (set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0}) - != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } } - if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } - rdev_munmap(&rdev, ct); return CB_SUCCESS; } diff --git a/src/include/cbfs.h b/src/include/cbfs.h index cc61b16..8cd5713 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -36,9 +36,12 @@ NOTE: Since this may return a direct pointer to memory-mapped hardware, compressed files are NOT transparently decompressed (unlike cbfs_load()). */ void *cbfs_map(const char *name, size_t *size); -/* Removes a mapping previously allocated with cbfs_map(). Should try to unmap - mappings in strict LIFO order where possible, since mapping backends often - don't support more complicated cases. */ +/* Like cbfs_map(), except that it will always read from the read-only CBFS + ("COREBOOT" FMAP region), even when CONFIG_VBOOT is enabled. */ +void *cbfs_ro_map(const char *name, size_t *size); +/* Removes a previously allocated CBFS mapping. Should try to unmap mappings in + strict LIFO order where possible, since mapping backends often don't support + more complicated cases. */ int cbfs_unmap(void *mapping); /* Locate file in a specific region of fmap. Return 0 on success. < 0 on error*/ int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, @@ -47,6 +50,9 @@ success or 0 on error. File will get decompressed as necessary. Same decompression requirements as cbfs_load_and_decompress(). */ size_t cbfs_load(const char *name, void *buf, size_t buf_size); +/* Like cbfs_load(), except that it will always read from the read-only CBFS + ("COREBOOT" FMAP region), even when CONFIG_VBOOT is enabled. */ +size_t cbfs_ro_load(const char *name, void *buf, size_t buf_size); /* Load |in_size| bytes from |rdev| at |offset| to the |buffer_size| bytes * large |buffer|, decompressing it according to |compression| in the process. * Returns the decompressed file size, or 0 on error. diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index c3660aa..ba50c34 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -79,9 +79,9 @@ return 0; } -void *cbfs_map(const char *name, size_t *size) +static void *_cbfs_map(const char *name, size_t *size, bool force_ro) { - const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(force_ro); union cbfs_mdata mdata; size_t data_offset; @@ -96,6 +96,16 @@ return rdev_mmap(&cbd->rdev, data_offset, data_size); } +void *cbfs_map(const char *name, size_t *size) +{ + return _cbfs_map(name, size, false); +} + +void *cbfs_ro_map(const char *name, size_t *size) +{ + return _cbfs_map(name, size, true); +} + int cbfs_unmap(void *mapping) { /* This works because munmap() only works on the root rdev and never @@ -215,7 +225,8 @@ return prog_entry(&stage); } -size_t cbfs_load(const char *name, void *buf, size_t buf_size) +static size_t _cbfs_load(const char *name, void *buf, size_t buf_size, + bool force_ro) { const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); union cbfs_mdata mdata; @@ -238,6 +249,16 @@ compression); } +size_t cbfs_load(const char *name, void *buf, size_t buf_size) +{ + return _cbfs_load(name, buf, buf_size, false); +} + +size_t cbfs_ro_load(const char *name, void *buf, size_t buf_size) +{ + return _cbfs_load(name, buf, buf_size, true); +} + size_t cbfs_prog_stage_section(struct prog *pstage, uintptr_t *base) { struct cbfs_stage stage; diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 8267833..00211bd 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -118,8 +118,6 @@ void sdram_initialize(struct pei_data *pei_data) { unsigned long entry; - uint32_t type = CBFS_TYPE_MRC; - struct cbfsf f; printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); @@ -144,12 +142,11 @@ /* * Locate and call UEFI System Agent binary. The binary needs to be at * a fixed offset in the flash and can therefore only reside in the - * COREBOOT fmap region + * COREBOOT fmap region. We don't care about leaking the mapping. */ - if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) + entry = (unsigned long)cbfs_ro_map("mrc.bin", NULL); + if (!entry) die("mrc.bin not found!"); - /* We don't care about leaking the mapping */ - entry = (unsigned long)rdev_mmap_full(&f.data); if (entry) { int rv; asm volatile ( diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 3759c1f..bcf7148 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -43,8 +43,6 @@ struct memory_info *mem_info; pei_wrapper_entry_t entry; int ret; - struct cbfsf f; - uint32_t type = CBFS_TYPE_MRC; broadwell_fill_pei_data(pei_data); @@ -76,15 +74,10 @@ pei_data->saved_data_size = 0; } - /* Determine if mrc.bin is in the cbfs. */ - if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) - die("mrc.bin not found!"); /* We don't care about leaking the mapping */ - entry = (pei_wrapper_entry_t)rdev_mmap_full(&f.data); - if (entry == NULL) { - printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); - return; - } + entry = cbfs_ro_map("mrc.bin", NULL); + if (entry == NULL) + die("mrc.bin not found!"); printk(BIOS_DEBUG, "Starting Memory Reference Code\n"); diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 4ac580e..3e08663 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -63,29 +63,16 @@ void *locate_rmu_file(size_t *rmu_file_len) { - struct cbfsf fh; size_t fsize; void *rmu_data; - uint32_t type; /* Locate the rmu.bin file in the read-only region of the flash */ - type = CBFS_TYPE_RAW; - if (cbfs_locate_file_in_region(&fh, "COREBOOT", "rmu.bin", &type)) + rmu_data = cbfs_ro_map("rmu.bin", &fsize); + if (!rmu_data) return NULL; - /* Get the file size */ - fsize = region_device_sz(&fh.data); if (rmu_file_len != NULL) *rmu_file_len = fsize; - /* Get the data address */ - rmu_data = rdev_mmap(&fh.data, 0, fsize); - - /* Since the SPI flash is directly mapped into memory, we do not need - * the mapping provided by the rdev service. Unmap the file to prevent - * a memory leak. Return/leak the SPI flash address for the rmu.bin - * file data which will be directly accessed by FSP MemoryInit. - */ - rdev_munmap(&fh.data, rmu_data); return rmu_data; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c55b022b6502a333a9805ab0e4891dd7b97ef7f Gerrit-Change-Number: 39306 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: sb/intel/bd82x6x: Only check device ID in `intel_me_finalize_smm`
by Angel Pons (Code Review) 11 Dec '20

11 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45258 ) Change subject: sb/intel/bd82x6x: Only check device ID in `intel_me_finalize_smm` ...................................................................... sb/intel/bd82x6x: Only check device ID in `intel_me_finalize_smm` There's no need to compare the vendor ID. Change-Id: I4368f2615e5ce72430992f1f5581908c90c970f0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/me.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/45258/1 diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index c51cca6..3876b02 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -168,16 +168,16 @@ void intel_me_finalize_smm(void) { - u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); + u16 did = pci_read_config16(PCH_ME_DEV, PCI_DEVICE_ID); switch (did) { - case 0x1c3a8086: + case 0x1c3a: intel_me7_finalize_smm(); break; - case 0x1e3a8086: + case 0x1e3a: intel_me8_finalize_smm(); break; default: - printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); + printk(BIOS_ERR, "No finalize handler for ME %04x.\n", did); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/45258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4368f2615e5ce72430992f1f5581908c90c970f0 Gerrit-Change-Number: 45258 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/volteer/var/voxel: change speaker smart amplifier to ALC1011
by Sheng-Liang Pan (Code Review) 11 Dec '20

11 Dec '20

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43549 ) Change subject: mb/google/volteer/var/voxel: change speaker smart amplifier to ALC1011 ...................................................................... mb/google/volteer/var/voxel: change speaker smart amplifier to ALC1011 voxel change amp to ALC1011 adding ALC1011 amp acpi info into devicetree BUG=b:160550394 BRANCH=None TEST=build and verify ALC1011 can be recognized. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: If3e7b829000a61a27f6a45a2688bb434e57f479a --- M src/mainboard/google/volteer/Kconfig.name M src/mainboard/google/volteer/fw_config.c M src/mainboard/google/volteer/variants/voxel/overridetree.cb 3 files changed, 15 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/43549/1 diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 06bbc58..a3ece12 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -37,6 +37,8 @@ bool "-> Voxel" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU + select CHROMEOS_DSM_CALIB + select DRIVERS_I2C_RT1011 config BOARD_GOOGLE_DELBIN bool "-> Delbin" diff --git a/src/mainboard/google/volteer/fw_config.c b/src/mainboard/google/volteer/fw_config.c index 61e20f4..6cbde24 100644 --- a/src/mainboard/google/volteer/fw_config.c +++ b/src/mainboard/google/volteer/fw_config.c @@ -72,7 +72,8 @@ gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); } if (fw_config_probe(FW_CONFIG(AUDIO, MAX98357_ALC5682I_I2S)) || - fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S))) { + fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S)) || + fw_config_probe(FW_CONFIG(AUDIO, RT1011_ALC5682I_I2S))) { printk(BIOS_INFO, "Configure GPIOs for I2S audio.\n"); gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 2219de0..8838705 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -12,24 +12,23 @@ register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" device i2c 1a on + probe AUDIO RT1011_ALC5682I_I2S end end - chip drivers/i2c/max98373 - register "vmon_slot_no" = "0" - register "imon_slot_no" = "1" + chip drivers/i2c/rt1011 + register "desc" = ""RT1011 Woofer Left Speaker Amp"" register "uid" = "0" - register "desc" = ""Right Speaker Amp"" - register "name" = ""MAXR"" - device i2c 31 on + register "name" = ""RTWL"" + device i2c 38 on + probe AUDIO RT1011_ALC5682I_I2S end end - chip drivers/i2c/max98373 - register "vmon_slot_no" = "2" - register "imon_slot_no" = "3" + chip drivers/i2c/rt1011 + register "desc" = ""RT1011 Woofer Right Speaker Amp"" register "uid" = "1" - register "desc" = ""Left Speaker Amp"" - register "name" = ""MAXL"" - device i2c 32 on + register "name" = ""RTWR"" + device i2c 39 on + probe AUDIO RT1011_ALC5682I_I2S end end end # I2C #0 0xA0E8 -- To view, visit https://review.coreboot.org/c/coreboot/+/43549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3e7b829000a61a27f6a45a2688bb434e57f479a Gerrit-Change-Number: 43549 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: sb/intel/bd82x6x: Make me_common.c a compilation unit
by Angel Pons (Code Review) 11 Dec '20

11 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42019 ) Change subject: sb/intel/bd82x6x: Make me_common.c a compilation unit ...................................................................... sb/intel/bd82x6x: Make me_common.c a compilation unit We need to make most things non-static so that the code builds. Change-Id: I17e561abf2378632f72d0aa9f0057cb1bee23514 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/Makefile.inc M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/me_common.c 5 files changed, 47 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/42019/1 diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 9e34e96..cf9bf50 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -15,6 +15,7 @@ ramstage-y += usb_xhci.c ramstage-y += me.c ramstage-y += me_8.x.c +ramstage-y += me_common.c ramstage-y += smbus.c ramstage-y += ../common/pciehp.c @@ -24,7 +25,7 @@ ramstage-$(CONFIG_ELOG) += elog.c -smm-y += smihandler.c me.c me_8.x.c pch.c +smm-y += smihandler.c me.c me_8.x.c pch.c me_common.c romstage-y += early_smbus.c me_status.c romstage-y += early_rcba.c diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 515f984..d2a3480 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -28,9 +28,6 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif -/* FIXME: For verification purposes only */ -#include "me_common.c" - /* Get ME firmware version */ static int __unused mkhi_get_fw_version(void) { diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 5aaf661..a55a1f2 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -221,6 +221,34 @@ ME_FIRMWARE_UPDATE_BIOS_PATH, } me_bios_path; +/* Defined in me_common.c for both ramstage and smm */ +const char *const me_get_bios_path_string(int path); + +void mei_read_dword_ptr(void *ptr, int offset); +void mei_write_dword_ptr(void *ptr, int offset); + +#ifndef __SIMPLE_DEVICE__ +void pci_read_dword_ptr(struct device *dev, void *ptr, int offset); +#endif + +void read_host_csr(struct mei_csr *csr); +void write_host_csr(struct mei_csr *csr); + +void read_me_csr(struct mei_csr *csr); + +void write_cb(u32 dword); +u32 read_cb(void); + +int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, + void *req_data, void *rsp_data, int rsp_bytes); + +int mkhi_end_of_post(void); +void update_mei_base_address(void); +bool is_mei_base_address_valid(void); +int intel_mei_setup(struct device *dev); +int intel_me_extend_valid(struct device *dev); +void intel_me_hide(struct device *dev); + /* Defined in me_status.c for both romstage and ramstage */ void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index fcf4dd3..1a331e9 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -28,9 +28,6 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif -/* FIXME: For verification purposes only */ -#include "me_common.c" - static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index 790b870..83e7fe6 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -25,7 +25,7 @@ [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -static inline const char *const me_get_bios_path_string(int path) +const char *const me_get_bios_path_string(int path) { return me_bios_path_values[path]; } @@ -70,14 +70,14 @@ * ME/MEI access helpers using memcpy to avoid aliasing. */ -static inline void mei_read_dword_ptr(void *ptr, int offset) +void mei_read_dword_ptr(void *ptr, int offset) { u32 dword = read32(mei_base_address + (offset / sizeof(u32))); memcpy(ptr, &dword, sizeof(dword)); mei_dump(ptr, dword, offset, "READ"); } -static inline void mei_write_dword_ptr(void *ptr, int offset) +void mei_write_dword_ptr(void *ptr, int offset) { u32 dword = 0; memcpy(&dword, ptr, sizeof(dword)); @@ -86,7 +86,7 @@ } #ifndef __SIMPLE_DEVICE__ -static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) +void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -94,28 +94,28 @@ } #endif -static inline void read_host_csr(struct mei_csr *csr) +void read_host_csr(struct mei_csr *csr) { mei_read_dword_ptr(csr, MEI_H_CSR); } -static inline void write_host_csr(struct mei_csr *csr) +void write_host_csr(struct mei_csr *csr) { mei_write_dword_ptr(csr, MEI_H_CSR); } -static inline void read_me_csr(struct mei_csr *csr) +void read_me_csr(struct mei_csr *csr) { mei_read_dword_ptr(csr, MEI_ME_CSR_HA); } -static inline void write_cb(u32 dword) +void write_cb(u32 dword) { write32(mei_base_address + (MEI_H_CB_WW / sizeof(u32)), dword); mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); } -static inline u32 read_cb(void) +u32 read_cb(void) { u32 dword = read32(mei_base_address + (MEI_ME_CB_RW / sizeof(u32))); mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); @@ -310,8 +310,8 @@ return mei_wait_for_me_ready(); } -static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data, void *rsp_data, int rsp_bytes) +int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, + void *req_data, void *rsp_data, int rsp_bytes) { if (mei_send_msg(mei, mkhi, req_data) < 0) return -1; @@ -321,7 +321,7 @@ } /* Send END OF POST message to the ME */ -static int __unused mkhi_end_of_post(void) +int mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -351,12 +351,12 @@ #ifdef __SIMPLE_DEVICE__ -static inline void update_mei_base_address(void) +void update_mei_base_address(void) { mei_base_address = (u32 *)(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); } -static inline bool is_mei_base_address_valid(void) +bool is_mei_base_address_valid(void) { return mei_base_address && mei_base_address != (u32 *)0xfffffff0; } @@ -364,7 +364,7 @@ #else /* Prepare ME for MEI messages */ -static int intel_mei_setup(struct device *dev) +int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -391,7 +391,7 @@ } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(struct device *dev) +int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -438,7 +438,7 @@ } /* Hide the ME virtual PCI devices */ -static void intel_me_hide(struct device *dev) +void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/42019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17e561abf2378632f72d0aa9f0057cb1bee23514 Gerrit-Change-Number: 42019 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: [TEST] mb/google/dedede: change temp thresholds
by Sumeet R Pawnikar (Code Review) 11 Dec '20

11 Dec '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44132 ) Change subject: [TEST] mb/google/dedede: change temp thresholds ...................................................................... [TEST] mb/google/dedede: change temp thresholds Change temp thersholds to avoid system shutdown during stress test. Change-Id: I11a2c7542577a08fbb67224c6024cc26a0cf48de Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/44132/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index d0609ef..d115ef7 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -171,13 +171,13 @@ device pci 02.0 on end # Integrated Graphics Device device pci 04.0 on chip drivers/intel/dptf - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 90, 10000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000)" - register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000)" + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 80, 10000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 60000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 45, 15000)" - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN)" - register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 115, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 100, SHUTDOWN)" + register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 110, SHUTDOWN)" register "controls.power_limits.pl1" = "{ .min_power = 3000, -- To view, visit https://review.coreboot.org/c/coreboot/+/44132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11a2c7542577a08fbb67224c6024cc26a0cf48de Gerrit-Change-Number: 44132 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: [TEST]: drawcia: set PL1 to higher value
by Sumeet R Pawnikar (Code Review) 11 Dec '20

11 Dec '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44803 ) Change subject: [TEST]: drawcia: set PL1 to higher value ...................................................................... [TEST]: drawcia: set PL1 to higher value Set PL1 to higher value Change-Id: Ibc0b2d2cedc68ab367bf0947034e048fbbfc0841 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/44803/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index ee95332..15e09db 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -40,7 +40,7 @@ }" register "power_limits_config" = "{ - .tdp_pl1_override = 6, + .tdp_pl1_override = 8, .tdp_pl2_override = 15, }" @@ -69,12 +69,12 @@ register "controls.power_limits.pl1" = "{ .min_power = 4800, - .max_power = 6000, + .max_power = 8000, .time_window_min = 1 * MSECS_PER_SEC, .time_window_max = 1 * MSECS_PER_SEC, .granularity = 200,}" register "controls.power_limits.pl2" = "{ - .min_power = 6000, + .min_power = 8000, .max_power = 15000, .time_window_min = 1 * MSECS_PER_SEC, .time_window_max = 1 * MSECS_PER_SEC, -- To view, visit https://review.coreboot.org/c/coreboot/+/44803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc0b2d2cedc68ab367bf0947034e048fbbfc0841 Gerrit-Change-Number: 44803 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: [WIP] mb/google/volteer: Use device aliases
by Duncan Laurie (Code Review) 09 Dec '20

09 Dec '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44039 ) Change subject: [WIP] mb/google/volteer: Use device aliases ...................................................................... [WIP] mb/google/volteer: Use device aliases Use the device aliases provided by tigerlake chipset.cb instead of the raw pci device+function. Take advantage of the default states in chipset.cb and only list the devices that are enabled for volteer. Change-Id: I5620004afd7fa4d50389f32dd79148960a2b2662 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/volteer/overridetree.cb 2 files changed, 36 insertions(+), 91 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/44039/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 53bbe5a..80e2041 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -47,7 +47,6 @@ register "HeciEnabled" = "1" # FSP configuration - register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "0" register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 @@ -286,10 +285,8 @@ }" device domain 0 on - #From EDS(575683) - device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y - device pci 02.0 on end # Graphics - device pci 04.0 on + device ref igpu on end + device ref dptf on # Default DPTF Policy for all Volteer boards if not overridden chip drivers/intel/dptf ## Active Policy @@ -379,81 +376,35 @@ device generic 0 on end end end # DPTF 0x9A03 - device pci 05.0 off end # IPU 0x9A19 - device pci 06.0 off end # PEG60 0x9A09 - device pci 07.0 on end # TBT_PCIe0 0x9A23 - device pci 07.1 on end # TBT_PCIe1 0x9A25 - device pci 07.2 off end # TBT_PCIe2 0x9A27 - device pci 07.3 off end # TBT_PCIe3 0x9A29 - device pci 08.0 on end # GNA 0x9A11 - device pci 09.0 off end # NPK 0x9A33 - device pci 0a.0 off end # Crash-log SRAM 0x9A0D - device pci 0d.0 on end # USB xHCI 0x9A13 - device pci 0d.1 off end # USB xDCI (OTG) 0x9A15 - device pci 0d.2 on end # TBT DMA0 0x9A1B - device pci 0d.3 off end # TBT DMA1 0x9A1D - device pci 0e.0 off end # VMD 0x9A0B - - # From PCH EDS(576591) - device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 - device pci 10.6 off end # THC0 0xA0D0 - device pci 10.7 off end # THC1 0xA0D1 - - device pci 12.0 off end # SensorHUB 0xA0FC - device pci 12.6 off end # GSPI2 0x34FB - - device pci 13.0 off end # GSPI3 0xA0FD - - device pci 14.0 on end # USB3.1 xHCI 0xA0ED - device pci 14.1 off end # USB3.1 xDCI 0xA0EE - device pci 14.2 on end # Shared RAM 0xA0EF + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref gna on end + device ref north_xhci on end + device ref tbt_dma0 on end + device ref cnvi_bt on end + device ref south_xhci on end + device ref shared_ram on end chip drivers/intel/wifi register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 + device ref cnvi_wifi on end end - device pci 15.0 on end # I2C #0 0xA0E8 - device pci 15.1 on end # I2C1 0xA0E9 - device pci 15.2 on end # I2C2 0xA0EA - device pci 15.3 on end # I2C3 0xA0EB - - device pci 16.0 on end # HECI1 0xA0E0 - device pci 16.1 off end # HECI2 0xA0E1 - device pci 16.2 off end # CSME 0xA0E2 - device pci 16.3 off end # CSME 0xA0E3 - device pci 16.4 off end # HECI3 0xA0E4 - device pci 16.5 off end # HECI4 0xA0E5 - - device pci 17.0 on end # SATA 0xA0D3 - - device pci 19.0 on end # I2C4 0xA0C5 - device pci 19.1 on end # I2C5 0xA0C6 - device pci 19.2 off end # UART2 0xA0C7 - - device pci 1c.0 on end # RP1 0xA0B8 - device pci 1c.1 off end # RP2 0xA0B9 - device pci 1c.2 off end # RP3 0xA0BA - device pci 1c.3 off end # RP4 0xA0BB - device pci 1c.4 off end # RP5 0xA0BC - device pci 1c.5 off end # WWAN RP6 0xA0BD - device pci 1c.6 on end # RP7 0xA0BE - device pci 1c.7 on end # SD Card RP8 0xA0BF - - device pci 1d.0 on end # RP9 0xA0B0 - device pci 1d.1 off end # RP10 0xA0B1 - device pci 1d.2 on end # RP11 0xA0B2 - device pci 1d.3 off end # RP12 0xA0B3 - - device pci 1e.0 on end # UART0 0xA0A8 - device pci 1e.1 off end # UART1 0xA0A9 - device pci 1e.2 on + device ref heci1 on end + device ref sata on end + device ref pcie_rp1 on end + device ref pcie_rp7 on end + device ref pcie_rp8 on end + device ref pcie_rp9 on end + device ref pcie_rp11 on end + device ref uart0 on end + device ref gspi0 on chip drivers/spi/acpi register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cr50"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" device spi 0 on end end - end # GSPI0 0xA0AA - device pci 1e.3 on + end + device ref gspi1 on chip drivers/spi/acpi register "name" = ""CRFP"" register "hid" = "ACPI_DT_NAMESPACE_HID" @@ -462,18 +413,12 @@ register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)" device spi 0 on end end # FPMCU - end # GSPI1 0xA0AB - device pci 1f.0 on + end + device ref pch_espi on chip ec/google/chromeec device pnp 0c09.0 on end end - end # eSPI 0xA080 - A09F - device pci 1f.1 off end # P2SB 0xA0A0 - device pci 1f.2 hidden end # PMC 0xA0A1 - device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF - device pci 1f.4 off end # SMBus 0xA0A3 - device pci 1f.5 on end # SPI 0xA0A4 - device pci 1f.6 off end # GbE 0x15E1/0x15E2 - device pci 1f.7 off end # TH 0xA0A6 + end + device ref hda on end end end diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index c7350cb..8c95956 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -44,7 +44,7 @@ }, }" device domain 0 on - device pci 15.0 on + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" register "name" = ""RT58"" @@ -81,7 +81,7 @@ end end end - device pci 15.1 on + device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" @@ -124,8 +124,8 @@ register "key.label" = ""pen_eject"" device generic 0 on end end - end # I2C1 0xA0E9 - device pci 15.2 on + end + device ref i2c2 on chip drivers/i2c/sx9310 register "desc" = ""SAR0 Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" @@ -156,8 +156,8 @@ register "reg_sar_ctrl2" = "0x3c" device i2c 28 on end end - end # I2C2 0xA0EA - device pci 19.1 on + end + device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -166,8 +166,8 @@ register "probed" = "1" device i2c 15 on end end - end # I2C5 0xA0C6 - device pci 1f.3 on + end + device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" @@ -197,7 +197,7 @@ end end end - device pci 1f.2 hidden + device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. chip drivers/intel/pmc_mux @@ -230,6 +230,6 @@ end end end - end # PMC + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/44039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5620004afd7fa4d50389f32dd79148960a2b2662 Gerrit-Change-Number: 44039 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020