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Change in coreboot[master]: soc/intel/cannonlake: Add Iccmax and loadlines for CML-S
by Gaggery Tsai (Code Review) 23 Dec '20

23 Dec '20

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38288 ) Change subject: soc/intel/cannonlake: Add Iccmax and loadlines for CML-S ...................................................................... soc/intel/cannonlake: Add Iccmax and loadlines for CML-S This patch adds Iccmax and AC/DC loadlines for CML-S CPUs. The information is from CML EDS volume 1, doc #606599. Change-Id: Id2797a979a8b6a52a34baae66f95c7136ed1dc72 Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/soc/intel/cannonlake/vr_config.c 1 file changed, 92 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38288/1 diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index 7096b62..78f51bc 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -91,37 +91,53 @@ /* * Iccmax table from Doc #337344 Section 7.2 DC Specifications for CFL. * Iccmax table from Doc #338023 Section 7.2 DC Specifications for WHL. + * Iccmax table from Doc #606599 Section 7.2 DC Specifications for CML. * * Platform Segment SA IA GT (GT/GTx) - * --------------------------------------------------------------------- - * CFL-U (28W) GT3 quad 8.5 64 64 - * CFL-U (28W) GT3 dual 8.5 64 64 + * ---------------------------------------------------------------------- + * CFL-U (28W) GT3 quad 8.5 64 64 + * CFL-U (28W) GT3 dual 8.5 64 64 * - * CFL-H (45W) GT2 hex 11.1 128 0 - * CFL-H (45W) GT2 quad 11.1 86 0 + * CFL-H (45W) GT2 hex 11.1 128 0 + * CFL-H (45W) GT2 quad 11.1 86 0 * - * CFL-S (95W) GT2 octa 11.1 193 45 + * CFL-S (95W) GT2 octa 11.1 193 45 * - * CFL-S (95W) GT2 hex 11.1 138 45 - * CFL-S (65W) GT2 hex 11.1 133 45 - * CFL-S (80W) GT2 hex 11.1 133 45 - * CFL-S (35W) GT2 hex 11.1 104 35 + * CFL-S (95W) GT2 hex 11.1 138 45 + * CFL-S (65W) GT2 hex 11.1 133 45 + * CFL-S (80W) GT2 hex 11.1 133 45 + * CFL-S (35W) GT2 hex 11.1 104 35 * - * CFL-S (91W) GT2 quad 11.1 100 45 - * CFL-S (83W) GT2 quad 11.1 100 45 - * CFL-S (71W) GT2 quad 11.1 100 45 - * CFL-S (65W) GT2 quad 11.1 79 45 - * CFL-S (62W) GT2 quad 11.1 79 45 - * CFL-S (35W) GT2 quad 11.1 66 35 + * CFL-S (91W) GT2 quad 11.1 100 45 + * CFL-S (83W) GT2 quad 11.1 100 45 + * CFL-S (71W) GT2 quad 11.1 100 45 + * CFL-S (65W) GT2 quad 11.1 79 45 + * CFL-S (62W) GT2 quad 11.1 79 45 + * CFL-S (35W) GT2 quad 11.1 66 35 * - * CFL-S (58W) GT2 dual 11.1 79 45 - * CFL-S (54W) GT2 dual 11.1 58 45 - * CFL-S (35W) GT2 dual 11.1 40 35 + * CFL-S (58W) GT2 dual 11.1 79 45 + * CFL-S (54W) GT2 dual 11.1 58 45 + * CFL-S (35W) GT2 dual 11.1 40 35 * - * CNL-U (15W) 13 34 0 + * CNL-U (15W) 13 34 0 * - * WHL-U (15W) GT2 quad 6 70 31 - * WHL-U (15W) GT2 dual 6 35 31 + * WHL-U (15W) GT2 quad 6 70 31 + * WHL-U (15W) GT2 dual 6 35 31 + * + * CML-S 10-Core (125W) GT2/0 11.1 245 35 + * CML-S 10-Core (65W) GT2/0 11.1 210 35 + * CML-S 10-Core (80W) GT2 11.1 210 35 + * CML-S 10-Core (35W) GT2 11.1 140 35 + * CML-S 8-Core (125W) GT2/0 11.1 245 35 + * CML-S 8-Core (65W) GT2/0 11.1 210 35 + * CML-S 8-Core (80W) GT2 11.1 210 35 + * CML-S 8-Core (35W) GT2 11.1 140 35 + * CML-S 6-Core (125/65/80W) 11.1 140 35 + * CML-S 6-Core (35W) GT2/0 11.1 104 35 + * CML-S 4-Core (65W) GT2 11.1 102 35 + * CML-S 4-Core (35W) GT2 11.1 65 35 + * CML-S 2-Core (58W) GT2/1 11.1 60 35 + * CML-S 2-Core (35W) GT2/1 11.1 55 35 * * GT0 versions are the same as GT2/GT3, but have GT/GTx set to 0. */ @@ -215,6 +231,39 @@ return icc_max[domain]; } + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 35, 35); + if (tdp > 35) { + if (tdp >= 125) + icc_max[VR_IA_CORE] = VR_CFG_AMP(245); + else + icc_max[VR_IA_CORE] = VR_CFG_AMP(210); + } + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35); + if (tdp > 35) + icc_max[VR_IA_CORE] = VR_CFG_AMP(140); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_4: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 65, 35, 35); + if (tdp > 35) + icc_max[VR_IA_CORE] = VR_CFG_AMP(102); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 55, 35, 35); + if (tdp > 35) + icc_max[VR_IA_CORE] = VR_CFG_AMP(60); + + return icc_max[domain]; + } default: printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); } @@ -273,6 +322,27 @@ VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1); return loadline[domain]; } + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2: { + uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0); + const uint16_t tdp = cpu_get_power_max(); + if (tdp > 35) + loadline[VR_IA_CORE] = 1.1; + + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_4: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_2: { + uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0); + const uint16_t tdp = cpu_get_power_max(); + if (tdp >= 125) + loadline[VR_IA_CORE] = 1.1; + + return loadline[domain]; + } default: printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2797a979a8b6a52a34baae66f95c7136ed1dc72 Gerrit-Change-Number: 38288 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboards: add GIGABYTE P34G v2
by Daniel Maslowski (Code Review) 22 Dec '20

22 Dec '20

Daniel Maslowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36072 ) Change subject: mainboards: add GIGABYTE P34G v2 ...................................................................... mainboards: add GIGABYTE P34G v2 Change-Id: I5d83fbc4e402a9c0819947b8ea1ef2e480c3e5cb Signed-off-by: Daniel Maslowski <info(a)orangecms.org> --- M 3rdparty/blobs A src/mainboard/gigabyte/p34g-v2/Kconfig A src/mainboard/gigabyte/p34g-v2/Kconfig.name A src/mainboard/gigabyte/p34g-v2/Makefile.inc A src/mainboard/gigabyte/p34g-v2/acpi/ec.asl A src/mainboard/gigabyte/p34g-v2/acpi/platform.asl A src/mainboard/gigabyte/p34g-v2/acpi/superio.asl A src/mainboard/gigabyte/p34g-v2/acpi/thermal.asl A src/mainboard/gigabyte/p34g-v2/acpi_tables.c A src/mainboard/gigabyte/p34g-v2/board_info.txt A src/mainboard/gigabyte/p34g-v2/cmos.default A src/mainboard/gigabyte/p34g-v2/cmos.layout A src/mainboard/gigabyte/p34g-v2/devicetree.cb A src/mainboard/gigabyte/p34g-v2/dsdt.asl A src/mainboard/gigabyte/p34g-v2/gma-mainboard.ads A src/mainboard/gigabyte/p34g-v2/gpio.c A src/mainboard/gigabyte/p34g-v2/hda_verb.c A src/mainboard/gigabyte/p34g-v2/mainboard.c A src/mainboard/gigabyte/p34g-v2/romstage.c A src/mainboard/gigabyte/p34g-v2/thermal.h M src/southbridge/intel/lynxpoint/lpc.c 21 files changed, 1,093 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/36072/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index 62aa0e0..5afdf04 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 62aa0e0c54295bbb7b1a3e5e73f960bafdb59d04 +Subproject commit 5afdf04b4fce5cff33d704d1b474fd9609cbab15 diff --git a/src/mainboard/gigabyte/p34g-v2/Kconfig b/src/mainboard/gigabyte/p34g-v2/Kconfig new file mode 100644 index 0000000..f625052 --- /dev/null +++ b/src/mainboard/gigabyte/p34g-v2/Kconfig @@ -0,0 +1,55 @@ +if BOARD_GIGABYTE_P34G_V2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_INTEL_HASWELL + select NORTHBRIDGE_INTEL_HASWELL + select SOUTHBRIDGE_INTEL_LYNXPOINT + select INTEL_INT15 + select INTEL_GMA_HAVE_VBT + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select EC_ACPI + select SUPERIO_ITE_IT8587E + select MAINBOARD_HAS_LIBGFXINIT + select SERIRQ_CONTINUOUS_MODE + select SYSTEM_TYPE_LAPTOP + select TSC_MONOTONIC_TIMER + +config MAINBOARD_DIR + string + default gigabyte/p34g-v2 + +config GFX_GMA_CPU_VARIANT + string + default "Normal" + +config MAINBOARD_PART_NUMBER + string + default "P34G_V2" + +config VGA_BIOS_FILE + string + default "pci8086,0416.rom" + +config VGA_BIOS_ID + string + default "8086,0416" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0xa456 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1458 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/gigabyte/p34g-v2/Kconfig.name b/src/mainboard/gigabyte/p34g-v2/Kconfig.name new file mode 100644 index 0000000..e6a7665 --- /dev/null +++ b/src/mainboard/gigabyte/p34g-v2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GIGABYTE_P34G_V2 + bool "P34G_V2" diff --git a/src/mainboard/gigabyte/p34g-v2/Makefile.inc b/src/mainboard/gigabyte/p34g-v2/Makefile.inc new file mode 100644 index 0000000..ebe01ae --- /dev/null +++ b/src/mainboard/gigabyte/p34g-v2/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/gigabyte/p34g-v2/acpi/ec.asl b/src/mainboard/gigabyte/p34g-v2/acpi/ec.asl new file mode 100644 index 0000000..aa083da --- /dev/null +++ b/src/mainboard/gigabyte/p34g-v2/acpi/ec.asl @@ -0,0 +1,22 @@ +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) + Device (BAT0) + { + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + /* vendor: + If ((BNUM & One)) + { + Return (0x1F) + } + Return (0x0B) + */ + Return (Zero) + } + } +} diff --git a/src/mainboard/gigabyte/p34g-v2/acpi/platform.asl b/src/mainboard/gigabyte/p34g-v2/acpi/platform.asl new file mode 100644 index 0000000..c2862c9 --- /dev/null +++ b/src/mainboard/gigabyte/p34g-v2/acpi/platform.asl @@ -0,0 +1,10 @@ +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/gigabyte/p34g-v2/acpi/superio.asl b/src/mainboard/gigabyte/p34g-v2/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/gigabyte/p34g-v2/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/gigabyte/p34g-v2/acpi/thermal.asl b/src/mainboard/gigabyte/p34g-v2/acpi/thermal.asl new file mode 100644 index 0000000..93421d2 --- /dev/null +++ b/src/mainboard/gigabyte/p34g-v2/acpi/thermal.asl @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Thermal Zone + +External (\PPKG, MethodObj) + +#define HAVE_THERMALZONE +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x08) + Name (_TC2, 0x08) + + // Ignore critical temps for the first few reads + // at boot to prevent unexpected shutdown + Name (IRDC, 4) + Name (CRDC, 0) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } +/* + Method (_AC0) { + If (LLessEqual (\FLVL, 0)) { + Return (CTOK (\F0OF)) + } Else { + Return (CTOK (\F0ON)) + } + } + + Method (_AC1) { + If (LLessEqual (\FLVL, 1)) { + Return (CTOK (\F1OF)) + } Else { + Return (CTOK (\F1ON)) + } + } + + Method (_AC2) { + If (LLessEqual (\FLVL, 2)) { + Return (CTOK (\F2OF)) + } Else { + Return (CTOK (\F2ON)) + } + } + + Method (_AC3) { + If (LLessEqual (\FLVL, 3)) { + Return (CTOK (\F3OF)) + } Else { + Return (CTOK (\F3ON)) + } + } + + Method (_AC4) { + If (LLessEqual (\FLVL, 4)) { + Return (CTOK (\F4OF)) + } Else { + Return (CTOK (\F4ON)) + } + } +*/ + } +} diff --git a/src/mainboard/gigabyte/p34g-v2/acpi_tables.c b/src/mainboard/gigabyte/p34g-v2/acpi_tables.c new file mode 100644 index 0000000..f5e30b6 --- /dev/null +++ b/src/mainboard/gigabyte/p34g-v2/acpi_tables.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/lynxpoint/nvs.h> + +#include "thermal.h" + +static global_nvs_t *gnvs_; + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->f4of = FAN4_THRESHOLD_OFF; + gnvs->f4on = FAN4_THRESHOLD_ON; + + gnvs->f3of = FAN3_THRESHOLD_OFF; + gnvs->f3on = FAN3_THRESHOLD_ON; + + gnvs->f2of = FAN2_THRESHOLD_OFF; + gnvs->f2on = FAN2_THRESHOLD_ON; + + gnvs->f1of = FAN1_THRESHOLD_OFF; + gnvs->f1on = FAN1_THRESHOLD_ON; + + gnvs->f0of = FAN0_THRESHOLD_OFF; + gnvs->f0on = FAN0_THRESHOLD_ON; + + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tmax = MAX_TEMPERATURE; + gnvs->flvl = 5; // Fan level +} + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs_ = gnvs; + + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + + acpi_update_thermal_table(gnvs); +} diff --git a/src/mainboard/gigabyte/p34g-v2/board_info.txt b/src/mainboard/gigabyte/p34g-v2/board_info.txt new file mode 100644 index 0000000..9135e44 --- /dev/null +++ b/src/mainboard/gigabyte/p34g-v2/board_info.txt @@ -0,0 +1,8 @@ +Category: laptop +Board URL: https://www.gigabyte.com/Laptop/P34G-v2 +Board name: Gigabyte P34G v2 GA-R3456R +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/gigabyte/p34g-v2/cmos.default b/src/mainboard/gigabyte/p34g-v2/cmos.default new file mode 100644 index 0000000..f404714 --- /dev/null +++ b/src/mainboard/gigabyte/p34g-v2/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Debug +nmi=Enable +power_on_after_fail=Keep +hide_ast2400=Disable diff --git a/src/mainboard/gigabyte/p34g-v2/cmos.layout b/src/mainboard/gigabyte/p34g-v2/cmos.layout new file mode 100644 index 0000000..cce1f18 --- /dev/null +++ b/src/mainboard/gigabyte/p34g-v2/cmos.layout @@ -0,0 +1,97 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 4 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 5 power_on_after_fail + +# coreboot config options: mainboard +416 1 e 1 hide_ast2400 + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Enable +2 1 Disable + +3 0 Fallback +3 1 Normal + +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +5 0 Disable +5 1 Enable +5 2 Keep + +# ----------------------------------------------------------------- +checksums + +checksum 392 423 984 diff --git a/src/mainboard/gigabyte/p34g-v2/devicetree.cb b/src/mainboard/gigabyte/p34g-v2/devicetree.cb new file mode 100644 index 0000000..063ff5d --- /dev/null +++ b/src/mainboard/gigabyte/p34g-v2/devicetree.cb @@ -0,0 +1,142 @@ +chip northbridge/intel/haswell # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.ndid" = "3" + + register "gpu_cpu_backlight" = "0x00000200" + register "gpu_pch_backlight" = "0x04000000" + + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "0x06" + register "gpu_dp_c_hotplug" = "0x00" + register "gpu_dp_d_hotplug" = "0x06" + register "gpu_panel_port_select" = "0" + + # register value in hex: 6h for 500ms, i.e., (6-1)*100 - power_off_time + register "gpu_panel_power_cycle_delay" = "6" # T12 + register "gpu_panel_power_up_delay" = "2000" # T3 + register "gpu_panel_power_down_delay" = "5000" # T10 + register "gpu_panel_power_backlight_on_delay" = "70" # T7 + register "gpu_panel_power_backlight_off_delay" = "2100" # T9 + + device cpu_cluster 0x0 on + chip cpu/intel/haswell + device lapic 0x0 on end + device lapic 0xacac off end + + register "c1_acpower" = "1" + register "c2_acpower" = "3" + register "c3_acpower" = "5" + + register "c1_battery" = "1" + register "c2_battery" = "3" + register "c3_battery" = "5" + end + end + + device domain 0x0 on + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x00000061" + register "gen2_dec" = "0x00040069" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "gpi7_routing" = "2" + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x03" + register "pirqc_routing" = "0x04" + register "pirqd_routing" = "0x0a" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x05" + register "pirqh_routing" = "0x0b" + register "sata_ahci" = "1" + register "sata_port_map" = "0x3" + device pci 14.0 on # xHCI Controller + subsystemid 0x1458 0xa456 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1458 0xa456 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + # device pci 19.0 off # Intel Gigabit Ethernet # FIXME + # end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1458 0xa456 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x1458 0xa456 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1458 0xa456 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x1458 0xa456 + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x1458 0xa456 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1458 0xa456 + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x1458 0xa456 + chip superio/ite/it8587e + # 0x4e according to superiotool.log + device pnp 4e.1 off end # UART 1 + device pnp 4e.2 off end # UART 2 + device pnp 4e.4 off end # sys wakeup + device pnp 4e.5 off end # mouse + device pnp 4e.6 on # keyboard FIXME: works? + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 4e.f off end # shared mem + device pnp 4e.10 off end # RTC + device pnp 4e.11 off end # PM1 + device pnp 4e.12 off end # PM2 + device pnp 4e.13 off end # SPI + device pnp 4e.17 off end # PM3 + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1458 0xa456 + end + device pci 1f.3 on # SMBus + subsystemid 0x1458 0xa456 + end + # device pci 1f.5 off # SATA Controller 2 # FIXME + # end + device pci 1f.6 on # Thermal + subsystemid 0x1458 0xa456 + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x1458 0xa456 + end + device pci 01.0 on # PCIe Bridge for discrete graphics Unsupported PCI device 8086:0c01 + subsystemid 0x1458 0xa456 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x1458 0xa456 + end + device pci 03.0 on # Mini-HD audio Audio controller + subsystemid 0x8086 0x2010 + end + end +end diff --git a/src/mainboard/gigabyte/p34g-v2/dsdt.asl b/src/mainboard/gigabyte/p34g-v2/dsdt.asl new file mode 100644 index 0000000..47ee50c --- /dev/null +++ b/src/mainboard/gigabyte/p34g-v2/dsdt.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + + /* Super I/O, EC */ + #include "acpi/superio.asl" + #include "acpi/ec.asl" + + /* Thermal handler */ + #include "acpi/thermal.asl" + + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/lynxpoint/acpi/platform.asl> + + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/gigabyte/p34g-v2/gma-mainboard.ads b/src/mainboard/gigabyte/p34g-v2/gma-mainboard.ads new file mode 100644 index 0000000..8a72a31 --- /dev/null +++ b/src/mainboard/gigabyte/p34g-v2/gma-mainboard.ads @@ -0,0 +1,30 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + HDMI1, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/gigabyte/p34g-v2/gpio.c b/src/mainboard/gigabyte/p34g-v2/gpio.c new file mode 100644 index 0000000..a700291 --- /dev/null +++ b/src/mainboard/gigabyte/p34g-v2/gpio.c @@ -0,0 +1,226 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_NATIVE, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_LOW, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_NATIVE, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_LOW, + .gpio46 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio46 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/p34g-v2/hda_verb.c b/src/mainboard/gigabyte/p34g-v2/hda_verb.c new file mode 100644 index 0000000..c2cb5a0 --- /dev/null +++ b/src/mainboard/gigabyte/p34g-v2/hda_verb.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x80862807, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x0, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x0, 0x06, 0x18560010), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x0, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/p34g-v2/mainboard.c b/src/mainboard/gigabyte/p34g-v2/mainboard.c new file mode 100644 index 0000000..be4a5aa --- /dev/null +++ b/src/mainboard/gigabyte/p34g-v2/mainboard.c @@ -0,0 +1,50 @@ +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <ec/acpi/ec.h> +#include <console/console.h> +#include <pc80/keyboard.h> + +static void mainboard_init(struct device *dev) +{ + /* FIXME: trim this down or remove if necessary */ + { + int i; + const u8 dmp[256] = { + /* 00 */ 0x0a, 0xe3, 0x5b, 0xa0, 0x80, 0x40, 0x60, 0x00, 0x00, 0x01, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, + /* 10 */ 0x54, 0x10, 0xa7, 0x0c, 0xdb, 0x0b, 0x2c, 0x42, 0xa2, 0x01, 0x65, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 20 */ 0x60, 0x3b, 0x00, 0x00, 0x9a, 0x0b, 0x01, 0x01, 0x00, 0x00, 0x55, 0x34, 0x4e, 0x00, 0x00, 0x00, + /* 30 */ 0x47, 0x42, 0x54, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 40 */ 0x00, 0x00, 0x00, 0x00, 0x55, 0x34, 0x4e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 50 */ 0x00, 0x00, 0x00, 0x00, 0xa7, 0x0c, 0x54, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 60 */ 0x3a, 0x37, 0x3a, 0x03, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x0b, 0xdb, + /* 70 */ 0x00, 0x65, 0x00, 0x00, 0x0c, 0xa7, 0x00, 0x00, 0x0b, 0x9a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, + /* 80 */ 0x01, 0x44, 0x02, 0x87, 0x03, 0xcb, 0x05, 0x0f, 0x06, 0x53, 0x0c, 0x05, 0x00, 0x00, 0x00, 0x00, + /* 90 */ 0x98, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, + /* a0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* b0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* c0 */ 0x00, 0x44, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* d0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* e0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* f0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + + printk(BIOS_DEBUG, "Replaying EC dump ..."); + for (i = 0; i < 256; i++) + ec_write (i, dmp[i]); + printk(BIOS_DEBUG, "done\n"); + } + pc_keyboard_init(NO_AUX_DEVICE); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/gigabyte/p34g-v2/romstage.c b/src/mainboard/gigabyte/p34g-v2/romstage.c new file mode 100644 index 0000000..7e09a49 --- /dev/null +++ b/src/mainboard/gigabyte/p34g-v2/romstage.c @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/romstage.h> +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/lynxpoint/pch.h> + +// root complex base addresses +static const struct rcba_config_instruction rcba_config[] = { + /* Device interrupt route registers */ + RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), + RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), + RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), + RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), + RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)), + RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + + /* Disable unused devices (board specific, copied from Beltino) */ + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +void mainboard_config_superio(void) +{ +} + +void mainboard_romstage_entry() +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 1, /* desktop/server */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + // left-shifted by 1 for mrc.bin + .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, + .ec_present = 0, + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + }, + .usb3_ports = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = &rcba_config[0], + }; + + /* SuperIO */ + pch_enable_lpc(); + + /* Main romstage entry */ + romstage_common(&romstage_params); +} diff --git a/src/mainboard/gigabyte/p34g-v2/thermal.h b/src/mainboard/gigabyte/p34g-v2/thermal.h new file mode 100644 index 0000000..210c702 --- /dev/null +++ b/src/mainboard/gigabyte/p34g-v2/thermal.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// taken from Samsung / lumpy +#ifndef P34V2_THERMAL_H +#define P34V2_THERMAL_H + +/* Fan is OFF */ +#define FAN4_THRESHOLD_OFF 0 +#define FAN4_THRESHOLD_ON 0 + +/* Fan is at LOW speed */ +#define FAN3_THRESHOLD_OFF 40 +#define FAN3_THRESHOLD_ON 44 + +/* Fan is at MEDIUM speed */ +#define FAN2_THRESHOLD_OFF 44 +#define FAN2_THRESHOLD_ON 48 + +/* Fan is at HIGH speed */ +#define FAN1_THRESHOLD_OFF 48 +#define FAN1_THRESHOLD_ON 54 + +/* Fan is at FULL speed */ +#define FAN0_THRESHOLD_OFF 54 +#define FAN0_THRESHOLD_ON 78 + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 80 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 100 + +#endif diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 28e3544..c1b3c50 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -962,8 +962,16 @@ { spi_finalize_ops(); - if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) + if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) { outb(APM_CNT_FINALIZE, APM_CNT); + if (CONFIG(CONSOLE_SPI_FLASH)) { + /* Re-init SPI driver to handle locked BAR. + This prevents flashconsole from hanging. + If other code needs to use SPI during + ramstage, whitelist it here. */ + spi_init(); + } + } } static struct pci_operations pci_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/36072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d83fbc4e402a9c0819947b8ea1ef2e480c3e5cb Gerrit-Change-Number: 36072 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: soc/mediatek/mt8192: Do dramc software impedance calibration
by CK HU (Code Review) 22 Dec '20

22 Dec '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44704 to review the following change. Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ...................................................................... soc/mediatek/mt8192: Do dramc software impedance calibration Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 3 files changed, 184 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44704/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index e82f182..bf819ec 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -16,7 +16,7 @@ verstage-y += ../common/uart.c romstage-y += ../common/cbmem.c -romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_utility.c +romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c dramc_utility.c romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c new file mode 100644 index 0000000..04ff5d7 --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <string.h> +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> +#include <timer.h> + +static const u8 imp_vref_sel[ODT_MAX][IMP_DRV_MAX] = { + /* DRVP DRVN ODTP ODTN */ + [ODT_OFF] = {0x37, 0x33, 0x00, 0x37}, + [ODT_ON] = {0x3a, 0x33, 0x00, 0x3a}, +}; + +static void dramc_imp_cal_vref_sel(dram_odt_state odt, imp_drv_type drv_type) +{ + u8 vref_tmp = 0; + vref_tmp = imp_vref_sel[odt][drv_type]; + + switch (drv_type) { + case DRVP: + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVP, vref_tmp); + break; + case DRVN: + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVN, vref_tmp); + break; + case ODTN: + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_VREF_SEL_ODTN, vref_tmp); + break; + default: + die("Can't support drv_type %d\n", drv_type); + break; + } +} + +static u32 dramc_sw_imp_cal_result(imp_drv_type drv_type) +{ + u32 drive = 0, cal_res = 0; + u32 change = (drv_type == DRVP) ? 1: 0; + + const char *drv_str = NULL; + switch (drv_type) { + case DRVP: + drv_str = "DRVP"; + break; + case DRVN: + drv_str = "DRVN"; + break; + case ODTP: + drv_str = "ODTP"; + break; + case ODTN: + drv_str = "ODTN"; + break; + default: + die("Can't support drv_type %d\n", drv_type); + break; + } + + for (drive = 0; drive < 32; drive++) { + if (drv_type == DRVP) + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPDRVP, drive); + else if (drv_type == DRVN || drv_type == ODTN) + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPDRVN, drive); + + udelay(1); + cal_res = READ32_BITFIELD(&ch[0].phy_nao.misc_phy_rgs_cmd, + MISC_PHY_RGS_CMD_RGS_RIMPCALOUT); + dramc_dbg("OCD %s=%d ,CALOUT=%d\n", drv_str, drive, cal_res); + + if (cal_res == change) { + dramc_info("%s calibration OK! result=%d\n", drv_str, drive); + break; + } + } + + if (drive == 32) { + drive = 31; + dramc_err("OCD %s calibration FAIL! %s=%d\n", drv_str, drv_str, drive); + } + + return drive; +} + +void dramc_sw_impedance_cal(dram_odt_state odt, struct dram_impedance *imp) +{ + u8 chn = 0, i_chn, enp, enn; + u32 bc_bak, impcal_bak, cal_res = 0; + u32 drvp_result = 0xff, odtn_result = 0xff, drvn_result = 0xff; + + bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (i_chn = 0; i_chn < CHANNEL_MAX; i_chn++) { + SET32_BITFIELDS(&ch[i_chn].phy_ao.misc_lp_ctrl, + MISC_LP_CTRL_RG_ARDMSUS_10, 0x0, + MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL, 0x0, + MISC_LP_CTRL_RG_RIMP_DMSUS_10, 0x0, + MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL, 0x0); + SET32_BITFIELDS(&ch[i_chn].phy_ao.misc_impcal, MISC_IMPCAL_IMPCAL_HW, 0); + } + + impcal_bak = read32(&ch[chn].phy_ao.misc_impcal); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_imp_ctrl1, MISC_IMP_CTRL1_RG_RIMP_PRE_EN, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_CALI_ENN, 0, + MISC_IMPCAL_IMPCAL_IMPPDP, 1, + MISC_IMPCAL_IMPCAL_IMPPDN, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_imp_ctrl1, + MISC_IMP_CTRL1_RG_IMP_EN, 1, + MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL, 0, + MISC_IMP_CTRL1_RG_RIMP_VREF_EN, 1, + MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL, 1); + udelay(1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, MISC_IMPCAL_IMPCAL_CALI_EN, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPDRVN, 0, + SHU_MISC_IMPCAL1_IMPDRVP, 0); + + for (imp_drv_type drv_type = DRVP; drv_type < IMP_DRV_MAX; drv_type++) { + if (drv_type == ODTP) + continue; + dramc_imp_cal_vref_sel(odt, drv_type); + + switch (drv_type) { + case DRVP: + enp = 0x1; + enn = 0x0; + drvp_result = 0; + break; + case DRVN: + case ODTN: + enp = 0x0; + enn = (drv_type == DRVN) ? 0x0 : 0x1; + break; + default: + die("Can't support drv_type %d\n", drv_type); + break; + } + + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_CALI_ENP, enp); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_CALI_ENN, enn); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPDRVP, drvp_result); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_DRV05, 0); + + cal_res = dramc_sw_imp_cal_result(drv_type); + switch (drv_type) { + case DRVP: + drvp_result = cal_res; + break; + case DRVN: + drvn_result = cal_res; + break; + case ODTN: + odtn_result = cal_res; + break; + default: + die("Can't support drv_type %d\n", drv_type); + break; + } + } + + imp->result[odt][DRVP] = drvp_result; + imp->result[odt][DRVN] = drvn_result; + imp->result[odt][ODTP] = 0; + imp->result[odt][ODTN] = odtn_result; + + dramc_info("freq_region=%d, Reg: DRVP=%d, DRVN=%d, ODTN=%d\n", + odt, drvp_result, drvn_result, odtn_result); + + write32(&ch[chn].phy_ao.misc_impcal, impcal_bak); + dramc_set_broadcast(bc_bak); +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 184479d..355cc9d 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -73,6 +73,9 @@ emi_mdl_init(cali.emi_config); dramc_set_broadcast(bc_bak); + dramc_sw_impedance_cal(ODT_OFF, &cali.impedance); + dramc_sw_impedance_cal(ODT_ON, &cali.impedance); + if (ddr_info->config_dvfs == DRAMC_ENABLE_DVFS) k_shuffle_end = CALI_SEQ_MAX; else -- To view, visit https://review.coreboot.org/c/coreboot/+/44704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d Gerrit-Change-Number: 44704 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

8 26

Change in coreboot[master]: soc/mediatek/mt8192: Do EMI init before dram calibration
by CK HU (Code Review) 22 Dec '20

22 Dec '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44703 to review the following change. Change subject: soc/mediatek/mt8192: Do EMI init before dram calibration ...................................................................... soc/mediatek/mt8192: Do EMI init before dram calibration Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I3b778698a09c999252fef3153ac1e869ea9d90cd --- M src/soc/mediatek/mt8192/dramc_pi_main.c M src/soc/mediatek/mt8192/emi.c 2 files changed, 407 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/44703/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index c36ff43..184479d 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -70,6 +70,7 @@ global_option_init(&cali); bc_bak = dramc_get_broadcast(); dramc_set_broadcast(DRAMC_BROADCAST_OFF); + emi_mdl_init(cali.emi_config); dramc_set_broadcast(bc_bak); if (ddr_info->config_dvfs == DRAMC_ENABLE_DVFS) @@ -82,6 +83,9 @@ set_vcore_voltage_for_each_freq(&cali); dfs_init_for_calibration(&cali); + if (first_freq_k) + emi_init2(); + dramc_calibration_all_channels(&cali); first_freq_k= false; diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c index f83acd3..eb110cc 100644 --- a/src/soc/mediatek/mt8192/emi.c +++ b/src/soc/mediatek/mt8192/emi.c @@ -1,6 +1,409 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> +#include <soc/infracfg.h> + +static struct emi_regs *emi_reg = (void *)EMI_BASE; +static struct emi_mpu_regs *const emi_mpu = (void *)EMI_MPU_BASE; +static struct infra_ao_mem_regs *infra_ao_mem = (void *)INFRACFG_AO_MEM_BASE; + +static void emi_center_config(void) +{ + write32(&emi_reg->cona, 0xf053f154); + write32(&emi_reg->conp, 0x182e2d33); + write32(&emi_reg->conb, 0x0f251025); + write32(&emi_reg->conq, 0x122a1027); + write32(&emi_reg->conc, 0x1a31162d); + write32(&emi_reg->conb_2nd, 0x182e2d33); + write32(&emi_reg->conc_2nd, 0x0f251025); + write32(&emi_reg->conp_2nd, 0x122a1027); + write32(&emi_reg->conq_2nd, 0x1a31162d); + write32(&emi_reg->conb_3rd, 0x1024202c); + write32(&emi_reg->conc_3rd, 0x0b210c21); + write32(&emi_reg->conp_3rd, 0x0f250d23); + write32(&emi_reg->conq_3rd, 0x152b1228); + write32(&emi_reg->conb_4th, 0x0c201a28); + write32(&emi_reg->conc_4th, 0x0d230a20); + write32(&emi_reg->conp_4th, 0x0e260d24); + write32(&emi_reg->conq_4th, 0x132d1229); + write32(&emi_reg->conb_5th, 0x0c201a28); + write32(&emi_reg->conc_5th, 0x0d230a20); + write32(&emi_reg->conp_5th, 0x0e260d24); + write32(&emi_reg->conq_5th, 0x132d1229); + write32(&emi_reg->conb_6th, 0x0c201a28); + write32(&emi_reg->conc_6th, 0x0d230a20); + write32(&emi_reg->conp_6th, 0x0e260d24); + write32(&emi_reg->conq_6th, 0x132d1229); + write32(&emi_reg->conb_7th, 0x0e290e28); + write32(&emi_reg->conc_7th, 0x091e1322); + write32(&emi_reg->mpud26_st, 0x0f29112a); + write32(&emi_reg->conq_7th, 0x0c240a1f); + write32(&emi_reg->conb_8th, 0x0e290e28); + write32(&emi_reg->conc_8th, 0x091e1322); + write32(&emi_reg->conp_8th, 0x0f29112a); + write32(&emi_reg->conq_8th, 0x0c240a1f); + write32(&emi_reg->cong, 0x37373a57); + write32(&emi_reg->conr, 0x3f3f3c39); + write32(&emi_reg->cong_2nd, 0x3836374e); + write32(&emi_reg->conr_2nd, 0x41413d3a); + write32(&emi_reg->cong_3rd, 0x33313241); + write32(&emi_reg->conr_3rd, 0x3a3a3835); + write32(&emi_reg->cong_4th, 0x34343542); + write32(&emi_reg->conr_4th, 0x3b3b3835); + write32(&emi_reg->cong_5th, 0x34343542); + write32(&emi_reg->conr_5th, 0x3b3b3835); + write32(&emi_reg->cong_6th, 0x34343542); + write32(&emi_reg->conr_6th, 0x3b3b3835); + write32(&emi_reg->cong_7th, 0x37333034); + write32(&emi_reg->conr_7th, 0x39393a39); + write32(&emi_reg->cong_8th, 0x37333034); + write32(&emi_reg->conr_8th, 0x39393a39); + write32(&emi_reg->cond, 0x3657587a); + write32(&emi_reg->cone, 0x0000c042); + write32(&emi_reg->conf, 0x08421000); + write32(&emi_reg->conh, 0x00000083); + write32(&emi_reg->conh_2nd, 0x00073210); + write32(&emi_reg->coni, 0x00008802); + write32(&emi_reg->conj, 0x00000000); + write32(&emi_reg->conm, 0x007812ff); + write32(&emi_reg->conn, 0x00000000); + write32(&emi_reg->mdct, 0x11120c1f); + write32(&emi_reg->shf0, 0x11120c1f); + write32(&emi_reg->mdct_2nd, 0x00001123); + write32(&emi_reg->shf1, 0x00001123); + write32(&emi_reg->iocl, 0xa8a8a8a8); + write32(&emi_reg->iocl_2nd, 0x25252525); + write32(&emi_reg->iocm, 0xa8a8a8a8); + write32(&emi_reg->iocm_2nd, 0x25252525); + write32(&emi_reg->testb, 0x00060037); + write32(&emi_reg->testc, 0x384a0014); + write32(&emi_reg->testd, 0xa0000000); + write32(&emi_reg->arba, 0x20107244); + write32(&emi_reg->arbb, 0x10107044); + write32(&emi_reg->arbc, 0x343450df); + write32(&emi_reg->arbd, 0x0000f0d0); + write32(&emi_reg->arbe, 0x10106048); + write32(&emi_reg->arbf, 0x343450df); + write32(&emi_reg->arbg, 0x83837044); + write32(&emi_reg->arbh, 0x83837044); + write32(&emi_reg->arbi, 0x00007108); + write32(&emi_reg->arbi_2nd, 0x00007108); + write32(&emi_reg->arbk, 0x090a4000); + write32(&emi_reg->slct, 0xff0bff00); + write32(&emi_reg->bmen, 0x00ff0001); + write32(&emi_reg->clua, 0x10000008); + write32(&emi_reg->slva, 0xffffffff); + write32(&emi_reg->thro_os0, 0x24240101); + write32(&emi_reg->thro_os1, 0x01012424); + write32(&emi_reg->thro_os2, 0x50500101); + write32(&emi_reg->thro_os3, 0x01015050); + write32(&emi_reg->thro_ctrl0, 0x0fc39a30); + write32(&emi_reg->thro_prd0, 0x05050003); + write32(&emi_reg->thro_prd1, 0x254dffff); + write32(&emi_reg->thro_lat0, 0x465a788c); + write32(&emi_reg->thro_lat1, 0x000003e8); + write32(&emi_reg->thro_lat2, 0x0000036b); + write32(&emi_reg->thro_lat3, 0x00000290); + write32(&emi_reg->thro_lat4, 0x00000200); + write32(&emi_reg->thro_lat5, 0x00000000); + write32(&emi_reg->thro_lat6, 0x00000000); + write32(&emi_reg->thro_ctrl1, 0x02531cff); + write32(&emi_reg->thro_prd2, 0x00002785); + write32(&emi_reg->thro_lat7, 0x000001b5); + write32(&emi_reg->thro_lat8, 0x003c0000); + write32(&emi_reg->thro_prd3, 0x0255250d); + write32(&emi_reg->bwlmta, 0xffff3c59); + write32(&emi_reg->bwlmtb, 0xffff00ff); + write32(&emi_reg->bwlmte, 0xffffffff); + write32(&emi_reg->bwlmtf, 0x0000ffff); + write32(&emi_reg->thro_lat9, 0x0000014b); + write32(&emi_reg->thro_lat10, 0x002d0000); + write32(&emi_reg->thro_lat11, 0x00000185); + write32(&emi_reg->thro_lat12, 0x003c0000); + write32(&emi_reg->thro_lat13, 0x00000185); + write32(&emi_reg->thro_lat14, 0x003c0000); + write32(&emi_reg->bwlmte_2nd, 0xffffffff); + write32(&emi_reg->bwlmtf_2nd, 0xffffffff); + write32(&emi_reg->bwlmtg_2nd, 0xffffffff); + write32(&emi_reg->bwlmte_4th, 0xffffffff); + write32(&emi_reg->bwlmtf_4th, 0x0000ffff); + write32(&emi_reg->bwlmte_5th, 0xffffffff); + write32(&emi_reg->bwlmtf_5th, 0xffffffff); + write32(&emi_reg->bwlmtg_5th, 0xffffffff); + write32(&emi_reg->thro_lat27, 0x41547082); + write32(&emi_reg->thro_lat28, 0x38382a38); + write32(&emi_reg->thro_lat29, 0x000001d4); + write32(&emi_reg->thro_lat30, 0x00000190); + write32(&emi_reg->thro_lat31, 0x0000012c); + write32(&emi_reg->thro_lat32, 0x000000ed); + write32(&emi_reg->thro_lat33, 0x000000c8); + write32(&emi_reg->thro_lat34, 0x00000096); + write32(&emi_reg->thro_lat35, 0x000000c8); + write32(&emi_reg->thro_lat36, 0x000000c8); + write32(&emi_reg->thro_lat41, 0x26304048); + write32(&emi_reg->thro_lat42, 0x20201820); + write32(&emi_reg->thro_lat55, 0x181e282f); + write32(&emi_reg->thro_lat56, 0x14140f18); + write32(&emi_reg->thro_lat69, 0x7496c8ea); + write32(&emi_reg->thro_lat70, 0x64644b64); + write32(&emi_reg->thro_lat83, 0x01010101); + write32(&emi_reg->thro_lat84, 0x01010101); + write32(&emi_reg->thro_lat97, 0x7496c8ea); + write32(&emi_reg->thro_lat98, 0x64644b64); + write32(&emi_reg->thro_lat111, 0x01010101); + write32(&emi_reg->thro_lat112, 0x01010101); + write32(&emi_reg->thro_prd5, 0x300ff025); + write32(&emi_reg->thro_lat113, 0x000003e8); + write32(&emi_reg->thro_lat114, 0x0000036b); + write32(&emi_reg->thro_lat115, 0x00000290); + write32(&emi_reg->thro_lat116, 0x00000200); + write32(&emi_reg->thro_lat117, 0x000001b5); + write32(&emi_reg->thro_lat118, 0x0000014b); + write32(&emi_reg->thro_lat119, 0x00000185); + write32(&emi_reg->thro_lat120, 0x00000185); + write32(&emi_reg->thro_lat125, 0x52698ca0); + write32(&emi_reg->thro_lat126, 0x46463546); + write32(&emi_reg->thro_lat139, 0x01010101); + write32(&emi_reg->thro_lat140, 0x01010101); + write32(&emi_reg->qos_mdr_be0a, 0x00000009); + write32(&emi_reg->qos_mdr_be1a, 0x00000000); + write32(&emi_reg->qos_mdr_shf0, 0x00730000); + write32(&emi_reg->qos_mdr_shf1, 0x00000808); + write32(&emi_reg->qos_mdw_be0a, 0x00000028); + write32(&emi_reg->qos_mdw_be1a, 0x00000000); + write32(&emi_reg->qos_mdw_shf0, 0x00730000); + write32(&emi_reg->qos_mdw_shf1, 0x00000808); + write32(&emi_reg->qos_apr_be0a, 0x00000080); + write32(&emi_reg->qos_apr_be1a, 0x00000000); + write32(&emi_reg->qos_apr_shf0, 0x30201008); + write32(&emi_reg->qos_apw_be0a, 0x00000800); + write32(&emi_reg->qos_apw_be1a, 0x00000000); + write32(&emi_reg->qos_mmr_be0a, 0x00008000); + write32(&emi_reg->qos_mmr_be1a, 0x00020000); + write32(&emi_reg->qos_mmr_be1b, 0x00001000); + write32(&emi_reg->qos_mmr_be2a, 0x00010000); + write32(&emi_reg->qos_mmr_be2b, 0x00000800); + write32(&emi_reg->qos_mmr_shf0, 0x08080000); + write32(&emi_reg->qos_mmr_shf1, 0x00073030); + write32(&emi_reg->qos_mmw_be0a, 0x00040000); + write32(&emi_reg->qos_mmw_be1a, 0x00100000); + write32(&emi_reg->qos_mmw_be1b, 0x00004000); + write32(&emi_reg->qos_mmw_be2a, 0x00080000); + write32(&emi_reg->qos_mmw_be2b, 0x00002000); + write32(&emi_reg->qos_mmw_shf0, 0x08080000); + write32(&emi_reg->qos_mmw_shf1, 0x00074040); + write32(&emi_reg->qos_mdhwr_be0a, 0x00400000); + write32(&emi_reg->qos_mdhwr_be1a, 0x00200000); + write32(&emi_reg->qos_mdhwr_shf0, 0x10100404); + write32(&emi_reg->qos_mdhww_be0a, 0x01000000); + write32(&emi_reg->qos_mdhww_be1a, 0x00800000); + write32(&emi_reg->qos_gpur_be0a, 0x04000000); + write32(&emi_reg->qos_gpur_be1a, 0x02000000); + write32(&emi_reg->qos_gpur_shf0, 0x60602010); + write32(&emi_reg->qos_gpuw_be0a, 0x10000000); + write32(&emi_reg->qos_gpuw_be1a, 0x08000000); + write32(&emi_reg->qos_arbr_be0a, 0x00000009); + write32(&emi_reg->qos_arbr_be1a, 0x04400080); + write32(&emi_reg->qos_arbr_shf0, 0x0f170f11); + write32(&emi_reg->qos_ctrl1, 0x0303f7f7); + write32(&emi_reg->ext_lt_con1_1st, 0x00000166); + write32(&emi_reg->ext_lt_con2_1st, 0xffffffff); + write32(&emi_reg->ext_lt_con3_1st, 0xffffffff); + write32(&emi_reg->ext_lt_con1_2nd, 0x00400166); + write32(&emi_reg->ext_lt_con2_2nd, 0xffffffff); + write32(&emi_reg->ext_lt_con3_2nd, 0xffffffff); + write32(&emi_reg->ext_lt_con1_3rd, 0x00000266); + write32(&emi_reg->ext_lt_con2_3rd, 0xffffffff); + write32(&emi_reg->ext_lt_con3_3rd, 0xffffffff); + write32(&emi_reg->ext_lt_con1_4th, 0x00400266); + write32(&emi_reg->ext_lt_con2_4th, 0xffffffff); + write32(&emi_reg->ext_lt_con3_4th, 0xffffffff); + write32(&emi_reg->prtcl_m0_cyc, 0xffffffff); + write32(&emi_reg->prtcl_m0_ctl, 0x001ffc85); + write32(&emi_reg->prtcl_m0_msk, 0xffffffff); + write32(&emi_reg->prtcl_m1_cyc, 0xffffffff); + write32(&emi_reg->prtcl_m1_ctl, 0x001ffc85); + write32(&emi_reg->prtcl_m1_msk, 0xffffffff); + write32(&emi_reg->prtcl_m2_cyc, 0xffffffff); + write32(&emi_reg->prtcl_m2_ctl, 0x001ffc85); + write32(&emi_reg->prtcl_m2_msk, 0xffffffff); + write32(&emi_reg->prtcl_m3_cyc, 0xffffffff); + write32(&emi_reg->prtcl_m3_ctl, 0x001ffc85); + write32(&emi_reg->prtcl_m3_msk, 0xffffffff); + write32(&emi_reg->prtcl_m4_cyc, 0xffffffff); + write32(&emi_reg->prtcl_m4_ctl, 0x001ffc85); + write32(&emi_reg->prtcl_m4_msk, 0xffffffff); + write32(&emi_reg->prtcl_m5_cyc, 0xffffffff); + write32(&emi_reg->prtcl_m5_ctl, 0x001ffc85); + write32(&emi_reg->prtcl_m5_msk, 0xffffffff); + write32(&emi_reg->prtcl_m6_cyc, 0xffffffff); + write32(&emi_reg->prtcl_m6_ctl, 0x001ffc85); + write32(&emi_reg->prtcl_m6_msk, 0xffffffff); + write32(&emi_reg->prtcl_m7_cyc, 0xffffffff); + write32(&emi_reg->prtcl_m7_ctl, 0x001ffc85); + write32(&emi_reg->prtcl_m7_msk, 0xffffffff); + write32(&emi_reg->dvfs_shf_con, 0x00000000); + write32(&emi_reg->mxto0, 0x60606060); + write32(&emi_reg->mxto1, 0x60606060); + write32(&emi_reg->conk, 0x00000000); + write32(&emi_reg->thro_slv_con0, 0x08ffbbff); + write32(&emi_reg->thro_slv_con1, 0xffff5b3c); + write32(&emi_reg->bwlmte_8th, 0xffff00ff); + write32(&emi_reg->bwlmtf_8th, 0x00ffffff); + write32(&emi_reg->bwlmtg_8th, 0xffff00ff); + write32(&emi_reg->bwlmth_8th, 0x00ffffff); + write32(&emi_reg->bwlmtg_7th, 0x00000000); + write32(&emi_reg->chn_hash0, 0xC0000000); +} + +static void emi_chn_config(void) +{ + write32(&ch[0].emi_chn.cona, 0x0400f051); + write32(&ch[0].emi_chn.conb, 0x00ff6048); + write32(&ch[0].emi_chn.conc, 0x00000004); + write32(&ch[0].emi_chn.mdct, 0x99f08c03); + write32(&ch[0].emi_chn.shf0, 0x9a508c17); + write32(&ch[0].emi_chn.testb, 0x00038137); + write32(&ch[0].emi_chn.testc, 0x38460002); + write32(&ch[0].emi_chn.testd, 0x00000000); + write32(&ch[0].emi_chn.ap_early_cke, 0x000002ff); + write32(&ch[0].emi_chn.dqfr, 0x00003111); + write32(&ch[0].emi_chn.arbi, 0x22607188); + write32(&ch[0].emi_chn.arbi_2nd, 0x22607188); + write32(&ch[0].emi_chn.arbj, 0x3719595e); + write32(&ch[0].emi_chn.arbj_2nd, 0x2719595e); + write32(&ch[0].emi_chn.arbk, 0x64f3ff79); + write32(&ch[0].emi_chn.arbk_2nd, 0x64f3ff79); + write32(&ch[0].emi_chn.slct, 0x011b0868); + write32(&ch[0].emi_chn.arb_rff, 0xa7414222); + write32(&ch[0].emi_chn.drs_mon0, 0x0000f801); + write32(&ch[0].emi_chn.drs_mon1, 0x40000000); + write32(&ch[0].emi_chn.rkarb0, 0x000c802f); + write32(&ch[0].emi_chn.rkarb1, 0xbd3f3f7e); + write32(&ch[0].emi_chn.rkarb2, 0x7e003d7e); + write32(&ch[0].emi_chn.eco3, 0x00000000); + write32(&ch[0].emi_chn.md_pre_mask, 0xaa0148ff); + write32(&ch[0].emi_chn.md_pre_mask_shf, 0xaa6168ff); + write32(&ch[0].emi_chn.md_pre_mask_shf0, 0xaa516cff); + write32(&ch[0].emi_chn.md_pre_mask_shf1, 0xaa0140ff); + write32(&ch[0].emi_chn.qos_mdr_shf0, 0x9f658633); +} + +static void emi_init(void) +{ + dramc_set_broadcast(DRAMC_BROADCAST_ON); + emi_center_config(); + emi_chn_config(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); +} + +void emi_mdl_init(const struct emi_mdl *emi_con) +{ + emi_init(); + + write32(&emi_reg->cona, emi_con->cona_val); + write32(&emi_reg->conf, emi_con->conf_val); + write32(&emi_reg->conh, emi_con->conh_val); + for (u8 chn = CHANNEL_A; chn < CHANNEL_MAX; chn++) + write32(&ch[chn].emi_chn.cona, emi_con->chn_cona_val); +} + +static void emi_sw_setting(void) +{ + setbits32(&emi_mpu->mpu_ctrl_d[1], BIT(4)); + setbits32(&emi_mpu->mpu_ctrl_d[7], BIT(4)); + + write32(&emi_reg->bwct0, 0x05008305); + write32(&emi_reg->bwct0_6th, 0x08ff8705); + write32(&emi_reg->bwct0_3rd, 0x0dff8a05); + setbits32(&emi_reg->thro_ctrl1, 0x3 << 8); +} + +static void dramc_dcm_setting(void) +{ + write32(&infra_ao_mem->emi_idle_bit_en_0, 0xFFFFFFFF); + write32(&infra_ao_mem->emi_idle_bit_en_1, 0xFFFFFFFF); + write32(&infra_ao_mem->emi_idle_bit_en_2, 0xFFFFFFFF); + write32(&infra_ao_mem->emi_idle_bit_en_3, 0xFFFFFFFF); + write32(&infra_ao_mem->emi_m0m1_idle_bit_en_0, 0x01F00000); + write32(&infra_ao_mem->emi_m0m1_idle_bit_en_1, 0xC0040180); + write32(&infra_ao_mem->emi_m0m1_idle_bit_en_2, 0x00000000); + write32(&infra_ao_mem->emi_m0m1_idle_bit_en_3, 0x00000003); + write32(&infra_ao_mem->emi_m2m5_idle_bit_en_0, 0x0C000000); + write32(&infra_ao_mem->emi_m2m5_idle_bit_en_1, 0x00C00000); + write32(&infra_ao_mem->emi_m2m5_idle_bit_en_2, 0x01F08000); + write32(&infra_ao_mem->emi_m2m5_idle_bit_en_3, 0x00000000); + write32(&infra_ao_mem->emi_m3_idle_bit_en_0, 0x20003040); + write32(&infra_ao_mem->emi_m3_idle_bit_en_1, 0x00000000); + write32(&infra_ao_mem->emi_m3_idle_bit_en_2, 0x00001000); + write32(&infra_ao_mem->emi_m3_idle_bit_en_3, 0x00000000); + write32(&infra_ao_mem->emi_m4_idle_bit_en_0, 0x10020F20); + write32(&infra_ao_mem->emi_m4_idle_bit_en_1, 0x00019000); + write32(&infra_ao_mem->emi_m4_idle_bit_en_2, 0x040A0818); + write32(&infra_ao_mem->emi_m4_idle_bit_en_3, 0x00000370); + write32(&infra_ao_mem->emi_m6m7_idle_bit_en_0, 0xC001C080); + write32(&infra_ao_mem->emi_m6m7_idle_bit_en_1, 0x33000E01); + write32(&infra_ao_mem->emi_m6m7_idle_bit_en_2, 0x180067E1); + write32(&infra_ao_mem->emi_m6m7_idle_bit_en_3, 0x000C008C); + write32(&infra_ao_mem->emi_sram_idle_bit_en_0, 0x020C0008); + write32(&infra_ao_mem->emi_sram_idle_bit_en_1, 0x0C00007E); + write32(&infra_ao_mem->emi_sram_idle_bit_en_2, 0x80050006); + write32(&infra_ao_mem->emi_sram_idle_bit_en_3, 0x00030000); + + write32(&infra_ao_mem->emi_dcm_cfg0, 0x0000000F); + write32(&infra_ao_mem->emi_dcm_cfg1, 0x00000000); + write32(&infra_ao_mem->emi_dcm_cfg2, 0x001F0044); + write32(&infra_ao_mem->top_ck_anchor_cfg, 0x200000FF); + + setbits32(&mt8192_infracfg->mem_dcm_ctrl, BIT(27)); +} + +static void dramc_dcm_setting_2(void) +{ + u32 emi_temp_data; + + write32(&infra_ao_mem->emi_disph_cfg, 0x00000007); + write32(&infra_ao_mem->emi_disph_cfg, 0x80000007); + + emi_temp_data = read32(&infra_ao_mem->emi_disph_cfg); + emi_temp_data = emi_temp_data & 0xf; + write32(&emi_reg->chn_hash0, read32(&emi_reg->chn_hash0) | emi_temp_data); +} + +void emi_init2(void) +{ + u32 tmp; + u32 bc_bak; + bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_ON); + setbits32(&ch[0].emi_chn.conc, 0x1 << 0); + setbits32(&emi_reg->conm, BIT(10)); + setbits32(&emi_mpu->mpu_ctrl, BIT(4)); + + clrbits32(&ch[0].emi_chn.rkarb0, 0x1 << 0); + tmp = (read32(&ch[0].emi_chn.cona) & 0x1); + write32(&ch[0].emi_chn.rkarb0, read32(&ch[0].emi_chn.rkarb0) | tmp); + + dramc_dcm_setting(); + write32((u32 *)0x40000000, read32((u32 *)0x40000000)); + write32((u32 *)0x40000100, read32((u32 *)0x40000100)); + write32((u32 *)0x40000200, read32((u32 *)0x40000200)); + write32((u32 *)0x40000300, read32((u32 *)0x40000300)); + + setbits32(&emi_reg->conn, BIT(22)); + setbits32(&ch[0].emi_chn.testc, BIT(2)); + + dramc_dcm_setting_2(); + + setbits32(&emi_reg->conn, BIT(21)); + setbits32(&ch[0].emi_chn.testc, BIT(4)); + write32(&ch[0].emi_chn.ebg_con, 0x40); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + emi_sw_setting(); + dramc_set_broadcast(bc_bak); +} size_t sdram_size(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/44703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b778698a09c999252fef3153ac1e869ea9d90cd Gerrit-Change-Number: 44703 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

6 42

Change in coreboot[master]: soc/mediatek/mt8192: Do memory pll init before calibration
by CK HU (Code Review) 22 Dec '20

22 Dec '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44702 to review the following change. Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ...................................................................... soc/mediatek/mt8192: Do memory pll init before calibration Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 --- M src/soc/mediatek/mt8192/dramc_pi_main.c 1 file changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index e2c7500..c36ff43 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -2,6 +2,8 @@ #include <soc/dramc_pi_api.h> #include <soc/dramc_register.h> +#include <soc/pll.h> +#include <soc/pll_common.h> #include <soc/mt6359p.h> static void set_vcore_voltage_for_each_freq(const struct ddr_cali *cali) @@ -16,6 +18,34 @@ { } +static void mem_pll_init(void) +{ + unsigned int tmp; + + write32(&mtk_apmixed->mpll_con3, 0x3); + + udelay(30); + tmp = read32(&mtk_apmixed->mpll_con3); + write32(&mtk_apmixed->mpll_con3, tmp & 0xfffffffd); + + udelay(1); + write32(&mtk_apmixed->mpll_con1, 0x84200000); + tmp = read32(&mtk_apmixed->mpll_con0); + write32(&mtk_apmixed->mpll_con0, tmp | 0x1); + + udelay(20); + tmp = read32(&mtk_apmixed->pllon_con0); + write32(&mtk_apmixed->pllon_con0, tmp & ~(0x1 << 2)); + tmp = read32(&mtk_apmixed->pllon_con0); + write32(&mtk_apmixed->pllon_con0, tmp & ~(0x1 << 11)); + tmp = read32(&mtk_apmixed->pllon_con1); + write32(&mtk_apmixed->pllon_con1, tmp & ~(0x1 << 20)); + tmp = read32(&mtk_apmixed->pllon_con2); + write32(&mtk_apmixed->pllon_con2, tmp & ~(0x1 << 2)); + tmp = read32(&mtk_apmixed->pllon_con3); + write32(&mtk_apmixed->pllon_con3, tmp & ~(0x1 << 2)); +} + void init_dram(const struct dramc_data *dparam) { u32 bc_bak; @@ -35,6 +65,7 @@ cali.emi_config = &ddr_info->emi_config; dramc_set_broadcast(DRAMC_BROADCAST_ON); + mem_pll_init(); global_option_init(&cali); bc_bak = dramc_get_broadcast(); -- To view, visit https://review.coreboot.org/c/coreboot/+/44702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 Gerrit-Change-Number: 44702 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

7 44

Change in libgfxinit[master]: gma: Export backlight control interface
by Nico Huber (Code Review) 22 Dec '20

22 Dec '20

Hello Angel Pons, I'd like you to do a code review. Please visit https://review.coreboot.org/c/libgfxinit/+/43668 to review the following change. Change subject: gma: Export backlight control interface ...................................................................... gma: Export backlight control interface Change-Id: I5a157d7849124fd3b4cca8f9de1d605092fd3c5e Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M common/hw-gfx-gma.adb M common/hw-gfx-gma.ads 2 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/68/43668/1 diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 9157bbe..fae40ed 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -388,6 +388,40 @@ ---------------------------------------------------------------------------- + procedure Backlight_On (Port : Active_Port_Type) + with + Refined_Global => (In_Out => Registers.Register_State) + is + begin + Panel.Backlight_On (Config_Helpers.To_Panel (Port)); + end Backlight_On; + + procedure Backlight_Off (Port : Active_Port_Type) + with + Refined_Global => (In_Out => Registers.Register_State) + is + begin + Panel.Backlight_Off (Config_Helpers.To_Panel (Port)); + end Backlight_Off; + + procedure Set_Brightness (Port : Active_Port_Type; Level : Word32) + with + Refined_Global => (In_Out => Registers.Register_State) + is + begin + Panel.Set_Backlight (Config_Helpers.To_Panel (Port), Level); + end Set_Brightness; + + procedure Get_Max_Brightness (Port : Active_Port_Type; Level : out Word32) + with + Refined_Global => (In_Out => Registers.Register_State) + is + begin + Panel.Get_Max_Backlight (Config_Helpers.To_Panel (Port), Level); + end Get_Max_Brightness; + + ---------------------------------------------------------------------------- + procedure Initialize (Write_Delay : in Word64 := 0; Clean_State : in Boolean := False; diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 1215fc5..747d2f1 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -161,6 +161,24 @@ ---------------------------------------------------------------------------- + procedure Backlight_On (Port : Active_Port_Type) + with + Global => (In_Out => Device_State); + + procedure Backlight_Off (Port : Active_Port_Type) + with + Global => (In_Out => Device_State); + + procedure Set_Brightness (Port : Active_Port_Type; Level : Word32) + with + Global => (In_Out => Device_State); + + procedure Get_Max_Brightness (Port : Active_Port_Type; Level : out Word32) + with + Global => (In_Out => Device_State); + + ---------------------------------------------------------------------------- + procedure Write_GTT (GTT_Page : GTT_Range; Device_Address : GTT_Address_Type; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/43668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I5a157d7849124fd3b4cca8f9de1d605092fd3c5e Gerrit-Change-Number: 43668 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: drivers/tpm: Implement full PPI
by Patrick Rudolph (Code Review) 21 Dec '20

21 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45568 ) Change subject: drivers/tpm: Implement full PPI ...................................................................... drivers/tpm: Implement full PPI Implement the ACPI PPI interface as described in "TCG PC Client Physical Presence Interface Specification" Version 1.3. Add a new Kconfig that allows to use the full PPI instead of the stub version compiled in. This doesn't add code to execute the PPI request, as that's up to the payload with graphical UI support. Tested on GNU/Linux 5.6 using the sysfs interface at: /sys/class/tpm/tpm0/ppi/ Change-Id: Ifffe1d9b715e2c37568e1b009e86c298025c89ac Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/commonlib/include/commonlib/cbmem_id.h M src/drivers/tpm/Kconfig M src/drivers/tpm/Makefile.inc A src/drivers/tpm/ppi.c M src/drivers/tpm/tpm_ppi.h 5 files changed, 732 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/45568/1 diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index ac271a0..38d0aee 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -55,6 +55,7 @@ #define CBMEM_ID_TCPA_TCG_LOG 0x54445041 #define CBMEM_ID_TIMESTAMP 0x54494d45 #define CBMEM_ID_TPM2_TCG_LOG 0x54504d32 +#define CBMEM_ID_TPM_PPI 0x54505049 #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 /* deprecated */ #define CBMEM_ID_VBOOT_SEL_REG 0x780074f1 /* deprecated */ #define CBMEM_ID_VBOOT_WORKBUF 0x78007343 diff --git a/src/drivers/tpm/Kconfig b/src/drivers/tpm/Kconfig index 8508210..d3d343c 100644 --- a/src/drivers/tpm/Kconfig +++ b/src/drivers/tpm/Kconfig @@ -5,3 +5,14 @@ help This driver automatically initializes the TPM if vboot is not used. The TPM driver init is done during the ramstage chip init phase. + +config TPM_PPI + bool "TPM: Generate ACPI code for physical presence interface" + depends on TPM1 || TPM2 + depends on HAVE_ACPI_TABLES + depends on !CHROMEOS + default y if PAYLOAD_TIANOCORE || PAYLOAD_SEABIOS + help + This driver automatically generates ACPI tables for the Physical + Presence Interface defined by the Tcg. If not activated only a Stub + will be generated without any functionality. diff --git a/src/drivers/tpm/Makefile.inc b/src/drivers/tpm/Makefile.inc index 5fc4632..af6e5a21 100644 --- a/src/drivers/tpm/Makefile.inc +++ b/src/drivers/tpm/Makefile.inc @@ -1,3 +1,7 @@ ramstage-$(CONFIG_TPM_INIT) += tpm.c +ifeq ($(CONFIG_TPM_PPI),y) +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ppi.c +else ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ppi_stub.c +endif diff --git a/src/drivers/tpm/ppi.c b/src/drivers/tpm/ppi.c new file mode 100644 index 0000000..7665973 --- /dev/null +++ b/src/drivers/tpm/ppi.c @@ -0,0 +1,624 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include <stddef.h> +#include <acpi/acpi.h> +#include <acpi/acpigen.h> +#include <acpi/acpi_device.h> +#include <cbmem.h> +#include <console/console.h> + +#include "tpm_ppi.h" + +/* This file contains PPI functions only, but no ACPI code! */ + +static void set_package_element_op(const char *package_name, unsigned int element, + uint8_t src_op) +{ + acpigen_write_store(); + acpigen_emit_byte(src_op); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring(package_name); + acpigen_write_integer(element); + acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */ +} + +static void set_package_element_name(const char *package_name, unsigned int element, + const char *src) +{ + acpigen_write_store(); + acpigen_emit_namestring(src); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring(package_name); + acpigen_write_integer(element); + acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */ +} + +/* PPI function is passed in src_op. Converted to Local2. Clobbers Local1 and Local2 */ +static void verify_supported_ppi(uint8_t src_op) +{ + /* + * Old OS incorrectly pass a Buffer instead of a Package. + * See Tcg Physical Presence Interface Specification Chapter 8.1.2 for details. + */ + + /* If (ObjectType(Arg3) == Package) */ + acpigen_write_store(); + acpigen_emit_byte(OBJ_TYPE_OP); + acpigen_emit_byte(src_op); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_if_lequal_op_int(LOCAL1_OP, 4); + acpigen_get_package_op_element(src_op, 0, LOCAL2_OP); + acpigen_pop_len(); + + /* If (ObjectType(Arg3) == Buffer) */ + acpigen_write_store(); + acpigen_emit_byte(OBJ_TYPE_OP); + acpigen_emit_byte(src_op); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_if_lequal_op_int(LOCAL1_OP, 3); + acpigen_write_to_integer(src_op, LOCAL2_OP); + acpigen_pop_len(); + + /* Check if it's a valid PPI function */ + acpigen_write_store(); + acpigen_emit_namestring("^FSUP"); + acpigen_emit_byte(LOCAL2_OP); + acpigen_emit_byte(CONFIG(TPM1) ? ONE_OP : ZERO_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_if_lequal_op_int(LOCAL1_OP, 0); + + /* + * Note: Must fake success for 1-4, 6-13, 15-16, 19-20 + * see "Trusted Execution Environment ACPI Profile" + * + * Even if not available, the TPM 1.2 PPI must be advertised as + * supported. Tests showed that Windows relies on it, even when + * a TPM2.0 is present! + * The functions aren't actually used when a TPM2.0 is present... + * Without this the Windows TPM 2.0 stack refuses to work. + */ + + /* + * Check if we have TPM1.2 but a TPM2 PPI function was called + * or if we have TPM2.0 but a TPM1.2 PPI function was called. + */ + acpigen_write_store(); + acpigen_emit_namestring("^FSUP"); + acpigen_emit_byte(LOCAL2_OP); + acpigen_emit_byte(CONFIG(TPM1) ? ZERO_OP : ONE_OP); + acpigen_emit_byte(LOCAL1_OP); + + acpigen_write_if_lequal_op_int(LOCAL1_OP, 1); + acpigen_write_return_integer(0); /* Fake Success, as per TPM spec */ + acpigen_pop_len(); + acpigen_write_return_integer(1); /* Not supported */ + + acpigen_pop_len(); +} + +/* TPM PPI functions */ + +static void tpm_ppi_func0_cb(void *arg) +{ + /* Functions 1-8. */ + u8 buf[] = {0xff, 0x01}; + acpigen_write_return_byte_buffer(buf, 2); +} + + /* + * PPI 1.0: 2.1.1 Get Physical Presence Interface Version + * + * Arg2 (Integer): Function Index = 1 + * Arg3 (Package): Arguments = Empty Package + * + * Returns: Type: String + */ +static void tpm_ppi_func1_cb(void *arg) +{ + if (CONFIG(TPM2)) + /* Interface version: 1.3 */ + acpigen_write_return_string("1.3"); + else + /* Interface version: 1.2 */ + acpigen_write_return_string("1.2"); +} + +/* + * Submit TPM Operation Request to Pre-OS Environment [Windows optional] + * PPI 1.0: 2.1.3 Submit TPM Operation Request to Pre-OS Environment + * + * Supported Revisions: 1 + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 2 + * Arg3 (Package): Arguments = Package: Type: Integer + * Operation Value of the Request + * + * Returns: Type: Integer + * 0: Success + * 1: Operation Value of the Request Not Supported + * 2: General Failure + */ +static void tpm_ppi_func2_cb(void *arg) +{ + /* Revision 1 */ + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + + /* Local2 = ConvertAndVerify(Arg3) */ + verify_supported_ppi(ARG3_OP); + + acpigen_write_store_op_to_namestr(LOCAL2_OP, "^CMDR"); + acpigen_write_store_op_to_namestr(ZERO_OP, "^OARG"); + acpigen_write_store_op_to_namestr(ZERO_OP, "^USER"); + + acpigen_write_return_integer (0); /* Success */ + acpigen_pop_len(); + + acpigen_write_return_integer(2); /* General Failure */ +} + +/* + * PPI 1.0: 2.1.4 Get Pending TPM Operation Requested By the OS + * + * Supported Revisions: 1, 2 + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 3 + * Arg3 (Package): Empty package + * + * Returns: Type: Package(Integer, Integer, Integer (optional)) + * Integer 1: + * 0: Success + * 1: General Failure + * Integer 2: + * Pending TPM operation requested by OS + * Integer 3: + * Pending TPM operation argument requested by OS + */ +static void tpm_ppi_func3_cb(void *arg) +{ + /* ^TPM3 [0] = One */ + set_package_element_op("^TPM3", 0, ONE_OP); + + /* ^TPM2 [0] = One */ + set_package_element_op("^TPM2", 0, ONE_OP); + + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + + /* Revision 1 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + + /* ^TPM2 [0] = Zero */ + set_package_element_op("^TPM2", 0, ZERO_OP); + + /* ^TPM2 [1] = ^CMDR */ + set_package_element_name("^TPM2", 1, "^CMDR"); + + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("^TPM2"); + acpigen_pop_len(); + + /* + * A return value of {0, 23, 1} indicates that operation 23 + * with argument 1 is pending. + */ + + /* Revision 2 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 2); + + /* ^TPM3 [0] = Zero */ + set_package_element_op("^TPM3", 0, ZERO_OP); + + /* ^TPM3 [1] = ^CMDR */ + set_package_element_name("^TPM3", 1, "^CMDR"); + + /* ^TPM3 [2] = ^OARG */ + set_package_element_name("^TPM3", 2, "^OARG"); + + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("^TPM3"); + acpigen_pop_len(); + + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("^TPM3"); +} + +/* + * PPI 1.0: 2.1.5 Get Platform-Specific Action to Transition to Pre-OS Environment + * + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 4 + * Arg3 (Package): Empty package + * + * Returns: Type: Integer + * 0: None + * 1: Shutdown + * 2: Reboot + * 3: Vendor specific + */ +static void tpm_ppi_func4_cb(void *arg) +{ + /* Pre-OS transition method: reboot. */ + acpigen_write_return_byte(2); +} + +/* + * PPI 1.0: 2.1.6 Return TPM Operation Response to OS Environment + * + * Supported Revisions: 1 + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 5 + * Arg3 (Package): Empty package + * + * Returns: Type: Package(Integer, Integer, Integer) + * Integer 1: + * 0: Success + * 1: General Failure + * Integer 2: + * Most recent TPM operation requested by OS + * Integer 3: + * Response to most recent TPM operation requested by OS + */ +static void tpm_ppi_func5_cb(void *arg) +{ + /* ^TPM3 [0] = One */ + set_package_element_op("^TPM3", 0, ONE_OP); + + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + + /* Revision 1 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + + /* ^TPM3 [0] = Zero */ + set_package_element_op("^TPM3", 0, ZERO_OP); + + /* ^TPM3 [1] = ^LCMD */ + set_package_element_name("^TPM3", 1, "^LCMD"); + + /* ^TPM3 [2] = ^RESU */ + set_package_element_name("^TPM3", 2, "^RESU"); + + acpigen_pop_len(); + + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("^TPM3"); +} + +/* + * PPI 1.2: 2.1.6 Submit preferred user language [Windows optional] + * + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 5 + * Arg3 (Package): Empty package + */ +static void tpm_ppi_func6_cb(void *arg) +{ + /* + * Set preferred user language: deprecated and must return 3 aka + * "not implemented". + */ + acpigen_write_return_byte(3); +} + +/* + * PPI 1.2: 2.1.7 Submit TPM Operation Request to Pre-OS Environment 2 + * + * Supported Revisions: 1, 2 + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 7 + * Arg3 (Package): Integer + * + * Returns: Type: Integer + * 0: Success + * 1: Not implemented + * 2: General Failure + * 3: Blocked by current BIOS settings + */ +static void tpm_ppi_func7_cb(void *arg) +{ + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + + /* Local2 = ConvertAndVerify(Arg3) */ + verify_supported_ppi(ARG3_OP); + + /* If (ObjectType(Arg3) == Buffer) */ + acpigen_write_store(); + acpigen_emit_byte(OBJ_TYPE_OP); + acpigen_emit_byte(ARG3_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_if_lequal_op_int(LOCAL1_OP, 3); + + /* Enforce use of Revision 1 that doesn't take an optional argument. */ + + /* Local0 = One */ + acpigen_write_store(); + acpigen_emit_byte(ONE_OP); + acpigen_emit_byte(LOCAL0_OP); + + acpigen_pop_len(); + + // FIXME: Only advertise supported functions + + /* Revision 1 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + + /* ^CMDR = Local2 */ + acpigen_write_store_op_to_namestr(LOCAL2_OP, "^CMDR"); + + /* ^OARG = Zero */ + acpigen_write_store_op_to_namestr(ZERO_OP, "^OARG"); + + acpigen_write_return_byte(0); /* Success */ + acpigen_pop_len(); + + /* Revision 2 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 2); + /* ^CMDR = Local2 */ + acpigen_write_store_op_to_namestr(LOCAL2_OP, "^CMDR"); + + /* ^OARG = Arg3 [1] */ + acpigen_get_package_op_element(ARG3_OP, 1, LOCAL3_OP); + acpigen_write_store(); + acpigen_emit_byte(LOCAL3_OP); + acpigen_emit_namestring("^OARG"); + + acpigen_write_return_byte(0); /* Success */ + acpigen_pop_len(); + + acpigen_write_return_byte(2); /* General failure */ +} + +/* + * PPI 1.2: 2.1.8 Get User Confirmation Status for Operation + * + * Returns if a command is supported and allowed by firmware + * Supported Revisions: 1 + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 7 + * Arg3 (Package): Integer + * + * Returns: Type: Integer + * 0: Not implemented + * 1: BIOS only + * 2: Blocked for OS by BIOS settings + * 3: Allowed and physical present user required + * 4: Allowed and physical present user not required + */ +static void tpm_ppi_func8_cb(void *arg) +{ + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + + /* Revision 1 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + acpigen_get_package_op_element(ARG3_OP, 0, LOCAL2_OP); + + /* Check if it's a valid PPI function */ + acpigen_write_store(); + acpigen_emit_namestring("^FSUP"); + acpigen_emit_byte(LOCAL2_OP); + acpigen_emit_byte(CONFIG(TPM1) ? ONE_OP : ZERO_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_if_lequal_op_int(LOCAL1_OP, 0); + acpigen_write_return_byte(0); /* Not implemented */ + acpigen_pop_len(); + + // FIXME: Only advertise supported functions + + if (CONFIG(TPM1)) { + /* + * Some functions do not require PP depending on configuration. + * Those aren't listed here, so the 'required PP' is always set for those. + */ + static const u32 tpm1_funcs[] = { + TPM_NOOP, + //FIXME + }; + for (size_t i = 0; i < ARRAY_SIZE(tpm1_funcs); i++) { + acpigen_write_if_lequal_op_int(LOCAL2_OP, tpm1_funcs[i]); + acpigen_write_return_integer(4); /* Supported, requires no PP */ + acpigen_pop_len(); /* Pop : If */ + } + } else if (CONFIG(TPM2)) { + /* + * Some functions do not require PP depending on configuration. + * Those aren't listed here, so the 'required PP' is always set for those. + */ + static const u32 tpm2_funcs[] = { + TPM2_NOOP, + TPM2_SET_PP_REQUIRED_FOR_CLEAR_TRUE, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_TRUE, + TPM2_SET_PP_REQUIRED_FOR_TURN_ON_TRUE, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_TRUE, + TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_TRUE, + TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_TRUE, + TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_TRUE, + }; + for (size_t i = 0; i < ARRAY_SIZE(tpm2_funcs); i++) { + acpigen_write_if_lequal_op_int(LOCAL2_OP, tpm2_funcs[i]); + acpigen_write_return_integer(4); /* Supported, requires no PP */ + acpigen_pop_len(); /* Pop : If */ + } + } + acpigen_write_return_integer(3); /* Supported, requires PP */ + + acpigen_pop_len(); + + acpigen_write_return_byte(0); /* Not implemented */ +} + +static void (*tpm_ppi_callbacks[])(void *) = { + tpm_ppi_func0_cb, + tpm_ppi_func1_cb, + tpm_ppi_func2_cb, + tpm_ppi_func3_cb, + tpm_ppi_func4_cb, + tpm_ppi_func5_cb, + tpm_ppi_func6_cb, + tpm_ppi_func7_cb, + tpm_ppi_func8_cb, +}; + +static void tpm_mci_func0_cb(void *arg) +{ + /* Function 1. */ + acpigen_write_return_singleton_buffer(0x3); +} +static void tpm_mci_func1_cb(void *arg) +{ + /* Just return success. */ + acpigen_write_return_byte(0); +} + +static void (*tpm_mci_callbacks[])(void *) = { + tpm_mci_func0_cb, + tpm_mci_func1_cb, +}; + +void tpm_ppi_acpi_fill_ssdt(const struct device *dev) +{ + u32 arg; + struct cb_tpm_ppi_payload_handshake *ppib; + + static const struct fieldlist list[] = { + FIELDLIST_NAMESTR("CMDR", 32),// The command requested by OS. 0 for NOP + FIELDLIST_NAMESTR("OARG", 32),// The command optional argument requested by OS + FIELDLIST_NAMESTR("LCMD", 32),// The last command requested by OS. + // Copied by firmware on command execution + FIELDLIST_NAMESTR("RESU", 32),// Result of the last operation (TPM error code) + }; + + /* + * On hot reset/ACPI S3 the contents are preserved. + */ + ppib = (void *)cbmem_add(CBMEM_ID_TPM_PPI, sizeof(*ppib)); + if (!ppib) { + printk(BIOS_ERR, "PPI: Failed to add CBMEM\n"); + return; + } + + /* Physical Presence OpRegion */ + struct opregion opreg = OPREGION("PPOP", SYSTEMMEMORY, (uintptr_t)ppib, + sizeof(*ppib)); + + acpigen_write_opregion(&opreg); + acpigen_write_field(opreg.name, list, ARRAY_SIZE(list), + FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); + + acpigen_write_name("TPM2"); + acpigen_write_package(2); + acpigen_write_dword(0); + acpigen_write_dword(0); + acpigen_pop_len(); /* Package */ + + acpigen_write_name("TPM3"); + acpigen_write_package(3); + acpigen_write_dword(0); + acpigen_write_dword(0); + acpigen_write_dword(0); + acpigen_pop_len(); /* Package */ + + /* + * Returns One if the PPI spec supports this functions. + * That doesn't necessarily mean that the firmware implemtents it, or the + * TPM can execute the function. + * + * Arg0: Integer PPI function + * Arg1: Integer TPMversion (0: TPM2, 1: TPM1.2) + */ + acpigen_write_method("FSUP", 2); + + acpigen_write_to_integer(ARG0_OP, LOCAL0_OP); + acpigen_write_to_integer(ARG1_OP, LOCAL1_OP); + acpigen_write_if(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_integer(0x80); + acpigen_write_return_integer(0); + acpigen_pop_len(); /* If */ + + acpigen_write_if_lequal_op_int(LOCAL1_OP, 1); + static const u32 tpm1_funcs[] = { + TPM_NOOP, + TPM_ENABLE, + TPM_DISABLE, + TPM_ACTIVATE, + TPM_DEACTIVATE, + TPM_CLEAR, + TPM_ENABLE_ACTIVATE, + TPM_DEACTIVATE_DISABLE, + TPM_SETOWNERINSTALL_TRUE, + TPM_SETOWNERINSTALL_FALSE, + TPM_ENABLE_ACTIVATE_SETOWNERINSTALL_TRUE, + TPM_SETOWNERINSTALL_FALSE_DEACTIVATE_DISABLE, + TPM_CLEAR_ENABLE_ACTIVATE, + TPM_SET_NOPPIPROVISION_FALSE, + TPM_SET_NOPPIPROVISION_TRUE, + TPM_ENABLE_ACTIVE_CLEAR, + TPM_ENABLE_ACTIVE_CLEAR_ENABLE_ACTIVE, + }; + for (size_t i = 0; i < ARRAY_SIZE(tpm1_funcs); i++) { + acpigen_write_if_lequal_op_int(LOCAL0_OP, tpm1_funcs[i]); + acpigen_write_return_integer(1); + acpigen_pop_len(); /* Pop : If */ + } + acpigen_pop_len(); /* If */ + + acpigen_write_if_lequal_op_int(LOCAL1_OP, 0); + static const u32 tpm2_funcs[] = { + TPM2_NOOP, + TPM2_ENABLE, + TPM2_DISABLE, + TPM2_CLEAR, + TPM2_CLEAR_ENABLE_ACTIVE, + TPM2_SET_PP_REQUIRED_FOR_CLEAR_TRUE, + TPM2_SET_PP_REQUIRED_FOR_CLEAR_FALSE, + TPM2_ENABLE_CLEAR, + TPM2_ENABLE_CLEAR2, + TPM2_SET_PCR_BANKS, + TPM2_CHANGE_EPS, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_FALSE, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_TRUE, + TPM2_SET_PP_REQUIRED_FOR_TURN_ON_FALSE, + TPM2_SET_PP_REQUIRED_FOR_TURN_ON_TRUE, + TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_FALSE, + TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_TRUE, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_FALSE, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_TRUE, + TPM2_LOG_ALL_DIGEST, + TPM2_DISABLE_ENDORSMENT_ENABLE_STORAGE_HISTORY, + TPM2_ENABLE_BLOCK_SID, + TPM2_DISABLE_BLOCK_SID, + TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_TRUE, + TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_FALSE, + TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_TRUE, + TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_FALSE, + }; + + for (size_t i = 0; i < ARRAY_SIZE(tpm2_funcs); i++) { + acpigen_write_if_lequal_op_int(LOCAL0_OP, tpm2_funcs[i]); + acpigen_write_return_integer(1); + acpigen_pop_len(); /* Pop : If */ + } + acpigen_pop_len(); /* If */ + + acpigen_write_return_integer(0); + acpigen_pop_len(); /* Method */ + + /* + * _DSM method + */ + struct dsm_uuid ids[] = { + /* Physical presence interface. + * This is used to submit commands like "Clear TPM" to + * be run at next reboot provided that user confirms + * them. + */ + DSM_UUID(TPM_PPI_UUID, &tpm_ppi_callbacks[0], + ARRAY_SIZE(tpm_ppi_callbacks), (void *) &arg), + /* Memory clearing on boot: just a dummy. */ + DSM_UUID(TPM_MCI_UUID, &tpm_mci_callbacks[0], + ARRAY_SIZE(tpm_mci_callbacks), (void *) &arg), + }; + + acpigen_write_dsm_uuid_arr(ids, ARRAY_SIZE(ids)); +} diff --git a/src/drivers/tpm/tpm_ppi.h b/src/drivers/tpm/tpm_ppi.h index 4bacbe5..4a61a38 100644 --- a/src/drivers/tpm/tpm_ppi.h +++ b/src/drivers/tpm/tpm_ppi.h @@ -18,4 +18,96 @@ /* TCG Memory Clear Interface */ #define TPM_MCI_UUID "376054ed-cc13-4675-901c-4756d7f2d45d" +/* + * Physical Presence Interface Specification Version 1.30 Revision 00.52 + * Table 1 Physical Presence Interface Operation Summary for TPM 1.2 + */ +#define TPM_NOOP 0 +#define TPM_ENABLE 1 +#define TPM_DISABLE 2 +#define TPM_ACTIVATE 3 +#define TPM_DEACTIVATE 4 +#define TPM_CLEAR 5 +#define TPM_ENABLE_ACTIVATE 6 +#define TPM_DEACTIVATE_DISABLE 7 +#define TPM_SETOWNERINSTALL_TRUE 8 +#define TPM_SETOWNERINSTALL_FALSE 9 +#define TPM_ENABLE_ACTIVATE_SETOWNERINSTALL_TRUE 10 +#define TPM_SETOWNERINSTALL_FALSE_DEACTIVATE_DISABLE 11 +#define TPM_CLEAR_ENABLE_ACTIVATE 14 +#define TPM_SET_NOPPIPROVISION_FALSE 15 +#define TPM_SET_NOPPIPROVISION_TRUE 16 +#define TPM_SET_NOPPICLEAR_FALSE 17 +#define TPM_SET_NOPPICLEAR_TRUE 18 +#define TPM_SET_NOPPIMAINTAINANCE_FALSE 19 +#define TPM_SET_NOPPIMAINTAINANCE_TRUE 20 +#define TPM_ENABLE_ACTIVE_CLEAR 21 +#define TPM_ENABLE_ACTIVE_CLEAR_ENABLE_ACTIVE 22 + +/* + * Physical Presence Interface Specification Version 1.30 Revision 00.52 + * Table 2 Physical Presence Interface Operation Summary for TPM 2.0 + */ +#define TPM2_NOOP 0 +#define TPM2_ENABLE 1 +#define TPM2_DISABLE 2 +#define TPM2_CLEAR 5 +#define TPM2_CLEAR_ENABLE_ACTIVE 14 +#define TPM2_SET_PP_REQUIRED_FOR_CLEAR_TRUE 17 +#define TPM2_SET_PP_REQUIRED_FOR_CLEAR_FALSE 18 +#define TPM2_ENABLE_CLEAR 21 +#define TPM2_ENABLE_CLEAR2 22 +#define TPM2_SET_PCR_BANKS 23 +#define TPM2_CHANGE_EPS 24 +#define TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_FALSE 25 +#define TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_TRUE 26 +#define TPM2_SET_PP_REQUIRED_FOR_TURN_ON_FALSE 27 +#define TPM2_SET_PP_REQUIRED_FOR_TURN_ON_TRUE 28 +#define TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_FALSE 29 +#define TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_TRUE 30 +#define TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_FALSE 31 +#define TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_TRUE 32 +#define TPM2_LOG_ALL_DIGEST 33 +#define TPM2_DISABLE_ENDORSMENT_ENABLE_STORAGE_HISTORY 34 +#define TPM2_ENABLE_BLOCK_SID 96 +#define TPM2_DISABLE_BLOCK_SID 97 +#define TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_TRUE 98 +#define TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_FALSE 99 +#define TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_TRUE 100 +#define TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_FALSE 101 + +/* TCG Physical Presence Interface */ +#define TPM_PPI_UUID "3dddfaa6-361b-4eb4-a424-8d10089d1653" +/* TCG Memory Clear Interface */ +#define TPM_MCI_UUID "376054ed-cc13-4675-901c-4756d7f2d45d" + +struct cb_tpm_ppi_payload_handshake { +#if 0 + //FIXME: filled by firmware that executes the PPI + /* + * Bitmask of supported PPI operations that doesn't require physical presence. + * To be set by firmware. + */ + u64 supported_functions1; + u64 supported_functions2; + /* + * Bitmask of supported PPI operations that require physical presence + * (due to user configuration). To be set by firmware. + */ + u64 supported_functions_pp1; + u64 supported_functions_pp2; +#endif + /* To be executed by firmware if user_fb_done and ppi_supported and + * user_fb_result is set. */ + u32 request; + /* To be executed by firmware if user_fb_done and ppi_supported and + * user_fb_result is set. */ + u32 request_argument; + /* Cleared on cold boot. Copy of request once firmware 'executed' the + * command. */ + u32 last_request; + /* Result of the requested command. Can also be a failure. */ + u32 last_result; +} __packed; + #endif /* _TPM_PPI_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifffe1d9b715e2c37568e1b009e86c298025c89ac Gerrit-Change-Number: 45568 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 18

Change in coreboot[master]: drivers/tpm/ppi_stub: Fix interface version
by Patrick Rudolph (Code Review) 21 Dec '20

21 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45569 ) Change subject: drivers/tpm/ppi_stub: Fix interface version ...................................................................... drivers/tpm/ppi_stub: Fix interface version The latest version defined by Tcg is 1.3. Change-Id: Idb12e2212d6d38c720c8fe989678724c871af6ef Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/tpm/ppi_stub.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/45569/1 diff --git a/src/drivers/tpm/ppi_stub.c b/src/drivers/tpm/ppi_stub.c index a4b8f57..a5d0252 100644 --- a/src/drivers/tpm/ppi_stub.c +++ b/src/drivers/tpm/ppi_stub.c @@ -20,7 +20,7 @@ { if (CONFIG(TPM2)) /* Interface version: 2.0 */ - acpigen_write_return_string("2.0"); + acpigen_write_return_string("1.3"); else /* Interface version: 1.2 */ acpigen_write_return_string("1.2"); -- To view, visit https://review.coreboot.org/c/coreboot/+/45569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb12e2212d6d38c720c8fe989678724c871af6ef Gerrit-Change-Number: 45569 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: drivers/ipmi: Avoid NULL pointer dereference
by Harshit Sharma (Code Review) 21 Dec '20

21 Dec '20

Harshit Sharma has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41654 ) Change subject: drivers/ipmi: Avoid NULL pointer dereference ...................................................................... drivers/ipmi: Avoid NULL pointer dereference There are multiple instances where NULL pointer conf could be dereferenced. This patch fixes those issues. Found-by: Coverity Scan #1407751, #1428709, #1428710, #1428714 Signed-off-by: Harshit Sharma <harshitsharmajs(a)gmail.com> Change-Id: I2d1cfe3f9b55288eeb55ab8785d857993e3989c0 --- M src/drivers/ipmi/ipmi_kcs_ops.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/41654/1 diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 0b90fb2..e43f3a5 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -84,6 +84,9 @@ if (dev->chip_info) conf = dev->chip_info; + if (!conf) + return; + /* Get IPMI version for ACPI and SMBIOS */ if (conf && conf->wait_for_bmc && conf->bmc_boot_timeout) { struct stopwatch sw; @@ -200,6 +203,9 @@ if (dev->chip_info) conf = dev->chip_info; + if (!conf) + return 0; + if (conf) { if (conf->have_gpe) gpe_interrupt = conf->gpe_interrupt; @@ -234,6 +240,9 @@ if (dev->chip_info) conf = dev->chip_info; + if (!conf) + return; + /* Use command to pass UID to ipmi_write_acpi_tables */ conf->uid = uid_cnt++; -- To view, visit https://review.coreboot.org/c/coreboot/+/41654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d1cfe3f9b55288eeb55ab8785d857993e3989c0 Gerrit-Change-Number: 41654 Gerrit-PatchSet: 1 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: autoport: Add a license header to non-empty asl files
by Iru Cai (vimacs) (Code Review) 17 Dec '20

17 Dec '20

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45464 to review the following change. Change subject: autoport: Add a license header to non-empty asl files ...................................................................... autoport: Add a license header to non-empty asl files Change-Id: I8078d8babf24feabb22856ee820ab45b7d466f62 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/autoport/ec_fixme.go M util/autoport/ec_lenovo.go M util/autoport/ec_none.go M util/autoport/main.go 4 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/45464/1 diff --git a/util/autoport/ec_fixme.go b/util/autoport/ec_fixme.go index f5d039c..54f78ab 100644 --- a/util/autoport/ec_fixme.go +++ b/util/autoport/ec_fixme.go @@ -19,6 +19,7 @@ SouthBridge.EnableGPE(SouthBridge.DecodeGPE(sbGPE)) } + Add_gpl(ap) ap.WriteString( `Method(_WAK, 1) { @@ -64,6 +65,7 @@ defer si.Close() if hasKeyboard { + Add_gpl(si) si.WriteString("#include <drivers/pc80/pc/ps2_controller.asl>\n") MainboardInit += fmt.Sprintf("\tpc_keyboard_init(NO_AUX_DEVICE);\n") MainboardIncludes = append(MainboardIncludes, "pc80/keyboard.h") @@ -72,6 +74,7 @@ ec := Create(ctx, "acpi/ec.asl") defer ec.Close() + Add_gpl(ec) ec.WriteString(`Device(EC) { Name (_HID, EISAID("PNP0C09")) diff --git a/util/autoport/ec_lenovo.go b/util/autoport/ec_lenovo.go index 6851d6d..763ac26 100644 --- a/util/autoport/ec_lenovo.go +++ b/util/autoport/ec_lenovo.go @@ -39,6 +39,7 @@ Value: "1", }, GPEDefine) + Add_gpl(ap) ap.WriteString( `Method(_WAK, 1) { @@ -57,6 +58,7 @@ si := Create(ctx, "acpi/superio.asl") defer si.Close() + Add_gpl(si) si.WriteString("#include <drivers/pc80/pc/ps2_controller.asl>\n") /* FIXME:XX Move this to ec/lenovo. */ @@ -163,6 +165,7 @@ ec := Create(ctx, "acpi/ec.asl") defer ec.Close() + Add_gpl(ec) ec.WriteString("#include <ec/lenovo/h8/acpi/ec.asl>\n") KconfigBool["EC_LENOVO_PMH7"] = true diff --git a/util/autoport/ec_none.go b/util/autoport/ec_none.go index eb2b87c..bcb61bf 100644 --- a/util/autoport/ec_none.go +++ b/util/autoport/ec_none.go @@ -4,6 +4,7 @@ ap := Create(ctx, "acpi/platform.asl") defer ap.Close() + Add_gpl(ap) ap.WriteString( `Method(_WAK, 1) { diff --git a/util/autoport/main.go b/util/autoport/main.go index 1a9050a..e8436bd 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -825,9 +825,9 @@ dsdt.WriteString("#define " + define.Key + " " + define.Value + "\n") } + Add_gpl(dsdt) dsdt.WriteString( ` - #include <acpi/acpi.h> DefinitionBlock( -- To view, visit https://review.coreboot.org/c/coreboot/+/45464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8078d8babf24feabb22856ee820ab45b7d466f62 Gerrit-Change-Number: 45464 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

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