Hello Duan huayang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/44702
to review the following change.
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
soc/mediatek/mt8192: Do memory pll init before calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 --- M src/soc/mediatek/mt8192/dramc_pi_main.c 1 file changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/1
diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index e2c7500..c36ff43 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -2,6 +2,8 @@
#include <soc/dramc_pi_api.h> #include <soc/dramc_register.h> +#include <soc/pll.h> +#include <soc/pll_common.h> #include <soc/mt6359p.h>
static void set_vcore_voltage_for_each_freq(const struct ddr_cali *cali) @@ -16,6 +18,34 @@ { }
+static void mem_pll_init(void) +{ + unsigned int tmp; + + write32(&mtk_apmixed->mpll_con3, 0x3); + + udelay(30); + tmp = read32(&mtk_apmixed->mpll_con3); + write32(&mtk_apmixed->mpll_con3, tmp & 0xfffffffd); + + udelay(1); + write32(&mtk_apmixed->mpll_con1, 0x84200000); + tmp = read32(&mtk_apmixed->mpll_con0); + write32(&mtk_apmixed->mpll_con0, tmp | 0x1); + + udelay(20); + tmp = read32(&mtk_apmixed->pllon_con0); + write32(&mtk_apmixed->pllon_con0, tmp & ~(0x1 << 2)); + tmp = read32(&mtk_apmixed->pllon_con0); + write32(&mtk_apmixed->pllon_con0, tmp & ~(0x1 << 11)); + tmp = read32(&mtk_apmixed->pllon_con1); + write32(&mtk_apmixed->pllon_con1, tmp & ~(0x1 << 20)); + tmp = read32(&mtk_apmixed->pllon_con2); + write32(&mtk_apmixed->pllon_con2, tmp & ~(0x1 << 2)); + tmp = read32(&mtk_apmixed->pllon_con3); + write32(&mtk_apmixed->pllon_con3, tmp & ~(0x1 << 2)); +} + void init_dram(const struct dramc_data *dparam) { u32 bc_bak; @@ -35,6 +65,7 @@ cali.emi_config = &ddr_info->emi_config;
dramc_set_broadcast(DRAMC_BROADCAST_ON); + mem_pll_init();
global_option_init(&cali); bc_bak = dramc_get_broadcast();
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44702/2/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44702/2/src/soc/mediatek/mt8192/dra... PS2, Line 23: unsigned int u32
Yidi Lin has uploaded a new patch set (#3) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
soc/mediatek/mt8192: Do memory pll init before calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 --- M src/soc/mediatek/mt8192/dramc_pi_main.c 1 file changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/3
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44702/2/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44702/2/src/soc/mediatek/mt8192/dra... PS2, Line 23: unsigned int
u32
Ack
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44702/6/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44702/6/src/soc/mediatek/mt8192/dra... PS6, Line 28: tmp = read32(&mtk_apmixed->mpll_con3); : write32(&mtk_apmixed->mpll_con3, tmp & 0xfffffffd); Could we use the SET32_BITFIELDS API? Or at least clrsetbits32?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44702/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44702/6//COMMIT_MSG@8 PS6, Line 8: Please elaborate. What did improve thank to PLL initialization?
Yidi Lin has uploaded a new patch set (#24) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
soc/mediatek/mt8192: Do memory pll init before calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 --- M src/soc/mediatek/mt8192/dramc_pi_main.c 1 file changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/24
Yidi Lin has uploaded a new patch set (#34) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
soc/mediatek/mt8192: Do memory pll init before calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 --- M src/soc/mediatek/mt8192/dramc_pi_main.c 1 file changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/34
Yidi Lin has uploaded a new patch set (#36) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
soc/mediatek/mt8192: Do memory pll init before calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 --- M src/soc/mediatek/mt8192/dramc_pi_main.c 1 file changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/36
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 36: Code-Review+2
Yidi Lin has uploaded a new patch set (#37) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
soc/mediatek/mt8192: Do memory pll init before calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 --- M src/soc/mediatek/mt8192/dramc_pi_main.c 1 file changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/37
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 40:
(3 comments)
https://review.coreboot.org/c/coreboot/+/44702/40/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44702/40/src/soc/mediatek/mt8192/dr... PS40, Line 28: tmp = read32(&mtk_apmixed->mpll_con3); : write32(&mtk_apmixed->mpll_con3, tmp & 0xfffffffd); Use clrsetbits32()
https://review.coreboot.org/c/coreboot/+/44702/40/src/soc/mediatek/mt8192/dr... PS40, Line 33: tmp = read32(&mtk_apmixed->mpll_con0); : write32(&mtk_apmixed->mpll_con0, tmp | 0x1); Use clrsetbits32()
https://review.coreboot.org/c/coreboot/+/44702/40/src/soc/mediatek/mt8192/dr... PS40, Line 37: tmp = read32(&mtk_apmixed->pllon_con0); : write32(&mtk_apmixed->pllon_con0, tmp & ~(0x1 << 2)); Use clrsetbits32(). Same below.
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 41:
(3 comments)
https://review.coreboot.org/c/coreboot/+/44702/40/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44702/40/src/soc/mediatek/mt8192/dr... PS40, Line 28: tmp = read32(&mtk_apmixed->mpll_con3); : write32(&mtk_apmixed->mpll_con3, tmp & 0xfffffffd);
Use clrsetbits32()
Ack
https://review.coreboot.org/c/coreboot/+/44702/40/src/soc/mediatek/mt8192/dr... PS40, Line 33: tmp = read32(&mtk_apmixed->mpll_con0); : write32(&mtk_apmixed->mpll_con0, tmp | 0x1);
Use clrsetbits32()
Ack
https://review.coreboot.org/c/coreboot/+/44702/40/src/soc/mediatek/mt8192/dr... PS40, Line 37: tmp = read32(&mtk_apmixed->pllon_con0); : write32(&mtk_apmixed->pllon_con0, tmp & ~(0x1 << 2));
Use clrsetbits32(). Same below.
Ack
Xi Chen has uploaded a new patch set (#42) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
soc/mediatek/mt8192: Do memory pll init before calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 --- M src/soc/mediatek/mt8192/dramc_pi_main.c 1 file changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/42
Xi Chen has uploaded a new patch set (#43) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
soc/mediatek/mt8192: Do memory pll init before calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 --- M src/soc/mediatek/mt8192/dramc_pi_main.c 1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/43
Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 43:
@Xi,
Please fix this compilation error.
CC romstage/soc/mediatek/mt8192/dramc_pi_main.o CC romstage/soc/mediatek/mt8192/dramc_utility.o src/soc/mediatek/mt8192/dramc_utility.c: In function 'set_cali_datas': src/soc/mediatek/mt8192/dramc_utility.c:138:40: error: initialization discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers] struct dfs_frequency_table *shuffle = &freq_shuffle_table[k_shu]; ^ src/soc/mediatek/mt8192/dramc_utility.c: At top level:
Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 43:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44702/6/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44702/6/src/soc/mediatek/mt8192/dra... PS6, Line 28: tmp = read32(&mtk_apmixed->mpll_con3); : write32(&mtk_apmixed->mpll_con3, tmp & 0xfffffffd);
Could we use the SET32_BITFIELDS API? Or at least clrsetbits32?
Done
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 43:
Patch Set 43:
@Xi,
Please fix this compilation error.
CC romstage/soc/mediatek/mt8192/dramc_pi_main.o CC romstage/soc/mediatek/mt8192/dramc_utility.osrc/soc/mediatek/mt8192/dramc_utility.c: In function 'set_cali_datas': src/soc/mediatek/mt8192/dramc_utility.c:138:40: error: initialization discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers] struct dfs_frequency_table *shuffle = &freq_shuffle_table[k_shu]; ^ src/soc/mediatek/mt8192/dramc_utility.c: At top level:
https://review.coreboot.org/c/coreboot/+/44701/42 fix it.
Xi Chen has uploaded a new patch set (#45) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
soc/mediatek/mt8192: Do memory pll init before calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 --- M src/soc/mediatek/mt8192/dramc_pi_main.c 1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/45
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 45:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44702/45/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44702/45/src/soc/mediatek/mt8192/dr... PS45, Line 23: 0x3 Please turn this (and following magic numbers) into definition of names.
You can use the SET_BITFIELDS32 API, which will apparently include names for register fields, and then define values for them.
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 45:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44702/45/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44702/45/src/soc/mediatek/mt8192/dr... PS45, Line 23: 0x3
Please turn this (and following magic numbers) into definition of names. […]
Done
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 45:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44702/45/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44702/45/src/soc/mediatek/mt8192/dr... PS45, Line 23: 0x3
Done
Not done?
Xi Chen has uploaded a new patch set (#46) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
soc/mediatek/mt8192: Do memory pll init before calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/dramc_pi_main.c M src/soc/mediatek/mt8192/include/soc/pll.h 3 files changed, 39 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/46
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 46: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/44702/45/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44702/45/src/soc/mediatek/mt8192/dr... PS45, Line 23: 0x3
Not done?
Done
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 46: Code-Review+2
really much easier to review and read now, thanks!
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 46:
- please rebase (it's 'merge conflict' now) - please explain more in the commit description, for example reference to the name of datasheet.
Xi Chen has uploaded a new patch set (#47) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
soc/mediatek/mt8192: Do memory pll init before calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/dramc_pi_main.c M src/soc/mediatek/mt8192/include/soc/pll.h 3 files changed, 39 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/47
Yidi Lin has uploaded a new patch set (#48) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
soc/mediatek/mt8192: Do memory pll init before calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/dramc_pi_main.c M src/soc/mediatek/mt8192/include/soc/pll.h 3 files changed, 39 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/48
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 48:
(2 comments)
build failure, add device/mmio in the header file.
https://review.coreboot.org/c/coreboot/+/44702/48/src/soc/mediatek/common/in... File src/soc/mediatek/common/include/soc/pll_common.h:
https://review.coreboot.org/c/coreboot/+/44702/48/src/soc/mediatek/common/in... PS48, Line 8: Add
#include <device/mmio.h>
https://review.coreboot.org/c/coreboot/+/44702/48/src/soc/mediatek/common/in... PS48, Line 58: DEFINE_BITFIELD for single bits you can do
DEFINE_BIT(PLL_POWER_ENABLE, 0)
(same to PLL_POWER_ENABLE and PLL_ISO_ENABLE)
Xi Chen has uploaded a new patch set (#49) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
soc/mediatek/mt8192: Do memory pll init before calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/dramc_pi_main.c M src/soc/mediatek/mt8192/include/soc/pll.h 3 files changed, 40 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/49
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 49:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44702/48/src/soc/mediatek/common/in... File src/soc/mediatek/common/include/soc/pll_common.h:
https://review.coreboot.org/c/coreboot/+/44702/48/src/soc/mediatek/common/in... PS48, Line 8:
Add […]
Ack
https://review.coreboot.org/c/coreboot/+/44702/48/src/soc/mediatek/common/in... PS48, Line 58: DEFINE_BITFIELD
for single bits you can do […]
Ack
Xi Chen has uploaded a new patch set (#50) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
soc/mediatek/mt8192: Do memory pll init before calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/dramc_pi_main.c M src/soc/mediatek/mt8192/include/soc/pll.h 3 files changed, 40 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/50
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 50:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44702/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44702/6//COMMIT_MSG@8 PS6, Line 8:
Please elaborate. […]
PLL initialization is dramc and ddrphy reference clock, it did the basic clock settings for dramc/ddrphy working well.
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 50:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44702/50//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44702/50//COMMIT_MSG@8 PS50, Line 8: Details about cause, solution and tested?
Xi Chen has uploaded a new patch set (#51) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
soc/mediatek/mt8192: Do memory pll init before calibration
Memory PLL is used to provide the basic clock for dram controller and DDRPHY, PLL must be initialized as predefined way. First, enable PLL POWER and ISO, wait at least 30us, release ISO, then config PLL frequency and enable PLL master switch. At last, enable control ability for SPM to switch between active and idle when system is switched between normal and low power mode.
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/dramc_pi_main.c M src/soc/mediatek/mt8192/include/soc/pll.h 3 files changed, 40 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/51
Xi Chen has uploaded a new patch set (#52) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
soc/mediatek/mt8192: Do memory pll init before calibration
Memory PLL is used to provide the basic clock for dram controller and DDRPHY, PLL must be initialized as predefined way. First, enable PLL POWER and ISO, wait at least 30us, release ISO, then config PLL frequency and enable PLL master switch. At last, enable control ability for SPM to switch between active and idle when system is switched between normal and low power mode.
TEST=Confirm Memory PLL frequency is right by frequency meter
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/dramc_pi_main.c M src/soc/mediatek/mt8192/include/soc/pll.h 3 files changed, 40 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/52
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 52:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44702/50//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44702/50//COMMIT_MSG@8 PS50, Line 8:
Details about cause, solution and tested?
Memory PLL is Dram controller and DDRPHY basic clock control, it should be initialized before dramc init and dram calibration.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 52:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44702/52//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44702/52//COMMIT_MSG@9 PS52, Line 9: Please remove the leading spaces.
https://review.coreboot.org/c/coreboot/+/44702/52//COMMIT_MSG@10 PS52, Line 10: , .
https://review.coreboot.org/c/coreboot/+/44702/52//COMMIT_MSG@12 PS52, Line 12: config configure
https://review.coreboot.org/c/coreboot/+/44702/52//COMMIT_MSG@16 PS52, Line 16: Remove spaces
Xi Chen has uploaded a new patch set (#53) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
soc/mediatek/mt8192: Do memory pll init before calibration
Memory PLL is used to provide the basic clock for dram controller and DDRPHY, PLL must be initialized as predefined way. First, enable PLL POWER and ISO, wait at least 30us, release ISO, then config PLL frequency and enable PLL master switch. At last, enable control ability for SPM to switch between active and idle when system is switched between normal and low power mode.
TEST=Confirm Memory PLL frequency is right by frequency meter
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/dramc_pi_main.c M src/soc/mediatek/mt8192/include/soc/pll.h 3 files changed, 40 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/53
Xi Chen has uploaded a new patch set (#54) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
soc/mediatek/mt8192: Do memory pll init before calibration
Memory PLL is used to provide the basic clock for dram controller and DDRPHY, PLL must be initialized as predefined way. First, enable PLL POWER and ISO, wait at least 30us, release ISO, then config PLL frequency and enable PLL master switch. At last, enable control ability for SPM to switch between active and idle when system is switched between normal and low power mode.
TEST=Confirm Memory PLL frequency is right by frequency meter
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/dramc_pi_main.c M src/soc/mediatek/mt8192/include/soc/pll.h 3 files changed, 40 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/54
Xi Chen has uploaded a new patch set (#55) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
soc/mediatek/mt8192: Do memory pll init before calibration
Memory PLL is used to provide the basic clock for dram controller and DDRPHY. PLL must be initialized as predefined way. First, enable PLL POWER and ISO, wait at least 30us, release ISO, then configure PLL frequency and enable PLL master switch. At last, enable control ability for SPM to switch between active and idle when system is switched between normal and low power mode.
TEST=Confirm Memory PLL frequency is right by frequency meter
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/dramc_pi_main.c M src/soc/mediatek/mt8192/include/soc/pll.h 3 files changed, 40 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/55
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 55:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44702/52//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44702/52//COMMIT_MSG@9 PS52, Line 9:
Please remove the leading spaces.
Ack
https://review.coreboot.org/c/coreboot/+/44702/52//COMMIT_MSG@10 PS52, Line 10: ,
.
Ack
https://review.coreboot.org/c/coreboot/+/44702/52//COMMIT_MSG@12 PS52, Line 12: config
configure
Ack
https://review.coreboot.org/c/coreboot/+/44702/52//COMMIT_MSG@16 PS52, Line 16:
Remove spaces
Ack
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 55: Code-Review+2
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 55: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
soc/mediatek/mt8192: Do memory pll init before calibration
Memory PLL is used to provide the basic clock for dram controller and DDRPHY. PLL must be initialized as predefined way. First, enable PLL POWER and ISO, wait at least 30us, release ISO, then configure PLL frequency and enable PLL master switch. At last, enable control ability for SPM to switch between active and idle when system is switched between normal and low power mode.
TEST=Confirm Memory PLL frequency is right by frequency meter
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44702 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Hung-Te Lin hungte@chromium.org Reviewed-by: Frans Hendriks fhendriks@eltan.com --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/dramc_pi_main.c M src/soc/mediatek/mt8192/include/soc/pll.h 3 files changed, 40 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Frans Hendriks: Looks good to me, approved Hung-Te Lin: Looks good to me, approved
diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index d9ba230..ae6ad64 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -3,6 +3,7 @@ #ifndef SOC_MEDIATEK_PLL_COMMON_H #define SOC_MEDIATEK_PLL_COMMON_H
+#include <device/mmio.h> #include <soc/addressmap.h> #include <types.h>
@@ -54,6 +55,15 @@ .div_rate = _div_rate, \ }
+/* every PLL can share the same POWER_EN/ISO_EN/EN bits, use the common BITFIELD macro */ +DEFINE_BIT(PLL_ENABLE, 0) + +DEFINE_BIT(PLL_POWER_ENABLE, 0) +DEFINE_BIT(PLL_ISO_ENABLE, 1) +DEFINE_BITFIELD(PLL_POWER_ISO_ENABLE, 1, 0) + +DEFINE_BITFIELD(PLL_CON1, 31, 0) + void pll_set_pcw_change(const struct pll *pll); void mux_set_sel(const struct mux *mux, u32 sel); int pll_set_rate(const struct pll *pll, u32 rate); diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index a2a4dea..cdb598f 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -2,6 +2,8 @@
#include <soc/dramc_pi_api.h> #include <soc/dramc_register.h> +#include <soc/pll.h> +#include <soc/pll_common.h> #include <soc/regulator.h>
static void set_vcore_voltage(const struct ddr_cali *cali) @@ -16,6 +18,25 @@ { }
+static void mem_pll_init(void) +{ + SET32_BITFIELDS(&mtk_apmixed->mpll_con3, PLL_POWER_ISO_ENABLE, 3); + + udelay(30); + SET32_BITFIELDS(&mtk_apmixed->mpll_con3, PLL_ISO_ENABLE, 0); + + udelay(1); + SET32_BITFIELDS(&mtk_apmixed->mpll_con1, PLL_CON1, MPLL_CON1_FREQ); + SET32_BITFIELDS(&mtk_apmixed->mpll_con0, PLL_ENABLE, 1); + + udelay(20); + SET32_BITFIELDS(&mtk_apmixed->pllon_con0, MPLL_IOS_SEL, 0); + SET32_BITFIELDS(&mtk_apmixed->pllon_con0, MPLL_EN_SEL, 0); + SET32_BITFIELDS(&mtk_apmixed->pllon_con1, MPLL_PWR_SEL, 0); + SET32_BITFIELDS(&mtk_apmixed->pllon_con2, MPLL_BY_ISO_DLY, 0); + SET32_BITFIELDS(&mtk_apmixed->pllon_con3, MPLL_BY_PWR_DLY, 0); +} + void init_dram(const struct dramc_data *dparam) { u32 bc_bak; @@ -35,6 +56,7 @@ cali.emi_config = &ddr_info->emi_config;
dramc_set_broadcast(DRAMC_BROADCAST_ON); + mem_pll_init();
global_option_init(&cali); bc_bak = dramc_get_broadcast(); diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index 52bf3c2..cd1c012 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -241,6 +241,8 @@ check_member(mtk_apmixed_regs, ap_pllgp2_con0, 0x0300); check_member(mtk_apmixed_regs, usbpll_con2, 0x03cc);
+#define MPLL_CON1_FREQ 0x84200000 + enum { USBPLL_EN = 0x1 << 2,
@@ -306,6 +308,12 @@ DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16)
+DEFINE_BIT(MPLL_IOS_SEL, 2) +DEFINE_BIT(MPLL_EN_SEL, 11) +DEFINE_BIT(MPLL_PWR_SEL, 20) +DEFINE_BIT(MPLL_BY_ISO_DLY, 2) +DEFINE_BIT(MPLL_BY_PWR_DLY, 2) + DEFINE_BITFIELD(WDT_SWSYSRST_KEY, 31, 24) DEFINE_BITFIELD(WDT_SWSYSRST_CONN_MCU, 12, 12)
-
CK HU (Code Review) -
Frans Hendriks (Code Review)
-
Hung-Te Lin (Code Review)
-
Paul Menzel (Code Review)
-
Xi Chen (Code Review)
-
Yidi Lin (Code Review)
-
Yu-Ping Wu (Code Review)