Xi Chen uploaded patch set #52 to the change originally created by CK HU.

View Change

soc/mediatek/mt8192: Do memory pll init before calibration

  Memory PLL is used to provide the basic clock for dram controller
and DDRPHY, PLL must be initialized as predefined way.
  First, enable PLL POWER and ISO, wait at least 30us, release ISO, then
config PLL frequency and enable PLL master switch.
  At last, enable control ability for SPM to switch between active and
idle when system is switched between normal and low power mode.

  TEST=Confirm Memory PLL frequency is right by frequency meter

Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6
---
M src/soc/mediatek/common/include/soc/pll_common.h
M src/soc/mediatek/mt8192/dramc_pi_main.c
M src/soc/mediatek/mt8192/include/soc/pll.h
3 files changed, 40 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/52

To view, visit change 44702. To unsubscribe, or for help writing mail filters, visit settings.