coreboot-gerrit September 2020

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Change in coreboot[master]: arch/x86/car.ld: Assert at buildtime that _ecar_stack is aligned
by Arthur Heymans (Code Review) 06 Jan '21

06 Jan '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37367 ) Change subject: arch/x86/car.ld: Assert at buildtime that _ecar_stack is aligned ...................................................................... arch/x86/car.ld: Assert at buildtime that _ecar_stack is aligned This can be used to avoid aligning the stack at runtime. Change-Id: I3aa068d947b6b6110fd7d002522f28a13e725cf7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/car.ld 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37367/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 483a908..2d1723e 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -124,3 +124,4 @@ #if !CONFIG(ROMCC_BOOTBLOCK) _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); #endif +_bogus4 = ASSERT(_ecar_stack == ((_ecar_stack + 0xf) & ~0xf), "_ecar_stack must be 16 aligned"); -- To view, visit https://review.coreboot.org/c/coreboot/+/37367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3aa068d947b6b6110fd7d002522f28a13e725cf7 Gerrit-Change-Number: 37367 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros
by Maxim Polyakov (Code Review) 05 Jan '21

05 Jan '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43411 ) Change subject: mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros ...................................................................... mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros Use the intelp2m utility [1,2] to convert the current pad configuration format to the format with the the PAD_CFG() macros (*). $ ./intelp2m -n -t 1 -p snr -file src/mainboard/51nb/x210/gpio.h Unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. [*] To do this, ignore some bit fields. See Patchset 1 | Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/razer/blade_stealth_kbl/gpio.h 1 file changed, 152 insertions(+), 152 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/43411/1 diff --git a/src/mainboard/razer/blade_stealth_kbl/gpio.h b/src/mainboard/razer/blade_stealth_kbl/gpio.h index c266dde..f8f5b08 100644 --- a/src/mainboard/razer/blade_stealth_kbl/gpio.h +++ b/src/mainboard/razer/blade_stealth_kbl/gpio.h @@ -10,158 +10,158 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { - /* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0), - /* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), - /* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), - /* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), - /* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), - /* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), - /* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A7, 0x84000102, 0x0), - /* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000702, 0x0), - /* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), - /* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A11, 0x40100102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x04000201, 0x0), - /* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), - /* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), - /* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x1000), - /* SD_1P8_SEL */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x0), - /* SD_PWR_EN# */ _PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0), - /* ISH_GP0 */ _PAD_CFG_STRUCT(GPP_A18, 0x44000702, 0x0), - /* ISH_GP1 */ _PAD_CFG_STRUCT(GPP_A19, 0x44000702, 0x0), - /* ISH_GP2 */ _PAD_CFG_STRUCT(GPP_A20, 0x44000702, 0x0), - /* ISH_GP3 */ _PAD_CFG_STRUCT(GPP_A21, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x40100102, 0x0), - /* CORE_VID0 */ _PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), - /* CORE_VID1 */ _PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), - /* VRALERT# */ _PAD_CFG_STRUCT(GPP_B2, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x80100100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0), - /* SRCCLKREQ0# */ _PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0), - /* SRCCLKREQ1# */ _PAD_CFG_STRUCT(GPP_B6, 0x44000700, 0x0), - /* SRCCLKREQ2# */ _PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B8, 0x44000300, 0x0), - /* SRCCLKREQ4# */ _PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B10, 0x44000300, 0x0), - /* EXT_PWR_GATE# */ _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), - /* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0), - /* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x42880100, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x80880102, 0x3000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x0), - /* GSPI1_CLK */ _PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000), - /* GSPI1_MISO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000), - /* GSPI1_MOSI */ _PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), - /* SMBCLK */ _PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), - /* SMBDATA */ _PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), - /* SML0CLK */ _PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x0), - /* SML0DATA */ _PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x40900100, 0x1000), - /* RESERVED */ _PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), - /* RESERVED */ _PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), - /* UART0_RXD */ _PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x0), - /* UART0_TXD */ _PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), - /* UART0_RTS# */ _PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), - /* UART0_CTS# */ _PAD_CFG_STRUCT(GPP_C11, 0x44000700, 0x0), - /* UART1_RXD */ _PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0), - /* UART1_TXD */ _PAD_CFG_STRUCT(GPP_C13, 0x44000700, 0x0), - /* UART1_RTS# */ _PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), - /* UART1_CTS# */ _PAD_CFG_STRUCT(GPP_C15, 0x44000702, 0x0), - /* I2C0_SDA */ _PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x0), - /* I2C0_SCL */ _PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x0), - /* I2C1_SDA */ _PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0), - /* I2C1_SCL */ _PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0), - /* UART2_RXD */ _PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), - /* UART2_TXD */ _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), - /* UART2_RTS# */ _PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), - /* UART2_CTS# */ _PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), - /* SPI1_CS# */ _PAD_CFG_STRUCT(GPP_D0, 0x44000700, 0x0), - /* SPI1_CLK */ _PAD_CFG_STRUCT(GPP_D1, 0x44000700, 0x0), - /* SPI1_MISO */ _PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), - /* SPI1_MOSI */ _PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), - /* FLASHTRIG */ _PAD_CFG_STRUCT(GPP_D4, 0x44000700, 0x0), - /* ISH_I2C0_SDA */ _PAD_CFG_STRUCT(GPP_D5, 0x44000700, 0x0), - /* ISH_I2C0_SCL */ _PAD_CFG_STRUCT(GPP_D6, 0x44000700, 0x0), - /* ISH_I2C1_SDA */ _PAD_CFG_STRUCT(GPP_D7, 0x44000700, 0x0), - /* ISH_I2C1_SCL */ _PAD_CFG_STRUCT(GPP_D8, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x40000100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x40000100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x40000100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x40000100, 0x0), - /* ISH_UART0_RXD */ _PAD_CFG_STRUCT(GPP_D13, 0x44000700, 0x0), - /* ISH_UART0_TXD */ _PAD_CFG_STRUCT(GPP_D14, 0x44000700, 0x0), - /* ISH_UART0_RTS# */ _PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), - /* ISH_UART0_CTS# */ _PAD_CFG_STRUCT(GPP_D16, 0x44000700, 0x0), - /* DMIC_CLK1 */ _PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), - /* DMIC_DATA1 */ _PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x0), - /* DMIC_CLK0 */ _PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), - /* DMIC_DATA0 */ _PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0), - /* SPI1_IO2 */ _PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), - /* SPI1_IO3 */ _PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), - /* I2S_MCLK */ _PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E0, 0x42880100, 0x0), - /* SATAXPCIE1 */ _PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0), - /* SATAXPCIE2 */ _PAD_CFG_STRUCT(GPP_E2, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x40000000, 0x0), - /* SATA_DEVSLP0 */ _PAD_CFG_STRUCT(GPP_E4, 0x04000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E5, 0x82880102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x44000200, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x80180102, 0x0), - /* SATALED# */ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E9, 0x44000200, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E10, 0x44000201, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E11, 0x44000201, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x0), - /* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_E13, 0x44000702, 0x0), - /* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E15, 0x42840102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0), - /* EDP_HPD */ _PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), - /* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0), - /* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), - /* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x0), - /* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E22, 0x40900100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E23, 0x84000200, 0x1000), - /* I2S2_SCLK */ _PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), - /* I2S2_SFRM */ _PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0), - /* I2S2_TXD */ _PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), - /* I2S2_RXD */ _PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0), - /* I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F4, 0x44000700, 0x2000000), - /* I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2000000), - /* I2C3_SDA */ _PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2000000), - /* I2C3_SCL */ _PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2000000), - /* I2C4_SDA */ _PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2000000), - /* I2C4_SCL */ _PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2000000), - /* ISH_I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2000000), - /* ISH_I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2000000), - /* EMMC_CMD */ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F13, 0x44000102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F14, 0x44000102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F15, 0x44000100, 0x0), - /* EMMC_DATA3 */ _PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0), - /* EMMC_DATA4 */ _PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0), - /* EMMC_DATA5 */ _PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0), - /* EMMC_DATA6 */ _PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0), - /* EMMC_DATA7 */ _PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0), - /* EMMC_RCLK */ _PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), - /* EMMC_CLK */ _PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), - /* SD_CMD */ _PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), - /* SD_DATA0 */ _PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0), - /* SD_DATA1 */ _PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), - /* SD_DATA2 */ _PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), - /* SD_DATA3 */ _PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), - /* SD_CD# */ _PAD_CFG_STRUCT(GPP_G5, 0x44000700, 0x0), - /* SD_CLK */ _PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_G7, 0x44000100, 0x0), +/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD0 */ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD1 */ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD2 */ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD3 */ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI), +/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP), +/* GPIO */ PAD_CFG_GPO(GPP_A12, 1, PWROK), +/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SUS_ACK# */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_GP2 */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_GP3 */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPO(GPP_A22, 1, DEEP), +/* GPIO */ PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP), +/* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* VRALERT# */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), +/* GPIO */ PAD_CFG_GPO(GPP_B4, 1, DEEP), +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), +/* GPIO */ PAD_CFG_GPO(GPP_B15, 0, DEEP), +/* GPIO */ PAD_NC(GPP_B16, NONE), +/* GPIO */ PAD_CFG_GPI_ACPI_SCI(GPP_B17, 20K_PD, DEEP, INVERT), +/* GPIO */ PAD_CFG_GPI_SCI(GPP_B18, 20K_PU, PLTRST, LEVEL, INVERT), +/* GPIO */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SMBDATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), +/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_APIC_INVERT(GPP_C5, 20K_PD, DEEP), +/* RESERVED - GPP_C6 */ +/* RESERVED - GPP_C7 */ +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_RTS# */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_CTS# */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_CTS# */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_CS# */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* FLASHTRIG */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, LEVEL, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, LEVEL, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, LEVEL, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, LEVEL, ACPI), +/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_UART0_RTS# */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_UART0_CTS# */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_IO2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_IO3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_ACPI_SCI(GPP_E0, NONE, DEEP, INVERT), +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPIO_BIDIRECT(GPP_E3, 0, NONE, DEEP, LEVEL, ACPI), +/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_ACPI_SCI(GPP_E5, NONE, PLTRST, INVERT), +/* GPIO */ PAD_CFG_GPO(GPP_E6, 0, DEEP), +/* GPIO */ PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, IOAPIC, SCI), +/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPO(GPP_E9, 0, DEEP), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_E10, 1, 20K_PD, DEEP), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_E11, 1, 20K_PD, DEEP), +/* GPIO */ PAD_NC(GPP_E12, NONE), +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, INVERT), +/* GPIO */ PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT), +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_APIC_INVERT(GPP_E22, NONE, DEEP), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_E23, 0, 20K_PD, PLTRST), +/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C3_SDA */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C2_SDA */ PAD_CFG_NF(GPP_F10, NONE, DEEP, NF2), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C2_SCL */ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF2), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP), +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, ACPI), }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/43411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468 Gerrit-Change-Number: 43411 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

5 21

Change in coreboot[master]: [WIP]drivers: Get rid of set_vbe_mode_info_valid
by Patrick Rudolph (Code Review) 04 Jan '21

04 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39006 ) Change subject: [WIP]drivers: Get rid of set_vbe_mode_info_valid ...................................................................... [WIP]drivers: Get rid of set_vbe_mode_info_valid Replace set_vbe_mode_info_valid with fb_new_framebuffer_info_from_edid and migrate to new header, that's independend of VBE. Change-Id: I0c145ebcf33ae0e4ff8489d4d0bc1e46869912f3 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/aspeed/common/ast_mode_corebootfb.c M src/include/edid.h M src/include/framebuffer_info.h M src/lib/edid_fill_fb.c M src/mainboard/google/daisy/mainboard.c M src/mainboard/google/kukui/mainboard.c M src/mainboard/google/oak/mainboard.c M src/mainboard/google/peach_pit/mainboard.c M src/northbridge/intel/i945/gma.c M src/soc/nvidia/tegra124/display.c M src/soc/rockchip/rk3288/display.c M src/soc/rockchip/rk3399/display.c 12 files changed, 21 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/39006/1 diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c index fed7754..2fa1a58 100644 --- a/src/drivers/aspeed/common/ast_mode_corebootfb.c +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -221,7 +221,7 @@ return ret; } - /* Updated edid for set_vbe_mode_info_valid */ + /* Updated edid for fb_fill_framebuffer_info */ edid.x_resolution = edid.mode.ha; edid.y_resolution = edid.mode.va; edid.framebuffer_bits_per_pixel = format.cpp[0] * 8; diff --git a/src/include/edid.h b/src/include/edid.h index 7c3e9c8..f61a71e 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -109,8 +109,6 @@ int decode_edid(unsigned char *edid, int size, struct edid *out); void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp, int row_byte_alignment); -struct edid_fb_info *set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr); -void set_vbe_framebuffer_orientation(enum lb_fb_orientation orientation); int set_display_mode(struct edid *edid, enum edid_modes mode); #endif /* EDID_H */ diff --git a/src/include/framebuffer_info.h b/src/include/framebuffer_info.h index 6d2f9a6..a2f2b39 100644 --- a/src/include/framebuffer_info.h +++ b/src/include/framebuffer_info.h @@ -42,4 +42,7 @@ void fb_fill_framebuffer_set_orientation(struct edid_fb_info *info, enum lb_fb_orientation orientation); +struct edid_fb_info *fb_new_framebuffer_info_from_edid(const struct edid *edid, + uintptr_t fb_addr); + #endif /* __FRAMEBUFFER_INFO_H_ */ diff --git a/src/lib/edid_fill_fb.c b/src/lib/edid_fill_fb.c index 1928335..d387802 100644 --- a/src/lib/edid_fill_fb.c +++ b/src/lib/edid_fill_fb.c @@ -139,7 +139,8 @@ /* * Take an edid, and create a framebuffer. Set fb_valid to 1. */ -struct edid_fb_info *set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr) +struct edid_fb_info *fb_new_framebuffer_info_from_edid(const struct edid *edid, + uintptr_t fb_addr) { struct edid_fb_info *info = fb_new_framebuffer_info(); if (!info) diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 30f8805..0d50953 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -32,6 +32,7 @@ #include <soc/usb.h> #include <symbols.h> #include <vbe.h> +#include <framebuffer_info.h> #include "exynos5250.h" @@ -277,7 +278,7 @@ sdmmc_vdd(); - set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)fb_addr); lcd_vdd(); diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 57014b4..8b4668e 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -173,7 +173,7 @@ return false; } mtk_ddp_mode_set(edid); - struct edid_fb_info *info = set_vbe_mode_info_valid(edid, 0); + struct edid_fb_info *info = fb_new_framebuffer_info_from_edid(edid, 0); if (info) fb_fill_framebuffer_set_orientation(info, panel->s->orientation); diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 421826c..cc583fe 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -32,6 +32,7 @@ #include <soc/pll.h> #include <soc/usb.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <framebuffer_info.h> enum { CODEC_I2C_BUS = 0, @@ -238,7 +239,7 @@ } mtk_ddp_mode_set(&edid); - set_vbe_mode_info_valid(&edid, (uintptr_t)0); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); } static void mainboard_init(struct device *dev) diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 553c2ad..40947e2 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -36,6 +36,7 @@ #include <string.h> #include <symbols.h> #include <vbe.h> +#include <framebuffer_info.h> /* convenient shorthand (in MB) */ #define DRAM_START ((uintptr_t)_dram/MiB) @@ -416,7 +417,7 @@ sdmmc_vdd(); - set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)fb_addr); /* * The reset value for FIMD SYSMMU register MMU_CTRL:0x14640000 diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 98e30e7..eff0b9b 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -34,6 +34,7 @@ #include <cbmem.h> #include <southbridge/intel/i82801gx/nvs.h> #include <types.h> +#include <framebuffer_info.h> #include "i945.h" #include "chip.h" @@ -386,7 +387,7 @@ (void *)pgfx, hactive * vactive * 4); memset((void *)pgfx, 0x00, hactive * vactive * 4); - set_vbe_mode_info_valid(&edid, pgfx); + fb_new_framebuffer_info_from_edid(&edid, pgfx); } else { vga_misc_write(0x67); diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 6fa3bdf..e4fd183 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -27,6 +27,7 @@ #include <soc/nvidia/tegra/pwm.h> #include <stdint.h> #include <string.h> +#include <framebuffer_info.h> #include "chip.h" @@ -330,5 +331,5 @@ edid.mode.ha = config->xres; edid_set_framebuffer_bits_per_pixel(&edid, config->framebuffer_bits_per_pixel, 32); - set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB)); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)(framebuffer_base_mb*MiB)); } diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index a66b2d4..fd85f8f 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -31,6 +31,7 @@ #include <soc/grf.h> #include <soc/soc.h> #include <soc/vop.h> +#include <framebuffer_info.h> #include "chip.h" @@ -138,5 +139,5 @@ break; } - set_vbe_mode_info_valid(&edid, (uintptr_t)lcdbase); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)lcdbase); } diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index 9cd4053..f76fe22 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -32,6 +32,7 @@ #include <soc/mipi.h> #include <soc/soc.h> #include <soc/vop.h> +#include <framebuffer_info.h> #include "chip.h" @@ -174,7 +175,7 @@ break; } mainboard_power_on_backlight(); - set_vbe_mode_info_valid(&edid, (uintptr_t)0); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c145ebcf33ae0e4ff8489d4d0bc1e46869912f3 Gerrit-Change-Number: 39006 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 30

Change in coreboot[master]: mb/google/octopus: Add ACPI backlight controls
by Matt DeVillier (Code Review) 04 Jan '21

04 Jan '21

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40594 ) Change subject: mb/google/octopus: Add ACPI backlight controls ...................................................................... mb/google/octopus: Add ACPI backlight controls Change-Id: I779f7f3f5a111018fc7b5c50c5750a9eb815d670 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/octopus/dsdt.asl M src/mainboard/google/octopus/variants/baseboard/devicetree.cb 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/40594/1 diff --git a/src/mainboard/google/octopus/dsdt.asl b/src/mainboard/google/octopus/dsdt.asl index 11313f9..4dbf1c5 100644 --- a/src/mainboard/google/octopus/dsdt.asl +++ b/src/mainboard/google/octopus/dsdt.asl @@ -26,6 +26,7 @@ #include <soc/intel/apollolake/acpi/northbridge.asl> #include <soc/intel/apollolake/acpi/southbridge.asl> #include <soc/intel/apollolake/acpi/pch_hda.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 9253f11..69ea309 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -3,6 +3,9 @@ device lapic 0 on end end + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "pcie_rp_clkreq_pin[2]" = "3" # wifi/bt # Disable unused clkreq of PCIe root ports register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" -- To view, visit https://review.coreboot.org/c/coreboot/+/40594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I779f7f3f5a111018fc7b5c50c5750a9eb815d670 Gerrit-Change-Number: 40594 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: romcc: cleanup leftovers
by Idwer Vollering (Code Review) 01 Jan '21

01 Jan '21

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37968 ) Change subject: romcc: cleanup leftovers ...................................................................... romcc: cleanup leftovers Change-Id: I5112e0ce66e3bcd8c1f020089278766d2f27edb8 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- M .gitignore M util/README.md M util/abuild/abuild.1 M util/lint/check_lint_tests M util/lint/lint-000-license-headers M util/lint/lint-014-qualified-types M util/lint/lint-extended-015-final-newlines M util/lint/lint-stable-010-asm-syntax 8 files changed, 2 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37968/1 diff --git a/.gitignore b/.gitignore index 0cc6ae2..86ddd19 100644 --- a/.gitignore +++ b/.gitignore @@ -115,7 +115,6 @@ util/nvramtool/nvramtool util/optionlist/Options.wiki util/pmh7tool/pmh7tool -util/romcc/build util/runfw/googlesnow util/superiotool/superiotool util/vgabios/testbios diff --git a/util/README.md b/util/README.md index 55bcaab..66438a9 100644 --- a/util/README.md +++ b/util/README.md @@ -86,8 +86,6 @@ * _sifive-gpt.py_ - Wraps the bootblock in a GPT partition for SiFive's bootrom. `Python3` * __rockchip__ - Generate Rockchip idblock bootloader. `Python2` -* __romcc__ - Compile a C source file generating a binary that does not -implicitly use RAM. `C` * __sconfig__ - coreboot device tree compiler `Lex` `Yacc` * __scripts__ * _config_ - Manipulate options in a .config file from the diff --git a/util/abuild/abuild.1 b/util/abuild/abuild.1 index 2eee84b..ccdfff6 100644 --- a/util/abuild/abuild.1 +++ b/util/abuild/abuild.1 @@ -78,7 +78,6 @@ .B abuild is covered by the GNU General Public License (GPL), version 2 or later. .SH SEE ALSO -.BR romcc (1), .BR flashrom (1). .SH COPYRIGHT 2004 Stefan Reinauer diff --git a/util/lint/check_lint_tests b/util/lint/check_lint_tests index 6b1860f..20d49a7 100755 --- a/util/lint/check_lint_tests +++ b/util/lint/check_lint_tests @@ -35,11 +35,6 @@ sed -i "s/for more details./for more details.\n \* You${SPACE}should${SPACE}have received a copy of the GNU General Public License\n \* along with this program; if not, write to the Free Software\n \* Foundation, Inc./" ${TESTFILE009} git add ${TESTFILE009} -#lint-stable-010-asm-syntax -TESTFILE010=src/arch/x86/bootblock_romcc.S -sed -i "1s/^/.att${UNDERSCORE}syntax noprefix\n/" ${TESTFILE010} -git add ${TESTFILE010} - #lint-stable-012-executable-bit TESTFILE012=src/lib/libgcc.c chmod +x ${TESTFILE012} diff --git a/util/lint/lint-000-license-headers b/util/lint/lint-000-license-headers index 9b3553b..5adbc7c 100755 --- a/util/lint/lint-000-license-headers +++ b/util/lint/lint-000-license-headers @@ -24,8 +24,6 @@ ^util/amdtools/example_input/|\ ^util/cbfstool/lzma/|\ ^util/kconfig/|\ -^util/romcc/tests|\ -^util/romcc/results|\ Kconfig|\ \<COPYING\>|\ \<LICENSE\>|\ diff --git a/util/lint/lint-014-qualified-types b/util/lint/lint-014-qualified-types index 98679ea..976748f 100755 --- a/util/lint/lint-014-qualified-types +++ b/util/lint/lint-014-qualified-types @@ -17,7 +17,7 @@ LC_ALL=C export LC_ALL INCLUDED_DIRS='^src/\|^util/\|payloads/libpayload\|payloads/coreinfo' -EXCLUDED_DIRS='^src/vendorcode\|^util/romcc\|cbfstool/lzma\|cbfstool/lz4' +EXCLUDED_DIRS='^src/vendorcode\|^util/cbfstool/lzma\|cbfstool/lz4' INCLUDED_FILES='\.[ch]:' # Use git grep if the code is in a git repo, otherwise use grep. diff --git a/util/lint/lint-extended-015-final-newlines b/util/lint/lint-extended-015-final-newlines index b5a503f..15462d6 100755 --- a/util/lint/lint-extended-015-final-newlines +++ b/util/lint/lint-extended-015-final-newlines @@ -18,7 +18,7 @@ PIDS="" INCLUDED_DIRS_AND_FILES='util/* src/* payloads/* configs/* Makefile *.inc' -EXCLUDED_DIRS='src/vendorcode/\|util/romcc/\|cbfstool/lzma/\|cbfstool/lz4/\|Documentation/\|build/\|3rdparty/\|\.git/\|coreboot-builds/\|util/nvidia/cbootimage/' +EXCLUDED_DIRS='src/vendorcode/\|util/cbfstool/lzma/\|cbfstool/lz4/\|Documentation/\|build/\|3rdparty/\|\.git/\|coreboot-builds/\|util/nvidia/cbootimage/' EXCLUDED_FILES='\.jpg$\|\.cksum$\|\.bin$\|\.vbt$\|\.hex$\|\.ico$\|\.o$\|\.bz2$\|\.xz$\|^.tmpconfig\|\.pyc$\|_shipped$\|sha256$\|\.png$\|\.patch$' # Use git ls-files if the code is in a git repo, otherwise use find. diff --git a/util/lint/lint-stable-010-asm-syntax b/util/lint/lint-stable-010-asm-syntax index a102a77..e69de29 100755 --- a/util/lint/lint-stable-010-asm-syntax +++ b/util/lint/lint-stable-010-asm-syntax @@ -1,18 +0,0 @@ -#!/bin/sh -# This file is part of the coreboot project. -# -# Copyright 2016 Google Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# DESCR: Check that we use a single assembler syntax - -LC_ALL=C export LC_ALL -git grep -n "\.$att\|intel$_syntax\>" | grep -v '\.patch:' -- To view, visit https://review.coreboot.org/c/coreboot/+/37968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5112e0ce66e3bcd8c1f020089278766d2f27edb8 Gerrit-Change-Number: 37968 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

6 10

Change in coreboot[master]: soc/mediatek/mt8192: Add dram control register define and bits define
by CK HU (Code Review) 31 Dec '20

31 Dec '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44699 to review the following change. Change subject: soc/mediatek/mt8192: Add dram control register define and bits define ...................................................................... soc/mediatek/mt8192: Add dram control register define and bits define Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Ifc64fb6c60d57184c4a2f9febe765b5cb69b39ae --- M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h A src/soc/mediatek/mt8192/include/soc/dramc_register.h A src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h 4 files changed, 5,002 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/44699/1 diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index e0cd536..4356d67 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -15,6 +15,7 @@ enum { CKSYS_BASE = IO_PHYS, INFRACFG_AO_BASE = IO_PHYS + 0x00001000, + INFRACFG_AO_MEM_BASE = IO_PHYS + 0x00002000, GPIO_BASE = IO_PHYS + 0x00005000, SPM_BASE = IO_PHYS + 0x00006000, RGU_BASE = IO_PHYS + 0x00007000, @@ -22,6 +23,9 @@ EINT_BASE = IO_PHYS + 0x0000B000, APMIXED_BASE = IO_PHYS + 0x0000C000, PWRAP_BASE = IO_PHYS + 0x0000D000, + EMI_BASE = IO_PHYS + 0x00219000, + EMI_MPU_BASE = IO_PHYS + 0x00226000, + DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, UART0_BASE = IO_PHYS + 0x01002000, SPI0_BASE = IO_PHYS + 0x0100A000, SPI1_BASE = IO_PHYS + 0x01010000, diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h new file mode 100644 index 0000000..c2dec82 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h @@ -0,0 +1,343 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_DRAMC_PI_API_H__ +#define __SOC_MEDIATEK_MT8192_DRAMC_PI_API_H__ + +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <stdint.h> +#include <types.h> + +#include <soc/addressmap.h> +#include <soc/dramc_common_mt8192.h> +#include <soc/dramc_register_bits_def.h> +#include <soc/emi.h> + +#define dramc_err(_x_...) printk(BIOS_ERR, _x_) +#define dramc_info(_x_...) printk(BIOS_INFO, _x_) +#if CONFIG(DEBUG_DRAM) +#define dramc_dbg(_x_...) printk(BIOS_INFO, _x_) +#else +#define dramc_dbg(_x_...) +#endif + +#define DRAMC_BROADCAST_ON 0x7f +#define DRAMC_BROADCAST_OFF 0x0 + +#define TX_DQ_UI_TO_PI_TAP 64 +#define TX_PHASE_DQ_UI_TO_PI_TAP 32 +#define LP4_TX_VREF_DATA_NUM 50 +#define LP4_TX_VREF_PASS_CONDITION 0 +#define TX_PASS_WIN_CRITERIA 7 +#define LP4_TX_VREF_BOUNDARY_NOT_READY 0xff +#define REG_SHU_OFFSET_WIDTH 0x700 +#define SHU_OFFSET (REG_SHU_OFFSET_WIDTH / 4) + +typedef enum { + DDRFREQ_400, + DDRFREQ_600, + DDRFREQ_800, + DDRFREQ_933, + DDRFREQ_1200, + DDRFREQ_1600, + DDRFREQ_2133, + DDRFREQ_MAX, +} dram_freq_grp; + +typedef enum { + CALI_SEQ0 = 0, + CALI_SEQ1, + CALI_SEQ2, + CALI_SEQ3, + CALI_SEQ4, + CALI_SEQ5, + CALI_SEQ6, + CALI_SEQ_MAX +} dram_cali_seq; + +typedef enum { + DIV8_MODE = 0, + DIV4_MODE, + UNKNOWN_MODE, +} dram_div_mode; + +typedef enum { + VREF_CALI_OFF = 0, + VREF_CALI_ON, +} vref_cali_mode; + +typedef enum { + DRVP = 0, + DRVN, + ODTP, + ODTN, + IMP_DRV_MAX +} imp_drv_type; + +typedef enum { + RX_WIN_RD_DQC = 0, + RX_WIN_TEST_ENG, +} rx_cali_type; + +typedef enum TX_CAL_TYPE { + TX_DQ_DQS_MOVE_DQ_ONLY, + TX_DQ_DQS_MOVE_DQM_ONLY, + TX_DQ_DQS_MOVE_DQ_DQM, +} tx_cali_type; + +typedef enum { + DCM_OFF = 0, + DCM_ON, +} dcm_state; + +typedef enum { + CBT_LOW_FREQ = 0, + CBT_HIGH_FREQ, + CBT_UNKNOWN_FREQ = 0xff, +} cbt_freq; + +typedef enum { + IN_CBT, + OUT_CBT, +} cbt_state; + +enum { + PHYPLL_MODE = 0, + CLRPLL_MODE, +}; + +enum { + DutyScan_K_DQ, + DutyScan_K_DQM, +}; + +typedef enum { + O1_OFF, + O1_ON, +} o1_state; + +typedef enum +{ + SINGLE_RANK_DDR = 1, + DUAL_RANK_DDR +} ddr_rank_num; + +enum { + DQS_8PH_DEGREE_0 = 0, + DQS_8PH_DEGREE_180, + DQS_8PH_DEGREE_45, + DQS_8PH_DEGREE_MAX, +}; + +struct dram_impedance { + u32 result[ODT_MAX][IMP_DRV_MAX]; +}; + +struct mr_values { + u8 mr01[FSP_MAX]; + u8 mr02[FSP_MAX]; + u8 mr03[FSP_MAX]; + u8 mr04[RANK_MAX]; + u8 mr11[FSP_MAX]; + u8 mr12[CHANNEL_MAX][RANK_MAX][FSP_MAX]; + u8 mr13[RANK_MAX]; + u8 mr14[CHANNEL_MAX][RANK_MAX][FSP_MAX]; + u8 mr18[CHANNEL_MAX][RANK_MAX]; + u8 mr19[CHANNEL_MAX][RANK_MAX]; + u8 mr20[FSP_MAX]; + u8 mr21[FSP_MAX]; + u8 mr22[FSP_MAX]; + u8 mr23[CHANNEL_MAX][RANK_MAX]; + u8 mr26[RANK_MAX]; + u8 mr30[RANK_MAX]; + u8 mr51[FSP_MAX]; +}; + +struct ddr_cali { + u8 chn; + u8 rank; + u8 fsp; + u8 density; + u8 *pll_mode; + u32 frequency; + u32 vcore_voltage; + dram_dfs_shu shu; + ddr_rank_num support_ranks; + dbi_mode w_dbi[FSP_MAX]; + vref_cali_mode vref_cali; + dram_odt_state odt_onoff; + dram_freq_grp freq_group; + dram_div_mode div_mode; + dram_pinmux_type pinmux_type; + dram_cbt_mode cbt_mode[RANK_MAX]; + struct dram_impedance impedance; + struct mr_values *mr_value; + const struct emi_mdl *emi_config; + const struct sdram_params *params; +}; + +struct reg_bak { + u32 *addr; + u32 value; +}; + +typedef struct _ana_top_config { + u8 dll_async_en; + u8 all_slave_en; + u8 rank_mode; + u8 dll_idle_mode; + u8 aphy_comb_en; + u8 tx_odt_dis; + u8 new_8x_mode; +} ana_top_config; + +typedef struct ana_dvfs_core_config { + u8 ckr; + u8 dq_p2s_ratio; + u8 ca_p2s_ratio; + u8 dq_ca_open; + u8 dq_semi_open; + u8 ca_semi_open; + u8 ca_full_rate; + u8 dq_ckdiv4_en; + u8 ca_ckdiv4_en; + u8 ca_prediv_en; + u8 ph8_dly; + u8 semi_open_ca_pick_mck_ratio; + u8 dq_aamck_div; + u8 ca_admck_div; + u8 dq_track_ca_en; + u32 pll_freq; +} ana_dvfs_core; + +typedef struct lp4_dram_config { + u8 ex_row_en[RANK_MAX]; + u8 mr_wl; + u8 dbi_wr; + u8 dbi_rd; + u8 lp4y_en; + u8 work_fsp; +} dram_config; + +typedef struct _dvfs_group_config { + u32 data_rate; + u8 dqsien_mode; + u8 dq_p2s_ratio; + u8 ckr; +} dvfs_group_config; + +struct gating_config { + u8 gat_track_en; + u8 rx_gating_mode; + u8 rx_gating_track_mode; + u8 valid_lat_value; +}; + +typedef struct _dramc_subsys_config { + dram_freq_grp freq_group; + ana_top_config *a_cfg; + ana_dvfs_core *dvfs_core; + dram_config *lp4_init; + dvfs_group_config *dfs_gp; + struct gating_config *gat_c; +} dramc_subsys_config; + +typedef struct _reg_transfer { + u32 *addr; + u8 offset; +} reg_transfer; + +void emi_init2(void); +u32 get_column_num(void); +u32 get_row_width_from_emi(u32 rank); +u8 dramc_mode_reg_read(u8 chn, u8 mr_idx); +u8 dramc_mode_reg_read_by_rank(u8 chn, u8 rank, u8 mr_idx); +void dramc_mode_reg_write_by_rank(const struct ddr_cali *cali, + u8 chn, u8 rank, u8 mr_idx, u8 value); +void after_calib(const struct ddr_cali* cali); +void init_dram(const struct dramc_data *dparam); +void global_option_init(struct ddr_cali *cali); +u32 dramc_get_broadcast(void); +void dramc_set_broadcast(u32 onoff); +void dramc_sw_impedance_cal(dram_odt_state odt, struct dram_impedance *imp); +void dramc_sw_impedance_save_register(const struct ddr_cali *cali); +void dfs_init_for_calibration(const struct ddr_cali *cali); +void dramc_auto_refresh_switch(u8 chn, bool flag); +void dramc_runtime_config(const struct ddr_cali *cali); +void emi_mdl_init(const struct emi_mdl *emi_con); +void cke_fix_onoff(const struct ddr_cali *cali, u8 chn, u8 rank, int option); +void enable_phy_dcm_shuffle(dcm_state enable, u8 shuffle_save); +void enable_phy_dcm_non_shuffle(dcm_state enable); +void dramc_8_phase_cal(const struct ddr_cali *cali); +void dramc_duty_calibration(const struct sdram_params *params); +void dramc_write_leveling(const struct ddr_cali* cali, u8 dqs_final_delay[2][2]); +void dramc_rx_dqs_gating_cal(const struct ddr_cali* cali, u8 *txdly_min, u8 *txdly_max); +void dramc_rx_dqs_gating_post_process(const struct ddr_cali* cali, + u8 txdly_min, u8 txdly_max); +void dramc_rx_datlat_cal(const struct ddr_cali* cali); +void dramc_dual_rank_rx_datlat_cal(const struct ddr_cali* cali); +void dramc_cmd_bus_training(const struct ddr_cali* cali); +void dramc_rx_window_perbit_cal(const struct ddr_cali* cali, rx_cali_type type); +void dramc_tx_window_perbit_cal(const struct ddr_cali* cali, tx_cali_type calType, + const u8 dqs_final_delay[2][2], bool u1VrefScanEnable); +void dramc_tx_oe_calibration(const struct ddr_cali* cali); +dram_freq_grp get_freq_group(const struct ddr_cali *cali); +dram_odt_state get_odt_state(const struct ddr_cali *cali); +u8 get_fsp(const struct ddr_cali *cali); +dram_dfs_shu get_shu(const struct ddr_cali *cali); +dram_freq_grp get_highest_freq_group(void); +dram_cbt_mode get_cbt_mode(const struct ddr_cali *cali); +u32 get_frequency(const struct ddr_cali *cali); +vref_cali_mode get_vref_cali(const struct ddr_cali *cali); +dram_div_mode get_div_mode(const struct ddr_cali *cali); +dbi_mode get_write_dbi(const struct ddr_cali *cali); +dram_dfs_shu get_shu_save_by_k_shu(dram_cali_seq k_shu); +dram_freq_grp get_freq_group_by_shu_save(dram_dfs_shu shu); +dram_pinmux_type get_pinmux_type(const struct ddr_cali *cali); +u32 get_frequency_by_shu(dram_dfs_shu shu); +u32 get_vcore_value(const struct ddr_cali *cali); +void set_cali_datas(struct ddr_cali *cali, const struct dramc_data *dparam, dram_cali_seq k_shu); +u8 get_mck2ui_div_shift(const struct ddr_cali *cali); +void tx_picg_setting(const struct ddr_cali *cali); +void xrtrtr_shu_setting(const struct ddr_cali *cali); +void cbt_switch_freq(const struct ddr_cali *cali, cbt_freq freq); +void enable_dfs_hw_mode_clk(void); +void dramc_dfs_direct_jump_rg_mode(const struct ddr_cali *cali, u8 shu_level); +void dramc_dfs_direct_jump_sram_shu_rg_mode(const struct ddr_cali *cali, + dram_dfs_shu shu_level); +void dramc_save_result_to_shuffle(dram_dfs_shu src, dram_dfs_shu dst); +void dramc_load_shuffle_to_dramc(dram_dfs_shu src, dram_dfs_shu dst); +void dvfs_settings(const struct ddr_cali *cali); +void dramc_dqs_precalculation_preset(const struct ddr_cali* cali); +void freq_jump_ratio_calculation(const struct ddr_cali *cali); +void dramc_hmr4_presetting(const struct ddr_cali* cali); +void dramc_enable_perbank_refresh(bool en); +void dramc_modified_refresh_mode(void); +void dramc_cke_debounce(const struct ddr_cali* cali); +void dramc_hw_dqsosc(const struct ddr_cali* cali, u8 chn); +void xrtwtw_shu_setting(const struct ddr_cali* cali); +void enable_write_DBI_after_calibration(const struct ddr_cali* cali); +void dramc_set_mr13_vrcg_to_normal(const struct ddr_cali* cali); +void ana_init(const struct ddr_cali *cali, dramc_subsys_config *subsys); +void dig_static_setting(const struct ddr_cali *cali, dramc_subsys_config *subsys); +void dig_config_shuf(const struct ddr_cali *cali, dramc_subsys_config *subsys); +void resetb_pull_dn(void); +void dramc_subsys_pre_config(dram_freq_grp freq_group, dramc_subsys_config *subsys); +void single_end_dramc_post_config(u8 lp4y_en); +void dram_configure(dram_freq_grp freq_group, dram_config *tr); +void ana_clk_div_config( ana_dvfs_core *tr,dvfs_group_config *dfs); +void apply_write_dbi_power_improve(bool onoff); +void dramc_write_dbi_onoff(u8 onoff); +void cbt_delay_ca_clk(u8 chn, u8 rank, s32 iDelay); +void dramc_cmd_UI_delay_setting(u8 chn, u8 value); +void dramc_dqsosc_set_mr18_mr19(const struct ddr_cali* cali, + u16 *osc_thrd_inc, u16 *osc_thrd_dec); +void dqsosc_shu_settings(const struct ddr_cali* cali, + u16 *osc_thrd_inc, u16 *osc_thrd_dec); +void shift_dq_ui(const struct ddr_cali* cali, u8 rk, s8 shift_ui); +void shuffle_dfs_to_fsp1(const struct ddr_cali* cali); +u8 get_cbt_vref_pinmux_value(const struct ddr_cali* cali, u8 range, u8 vref_lev); +void o1_path_on_off(const struct ddr_cali* cali, o1_state o1); + +#endif /* __SOC_MEDIATEK_MT8192_DRAMC_PI_API_H__ */ diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_register.h b/src/soc/mediatek/mt8192/include/soc/dramc_register.h new file mode 100644 index 0000000..ae7e169 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dramc_register.h @@ -0,0 +1,1818 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_DRAMC_REGISTER_H__ +#define __SOC_MEDIATEK_MT8192_DRAMC_REGISTER_H__ + +#include <types.h> +#include <soc/addressmap.h> +#include <soc/dpm.h> + +struct dramc_nao_regs { + u32 testmode; + u32 rsvd_0[4]; + u32 rdqc_cmp; + u32 rdqc_dqm_cmp; + u32 rsvd_1[2]; + u32 dmmonitor; + u32 rsvd_2[2]; + u32 initk_pat0; + u32 initk_pat1; + u32 initk_pat2; + u32 initk_pat3; + u32 initk_pat4; + u32 rsvd_3[3]; + u32 spcmdresp3; + u32 cbt_wlev_status2; + u32 rsvd_4[10]; + u32 misc_statusa; + u32 special_status; + u32 spcmdresp; + u32 mrr_status; + u32 mrr_status2; + u32 mrrdata0; + u32 mrrdata1; + u32 mrrdata2; + u32 mrrdata3; + u32 ref_status; + u32 rsvd_5[2]; + u32 wck_status; + u32 rsvd_6[3]; + u32 tcmdo1lat; + u32 cbt_wlev_status1; + u32 cbt_wlev_status; + u32 spcmdresp2; + u32 cbt_wlev_atk_result0; + u32 cbt_wlev_atk_result1; + u32 cbt_wlev_atk_result2; + u32 cbt_wlev_atk_result3; + u32 cbt_wlev_atk_result4; + u32 cbt_wlev_atk_result5; + u32 cbt_wlev_atk_result6; + u32 cbt_wlev_atk_result7; + u32 cbt_wlev_atk_result8; + u32 cbt_wlev_atk_result9; + u32 cbt_wlev_atk_result10; + u32 cbt_wlev_atk_result11; + u32 cbt_wlev_atk_result12; + u32 cbt_wlev_atk_result13; + u32 rsvd_7[1]; + u32 hwmrr_push2pop_cnt; + u32 hwmrr_status; + u32 hw_refrate_mon; + u32 hw_refrate_mon2; + u32 hw_refrate_mon3; + u32 testrpt; + u32 cmp_err; + u32 test_abit_status1; + u32 test_abit_status2; + u32 test_abit_status3; + u32 test_abit_status4; + u32 test_abit_status5; + u32 test_abit_status6; + u32 test_abit_status7; + u32 test_abit_status8; + u32 test_rf_error_flag0; + u32 test_rf_error_flag1; + u32 test_rf_error_cnt1; + u32 test_rf_error_cnt2; + u32 test_rf_error_cnt3; + u32 test_rf_error_cnt4; + u32 test_rf_error_cnt5; + u32 test_rf_error_cnt6; + u32 test_rf_error_cnt7; + u32 test_rf_error_cnt8; + u32 test_loop_cnt; + u32 rsvd_8[3]; + u32 sref_dly_cnt; + u32 rsvd_9[31]; + u32 tx_atk_set0; + u32 tx_atk_set1; + u32 rsvd_10[2]; + u32 tx_atk_result0; + u32 tx_atk_result1; + u32 tx_atk_result2; + u32 tx_atk_result3; + u32 tx_atk_result4; + u32 tx_atk_result5; + u32 tx_atk_result6; + u32 tx_atk_result7; + u32 tx_atk_result8; + u32 rsvd_11[3]; + u32 tx_atk_dbg_bit_status1; + u32 tx_atk_dbg_bit_status2; + u32 tx_atk_dbg_bit_status3; + u32 tx_atk_dbg_bit_status4; + u32 rsvd_12[34]; + u32 lp5_pdx_pde_mon; + u32 lp5_pdx_pde_max_mon; + u32 dram_clk_en_0_old_counter; + u32 aphypi_cg_ck_old_counter; + u32 ckeo_pre_old_counter; + u32 cke1o_pre_old_counter; + u32 dram_clk_en_0_new_counter; + u32 aphypi_cg_ck_new_counter; + u32 ckeo_pre_new_counter; + u32 cke1o_pre_new_counter; + u32 refresh_pop_counter; + u32 freerun_26m_counter; + u32 dramc_idle_counter; + u32 r2r_page_hit_counter; + u32 r2r_page_miss_counter; + u32 r2r_interbank_counter; + u32 r2w_page_hit_counter; + u32 r2w_page_miss_counter; + u32 r2w_interbank_counter; + u32 w2r_page_hit_counter; + u32 w2r_page_miss_counter; + u32 w2r_interbank_counter; + u32 w2w_page_hit_counter; + u32 w2w_page_miss_counter; + u32 w2w_interbank_counter; + u32 rk0_pre_standby_counter; + u32 rk0_pre_powerdown_counter; + u32 rk0_act_standby_counter; + u32 rk0_act_powerdown_counter; + u32 rk1_pre_standby_counter; + u32 rk1_pre_powerdown_counter; + u32 rk1_act_standby_counter; + u32 rk1_act_powerdown_counter; + u32 rk2_pre_standby_counter; + u32 rk2_pre_powerdown_counter; + u32 rk2_act_standby_counter; + u32 rk2_act_powerdown_counter; + u32 dq0_toggle_counter; + u32 dq1_toggle_counter; + u32 dq2_toggle_counter; + u32 dq3_toggle_counter; + u32 dq0_toggle_counter_r; + u32 dq1_toggle_counter_r; + u32 dq2_toggle_counter_r; + u32 dq3_toggle_counter_r; + u32 read_bytes_counter; + u32 write_bytes_counter; + u32 max_sref_req_to_ack_latency_counter; + u32 rsvd_13[2]; + u32 dramc_idle_dcm_counter; + u32 ddrphy_clk_en_counter; + u32 ddrphy_clk_en_comb_counter; + u32 rsvd_14[1]; + u32 ebg_counter_cnt0; + u32 ebg_counter_cnt1; + u32 ebg_counter_cnt2; + u32 rsvd_15[1]; + u32 lat_counter_cmd0; + u32 lat_counter_cmd1; + u32 lat_counter_cmd2; + u32 lat_counter_cmd3; + u32 lat_counter_cmd4; + u32 lat_counter_cmd5; + u32 lat_counter_cmd6; + u32 lat_counter_cmd7; + u32 lat_counter_aver; + u32 lat_counter_num; + u32 lat_counter_block_ale; + u32 rsvd_16[70]; + u32 dramc_loop_bak_adr; + u32 dramc_loop_bak_rk; + u32 rsvd_17[1]; + u32 dramc_loop_bak_wdat0; + u32 dramc_loop_bak_wdat1; + u32 dramc_loop_bak_wdat2; + u32 dramc_loop_bak_wdat3; + u32 dramc_loop_bak_wdat4; + u32 dramc_loop_bak_wdat5; + u32 dramc_loop_bak_wdat6; + u32 dramc_loop_bak_wdat7; + u32 rsvd_18[52]; + u32 rk0_dqsosc_status; + u32 rk0_dqsosc_delta; + u32 rk0_dqsosc_delta2; + u32 rsvd_19[1]; + u32 rk0_current_tx_setting1; + u32 rk0_current_tx_setting2; + u32 rk0_current_tx_setting3; + u32 rk0_current_tx_setting4; + u32 rk0_dummy_rd_data0; + u32 rk0_dummy_rd_data1; + u32 rk0_dummy_rd_data2; + u32 rk0_dummy_rd_data3; + u32 rk0_dummy_rd_data4; + u32 rk0_dummy_rd_data5; + u32 rk0_dummy_rd_data6; + u32 rk0_dummy_rd_data7; + u32 rsvd_20[8]; + u32 rk0_pi_dq_cal; + u32 rsvd_21[1]; + u32 rk0_pi_dqm_cal; + u32 rsvd_22[37]; + u32 rk1_dqsosc_status; + u32 rk1_dqsosc_delta; + u32 rk1_dqsosc_delta2; + u32 rsvd_23[1]; + u32 rk1_current_tx_setting1; + u32 rk1_current_tx_setting2; + u32 rk1_current_tx_setting3; + u32 rk1_current_tx_setting4; + u32 rk1_dummy_rd_data0; + u32 rk1_dummy_rd_data1; + u32 rk1_dummy_rd_data2; + u32 rk1_dummy_rd_data3; + u32 rk1_dummy_rd_data4; + u32 rk1_dummy_rd_data5; + u32 rk1_dummy_rd_data6; + u32 rk1_dummy_rd_data7; + u32 rsvd_24[8]; + u32 rk1_pi_dq_cal; + u32 rsvd_25[1]; + u32 rk1_pi_dqm_cal; + u32 rsvd_26[101]; + u32 mr_backup_00_rk0_fsp0; + u32 mr_backup_01_rk0_fsp0; + u32 mr_backup_02_rk0_fsp0; + u32 mr_backup_03_rk0_fsp0; + u32 mr_backup_04_rk0_fsp0; + u32 mr_backup_05_rk0_fsp0; + u32 mr_backup_06_rk0_fsp0; + u32 mr_backup_07_rk0_fsp0; + u32 mr_backup_08_rk0_fsp0; + u32 mr_backup_09_rk0_fsp0; + u32 rsvd_27[2]; + u32 mr_backup_00_rk0_fsp1; + u32 mr_backup_01_rk0_fsp1; + u32 mr_backup_02_rk0_fsp1; + u32 mr_backup_03_rk0_fsp1; + u32 mr_backup_04_rk0_fsp1; + u32 rsvd_28[7]; + u32 mr_backup_00_rk0_fsp2; + u32 mr_backup_01_rk0_fsp2; + u32 mr_backup_02_rk0_fsp2; + u32 mr_backup_03_rk0_fsp2; + u32 rsvd_29[100]; + u32 mr_backup_00_rk1_fsp0; + u32 mr_backup_01_rk1_fsp0; + u32 mr_backup_02_rk1_fsp0; + u32 mr_backup_03_rk1_fsp0; + u32 mr_backup_04_rk1_fsp0; + u32 mr_backup_05_rk1_fsp0; + u32 mr_backup_06_rk1_fsp0; + u32 mr_backup_07_rk1_fsp0; + u32 mr_backup_08_rk1_fsp0; + u32 mr_backup_09_rk1_fsp0; + u32 rsvd_30[2]; + u32 mr_backup_00_rk1_fsp1; + u32 mr_backup_01_rk1_fsp1; + u32 mr_backup_02_rk1_fsp1; + u32 mr_backup_03_rk1_fsp1; + u32 mr_backup_04_rk1_fsp1; + u32 rsvd_31[7]; + u32 mr_backup_00_rk1_fsp2; + u32 mr_backup_01_rk1_fsp2; + u32 mr_backup_02_rk1_fsp2; + u32 mr_backup_03_rk1_fsp2; +}; + +struct ddrphy_nao_regs { + u32 misc_sta_extlb0; + u32 misc_sta_extlb1; + u32 misc_sta_extlb2; + u32 rsvd_0[1]; + u32 misc_dma_debug0; + u32 misc_dma_debug1; + u32 misc_retry_dbg0; + u32 misc_retry_dbg1; + u32 misc_retry_dbg2; + u32 misc_rdsel_track_dbg; + u32 rsvd_1[22]; + u32 misc_dq_rxdly_trro0; + u32 misc_dq_rxdly_trro1; + u32 misc_dq_rxdly_trro2; + u32 misc_dq_rxdly_trro3; + u32 misc_dq_rxdly_trro4; + u32 misc_dq_rxdly_trro5; + u32 misc_dq_rxdly_trro6; + u32 misc_dq_rxdly_trro7; + u32 misc_dq_rxdly_trro8; + u32 misc_dq_rxdly_trro9; + u32 misc_dq_rxdly_trro10; + u32 misc_dq_rxdly_trro11; + u32 misc_dq_rxdly_trro12; + u32 misc_dq_rxdly_trro13; + u32 misc_dq_rxdly_trro14; + u32 misc_dq_rxdly_trro15; + u32 misc_dq_rxdly_trro16; + u32 misc_dq_rxdly_trro17; + u32 misc_dq_rxdly_trro18; + u32 misc_dq_rxdly_trro19; + u32 misc_dq_rxdly_trro20; + u32 misc_dq_rxdly_trro21; + u32 misc_dq_rxdly_trro22; + u32 misc_dq_rxdly_trro23; + u32 misc_dq_rxdly_trro24; + u32 misc_dq_rxdly_trro25; + u32 misc_dq_rxdly_trro26; + u32 misc_dq_rxdly_trro27; + u32 misc_dq_rxdly_trro28; + u32 misc_dq_rxdly_trro29; + u32 misc_dq_rxdly_trro30; + u32 misc_dq_rxdly_trro31; + u32 rsvd_2[20]; + u32 misc_ca_rxdly_trro20; + u32 misc_ca_rxdly_trro21; + u32 misc_ca_rxdly_trro22; + u32 misc_ca_rxdly_trro23; + u32 misc_ca_rxdly_trro24; + u32 misc_ca_rxdly_trro25; + u32 misc_ca_rxdly_trro26; + u32 misc_ca_rxdly_trro27; + u32 misc_ca_rxdly_trro28; + u32 misc_ca_rxdly_trro29; + u32 misc_ca_rxdly_trro30; + u32 misc_ca_rxdly_trro31; + u32 misc_dqo1; + u32 misc_cao1; + u32 misc_ad_rx_dq_o1; + u32 misc_ad_rx_cmd_o1; + u32 misc_phy_rgs_dq; + u32 misc_phy_rgs_cmd; + u32 misc_phy_rgs_stben_b0; + u32 misc_phy_rgs_stben_b1; + u32 misc_phy_rgs_stben_cmd; + u32 misc_phy_picg_mon_s0; + u32 misc_phy_picg_mon_s1; + u32 misc_phy_picg_mon_s2; + u32 misc_phy_picg_mon_s3; + u32 misc_phy_picg_mon_s4; + u32 misc_phy_picg_mon_s5; + u32 misc_phy_picg_mon_s6; + u32 misc_phy_picg_mon_s7; + u32 misc_phy_picg_mon_s8; + u32 misc_mbist_status; + u32 misc_mbist_status2; + u32 misc_impcal_status1; + u32 misc_impcal_status2; + u32 misc_impcal_status3; + u32 misc_impcal_status4; + u32 misc_impcal_status5; + u32 misc_impcal_status6; + u32 misc_impcal_status7; + u32 misc_impcal_status8; + u32 rsvd_3[1]; + u32 misc_impcal_status9; + u32 misc_sta_toglb0; + u32 misc_sta_toglb1; + u32 rsvd_4[5]; + u32 misc_sta_extlb_dbg0; + u32 misc_sta_extlb_dbg1; + u32 misc_sta_extlb_dbg2; + u32 misc_sta_extlb_dbg3; + u32 misc_duty_toggle_cnt; + u32 misc_duty_dqs0_err_cnt; + u32 misc_duty_dq_err_cnt0; + u32 misc_duty_dqs1_err_cnt; + u32 misc_duty_dq_err_cnt1; + u32 misc_duty_dqs2_err_cnt; + u32 misc_duty_dq_err_cnt2; + u32 misc_duty_dqs3_err_cnt; + u32 misc_duty_dq_err_cnt3; + u32 misc_jmeter_st0; + u32 misc_jmeter_st1; + u32 misc_emi_lpbk0; + u32 misc_emi_lpbk1; + u32 misc_emi_lpbk2; + u32 misc_emi_lpbk3; + u32 misc_emi_lpbk4; + u32 misc_emi_lpbk5; + u32 misc_emi_lpbk6; + u32 misc_emi_lpbk7; + u32 misc_ft_status0; + u32 misc_ft_status1; + u32 misc_ft_status2; + u32 misc_ft_status3; + u32 misc_ft_status4; + u32 misc_sta_toglb2; + u32 misc_sta_toglb3; + u32 misc_sta_extlb3; + u32 misc_sta_extlb4; + u32 misc_sta_extlb5; + u32 rsvd_5[90]; + u32 debug_aphy_rx_ctl; + u32 rsvd_6[3]; + u32 gating_err_infor; + u32 debug_dqsien_b0; + u32 debug_dqsien_b1; + u32 debug_dqsien_ca; + u32 gating_err_latch_dly_b0_rk0; + u32 gating_err_latch_dly_b1_rk0; + u32 gating_err_latch_dly_ca_rk0; + u32 rsvd_7[1]; + u32 gating_err_latch_dly_b0_rk1; + u32 gating_err_latch_dly_b1_rk1; + u32 gating_err_latch_dly_ca_rk1; + u32 rsvd_8[1]; + u32 debug_rodt_ctl; + u32 rsvd_9[47]; + u32 cal_dqsg_cnt_b0; + u32 cal_dqsg_cnt_b1; + u32 cal_dqsg_cnt_ca; + u32 dvfs_status; + u32 rx_autok_status0; + u32 rx_autok_status1; + u32 rx_autok_status2; + u32 rx_autok_status3; + u32 rx_autok_status4; + u32 rx_autok_status5; + u32 rx_autok_status6; + u32 rx_autok_status7; + u32 rx_autok_status8; + u32 rx_autok_status9; + u32 rx_autok_status10; + u32 rx_autok_status11; + u32 rx_autok_status12; + u32 rx_autok_status13; + u32 rx_autok_status14; + u32 rx_autok_status15; + u32 rx_autok_status16; + u32 rx_autok_status17; + u32 rx_autok_status18; + u32 rx_autok_status19; + u32 rx_autok_status20; + u32 rsvd_10[39]; + u32 dqsien_autok_b0_rk0_status0; + u32 dqsien_autok_b0_rk0_status1; + u32 dqsien_autok_b0_rk0_dbg_status0; + u32 dqsien_autok_b0_rk0_dbg_status1; + u32 dqsien_autok_b0_rk0_dbg_status2; + u32 dqsien_autok_b0_rk0_dbg_status3; + u32 dqsien_autok_b0_rk0_dbg_status4; + u32 dqsien_autok_b0_rk0_dbg_status5; + u32 dqsien_autok_b0_rk1_status0; + u32 dqsien_autok_b0_rk1_status1; + u32 dqsien_autok_b0_rk1_dbg_status0; + u32 dqsien_autok_b0_rk1_dbg_status1; + u32 dqsien_autok_b0_rk1_dbg_status2; + u32 dqsien_autok_b0_rk1_dbg_status3; + u32 dqsien_autok_b0_rk1_dbg_status4; + u32 dqsien_autok_b0_rk1_dbg_status5; + u32 dqsien_autok_b1_rk0_status0; + u32 dqsien_autok_b1_rk0_status1; + u32 dqsien_autok_b1_rk0_dbg_status0; + u32 dqsien_autok_b1_rk0_dbg_status1; + u32 dqsien_autok_b1_rk0_dbg_status2; + u32 dqsien_autok_b1_rk0_dbg_status3; + u32 dqsien_autok_b1_rk0_dbg_status4; + u32 dqsien_autok_b1_rk0_dbg_status5; + u32 dqsien_autok_b1_rk1_status0; + u32 dqsien_autok_b1_rk1_status1; + u32 dqsien_autok_b1_rk1_dbg_status0; + u32 dqsien_autok_b1_rk1_dbg_status1; + u32 dqsien_autok_b1_rk1_dbg_status2; + u32 dqsien_autok_b1_rk1_dbg_status3; + u32 dqsien_autok_b1_rk1_dbg_status4; + u32 dqsien_autok_b1_rk1_dbg_status5; + u32 dqsien_autok_ca_rk0_status0; + u32 dqsien_autok_ca_rk0_status1; + u32 dqsien_autok_ca_rk0_dbg_status0; + u32 dqsien_autok_ca_rk0_dbg_status1; + u32 dqsien_autok_ca_rk0_dbg_status2; + u32 dqsien_autok_ca_rk0_dbg_status3; + u32 dqsien_autok_ca_rk0_dbg_status4; + u32 dqsien_autok_ca_rk0_dbg_status5; + u32 rsvd_11[24]; + u32 dqsien_autok_ca_rk1_status0; + u32 dqsien_autok_ca_rk1_status1; + u32 dqsien_autok_ca_rk1_dbg_status0; + u32 dqsien_autok_ca_rk1_dbg_status1; + u32 dqsien_autok_ca_rk1_dbg_status2; + u32 dqsien_autok_ca_rk1_dbg_status3; + u32 dqsien_autok_ca_rk1_dbg_status4; + u32 dqsien_autok_ca_rk1_dbg_status5; + u32 dqsien_autok_ctrl_status; + u32 ad_dline_mon; + u32 dline_mon_track_dbg; + u32 misc_dutycal_status; + u32 misc_dbg_db_imp_message0; + u32 misc_dbg_db_imp_message1; + u32 misc_dbg_db_imp_message2; + u32 misc_dbg_db_imp_message3; + u32 misc_dbg_db_imp_message4; + u32 misc_dbg_db_imp_message5; + u32 misc_dbg_db_imp_message6; + u32 misc_dbg_db_imp_message7; + u32 misc_dbg_db_imp_message8; + u32 misc_dbg_db_imp_message9; + u32 misc_dbg_db_imp_message10; + u32 misc_dbg_db_imp_message11; + u32 rsvd_12[40]; + u32 misc_dma_sram_mbist; + u32 rsvd_13[7]; + u32 misc_aphy_obs0; + u32 misc_aphy_obs1; + u32 misc_aphy_obs2; + u32 misc_aphy_obs3; + u32 misc_aphy_obs4; + u32 misc_aphy_obs5; + u32 misc_aphy_obs6; + u32 misc_aphy_obs7; + u32 misc_aphy_obs8; +}; + +struct dramc_ao_rk { + u32 rk_test2_a1; + u32 rk_dummy_rd_wdata0; + u32 rk_dummy_rd_wdata1; + u32 rk_dummy_rd_wdata2; + u32 rk_dummy_rd_wdata3; + u32 rk_dummy_rd_adr; + u32 rsvd_0[15]; + u32 rk_dummy_rd_adr2; + u32 rsvd_1[4]; + u32 rk_sref_dpd_tck_rk_ctrl; + u32 rsvd_2[9]; + u32 rk_dqsosc; + u32 rsvd_3[91]; +}; + +struct dramc_ao_shu_rk { + u32 shurk_selph_dq0; + u32 shurk_selph_dq1; + u32 shurk_selph_dq2; + u32 shurk_selph_dq3; + u32 shurk_dqs2dq_cal1; + u32 shurk_dqs2dq_cal2; + u32 shurk_dqs2dq_cal3; + u32 shurk_dqs2dq_cal4; + u32 shurk_dqs2dq_cal5; + u32 shurk_pi; + u32 shurk_dqsosc; + u32 shurk_dqsosc_thrd; + u32 shurk_aphy_tx_picg_ctrl; + u32 rsvd_25[3]; + u32 shurk_wck_wr_mck; + u32 shurk_wck_rd_mck; + u32 shurk_wck_fs_mck; + u32 shurk_wck_wr_ui; + u32 shurk_wck_rd_ui; + u32 shurk_wck_fs_ui; + u32 rsvd_26[2]; + u32 shurk_cke_ctrl; + u32 rsvd_27[103]; +}; + +struct dramc_ao_regs { + u32 ddrcommon0; + u32 rsvd_0[2]; + u32 sa_reserve; + u32 rsvd_1[59]; + u32 nonshu_rsv; + u32 test2_a0; + u32 test2_a2; + u32 test2_a3; + u32 test2_a4; + u32 dummy_rd; + u32 dummy_rd_intv; + u32 bus_mon1; + u32 dramc_dbg_sel1; + u32 dramc_dbg_sel2; + u32 swcmd_en; + u32 swcmd_ctrl0; + u32 swcmd_ctrl1; + u32 swcmd_ctrl2; + u32 rddqcgolden1; + u32 rddqcgolden; + u32 rtmrw_ctrl0; + u32 rtmrw_ctrl1; + u32 rtmrw_ctrl2; + u32 rtmrw_ctrl3; + u32 cbt_wlev_ctrl0; + u32 cbt_wlev_ctrl1; + u32 cbt_wlev_ctrl2; + u32 cbt_wlev_ctrl3; + u32 cbt_wlev_ctrl4; + u32 cbt_wlev_atk_ctrl0; + u32 cbt_wlev_atk_ctrl1; + u32 sref_dpd_ctrl; + u32 cfc_ctrl; + u32 dllfrz_ctrl; + u32 mpc_ctrl; + u32 hw_mrr_fun; + u32 scheduler_com; + u32 rsvd_2[4]; + u32 actiming_ctrl; + u32 rsvd_3[3]; + u32 zq_set0; + u32 zq_set1; + u32 rsvd_4[2]; + u32 tx_tracking_set0; + u32 rsvd_5[3]; + u32 tx_retry_set0; + u32 rsvd_6[1]; + u32 mpc_option; + u32 rsvd_7[1]; + u32 mrr_bit_mux1; + u32 mrr_bit_mux2; + u32 mrr_bit_mux3; + u32 mrr_bit_mux4; + u32 rsvd_8[6]; + u32 shuctrl; + u32 dramc_pd_ctrl; + u32 dcm_ctrl0; + u32 ckectrl; + u32 dvfs_ctrl0; + u32 shuctrl1; + u32 dvfs_timing_ctrl1; + u32 shuctrl3; + u32 dvfs_timing_ctrl3; + u32 cmd_dec_ctrl0; + u32 hmr4; + u32 bypass_fspop; + u32 rkcfg; + u32 slp4_testmode; + u32 dq_mux_set0; + u32 dbiwr_protect; + u32 tx_set0; + u32 tx_cg_set0; + u32 rx_set0; + u32 rx_cg_set0; + u32 dqsoscr; + u32 dramctrl; + u32 misctl0; + u32 perfctl0; + u32 arbctl; + u32 datascr; + u32 clkar; + u32 refctrl0; + u32 refctrl1; + u32 ref_bounce1; + u32 ref_bounce2; + u32 rsvd_9[1]; + u32 refpend1; + u32 refpend2; + u32 refque_cnt; + u32 scsmctrl; + u32 scsmctrl_cg; + u32 refctrl2; + u32 tx_freq_ratio_old_mode0; + u32 tx_freq_ratio_old_mode1; + u32 tx_freq_ratio_old_mode2; + u32 wdt_rst; + u32 seda_loop_bak_err_pat_b01; + u32 seda_loop_bak_err_pat_b23; + u32 seda_loop_bak_err_pat_b45; + u32 seda_loop_bak_err_pat_b67; + u32 seda_loop_bak_set; + u32 rsvd_10[3]; + u32 dbg_cmddec_cmdsel0; + u32 dbg_cmddec_cmdsel1; + u32 dbg_cmddec_cmdsel2; + u32 dbg_cmddec_cmdsel3; + u32 dbg_cmddec_cmdsel4; + u32 rtswcmd_cnt; + u32 refctrl3; + u32 rsvd_11[1]; + u32 dramc_irq_en; + u32 dramc_irq_clear; + u32 irq_rsv1; + u32 irq_rsv2; + u32 refcnt_fr_clk1; + u32 refcnt_fr_clk2; + u32 refcnt_fr_clk3; + u32 refcnt_fr_clk4; + u32 refcnt_fr_clk5; + u32 refcnt_fr_clk6; + u32 refcnt_fr_clk7; + u32 rsvd_12[1]; + u32 dcm_sub_ctrl; + u32 rsvd_13[3]; + u32 cbt_wlev_ctrl5; + u32 rsvd_14[3]; + u32 dram_clk_ctrl; + u32 rsvd_15[115]; + struct dramc_ao_rk rk[RANK_MAX]; + u32 rsvd_19[256]; + u32 wdt_dbg_signal; + u32 rsvd_20[1]; + u32 selfref_hwsave_flag; + u32 rsvd_21[125]; + u32 dramc_irq_status1; + u32 dramc_irq_status2; + u32 rsvd_22[2]; + u32 dramc_irq_info1; + u32 dramc_irq_info1a; + u32 rsvd_23[2]; + u32 dramc_irq_info2; + u32 dramc_irq_info3; + u32 dramc_irq_info4; + u32 dramc_irq_info5; + u32 rsvd_24[180]; + struct dramc_ao_shu_rk shu_rk[RANK_MAX]; + u32 shu_matype; + u32 shu_common0; + u32 shu_sref_ctrl; + u32 shu_scheduler; + u32 shu_dcm_ctrl0; + u32 shu_hmr4_dvfs_ctrl0; + u32 shu_selph_ca1; + u32 shu_selph_ca2; + u32 shu_selph_ca3; + u32 shu_selph_ca4; + u32 shu_selph_ca5; + u32 shu_selph_ca6; + u32 shu_selph_ca7; + u32 shu_selph_ca8; + u32 shu_hwset_mr2; + u32 shu_hwset_mr13; + u32 shu_hwset_vrcg; + u32 shu_actim0; + u32 shu_actim1; + u32 shu_actim2; + u32 shu_actim3; + u32 shu_actim4; + u32 shu_actim5; + u32 shu_actim6; + u32 shu_actim_xrt; + u32 shu_ac_time_05t; + u32 shu_ac_derating0; + u32 shu_ac_derating1; + u32 shu_ac_derating_05t; + u32 shu_actiming_conf; + u32 shu_ckectrl; + u32 shu_selph_dqs0; + u32 shu_selph_dqs1; + u32 shu_wodt; + u32 shu_tx_set0; + u32 shu_rx_cg_set0; + u32 shu_dqsosc_set0; + u32 shu_dqsoscr; + u32 shu_tx_rankctl; + u32 shu_zq_set0; + u32 shu_conf0; + u32 shu_misc; + u32 shu_new_xrw2w_ctrl; + u32 shu_aphy_tx_picg_ctrl; + u32 shu_freq_ratio_set0; + u32 shu_freq_ratio_set1; + u32 shu_freq_ratio_set2; + u32 shureg_rsv; + u32 shu_wckctrl; + u32 shu_wckctrl_1; + u32 rsvd_28[2]; + u32 shu_rx_set0; + u32 shu_ref0; + u32 rsvd_29[2]; + u32 shu_lp5_cmd; + u32 shu_lp5_sact; + u32 shu_actim7; +}; + +struct emi_regs { + u32 cona; + u32 conp; + u32 conb; + u32 conq; + u32 conc; + u32 conr; + u32 cond; + u32 conp_2nd; + u32 cone; + u32 conq_2nd; + u32 conf; + u32 conr_2nd; + u32 cong; + u32 conb_3rd; + u32 conh; + u32 conh_2nd; + u32 coni; + u32 conb_4th; + u32 conj; + u32 conb_5th; + u32 conk; + u32 conb_6th; + u32 rsvd_0[1]; + u32 conb_7th; + u32 conm; + u32 conb_8th; + u32 conn; + u32 conc_3rd; + u32 cono; + u32 conc_4th; + u32 mdct; + u32 mdct_2nd; + u32 rsvd_1[1]; + u32 conc_5th; + u32 rsvd_2[1]; + u32 conc_6th; + u32 rsvd_3[1]; + u32 conc_7th; + u32 rsvd_4[1]; + u32 conc_8th; + u32 rsvd_5[9]; + u32 cong_3rd; + u32 cong_4th; + u32 cong_5th; + u32 iocl; + u32 iocl_2nd; + u32 iocm; + u32 iocm_2nd; + u32 rsvd_6[1]; + u32 cong_6th; + u32 testb; + u32 rsvd_7[1]; + u32 testc; + u32 cong_7th; + u32 testd; + u32 rsvd_8[1]; + u32 arba; + u32 rsvd_9[1]; + u32 arbb; + u32 rsvd_10[1]; + u32 arbc; + u32 rsvd_11[1]; + u32 arbd; + u32 rsvd_12[1]; + u32 arbe; + u32 rsvd_13[1]; + u32 arbf; + u32 cong_8th; + u32 arbg; + u32 rsvd_14[1]; + u32 arbh; + u32 conp_3rd; + u32 arbi; + u32 arbi_2nd; + u32 rsvd_15[1]; + u32 arbj_2nd; + u32 arbk; + u32 arbk_2nd; + u32 slct; + u32 rsvd_16[1]; + u32 mpud0_st; + u32 mpud1_st; + u32 mpud2_st; + u32 mpud3_st; + u32 mpud4_st; + u32 mpud5_st; + u32 mpud6_st; + u32 mpud7_st; + u32 mpud8_st; + u32 mpud9_st; + u32 mpud10_st; + u32 mpud11_st; + u32 mpud12_st; + u32 mpud13_st; + u32 mpud14_st; + u32 mpud15_st; + u32 mpud16_st; + u32 mpud17_st; + u32 mpud18_st; + u32 mpud19_st; + u32 mpud20_st; + u32 mpud21_st; + u32 mpud22_st; + u32 mpud23_st; + u32 mpud24_st; + u32 mpud25_st; + u32 mpud26_st; + u32 mpud27_st; + u32 mpud28_st; + u32 mpud29_st; + u32 mpud30_st; + u32 mpud31_st; + u32 conp_4th; + u32 conp_5th; + u32 conp_6th; + u32 rsvd_17[1]; + u32 mpus; + u32 conp_8th; + u32 mput; + u32 mput_2nd; + u32 d0_st2; + u32 d1_st2; + u32 d2_st2; + u32 d3_st2; + u32 d4_st2; + u32 d5_st2; + u32 d6_st2; + u32 d7_st2; + u32 d8_st2; + u32 d9_st2; + u32 d10_st2; + u32 d11_st2; + u32 d12_st2; + u32 d13_st2; + u32 d14_st2; + u32 d15_st2; + u32 d16_st2; + u32 d17_st2; + u32 d18_st2; + u32 d19_st2; + u32 d20_st2; + u32 d21_st2; + u32 d22_st2; + u32 d23_st2; + u32 d24_st2; + u32 d25_st2; + u32 d26_st2; + u32 d27_st2; + u32 d28_st2; + u32 d29_st2; + u32 d30_st2; + u32 d31_st2; + u32 rsvd_18[33]; + u32 prtcl_m0_cyc; + u32 rsvd_19[1]; + u32 prtcl_m0_ctl; + u32 rsvd_20[1]; + u32 prtcl_m0_msk; + u32 rsvd_21[13]; + u32 prtcl_m1_cyc; + u32 rsvd_22[1]; + u32 prtcl_m1_ctl; + u32 rsvd_23[1]; + u32 prtcl_m1_msk; + u32 rsvd_24[13]; + u32 prtcl_m2_cyc; + u32 rsvd_25[1]; + u32 prtcl_m2_ctl; + u32 rsvd_26[1]; + u32 prtcl_m2_msk; + u32 rsvd_27[12]; + u32 prtcl_m3_cyc; + u32 prtcl_m3_ctl; + u32 prtcl_m3_msk; + u32 rsvd_28[6]; + u32 prtcl_m4_cyc; + u32 bmen; + u32 bstp; + u32 bcnt; + u32 prtcl_m4_ctl; + u32 tact; + u32 prtcl_m4_msk; + u32 tsct; + u32 rsvd_29[1]; + u32 wact; + u32 rsvd_30[1]; + u32 wsct; + u32 rsvd_31[1]; + u32 bact; + u32 rsvd_32[1]; + u32 bsct; + u32 rsvd_33[1]; + u32 msel; + u32 rsvd_34[1]; + u32 tsct2; + u32 prtcl_m5_cyc; + u32 tsct3; + u32 prtcl_m5_ctl; + u32 wsct2; + u32 prtcl_m5_msk; + u32 wsct3; + u32 wsct4; + u32 msel2; + u32 rsvd_35[1]; + u32 msel3; + u32 rsvd_36[1]; + u32 msel4; + u32 rsvd_37[1]; + u32 msel5; + u32 rsvd_38[1]; + u32 msel6; + u32 rsvd_39[1]; + u32 msel7; + u32 rsvd_40[1]; + u32 msel8; + u32 prtcl_m6_cyc; + u32 msel9; + u32 prtcl_m6_ctl; + u32 msel10; + u32 prtcl_m6_msk; + u32 bmid0; + u32 bmid1; + u32 bmid2; + u32 bmid3; + u32 bmid4; + u32 bmid5; + u32 bmid6; + u32 bmid7; + u32 bmid8; + u32 bmid9; + u32 bmid10; + u32 rsvd_41[1]; + u32 bmen1; + u32 rsvd_42[1]; + u32 bmen2; + u32 rsvd_43[3]; + u32 bmrw0; + u32 bmrw1; + u32 ttype1; + u32 rsvd_44[1]; + u32 ttype2; + u32 prtcl_m7_cyc; + u32 ttype3; + u32 prtcl_m7_ctl; + u32 ttype4; + u32 prtcl_m7_msk; + u32 ttype5; + u32 rsvd_45[1]; + u32 ttype6; + u32 rsvd_46[1]; + u32 ttype7; + u32 rsvd_47[1]; + u32 ttype8; + u32 rsvd_48[1]; + u32 ttype9; + u32 rsvd_49[1]; + u32 ttype10; + u32 rsvd_50[1]; + u32 ttype11; + u32 rsvd_51[1]; + u32 ttype12; + u32 rsvd_52[1]; + u32 ttype13; + u32 rsvd_53[1]; + u32 ttype14; + u32 rsvd_54[1]; + u32 ttype15; + u32 rsvd_55[1]; + u32 ttype16; + u32 rsvd_56[1]; + u32 ttype17; + u32 rsvd_57[1]; + u32 ttype18; + u32 rsvd_58[1]; + u32 ttype19; + u32 rsvd_59[1]; + u32 ttype20; + u32 rsvd_60[1]; + u32 ttype21; + u32 rsvd_61[3]; + u32 bwct0; + u32 bwct1; + u32 bwct2; + u32 bwct3; + u32 bwct4; + u32 bwst0; + u32 bwst1; + u32 rsvd_62[1]; + u32 ex_con; + u32 ex_st0; + u32 ex_st1; + u32 ex_st2; + u32 wp_adr; + u32 wp_adr_2nd; + u32 wp_ctrl; + u32 rsvd_63[1]; + u32 chker; + u32 chker_type; + u32 chker_adr; + u32 chker_adr_2nd; + u32 rsvd_64[7]; + u32 thro_slv_con0; + u32 rsvd_65[1]; + u32 thro_slv_con1; + u32 mxto0; + u32 mxto1; + u32 rsvd_66[4]; + u32 conq_3rd; + u32 conq_4th; + u32 conq_5th; + u32 conq_6th; + u32 rsvd_67[4]; + u32 conq_7th; + u32 conq_8th; + u32 conr_3rd; + u32 conr_4th; + u32 rsvd_68[9]; + u32 conr_5th; + u32 rsvd_69[2]; + u32 bwct0_2nd; + u32 rsvd_70[25]; + u32 conr_6th; + u32 conr_7th; + u32 shf0; + u32 dvfs_shf_con; + u32 shf1; + u32 clua; + u32 rsvd_71[10]; + u32 conr_8th; + u32 rsvd_72[1]; + u32 ltct0_2nd; + u32 ltct1_2nd; + u32 ltct2_2nd; + u32 ltct3_2nd; + u32 rsvd_73[4]; + u32 bwct0_3rd; + u32 bwlmte_8th; + u32 rsvd_74[1]; + u32 bwlmtf_8th; + u32 bwct0_4th; + u32 bwlmtg_8th; + u32 rsvd_75[1]; + u32 bwlmth_8th; + u32 rsvd_76[5]; + u32 chn_hash0; + u32 rsvd_77[2]; + u32 bwct0_5th; + u32 rsvd_78[5]; + u32 bwct0_6th; + u32 rsvd_79[11]; + u32 snst; + u32 rsvd_80[1]; + u32 slva; + u32 rsvd_81[7]; + u32 thro_os0; + u32 thro_os1; + u32 thro_os2; + u32 thro_os3; + u32 thro_ctrl0; + u32 thro_prd0; + u32 thro_prd1; + u32 thro_lat0; + u32 thro_lat1; + u32 thro_lat2; + u32 thro_lat3; + u32 thro_lat4; + u32 thro_lat5; + u32 thro_lat6; + u32 thro_ctrl1; + u32 thro_prd2; + u32 rsvd_82[5]; + u32 thro_lat7; + u32 thro_lat8; + u32 thro_prd3; + u32 rsvd_83[4]; + u32 bwlmta; + u32 bwlmtb; + u32 rsvd_84[2]; + u32 bwlmte; + u32 bwlmtf; + u32 rsvd_85[2]; + u32 conb_2nd; + u32 conc_2nd; + u32 cong_2nd; + u32 rsvd_86[1]; + u32 thro_lat9; + u32 thro_lat10; + u32 thro_lat11; + u32 thro_lat12; + u32 thro_lat13; + u32 thro_lat14; + u32 rsvd_87[2]; + u32 bwlmte_2nd; + u32 bwlmtf_2nd; + u32 bwlmtg_2nd; + u32 rsvd_88[13]; + u32 bwlmte_4th; + u32 bwlmtf_4th; + u32 rsvd_89[2]; + u32 bwlmte_5th; + u32 bwlmtf_5th; + u32 bwlmtg_5th; + u32 rsvd_90[7]; + u32 bwlmtg_7th; + u32 rsvd_91[12]; + u32 axi_bist_adr0; + u32 axi_bist_adr1; + u32 axi_bist_adr2; + u32 rsvd_92[22]; + u32 thro_lat27; + u32 thro_lat28; + u32 thro_lat29; + u32 thro_lat30; + u32 rsvd_93[64]; + u32 thro_lat31; + u32 thro_lat32; + u32 thro_lat33; + u32 thro_lat34; + u32 thro_lat35; + u32 thro_lat36; + u32 rsvd_94[4]; + u32 thro_lat41; + u32 thro_lat42; + u32 rsvd_95[12]; + u32 thro_lat55; + u32 thro_lat56; + u32 rsvd_96[12]; + u32 thro_lat69; + u32 thro_lat70; + u32 rsvd_97[12]; + u32 thro_lat83; + u32 thro_lat84; + u32 rsvd_98[12]; + u32 thro_lat97; + u32 thro_lat98; + u32 rsvd_99[12]; + u32 thro_lat111; + u32 thro_lat112; + u32 rsvd_100[1]; + u32 thro_prd5; + u32 rsvd_101[12]; + u32 thro_lat113; + u32 thro_lat114; + u32 thro_lat115; + u32 thro_lat116; + u32 thro_lat117; + u32 thro_lat118; + u32 thro_lat119; + u32 thro_lat120; + u32 rsvd_102[4]; + u32 thro_lat125; + u32 thro_lat126; + u32 rsvd_103[16]; + u32 thro_lat139; + u32 thro_lat140; + u32 rsvd_104[1]; + u32 qos_mdr_be0a; + u32 rsvd_105[1]; + u32 qos_mdr_be1a; + u32 rsvd_106[1]; + u32 qos_mdr_shf0; + u32 qos_mdr_shf1; + u32 qos_mdw_be0a; + u32 rsvd_107[1]; + u32 qos_mdw_be1a; + u32 rsvd_108[1]; + u32 qos_mdw_shf0; + u32 qos_mdw_shf1; + u32 qos_apr_be0a; + u32 rsvd_109[1]; + u32 qos_apr_be1a; + u32 rsvd_110[1]; + u32 qos_apr_shf0; + u32 qos_apw_be0a; + u32 rsvd_111[1]; + u32 qos_apw_be1a; + u32 rsvd_112[1]; + u32 qos_mmr_be0a; + u32 rsvd_113[1]; + u32 qos_mmr_be1a; + u32 qos_mmr_be1b; + u32 qos_mmr_be2a; + u32 qos_mmr_be2b; + u32 qos_mmr_shf0; + u32 qos_mmr_shf1; + u32 qos_mmw_be0a; + u32 rsvd_114[1]; + u32 qos_mmw_be1a; + u32 qos_mmw_be1b; + u32 qos_mmw_be2a; + u32 qos_mmw_be2b; + u32 qos_mmw_shf0; + u32 qos_mmw_shf1; + u32 qos_mdhwr_be0a; + u32 rsvd_115[1]; + u32 qos_mdhwr_be1a; + u32 rsvd_116[1]; + u32 qos_mdhwr_shf0; + u32 qos_mdhww_be0a; + u32 rsvd_117[1]; + u32 qos_mdhww_be1a; + u32 rsvd_118[1]; + u32 qos_gpur_be0a; + u32 rsvd_119[1]; + u32 qos_gpur_be1a; + u32 rsvd_120[1]; + u32 qos_gpur_shf0; + u32 qos_gpuw_be0a; + u32 rsvd_121[1]; + u32 qos_gpuw_be1a; + u32 rsvd_122[1]; + u32 qos_arbr_be0a; + u32 rsvd_123[1]; + u32 qos_arbr_be1a; + u32 rsvd_124[1]; + u32 qos_arbr_shf0; + u32 qos_ctrl1; + u32 rsvd_125[3]; + u32 ext_lt_con1_1st; + u32 ext_lt_con2_1st; + u32 ext_lt_con3_1st; + u32 rsvd_126[1]; + u32 ext_lt_con1_2nd; + u32 ext_lt_con2_2nd; + u32 ext_lt_con3_2nd; + u32 rsvd_127[1]; + u32 ext_lt_con1_3rd; + u32 ext_lt_con2_3rd; + u32 ext_lt_con3_3rd; + u32 rsvd_128[1]; + u32 ext_lt_con1_4th; + u32 ext_lt_con2_4th; + u32 ext_lt_con3_4th; +}; + +struct phy_ao_rk { + u32 shu_r0_b0_txdly0; + u32 shu_r0_b0_txdly1; + u32 shu_r0_b0_txdly2; + u32 shu_r0_b0_txdly3; + u32 shu_r0_b0_txdly4; + u32 shu_r0_b0_rxdly0; + u32 shu_r0_b0_rxdly1; + u32 shu_r0_b0_rxdly2; + u32 shu_r0_b0_rxdly3; + u32 shu_r0_b0_rxdly4; + u32 shu_r0_b0_rxdly5; + u32 shu_rk_b0_dq1; + u32 shu_b0_phy_vref_sel; + u32 shu_r0_b0_dq0; + u32 shu_r0_b0_ini_uipi; + u32 shu_r0_b0_next_ini_uipi; + u32 shu_dqsien_mck_ui_dly; + u32 shu_rk_b0_dqsien_pi_dly; + u32 shu_rk_b0_rodten_mck_ui_dly; + u32 shu_rk_b0_dq0; + u32 rsvd_0[4]; + u32 shu_rk_b0_bist_ctrl; + u32 rsvd_1[7]; +}; + +struct phy_ao_shu_byte { + struct phy_ao_rk rk[RANK_MAX]; + u32 shu_b0_dq0; + u32 shu_b0_dq3; + u32 shu_b0_dq4; + u32 shu_b0_dq5; + u32 shu_b0_dq6; + u32 shu_b0_dq1; + u32 shu_b0_dq2; + u32 shu_b0_dq10; + u32 shu_b0_dq11; + u32 shu_b0_dq7; + u32 shu_b0_dq8; + u32 shu_b0_dq9; + u32 shu_b0_dq12; + u32 shu_b0_dll0; + u32 shu_b0_dll1; + u32 shu_b0_dll2; + u32 shu_b0_rank_selph_ui_dly; + u32 shu_b0_dll_arpi2; + u32 shu_b0_dll_arpi3; + u32 shu_b0_txduty; + u32 shu_b0_vref; + u32 shu_b0_dq13; + u32 shu_b0_dq14; + u32 b0_shu_midpi_ctrl; + u32 rsvd_16[8]; +}; + +struct phy_ao_rx_dvs_byte { + struct { + u32 rk_b0_rxdvs0; + u32 rk_b0_rxdvs1; + u32 rk_b0_rxdvs2; + u32 rk_b0_rxdvs3; + u32 rk_b0_rxdvs4; + u32 rsvd[27]; + } rk[RANK_MAX]; + u32 b0_lp_ctrl0; + u32 b0_rxdvs0; + u32 b0_rxdvs1; + u32 b0_dll_arpi0; + u32 b0_dll_arpi1; + u32 b0_dll_arpi4; + u32 b0_dll_arpi5; + u32 b0_dq2; + u32 b0_dq3; + u32 b0_dq4; + u32 b0_dq5; + u32 b0_dq6; + u32 b0_dq7; + u32 b0_dq8; + u32 b0_dq9; + u32 b0_dq10; + u32 b0_dq11; + u32 b0_phy2; + u32 b0_phy3; + u32 b0_tx_mck; + u32 rsvd_3[12]; +}; + +struct phy_ao_ca_rk { + u32 shu_r0_ca_txdly0; + u32 shu_r0_ca_txdly1; + u32 shu_r0_ca_txdly2; + u32 shu_r0_ca_txdly3; + u32 shu_r0_ca_txdly4; + u32 shu_r0_ca_rxdly0; + u32 shu_r0_ca_rxdly1; + u32 shu_r0_ca_rxdly2; + u32 shu_r0_ca_rxdly6; + u32 shu_r0_ca_rxdly3; + u32 shu_r0_ca_rxdly4; + u32 shu_r0_ca_rxdly5; + u32 shu_r0_ca_rxdly7; + u32 shu_r0_ca_cmd0; + u32 shu_r0_ca_ini_uipi; + u32 shu_r0_ca_next_ini_uipi; + u32 shu_rk_ca_dqsien_mck_ui_dly; + u32 shu_rk_ca_dqsien_pi_dly; + u32 shu_rk_ca_rodten_mck_ui_dly; + u32 shu_rk_ca_cmd0; + u32 shu_rk_ca_cmd1; + u32 shu_ca_phy_vref_sel; + u32 rsvd[10]; +}; + +struct phy_ao_misc_rk { + u32 misc_shu_rk_dqsctl; + u32 misc_shu_rk_dqsien_picg_ctrl; + u32 misc_shu_rk_dqscal; + u32 rsvd[29]; +}; + +struct ddrphy_ao_regs { + u32 phypll0; + u32 phypll1; + u32 phypll2; + u32 rsvd_0[5]; + u32 clrpll0; + u32 rsvd_1[15]; + struct phy_ao_rx_dvs_byte dvs_b[BYTE_NUM]; + u32 rk_ca_rxdvs0; + u32 rk_ca_rxdvs1; + u32 rk_ca_rxdvs2; + u32 rk_ca_rxdvs3; + u32 rk_ca_rxdvs4; + u32 rsvd_6[59]; + u32 ca_lp_ctrl0; + u32 ca_rxdvs0; + u32 ca_rxdvs1; + u32 ca_dll_arpi0; + u32 ca_dll_arpi1; + u32 ca_dll_arpi4; + u32 ca_dll_arpi5; + u32 ca_cmd2; + u32 ca_cmd3; + u32 ca_cmd4; + u32 ca_cmd5; + u32 ca_cmd6; + u32 ca_cmd7; + u32 ca_cmd8; + u32 ca_cmd9; + u32 ca_cmd10; + u32 ca_cmd11; + u32 ca_phy2; + u32 ca_phy3; + u32 ca_tx_mck; + u32 rsvd_7[12]; + u32 misc_stbcal; + u32 misc_stbcal1; + u32 misc_stbcal2; + u32 misc_cg_ctrl0; + u32 misc_cg_ctrl1; + u32 misc_cg_ctrl2; + u32 misc_cg_ctrl3; + u32 rsvd_8[1]; + u32 misc_cg_ctrl5; + u32 misc_cg_ctrl7; + u32 misc_cg_ctrl9; + u32 misc_cg_ctrl10; + u32 misc_dvfsctl; + u32 misc_dvfsctl2; + u32 misc_dvfsctl3; + u32 misc_ckmux_sel; + u32 misc_clk_ctrl; + u32 misc_dqsg_retry1; + u32 misc_rdsel_track; + u32 misc_pre_tdqsck1; + u32 misc_cdc_ctrl; + u32 misc_lp_ctrl; + u32 misc_rg_dfs_ctrl; + u32 misc_ddr_reserve; + u32 misc_imp_ctrl1; + u32 misc_impcal; + u32 misc_impcal1; + u32 misc_impedamce_ctrl1; + u32 misc_impedamce_ctrl2; + u32 misc_impedamce_ctrl3; + u32 misc_impedamce_ctrl4; + u32 misc_peripher_ctrl2; + u32 misc_apb; + u32 misc_extlb0; + u32 misc_extlb1; + u32 misc_extlb2; + u32 misc_extlb3; + u32 misc_extlb4; + u32 misc_extlb5; + u32 misc_extlb6; + u32 misc_extlb7; + u32 misc_extlb8; + u32 misc_extlb9; + u32 misc_extlb10; + u32 misc_extlb11; + u32 misc_extlb12; + u32 misc_extlb13; + u32 misc_extlb14; + u32 misc_extlb15; + u32 misc_extlb16; + u32 misc_extlb17; + u32 misc_extlb18; + u32 misc_extlb19; + u32 misc_extlb20; + u32 misc_extlb21; + u32 misc_extlb22; + u32 misc_extlb23; + u32 misc_extlb_rx0; + u32 misc_extlb_rx1; + u32 misc_extlb_rx2; + u32 misc_extlb_rx3; + u32 misc_extlb_rx4; + u32 misc_extlb_rx5; + u32 misc_extlb_rx6; + u32 misc_extlb_rx7; + u32 misc_extlb_rx8; + u32 misc_extlb_rx9; + u32 misc_extlb_rx10; + u32 misc_extlb_rx11; + u32 misc_extlb_rx12; + u32 misc_extlb_rx13; + u32 misc_extlb_rx14; + u32 misc_extlb_rx15; + u32 misc_extlb_rx16; + u32 misc_extlb_rx17; + u32 misc_extlb_rx18; + u32 misc_extlb_rx19; + u32 misc_extlb_rx20; + u32 misc_sram_dma0; + u32 misc_sram_dma1; + u32 misc_sram_dma2; + u32 misc_dutyscan1; + u32 misc_miock_jit_mtr; + u32 misc_jmeter; + u32 misc_dvfs_emi_clk; + u32 misc_rx_in_gate_en_ctrl; + u32 misc_rx_in_buff_en_ctrl; + u32 misc_ctrl0; + u32 misc_ctrl1; + u32 misc_ctrl2; + u32 misc_ctrl3; + u32 misc_ctrl4; + u32 misc_ctrl5; + u32 misc_ctrl6; + u32 misc_vref_ctrl; + u32 misc_shu_opt; + u32 misc_rxdvs0; + u32 misc_rxdvs2; + u32 misc_dqsien_autok_cfg0; + u32 misc_dline_mon_cfg; + u32 misc_rx_autok_cfg0; + u32 misc_rx_autok_cfg1; + u32 rsvd_9[2]; + u32 misc_dbg_irq_ctrl0; + u32 misc_dbg_irq_ctrl1; + u32 misc_dbg_irq_ctrl2; + u32 misc_dbg_irq_ctrl3; + u32 misc_dbg_irq_ctrl4; + u32 misc_dbg_irq_ctrl5; + u32 misc_dbg_irq_ctrl6; + u32 misc_dbg_irq_ctrl7; + u32 misc_dbg_irq_ctrl8; + u32 misc_dbg_irq_ctrl9; + u32 rsvd_10[2]; + u32 misc_dq_se_pinmux_ctrl0; + u32 misc_dq_se_pinmux_ctrl1; + u32 rsvd_11[2]; + u32 misc_bist_lpbk_ctrl0; + u32 rsvd_12[15]; + u32 shu_phypll0; + u32 shu_phypll1; + u32 shu_phypll2; + u32 shu_phypll3; + u32 shu_phypll4; + u32 shu_phypll5; + u32 shu_phypll6; + u32 shu_phypll7; + u32 shu_clrpll0; + u32 shu_clrpll1; + u32 shu_clrpll2; + u32 shu_clrpll3; + u32 shu_clrpll4; + u32 shu_clrpll5; + u32 shu_clrpll6; + u32 shu_clrpll7; + u32 shu_pll0; + u32 shu_pll1; + u32 shu_pll2; + u32 rsvd_13[5]; + struct phy_ao_shu_byte byte[BYTE_NUM]; + struct phy_ao_ca_rk ca_rk[RANK_MAX]; + u32 shu_ca_cmd0; + u32 shu_ca_cmd3; + u32 shu_ca_cmd4; + u32 shu_ca_cmd5; + u32 shu_ca_cmd6; + u32 shu_ca_cmd1; + u32 shu_ca_cmd2; + u32 shu_ca_cmd10; + u32 shu_ca_cmd11; + u32 shu_ca_cmd7; + u32 shu_ca_cmd8; + u32 shu_ca_cmd9; + u32 shu_ca_cmd12; + u32 shu_ca_dll0; + u32 shu_ca_dll1; + u32 shu_ca_dll2; + u32 shu_ca_rank_selph_ui_dly; + u32 shu_ca_dll_arpi2; + u32 shu_ca_dll_arpi3; + u32 shu_ca_txduty; + u32 shu_ca_vref; + u32 shu_ca_cmd13; + u32 shu_ca_cmd14; + u32 ca_shu_midpi_ctrl; + u32 rsvd_21[8]; + struct phy_ao_misc_rk misc_rk[RANK_MAX]; + u32 misc_shu_drving7; + u32 misc_shu_drving8; + u32 misc_shu_impedamce_offset1; + u32 misc_shu_impedamce_offset2; + u32 misc_shu_impedamce_offset3; + u32 misc_shu_impedamce_offset4; + u32 misc_shu_impedamce_offset5; + u32 misc_shu_impedamce_offset6; + u32 misc_shu_impedamce_offset7; + u32 misc_shu_impedamce_offset8; + u32 misc_shu_impedamce_offset9; + u32 misc_shu_impedamce_upd_dis1; + u32 shu_misc_sw_impcal; + u32 misc_shu_stbcal; + u32 misc_shu_stbcal1; + u32 misc_shu_dvfsdll; + u32 misc_shu_rankctl; + u32 misc_shu_phy_rx_ctrl; + u32 misc_shu_odtctrl; + u32 misc_shu_rodtenstb; + u32 misc_shu_rodtenstb1; + u32 misc_shu_dqsg_retry1; + u32 misc_shu_rdat; + u32 misc_shu_rdat1; + u32 shu_misc_clk_ctrl0; + u32 shu_misc_impcal1; + u32 shu_misc_drving1; + u32 shu_misc_drving2; + u32 shu_misc_drving3; + u32 shu_misc_drving4; + u32 shu_misc_drving5; + u32 shu_misc_drving6; + u32 shu_misc_duty_scan; + u32 shu_misc_dma; + u32 shu_misc_rvref; + u32 shu_misc_rx_pipe_ctrl; + u32 shu_misc_tx_pipe_ctrl; + u32 shu_misc_emi_ctrl; + u32 shu_misc_rank_sel_stb; + u32 shu_misc_rdsel_track; + u32 shu_misc_pre_tdqsck; + u32 shu_misc_async_fifo_ctrl; + u32 misc_shu_rx_selph_mode; + u32 misc_shu_rank_sel_lat; + u32 misc_shu_dline_mon_ctrl; + u32 misc_shu_dline_mon_cnt; + u32 misc_shu_midpi_ctrl; + u32 rsvd_23[1]; + u32 misc_shu_rx_cg_ctrl; + u32 misc_shu_cg_ctrl0; + u32 rsvd_24[470]; + u32 misc_stberr_all; + u32 misc_stberr_rk0_r; + u32 misc_stberr_rk0_f; + u32 misc_stberr_rk1_r; + u32 misc_stberr_rk1_f; + u32 rsvd_25[3]; + u32 misc_ddr_reserve_state; + u32 rsvd_26[3]; + u32 misc_irq_status0; + u32 misc_irq_status1; + u32 misc_irq_status2; + u32 rsvd_27[49]; + u32 misc_dbg_db_message0; + u32 misc_dbg_db_message1; + u32 misc_dbg_db_message2; + u32 misc_dbg_db_message3; + u32 misc_dbg_db_message4; + u32 misc_dbg_db_message5; + u32 misc_dbg_db_message6; + u32 misc_dbg_db_message7; +}; + +struct emi_chn_regs { + u32 cona; + u32 rsvd_0[1]; + u32 conb; + u32 rsvd_1[1]; + u32 conc; + u32 rsvd_2[1]; + u32 mdct; + u32 rsvd_3[1]; + u32 ebg_con; + u32 rsvd_4[9]; + u32 testb; + u32 rsvd_5[1]; + u32 testc; + u32 rsvd_6[1]; + u32 testd; + u32 rsvd_7[9]; + u32 md_pre_mask; + u32 rsvd_8[1]; + u32 md_pre_mask_shf; + u32 rsvd_9[1]; + u32 ap_early_cke; + u32 rsvd_10[1]; + u32 dqfr; + u32 rsvd_11[41]; + u32 arbi; + u32 arbi_2nd; + u32 arbj; + u32 arbj_2nd; + u32 arbk; + u32 arbk_2nd; + u32 slct; + u32 arb_rff; + u32 rsvd_12[3]; + u32 drs_mon0; + u32 drs_mon1; + u32 rsvd_13[15]; + u32 rkarb0; + u32 rkarb1; + u32 rkarb2; + u32 rsvd_14[144]; + u32 eco3; + u32 rsvd_15[1]; + u32 md_pre_mask_shf0; + u32 md_pre_mask_shf1; + u32 qos_mdr_shf0; + u32 rsvd_16[192]; + u32 shf0; +}; + +struct emi_mpu_regs { + u32 mpu_ctrl; + u32 rsvd[511]; + u32 mpu_ctrl_d[16]; +}; + +struct infra_ao_mem_regs { + u32 rsvd_0[10]; + u32 emi_dcm_cfg0; + u32 emi_dcm_cfg1; + u32 emi_dcm_cfg2; + u32 emi_dcm_cfg3; + u32 top_ck_anchor_cfg; + u32 rsvd_2[5]; + u32 emi_disph_cfg; + u32 rsvd_3[43]; + u32 emi_idle_bit_en_0; + u32 emi_idle_bit_en_1; + u32 emi_idle_bit_en_2; + u32 emi_idle_bit_en_3; + u32 emi_m0m1_idle_bit_en_0; + u32 emi_m0m1_idle_bit_en_1; + u32 emi_m0m1_idle_bit_en_2; + u32 emi_m0m1_idle_bit_en_3; + u32 emi_m2m5_idle_bit_en_0; + u32 emi_m2m5_idle_bit_en_1; + u32 emi_m2m5_idle_bit_en_2; + u32 emi_m2m5_idle_bit_en_3; + u32 emi_m3_idle_bit_en_0; + u32 emi_m3_idle_bit_en_1; + u32 emi_m3_idle_bit_en_2; + u32 emi_m3_idle_bit_en_3; + u32 emi_m4_idle_bit_en_0; + u32 emi_m4_idle_bit_en_1; + u32 emi_m4_idle_bit_en_2; + u32 emi_m4_idle_bit_en_3; + u32 emi_m6m7_idle_bit_en_0; + u32 emi_m6m7_idle_bit_en_1; + u32 emi_m6m7_idle_bit_en_2; + u32 emi_m6m7_idle_bit_en_3; + u32 emi_sram_idle_bit_en_0; + u32 emi_sram_idle_bit_en_1; + u32 emi_sram_idle_bit_en_2; + u32 emi_sram_idle_bit_en_3; +}; + +struct dramc_channel_regs { + union { + struct dramc_ao_regs ao; + uint8_t raw_ao_regs[0x4000]; + }; + union { + struct dramc_nao_regs nao; + uint8_t raw_nao_regs[0x1000]; + }; + union { + struct emi_chn_regs emi_chn; + uint8_t raw_emi_regs[0x1000]; + }; + union { + struct ddrphy_nao_regs phy_nao; + uint8_t raw_ddrphy_nao_regs[0x2000]; + }; + union { + struct ddrphy_ao_regs phy_ao; + uint8_t raw_ddrphy_ao_regs[0x8000]; + }; +}; + +static struct dramc_channel_regs *const ch = (void *)DRAMC_CHA_AO_BASE; +#endif /* __SOC_MEDIATEK_MT8192_DRAMC_REGISTER_H__ */ diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h b/src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h new file mode 100644 index 0000000..15d138f --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h @@ -0,0 +1,2837 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_DRAMC_MACRO_DEF_H__ +#define __SOC_MEDIATEK_MT8192_DRAMC_MACRO_DEF_H__ + +/* DDRPHY_REG_PHYPLL1 */ +DEFINE_BIT(PHYPLL1_RG_RPHYPLL_TSTOP_EN, 0) +DEFINE_BIT(PHYPLL1_RG_RPHYPLL_TST_EN, 4) + +/* DDRPHY_REG_SHU_PHYPLL0 */ +DEFINE_BITFIELD(SHU_PHYPLL0_RG_RPHYPLL_RESERVED, 15, 0) +DEFINE_BITFIELD(SHU_PHYPLL0_RG_RPHYPLL_ICHP, 25, 24) + +/* DDRPHY_REG_SHU_CLRPLL0 */ +DEFINE_BITFIELD(SHU_CLRPLL0_RG_RCLRPLL_RESERVED, 15, 0) +DEFINE_BITFIELD(SHU_CLRPLL0_RG_RCLRPLL_ICHP, 25, 24) + +/* DDRPHY_REG_SHU_PHYPLL2 */ +DEFINE_BITFIELD(SHU_PHYPLL2_RG_RPHYPLL_POSDIV, 2, 0) +DEFINE_BITFIELD(SHU_PHYPLL2_RG_RPHYPLL_PREDIV, 19, 18) + +/* DDRPHY_REG_SHU_CLRPLL2 */ +DEFINE_BITFIELD(SHU_CLRPLL2_RG_RCLRPLL_POSDIV, 2, 0) +DEFINE_BITFIELD(SHU_CLRPLL2_RG_RCLRPLL_PREDIV, 19, 18) + +/* DDRPHY_REG_SHU_PHYPLL1 */ +DEFINE_BIT(SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN, 0) +DEFINE_BIT(SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG, 1) +DEFINE_BITFIELD(SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW, 31, 16) + +/* DDRPHY_REG_SHU_CLRPLL1 */ +DEFINE_BIT(SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN, 0) +DEFINE_BIT(SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG, 1) +DEFINE_BITFIELD(SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW, 31, 16) + +/* DDRPHY_REG_SHU_PLL1 */ +DEFINE_BIT(SHU_PLL1_RG_RPHYPLLGP_CK_SEL, 0) +DEFINE_BIT(SHU_PLL1_R_SHU_AUTO_PLL_MUX, 4) + +/* DDRPHY_REG_SHU_PHYPLL3 */ +DEFINE_BIT(SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL, 0) +DEFINE_BIT(SHU_PHYPLL3_RG_RPHYPLL_FBKSEL, 6) +DEFINE_BITFIELD(SHU_PHYPLL3_RG_RPHYPLL_RST_DLY, 9, 8) +DEFINE_BIT(SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN, 12) +DEFINE_BIT(SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN, 16) + +/* DDRPHY_REG_SHU_CLRPLL3 */ +DEFINE_BIT(SHU_CLRPLL3_RG_RCLRPLL_DIV_CK_SEL, 0) +DEFINE_BIT(SHU_CLRPLL3_RG_RCLRPLL_FBKSEL, 6) +DEFINE_BITFIELD(SHU_CLRPLL3_RG_RCLRPLL_RST_DLY, 9, 8) +DEFINE_BIT(SHU_CLRPLL3_RG_RCLRPLL_LVROD_EN, 12) +DEFINE_BIT(SHU_CLRPLL3_RG_RCLRPLL_MONCK_EN, 16) + +/* DDRPHY_REG_SHU_MISC_CLK_CTRL0 */ +DEFINE_BIT(SHU_MISC_CLK_CTRL0_M_CK_OPENLOOP_MODE_SEL, 4) + +/* DDRPHY_REG_SHU_B0_DQ14 */ +DEFINE_BIT(SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0, 2) +DEFINE_BITFIELD(SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0, 5, 4) +DEFINE_BIT(SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0, 11) +DEFINE_BITFIELD(SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0, 23, 16) + +/* DDRPHY_REG_SHU_B1_DQ14 */ +DEFINE_BIT(SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1, 2) +DEFINE_BITFIELD(SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1, 5, 4) +DEFINE_BIT(SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1, 11) +DEFINE_BITFIELD(SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1, 23, 16) + +/* DDRPHY_REG_SHU_B0_DQ6 */ +DEFINE_BITFIELD(SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0, 18, 12) +DEFINE_BIT(SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0, 20) +DEFINE_BIT(SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0, 21) +DEFINE_BITFIELD(SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0, 23, 22) +DEFINE_BIT(SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0, 29) + +/* DDRPHY_REG_SHU_B1_DQ6 */ +DEFINE_BITFIELD(SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1, 18, 12) +DEFINE_BIT(SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1, 20) +DEFINE_BIT(SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1, 21) +DEFINE_BITFIELD(SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1, 23, 22) +DEFINE_BIT(SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1, 29) + +/* DDRPHY_REG_SHU_CA_CMD11 */ +DEFINE_BIT(SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA, 0) +DEFINE_BIT(SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA, 1) +DEFINE_BIT(SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA, 2) +DEFINE_BITFIELD(SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA, 17, 16) +DEFINE_BITFIELD(SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA, 19, 18) + +/* DDRPHY_REG_SHU_B0_DQ11 */ +DEFINE_BIT(SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0, 0) +DEFINE_BIT(SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0, 1) +DEFINE_BIT(SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0, 2) +DEFINE_BIT(SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0, 7) +DEFINE_BITFIELD(SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0, 17, 16) +DEFINE_BITFIELD(SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0, 19, 18) + +/* DDRPHY_REG_SHU_B1_DQ11 */ +DEFINE_BIT(SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1, 0) +DEFINE_BIT(SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1, 1) +DEFINE_BIT(SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1, 2) +DEFINE_BIT(SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1, 7) +DEFINE_BITFIELD(SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1, 17, 16) +DEFINE_BITFIELD(SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1, 19, 18) + +/* DDRPHY_REG_SHU_CA_CMD14 */ +DEFINE_BITFIELD(SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA, 5, 4) +DEFINE_BIT(SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA, 11) +DEFINE_BITFIELD(SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA, 23, 16) + +/* DDRPHY_REG_SHU_CA_CMD6 */ +DEFINE_BITFIELD(SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA, 5, 0) +DEFINE_BITFIELD(SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA, 18, 12) +DEFINE_BIT(SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA, 20) +DEFINE_BIT(SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA, 21) +DEFINE_BITFIELD(SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA, 23, 22) +DEFINE_BIT(SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA, 26) +DEFINE_BIT(SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA, 27) +DEFINE_BIT(SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE, 29) + +/* DDRPHY_REG_SHU_B0_DLL1 */ +DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0, 4) +DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0, 6) +DEFINE_BITFIELD(SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0, 9, 8) +DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PS_EN_B0, 10) +DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0, 11) +DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PHDIV_B0, 12) +DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0, 13) +DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0, 14) +DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, 16) +DEFINE_BITFIELD(SHU_B0_DLL1_RG_ARDLL_PGAIN_B0, 23, 20) +DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0, 24) + +/* DDRPHY_REG_SHU_B1_DLL1 */ +DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1, 4) +DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1, 6) +DEFINE_BITFIELD(SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1, 9, 8) +DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PS_EN_B1, 10) +DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1, 11) +DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PHDIV_B1, 12) +DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1, 13) +DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1, 14) +DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, 16) +DEFINE_BITFIELD(SHU_B1_DLL1_RG_ARDLL_PGAIN_B1, 23, 20) +DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1, 24) + +/* DDRPHY_REG_SHU_CA_DLL1 */ +DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA, 4) +DEFINE_BITFIELD(SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA, 9, 8) +DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PS_EN_CA, 10) +DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA, 11) +DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PHDIV_CA, 12) +DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA, 13) +DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA, 14) +DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 16) +DEFINE_BITFIELD(SHU_CA_DLL1_RG_ARDLL_PGAIN_CA, 23, 20) +DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA, 24) + +/* DDRPHY_REG_SHU_B0_DQ1 */ +DEFINE_BIT(SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0, 0) +DEFINE_BIT(SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0, 2) +DEFINE_BITFIELD(SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0, 12, 8) +DEFINE_BITFIELD(SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0, 17, 16) +DEFINE_BIT(SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0, 26) +DEFINE_BIT(SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0, 27) +DEFINE_BIT(SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0, 31) + +/* DDRPHY_REG_SHU_B1_DQ1 */ +DEFINE_BIT(SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1, 0) +DEFINE_BIT(SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1, 2) +DEFINE_BITFIELD(SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1, 12, 8) +DEFINE_BITFIELD(SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1, 17, 16) +DEFINE_BIT(SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1, 26) +DEFINE_BIT(SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1, 27) +DEFINE_BIT(SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1, 31) + +/* DDRPHY_REG_SHU_CA_DLL_ARPI3 */ +DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN, 11) +DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN, 13) +DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN, 15) +DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN, 16) +DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA, 17) +DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA, 19) + +/* DDRPHY_REG_SHU_CA_CMD13 */ +DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA, 0) +DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCA_FRATE_EN_CA, 1) +DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA, 2) +DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA, 7) +DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA, 16) +DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA, 17) +DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA, 24) +DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA, 25) + +/* DDRPHY_REG_SHU_CA_CMD1 */ +DEFINE_BIT(SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA, 0) +DEFINE_BIT(SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA, 1) +DEFINE_BIT(SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA, 2) +DEFINE_BITFIELD(SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA, 12, 8) +DEFINE_BITFIELD(SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA, 17, 16) +DEFINE_BIT(SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA, 27) +DEFINE_BIT(SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA, 31) + +/* DDRPHY_REG_SHU_CA_DLL_ARPI2 */ +DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA, 10) +DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN, 11) +DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD, 13) +DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK, 15) +DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS, 16) +DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA, 17) +DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA, 19) +DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA, 27) +DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA, 31) + +/* DDRPHY_REG_CA_DLL_ARPI5 */ +DEFINE_BITFIELD(CA_DLL_ARPI5_RG_ARDLL_MON_SEL_CA, 7, 4) +DEFINE_BIT(CA_DLL_ARPI5_RG_ARDLL_DIV_DEC_CA, 8) +DEFINE_BIT(CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_CA, 25) +DEFINE_BIT(CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_CA, 26) +DEFINE_BIT(CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA, 28) +DEFINE_BITFIELD(CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA, 31, 29) + +/* DDRPHY_REG_B0_DLL_ARPI5 */ +DEFINE_BITFIELD(B0_DLL_ARPI5_RG_ARDLL_MON_SEL_B0, 7, 4) +DEFINE_BIT(B0_DLL_ARPI5_RG_ARDLL_DIV_DEC_B0, 8) +DEFINE_BIT(B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B0, 25) +DEFINE_BIT(B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B0, 26) +DEFINE_BIT(B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0, 28) +DEFINE_BITFIELD(B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0, 31, 29) + +/* DDRPHY_REG_B1_DLL_ARPI5 */ +DEFINE_BITFIELD(B1_DLL_ARPI5_RG_ARDLL_MON_SEL_B1, 7, 4) +DEFINE_BIT(B1_DLL_ARPI5_RG_ARDLL_DIV_DEC_B1, 8) +DEFINE_BIT(B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B1, 25) +DEFINE_BIT(B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B1, 26) +DEFINE_BIT(B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1, 28) +DEFINE_BITFIELD(B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1, 31, 29) + +/* DDRPHY_REG_CA_DLL_ARPI1 */ +DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_CLKIEN_JUMP_EN, 11) +DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_CMD_JUMP_EN, 13) +DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_CLK_JUMP_EN, 15) +DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_CS_JUMP_EN, 16) +DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_CA, 17) +DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_CA, 19) +DEFINE_BIT(CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT, 20) +DEFINE_BIT(CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA, 21) + +/* DDRPHY_REG_B0_DLL_ARPI1 */ +DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B0, 11) +DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B0, 13) +DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B0, 14) +DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B0, 15) +DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B0, 17) +DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B0, 19) +DEFINE_BIT(B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0_REG_OPT, 20) +DEFINE_BIT(B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0, 21) + +/* DDRPHY_REG_B1_DLL_ARPI1 */ +DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B1, 11) +DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B1, 13) +DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B1, 14) +DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B1, 15) +DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B1, 17) +DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B1, 19) +DEFINE_BIT(B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1_REG_OPT, 20) +DEFINE_BIT(B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1, 21) + +/* DDRPHY_REG_SHU_CA_DLL0 */ +DEFINE_BITFIELD(SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA, 15, 12) +DEFINE_BITFIELD(SHU_CA_DLL0_RG_ARDLL_GAIN_CA, 23, 20) +DEFINE_BIT(SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA, 25) +DEFINE_BIT(SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA, 26) +DEFINE_BIT(SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA, 27) + +/* DDRPHY_REG_SHU_B0_DLL0 */ +DEFINE_BITFIELD(SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0, 15, 12) +DEFINE_BITFIELD(SHU_B0_DLL0_RG_ARDLL_GAIN_B0, 23, 20) +DEFINE_BIT(SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0, 25) +DEFINE_BIT(SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0, 26) +DEFINE_BIT(SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0, 27) + +/* DDRPHY_REG_SHU_B1_DLL0 */ +DEFINE_BITFIELD(SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1, 15, 12) +DEFINE_BITFIELD(SHU_B1_DLL0_RG_ARDLL_GAIN_B1, 23, 20) +DEFINE_BIT(SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1, 25) +DEFINE_BIT(SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1, 26) +DEFINE_BIT(SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1, 27) + +/* DDRPHY_REG_SHU_B0_DLL_ARPI3 */ +DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0, 11) +DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0, 13) +DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0, 14) +DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0, 15) +DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_FB_EN_B0, 17) +DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0, 19) + +/* DDRPHY_REG_SHU_B1_DLL_ARPI3 */ +DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1, 11) +DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1, 13) +DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1, 14) +DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1, 15) +DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_FB_EN_B1, 17) +DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1, 19) + +/* DDRPHY_REG_SHU_CA_CMD2 */ +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA, 0) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA, 4) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA, 5) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA, 6) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA, 8) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA, 9) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA, 10) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA, 11) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU, 12) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA, 13) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA, 16) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA, 17) + +/* DDRPHY_REG_SHU_B0_DQ2 */ +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0, 0) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0, 4) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0, 5) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0, 6) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0, 8) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0, 9) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0, 10) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0, 11) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU, 12) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0, 13) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0, 16) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0, 17) + +/* DDRPHY_REG_SHU_B1_DQ2 */ +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1, 0) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1, 4) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1, 5) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1, 6) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1, 8) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1, 9) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1, 10) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1, 11) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU, 12) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1, 13) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1, 16) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1, 17) + +/* DDRPHY_REG_SHU_B0_DQ7 */ +DEFINE_BITFIELD(SHU_B0_DQ7_R_DMRANKRXDVS_B0, 3, 0) +DEFINE_BIT(SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0, 6) +DEFINE_BIT(SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 7) +DEFINE_BITFIELD(SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 11, 8) +DEFINE_BIT(SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 12) +DEFINE_BIT(SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 13) +DEFINE_BIT(SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0, 14) +DEFINE_BIT(SHU_B0_DQ7_R_DMRODTEN_B0, 15) +DEFINE_BIT(SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0, 16) +DEFINE_BIT(SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 17) +DEFINE_BIT(SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 18) +DEFINE_BIT(SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 19) +DEFINE_BIT(SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, 20) +DEFINE_BIT(SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0, 24) +DEFINE_BITFIELD(SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0, 27, 25) +DEFINE_BIT(SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0, 28) +DEFINE_BITFIELD(SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0, 31, 29) + +/* DDRPHY_REG_SHU_B1_DQ7 */ +DEFINE_BITFIELD(SHU_B1_DQ7_R_DMRANKRXDVS_B1, 3, 0) +DEFINE_BIT(SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1, 6) +DEFINE_BIT(SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 7) +DEFINE_BITFIELD(SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 11, 8) +DEFINE_BIT(SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 12) +DEFINE_BIT(SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 13) +DEFINE_BIT(SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1, 14) +DEFINE_BIT(SHU_B1_DQ7_R_DMRODTEN_B1, 15) +DEFINE_BIT(SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1, 16) +DEFINE_BIT(SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 17) +DEFINE_BIT(SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 18) +DEFINE_BIT(SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 19) +DEFINE_BIT(SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, 20) +DEFINE_BIT(SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1, 24) +DEFINE_BITFIELD(SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1, 27, 25) +DEFINE_BIT(SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1, 28) +DEFINE_BITFIELD(SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1, 31, 29) + +/* DDRPHY_REG_SHU_CA_CMD7 */ +DEFINE_BIT(SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW, 17) +DEFINE_BIT(SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW, 19) +DEFINE_BIT(SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK, 20) + +/* DDRPHY_REG_CA_CMD6 */ +DEFINE_BIT(CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN, 6) +DEFINE_BITFIELD(CA_CMD6_RG_RX_ARCMD_BIAS_VREF_SEL, 15, 14) +DEFINE_BIT(CA_CMD6_RG_RX_ARCMD_DDR4_SEL, 16) +DEFINE_BIT(CA_CMD6_RG_TX_ARCMD_DDR4_SEL, 17) +DEFINE_BIT(CA_CMD6_RG_RX_ARCMD_DDR3_SEL, 18) +DEFINE_BIT(CA_CMD6_RG_TX_ARCMD_DDR3_SEL, 19) +DEFINE_BIT(CA_CMD6_RG_TX_ARCMD_LP4_SEL, 21) + +/* DDRPHY_REG_B0_DQ6 */ +DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B0, 6) +DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0, 7) +DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_O1_SEL_B0, 9) +DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0, 12) +DEFINE_BITFIELD(B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0, 15, 14) +DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_DDR4_SEL_B0, 16) +DEFINE_BIT(B0_DQ6_RG_TX_ARDQ_DDR4_SEL_B0, 17) +DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0, 18) +DEFINE_BIT(B0_DQ6_RG_TX_ARDQ_DDR3_SEL_B0, 19) +DEFINE_BIT(B0_DQ6_RG_TX_ARDQ_LP4_SEL_B0, 21) +DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0, 28) +DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0, 31) + +/* DDRPHY_REG_B1_DQ6 */ +DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B1, 6) +DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1, 7) +DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_O1_SEL_B1, 9) +DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1, 12) +DEFINE_BITFIELD(B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1, 15, 14) +DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_DDR4_SEL_B1, 16) +DEFINE_BIT(B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1, 17) +DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_DDR3_SEL_B1, 18) +DEFINE_BIT(B1_DQ6_RG_TX_ARDQ_DDR3_SEL_B1, 19) +DEFINE_BIT(B1_DQ6_RG_TX_ARDQ_LP4_SEL_B1, 21) +DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1, 28) +DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1, 31) + +/* DDRPHY_REG_CA_CMD2 */ +DEFINE_BIT(CA_CMD2_RG_TX_ARCLK_ODTEN_DIS_CA, 0) +DEFINE_BIT(CA_CMD2_RG_TX_ARCLK_OE_DIS_CA, 1) +DEFINE_BIT(CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA, 2) +DEFINE_BIT(CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA, 3) +DEFINE_BIT(CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA, 14) +DEFINE_BIT(CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA, 15) +DEFINE_BIT(CA_CMD2_RG_TX_ARCMD_ODTEN_DIS_CA, 20) +DEFINE_BIT(CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 21) +DEFINE_BIT(CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 22) +DEFINE_BITFIELD(CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 31, 24) + +/* DDRPHY_REG_B0_DQ2 */ +DEFINE_BIT(B0_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B0, 0) +DEFINE_BIT(B0_DQ2_RG_TX_ARDQS0_OE_DIS_B0, 1) +DEFINE_BIT(B0_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B0, 2) +DEFINE_BIT(B0_DQ2_RG_TX_ARDQS_OE_TIE_EN_B0, 3) +DEFINE_BIT(B0_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B0, 8) +DEFINE_BIT(B0_DQ2_RG_TX_ARWCK_OE_TIE_EN_B0, 9) +DEFINE_BIT(B0_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B0, 10) +DEFINE_BIT(B0_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B0, 11) +DEFINE_BIT(B0_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B0, 12) +DEFINE_BIT(B0_DQ2_RG_TX_ARDQM0_OE_DIS_B0, 13) +DEFINE_BIT(B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0, 14) +DEFINE_BIT(B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0, 15) +DEFINE_BIT(B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0, 20) +DEFINE_BIT(B0_DQ2_RG_TX_ARDQ_OE_DIS_B0, 21) +DEFINE_BIT(B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0, 22) +DEFINE_BITFIELD(B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0, 31, 24) + +/* DDRPHY_REG_B1_DQ2 */ +DEFINE_BIT(B1_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B1, 0) +DEFINE_BIT(B1_DQ2_RG_TX_ARDQS0_OE_DIS_B1, 1) +DEFINE_BIT(B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1, 2) +DEFINE_BIT(B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1, 3) +DEFINE_BIT(B1_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B1, 8) +DEFINE_BIT(B1_DQ2_RG_TX_ARWCK_OE_TIE_EN_B1, 9) +DEFINE_BIT(B1_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B1, 10) +DEFINE_BIT(B1_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B1, 11) +DEFINE_BIT(B1_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B1, 12) +DEFINE_BIT(B1_DQ2_RG_TX_ARDQM0_OE_DIS_B1, 13) +DEFINE_BIT(B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1, 14) +DEFINE_BIT(B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1, 15) +DEFINE_BIT(B1_DQ2_RG_TX_ARDQ_ODTEN_DIS_B1, 20) +DEFINE_BIT(B1_DQ2_RG_TX_ARDQ_OE_DIS_B1, 21) +DEFINE_BIT(B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1, 22) +DEFINE_BITFIELD(B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1, 31, 24) + +/* DDRPHY_REG_CA_CMD3 */ +DEFINE_BIT(CA_CMD3_RG_TX_ARCMD_EN, 2) +DEFINE_BIT(CA_CMD3_RG_ARCMD_RESETB, 3) + +/* DDRPHY_REG_B0_DQ3 */ +DEFINE_BIT(B0_DQ3_RG_RX_ARDQ_SMT_EN_B0, 1) +DEFINE_BIT(B0_DQ3_RG_TX_ARDQ_EN_B0, 2) +DEFINE_BIT(B0_DQ3_RG_ARDQ_RESETB_B0, 3) +DEFINE_BIT(B0_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B0, 5) +DEFINE_BIT(B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0, 7) +DEFINE_BIT(B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0, 10) + +/* DDRPHY_REG_B1_DQ3 */ +DEFINE_BIT(B1_DQ3_RG_RX_ARDQ_SMT_EN_B1, 1) +DEFINE_BIT(B1_DQ3_RG_TX_ARDQ_EN_B1, 2) +DEFINE_BIT(B1_DQ3_RG_ARDQ_RESETB_B1, 3) +DEFINE_BIT(B1_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B1, 5) +DEFINE_BIT(B1_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B1, 7) +DEFINE_BIT(B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1, 10) + +/* DDRPHY_REG_SHU_B0_DQ13 */ +DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0, 0) +DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0, 2) +DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0, 3) +DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0, 7) +DEFINE_BITFIELD(SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0, 13, 12) +DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0, 15) +DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0, 16) +DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0, 17) +DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0, 18) +DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0, 24) +DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0, 25) + +/* DDRPHY_REG_SHU_B1_DQ13 */ +DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1, 0) +DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1, 2) +DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1, 3) +DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1, 7) +DEFINE_BITFIELD(SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1, 13, 12) +DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1, 15) +DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1, 16) +DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1, 17) +DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1, 18) +DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1, 24) +DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1, 25) + +/* DDRPHY_REG_SHU_B0_DQ10 */ +DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0, 0) +DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0, 1) +DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0, 2) +DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0, 3) +DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0, 4) +DEFINE_BITFIELD(SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0, 10, 8) +DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0, 15) +DEFINE_BITFIELD(SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0, 19, 18) + +/* DDRPHY_REG_SHU_B1_DQ10 */ +DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1, 0) +DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1, 1) +DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1, 2) +DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1, 3) +DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1, 4) +DEFINE_BITFIELD(SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1, 10, 8) +DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1, 15) +DEFINE_BITFIELD(SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1, 19, 18) + +/* DDRPHY_REG_SHU_CA_CMD10 */ +DEFINE_BIT(SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_RANK_SEL_LAT_EN_CA, 2) +DEFINE_BIT(SHU_CA_CMD10_RG_RX_ARCLK_RANK_SEL_LAT_EN_CA, 3) +DEFINE_BIT(SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA, 15) +DEFINE_BITFIELD(SHU_CA_CMD10_RG_RX_ARCLK_BW_SEL_CA, 19, 18) + +/* DDRPHY_REG_B0_DQ5 */ +DEFINE_BITFIELD(B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0, 13, 8) +DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 16) +DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 17) +DEFINE_BITFIELD(B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0, 23, 20) +DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 24) +DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0, 25) +DEFINE_BIT(B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 31) + +/* DDRPHY_REG_B1_DQ5 */ +DEFINE_BITFIELD(B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1, 13, 8) +DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 16) +DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 17) +DEFINE_BITFIELD(B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1, 23, 20) +DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 24) +DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1, 25) +DEFINE_BIT(B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 31) + +/* DDRPHY_REG_CA_CMD9 */ +DEFINE_BIT(CA_CMD9_RG_RX_ARCMD_STBEN_RESETB, 0) +DEFINE_BIT(CA_CMD9_RG_RX_ARCLK_STBEN_RESETB, 4) + +/* DDRPHY_REG_B0_DQ9 */ +DEFINE_BIT(B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0) +DEFINE_BIT(B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 4) +DEFINE_BIT(B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 5) +DEFINE_BIT(B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 6) +DEFINE_BIT(B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 7) +DEFINE_BITFIELD(B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 15, 8) +DEFINE_BITFIELD(B0_DQ9_R_DMDQSIEN_VALID_LAT_B0, 18, 16) +DEFINE_BITFIELD(B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0, 22, 20) +DEFINE_BITFIELD(B0_DQ9_R_DMRXDVS_VALID_LAT_B0, 26, 24) +DEFINE_BITFIELD(B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0, 30, 28) + +/* DDRPHY_REG_B1_DQ9 */ +DEFINE_BIT(B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0) +DEFINE_BIT(B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 4) +DEFINE_BIT(B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 5) +DEFINE_BIT(B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 6) +DEFINE_BIT(B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 7) +DEFINE_BITFIELD(B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 15, 8) +DEFINE_BITFIELD(B1_DQ9_R_DMDQSIEN_VALID_LAT_B1, 18, 16) +DEFINE_BITFIELD(B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1, 22, 20) +DEFINE_BITFIELD(B1_DQ9_R_DMRXDVS_VALID_LAT_B1, 26, 24) +DEFINE_BITFIELD(B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1, 30, 28) + +/* DDRPHY_REG_CA_CMD8 */ +DEFINE_BIT(CA_CMD8_RG_RX_ARCLK_SER_RST_MODE, 13) +DEFINE_BIT(CA_CMD8_RG_ARDLL_RESETB_CA, 15) + +/* DDRPHY_REG_B0_DQ8 */ +DEFINE_BIT(B0_DQ8_RG_RX_ARDQS_SER_RST_MODE_B0, 13) +DEFINE_BIT(B0_DQ8_RG_ARDLL_RESETB_B0, 15) + +/* DDRPHY_REG_B1_DQ8 */ +DEFINE_BIT(B1_DQ8_RG_RX_ARDQS_SER_RST_MODE_B1, 13) +DEFINE_BIT(B1_DQ8_RG_ARDLL_RESETB_B1, 15) + +/* DDRPHY_REG_CA_CMD11 */ +DEFINE_BITFIELD(CA_CMD11_RG_RRESETB_DRVP, 4, 0) +DEFINE_BITFIELD(CA_CMD11_RG_RRESETB_DRVN, 12, 8) +DEFINE_BIT(CA_CMD11_RG_TX_RRESETB_DDR3_SEL, 19) +DEFINE_BIT(CA_CMD11_RG_TX_RRESETB_PULL_DN, 20) + +/* DDRPHY_REG_MISC_CTRL1 */ +DEFINE_BIT(MISC_CTRL1_R_RK_PINMUXSWAP_EN, 0) +DEFINE_BIT(MISC_CTRL1_R_DMPHYRST, 1) +DEFINE_BIT(MISC_CTRL1_R_DM_TX_ARCLK_OE, 2) +DEFINE_BIT(MISC_CTRL1_R_DM_TX_ARCMD_OE, 3) +DEFINE_BIT(MISC_CTRL1_R_DMARPIDQ_SW, 7) +DEFINE_BITFIELD(MISC_CTRL1_R_DMPINMUX, 9, 8) +DEFINE_BIT(MISC_CTRL1_R_DMRRESETB_I_OPT, 12) +DEFINE_BIT(MISC_CTRL1_R_DMDA_RRESETB_I, 13) +DEFINE_BIT(MISC_CTRL1_R_DMDQSIENCG_EN, 24) +DEFINE_BIT(MISC_CTRL1_R_DMSTBENCMP_RK_OPT, 25) +DEFINE_BIT(MISC_CTRL1_R_DMDA_RRESETB_E, 31) + +/* DDRPHY_REG_B0_LP_CTRL0 */ +DEFINE_BIT(B0_LP_CTRL0_RG_ARDMSUS_10_B0, 0) +DEFINE_BIT(B0_LP_CTRL0_RG_ARDMSUS_10_B0_LP_SEL, 4) +DEFINE_BIT(B0_LP_CTRL0_RG_ARDQ_RESETB_B0_LP_SEL, 8) +DEFINE_BIT(B0_LP_CTRL0_RG_ARPI_RESETB_B0_LP_SEL, 9) +DEFINE_BIT(B0_LP_CTRL0_RG_B0_MS_SLV_LP_SEL, 12) +DEFINE_BIT(B0_LP_CTRL0_RG_ARDLL_PHDET_EN_B0_LP_SEL, 13) +DEFINE_BIT(B0_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B0_LP_SEL, 16) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_MCK_B0_LP_SEL, 17) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B0_LP_SEL, 18) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_MCTL_B0_LP_SEL, 19) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_FB_B0_LP_SEL, 20) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_DQ_B0_LP_SEL, 21) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_DQM_B0_LP_SEL, 22) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_DQS_B0_LP_SEL, 23) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_DQSIEN_B0_LP_SEL, 24) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_MPDIV_CG_B0_LP_SEL, 25) +DEFINE_BIT(B0_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B0_LP_SEL, 26) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_MIDPI_EN_B0_LP_SEL, 27) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B0_LP_SEL, 28) + +/* DDRPHY_REG_B1_LP_CTRL0 */ +DEFINE_BIT(B1_LP_CTRL0_RG_ARDMSUS_10_B1, 0) +DEFINE_BIT(B1_LP_CTRL0_RG_ARDMSUS_10_B1_LP_SEL, 4) +DEFINE_BIT(B1_LP_CTRL0_RG_ARDQ_RESETB_B1_LP_SEL, 8) +DEFINE_BIT(B1_LP_CTRL0_RG_ARPI_RESETB_B1_LP_SEL, 9) +DEFINE_BIT(B1_LP_CTRL0_RG_B1_MS_SLV_LP_SEL, 12) +DEFINE_BIT(B1_LP_CTRL0_RG_ARDLL_PHDET_EN_B1_LP_SEL, 13) +DEFINE_BIT(B1_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B1_LP_SEL, 16) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_MCK_B1_LP_SEL, 17) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B1_LP_SEL, 18) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_MCTL_B1_LP_SEL, 19) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_FB_B1_LP_SEL, 20) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_DQ_B1_LP_SEL, 21) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_DQM_B1_LP_SEL, 22) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_DQS_B1_LP_SEL, 23) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_DQSIEN_B1_LP_SEL, 24) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_MPDIV_CG_B1_LP_SEL, 25) +DEFINE_BIT(B1_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B1_LP_SEL, 26) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_MIDPI_EN_B1_LP_SEL, 27) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B1_LP_SEL, 28) + +/* DDRPHY_REG_CA_LP_CTRL0 */ +DEFINE_BIT(CA_LP_CTRL0_RG_ARDMSUS_10_CA, 0) +DEFINE_BIT(CA_LP_CTRL0_RG_TX_ARCA_PULL_DN_LP_SEL, 1) +DEFINE_BIT(CA_LP_CTRL0_RG_TX_ARCA_PULL_UP_LP_SEL, 2) +DEFINE_BIT(CA_LP_CTRL0_RG_TX_ARCS_PULL_DN_LP_SEL, 3) +DEFINE_BIT(CA_LP_CTRL0_RG_ARDMSUS_10_CA_LP_SEL, 4) +DEFINE_BIT(CA_LP_CTRL0_RG_ARCMD_RESETB_LP_SEL, 8) +DEFINE_BIT(CA_LP_CTRL0_RG_ARPI_RESETB_CA_LP_SEL, 9) +DEFINE_BIT(CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL, 12) +DEFINE_BIT(CA_LP_CTRL0_RG_ARDLL_PHDET_EN_CA_LP_SEL, 13) +DEFINE_BIT(CA_LP_CTRL0_RG_TX_ARCS_PULL_UP_LP_SEL, 15) +DEFINE_BIT(CA_LP_CTRL0_RG_RX_ARCMD_BIAS_EN_LP_SEL, 16) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_MCK_CA_LP_SEL, 17) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_CA_LP_SEL, 18) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_MCTL_CA_LP_SEL, 19) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_FB_CA_LP_SEL, 20) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_CS_LP_SEL, 21) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_CLK_LP_SEL, 22) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_CMD_LP_SEL, 23) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_CLKIEN_LP_SEL, 24) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_MPDIV_CG_CA_LP_SEL, 25) +DEFINE_BIT(CA_LP_CTRL0_RG_RX_ARCMD_VREF_EN_LP_SEL, 26) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_MIDPI_EN_CA_LP_SEL, 27) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_CA_LP_SEL, 28) + +/* DDRPHY_REG_MISC_LP_CTRL */ +DEFINE_BIT(MISC_LP_CTRL_RG_ARDMSUS_10, 0) +DEFINE_BIT(MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL, 1) +DEFINE_BIT(MISC_LP_CTRL_RG_RIMP_DMSUS_10, 2) +DEFINE_BIT(MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL, 3) +DEFINE_BIT(MISC_LP_CTRL_RG_RRESETB_LP_SEL, 4) +DEFINE_BIT(MISC_LP_CTRL_RG_RPHYPLL_RESETB_LP_SEL, 5) +DEFINE_BIT(MISC_LP_CTRL_RG_RPHYPLL_EN_LP_SEL, 6) +DEFINE_BIT(MISC_LP_CTRL_RG_RCLRPLL_EN_LP_SEL, 7) +DEFINE_BIT(MISC_LP_CTRL_RG_RPHYPLL_ADA_MCK8X_EN_LP_SEL, 8) +DEFINE_BIT(MISC_LP_CTRL_RG_RPHYPLL_AD_MCK8X_EN_LP_SEL, 9) +DEFINE_BIT(MISC_LP_CTRL_RG_RPHYPLL_TOP_REV_0_LP_SEL, 10) +DEFINE_BIT(MISC_LP_CTRL_RG_SC_ARPI_RESETB_8X_SEQ_LP_SEL, 11) +DEFINE_BIT(MISC_LP_CTRL_RG_ADA_MCK8X_8X_SEQ_LP_SEL, 12) +DEFINE_BIT(MISC_LP_CTRL_RG_AD_MCK8X_8X_SEQ_LP_SEL, 13) +DEFINE_BIT(MISC_LP_CTRL_RG_MIDPI_EN_8X_SEQ_LP_SEL, 17) +DEFINE_BIT(MISC_LP_CTRL_RG_MIDPI_CKDIV4_EN_8X_SEQ_LP_SEL, 18) +DEFINE_BIT(MISC_LP_CTRL_RG_MCK8X_CG_SRC_LP_SEL, 19) +DEFINE_BIT(MISC_LP_CTRL_RG_MCK8X_CG_SRC_AND_LP_SEL, 20) + +/* DDRPHY_REG_MISC_CG_CTRL9 */ +DEFINE_BIT(MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN, 4) +DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN, 8) +DEFINE_BIT(MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF, 9) +DEFINE_BIT(MISC_CG_CTRL9_RG_DDR400_MCK4X_I_FORCE_ON, 10) +DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_I_FB_CK_CG_OFF, 11) +DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_Q_OPENLOOP_MODE_EN, 12) +DEFINE_BIT(MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF, 13) +DEFINE_BIT(MISC_CG_CTRL9_RG_DDR400_MCK4X_Q_FORCE_ON, 14) +DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF, 15) +DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_O_OPENLOOP_MODE_EN, 16) +DEFINE_BIT(MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_O_OFF, 17) +DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_O_FB_CK_CG_OFF, 19) + +/* DDRPHY_REG_MISC_SHU_RX_CG_CTRL */ +DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_DCM_OPT, 0) +DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT, 1) +DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_RODT_DCM_OPT, 2) +DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_DQSIEN_STBCAL_CG_EN, 4) +DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_DQSIEN_AUTOK_CG_EN, 5) +DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN, 8) +DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN, 9) +DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN, 10) +DEFINE_BITFIELD(MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY, 19, 16) +DEFINE_BITFIELD(MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY, 23, 20) + +/* DDRPHY_REG_MISC_SHU_CG_CTRL0 */ +DEFINE_BITFIELD(MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL, 31, 0) + +/* DDRPHY_REG_MISC_IMP_CTRL1 */ +DEFINE_BIT(MISC_IMP_CTRL1_RG_IMP_EN, 1) +DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL, 2) +DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL, 3) +DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_BIAS_EN, 4) +DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_ODT_EN, 5) +DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_PRE_EN, 6) +DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_VREF_EN, 7) +DEFINE_BIT(MISC_IMP_CTRL1_IMP_ABN_LAT_CLR, 14) +DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_SUS_ECO_OPT, 31) + +/* DDRPHY_REG_MISC_CG_CTRL0 */ +DEFINE_BIT(MISC_CG_CTRL0_W_CHG_MEM, 0) +DEFINE_BITFIELD(MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1, 3, 1) +DEFINE_BITFIELD(MISC_CG_CTRL0_CLK_MEM_SEL, 5, 4) +DEFINE_BIT(MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT7, 7) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE, 8) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE, 9) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE, 10) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE, 11) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE, 12) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE, 13) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE, 14) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE, 15) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE, 16) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE, 17) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN, 18) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE, 19) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF, 20) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF, 22) +DEFINE_BIT(MISC_CG_CTRL0_RG_FREERUN_MCK_CG, 29) + +/* DDRPHY_REG_MISC_CKMUX_SEL */ +DEFINE_BIT(MISC_CKMUX_SEL_R_PHYCTRLMUX, 0) +DEFINE_BIT(MISC_CKMUX_SEL_R_PHYCTRLDCM, 1) +DEFINE_BIT(MISC_CKMUX_SEL_RG_52M_104M_SEL, 12) +DEFINE_BITFIELD(MISC_CKMUX_SEL_FMEM_CK_MUX, 19, 18) + +/* DDRPHY_REG_PHYPLL2 */ +DEFINE_BIT(PHYPLL2_RG_RPHYPLL_RESETB, 16) +DEFINE_BIT(PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN, 21) +DEFINE_BIT(PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN, 22) + +/* DDRPHY_REG_PHYPLL0 */ +DEFINE_BIT(PHYPLL0_RG_RPHYPLL_EN, 31) + +/* DDRPHY_REG_SHU_B0_DLL_ARPI2 */ +DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0, 10) +DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 11) +DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0, 13) +DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0, 14) +DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0, 15) +DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0, 17) +DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0, 19) +DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0, 27) +DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0, 31) + +/* DDRPHY_REG_SHU_B1_DLL_ARPI2 */ +DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1, 10) +DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 11) +DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1, 13) +DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1, 14) +DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1, 15) +DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1, 17) +DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1, 19) +DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1, 27) +DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1, 31) + +/* DDRPHY_REG_SHU_PLL2 */ +DEFINE_BIT(SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU, 0) + +/* DDRPHY_REG_B0_SHU_MIDPI_CTRL */ +DEFINE_BIT(B0_SHU_MIDPI_CTRL_MIDPI_ENABLE_B0, 0) +DEFINE_BIT(B0_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B0, 1) + +/* DDRPHY_REG_B1_SHU_MIDPI_CTRL */ +DEFINE_BIT(B1_SHU_MIDPI_CTRL_MIDPI_ENABLE_B1, 0) +DEFINE_BIT(B1_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B1, 1) + +/* DDRPHY_REG_CA_SHU_MIDPI_CTRL */ +DEFINE_BIT(CA_SHU_MIDPI_CTRL_MIDPI_ENABLE_CA, 0) +DEFINE_BIT(CA_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_CA, 1) + +/* DDRPHY_REG_CA_DLL_ARPI0 */ +DEFINE_BIT(CA_DLL_ARPI0_RG_ARPI_RESETB_CA, 3) + +/* DDRPHY_REG_B0_DLL_ARPI0 */ +DEFINE_BIT(B0_DLL_ARPI0_RG_ARPI_RESETB_B0, 3) + +/* DDRPHY_REG_B1_DLL_ARPI0 */ +DEFINE_BIT(B1_DLL_ARPI0_RG_ARPI_RESETB_B1, 3) + +/* DDRPHY_REG_MISC_CG_CTRL2 */ +DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0) +DEFINE_BITFIELD(MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL, 5, 1) +DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON, 6) +DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN, 7) +DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN, 8) +DEFINE_BITFIELD(MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT, 15, 9) +DEFINE_BITFIELD(MISC_CG_CTRL2_RG_MEM_DCM_FSEL, 20, 16) +DEFINE_BITFIELD(MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL, 25, 21) +DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF, 26) +DEFINE_BIT(MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27, 27) +DEFINE_BIT(MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE, 28) +DEFINE_BIT(MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE, 29) +DEFINE_BIT(MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30, 30) +DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE, 31) + +/* DDRPHY_REG_MISC_CTRL0 */ +DEFINE_BIT(MISC_CTRL0_R_DMDQSIEN_FIFO_EN, 0) +DEFINE_BIT(MISC_CTRL0_R_DMSTBEN_SYNCOPT, 2) +DEFINE_BIT(MISC_CTRL0_R_DMVALID_DLY_OPT, 4) +DEFINE_BIT(MISC_CTRL0_R_DMVALID_NARROW_IG, 5) +DEFINE_BITFIELD(MISC_CTRL0_R_DMVALID_DLY, 10, 8) +DEFINE_BIT(MISC_CTRL0_IMPCAL_CHAB_EN, 12) +DEFINE_BIT(MISC_CTRL0_IMPCAL_TRACK_DISABLE, 13) +DEFINE_BIT(MISC_CTRL0_IMPCAL_LP_ECO_OPT, 18) +DEFINE_BIT(MISC_CTRL0_IMPCAL_CDC_ECO_OPT, 19) +DEFINE_BIT(MISC_CTRL0_IDLE_DCM_CHB_CDC_ECO_OPT, 20) +DEFINE_BIT(MISC_CTRL0_R_DMSHU_PHYDCM_FORCEOFF, 27) +DEFINE_BIT(MISC_CTRL0_R_DQS0IEN_DIV4_CK_CG_CTRL, 28) +DEFINE_BIT(MISC_CTRL0_R_DQS1IEN_DIV4_CK_CG_CTRL, 29) +DEFINE_BIT(MISC_CTRL0_R_CLKIEN_DIV4_CK_CG_CTRL, 30) +DEFINE_BIT(MISC_CTRL0_R_STBENCMP_DIV4CK_EN, 31) + +/* DDRPHY_REG_MISC_RXDVS2 */ +DEFINE_BIT(MISC_RXDVS2_R_DMRXDVS_DEPTH_HALF, 0) +DEFINE_BIT(MISC_RXDVS2_R_DMRXDVS_SHUFFLE_CTRL_CG_IG, 8) +DEFINE_BIT(MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN, 16) +DEFINE_BIT(MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR, 17) +DEFINE_BIT(MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN, 18) + +/* DDRPHY_REG_MISC_DVFS_EMI_CLK */ +DEFINE_BIT(MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY, 24) + +/* DDRPHY_REG_B0_DQ10 */ +DEFINE_BIT(B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0, 0) + +/* DDRPHY_REG_B1_DQ10 */ +DEFINE_BIT(B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1, 0) + +/* DDRPHY_REG_MISC_DVFSCTL */ +DEFINE_BITFIELD(MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW, 3, 0) +DEFINE_BITFIELD(MISC_DVFSCTL_R_DVFS_PICG_MARGIN2_NEW, 7, 4) +DEFINE_BITFIELD(MISC_DVFSCTL_R_DVFS_PICG_MARGIN3_NEW, 11, 8) +DEFINE_BITFIELD(MISC_DVFSCTL_R_DVFS_PICG_MARGIN4_NEW, 15, 12) +DEFINE_BIT(MISC_DVFSCTL_R_DMSHUFFLE_CHANGE_FREQ_OPT, 18) +DEFINE_BIT(MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE, 26) +DEFINE_BIT(MISC_DVFSCTL_R_DVFS_PICG_POSTPONE, 27) +DEFINE_BITFIELD(MISC_DVFSCTL_R_DVFS_MCK8X_MARGIN, 31, 28) + +/* DDRPHY_REG_MISC_STBCAL1 */ +DEFINE_BIT(MISC_STBCAL1_STBCNT_SHU_RST_EN, 0) +DEFINE_BIT(MISC_STBCAL1_DIS_PI_TRACK_AS_NOT_RD, 2) +DEFINE_BIT(MISC_STBCAL1_STBCNT_MODESEL, 4) +DEFINE_BIT(MISC_STBCAL1_DQSIEN_7UI_EN, 5) +DEFINE_BIT(MISC_STBCAL1_STB_SHIFT_DTCOUT_IG, 6) +DEFINE_BIT(MISC_STBCAL1_STB_FLAGCLR_OPT, 8) +DEFINE_BIT(MISC_STBCAL1_STBCNT_SW_RST, 15) +DEFINE_BITFIELD(MISC_STBCAL1_STBCAL_FILTER, 31, 16) + +/* DDRPHY_REG_MISC_STBCAL2 */ +DEFINE_BIT(MISC_STBCAL2_STB_PIDLYCG_IG, 0) +DEFINE_BIT(MISC_STBCAL2_STB_UIDLYCG_IG, 1) +DEFINE_BITFIELD(MISC_STBCAL2_STB_DBG_EN, 7, 4) +DEFINE_BIT(MISC_STBCAL2_STB_DBG_CG_AO, 8) +DEFINE_BIT(MISC_STBCAL2_STB_DBG_UIPI_UPD_OPT, 9) +DEFINE_BIT(MISC_STBCAL2_DQSGCNT_BYP_REF, 10) +DEFINE_BIT(MISC_STBCAL2_STB_PICG_EARLY_1T_EN, 16) +DEFINE_BIT(MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN, 17) +DEFINE_BIT(MISC_STBCAL2_STB_IG_XRANK_CG_RST, 18) +DEFINE_BIT(MISC_STBCAL2_STB_RST_BY_RANK, 19) +DEFINE_BIT(MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN, 20) +DEFINE_BIT(MISC_STBCAL2_STB_GERRSTOP, 28) +DEFINE_BIT(MISC_STBCAL2_STB_GERR_RST, 29) +DEFINE_BIT(MISC_STBCAL2_STB_GERR_B01, 30) +DEFINE_BIT(MISC_STBCAL2_STB_GERR_B23, 31) + +/* DDRPHY_REG_MISC_SHU_STBCAL */ +DEFINE_BITFIELD(MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE, 13, 12) +DEFINE_BIT(MISC_SHU_STBCAL_DQSIEN_BURST_MODE, 14) +DEFINE_BIT(MISC_SHU_STBCAL_STBCALEN, 16) +DEFINE_BIT(MISC_SHU_STBCAL_STB_SELPHCALEN, 17) + +/* DDRPHY_REG_MISC_STBCAL */ +DEFINE_BIT(MISC_STBCAL_PIMASK_RKCHG_OPT, 0) +DEFINE_BIT(MISC_STBCAL_STBDLELAST_OPT, 4) +DEFINE_BITFIELD(MISC_STBCAL_STBDLELAST_PULSE, 11, 8) +DEFINE_BIT(MISC_STBCAL_STBDLELAST_FILTER, 12) +DEFINE_BIT(MISC_STBCAL_STBSTATE_OPT, 15) +DEFINE_BIT(MISC_STBCAL_PHYVALID_IG, 16) +DEFINE_BIT(MISC_STBCAL_SREF_DQSGUPD, 17) +DEFINE_BIT(MISC_STBCAL_RKCHGMASKDIS, 19) +DEFINE_BIT(MISC_STBCAL_PICGEN, 20) +DEFINE_BIT(MISC_STBCAL_REFUICHG, 21) +DEFINE_BIT(MISC_STBCAL_STBCAL2R, 23) +DEFINE_BIT(MISC_STBCAL_PICHGBLOCK_NORD, 26) +DEFINE_BIT(MISC_STBCAL_STB_DQIEN_IG, 27) +DEFINE_BIT(MISC_STBCAL_DQSIENCG_CHG_EN, 28) +DEFINE_BIT(MISC_STBCAL_DQSIENCG_NORMAL_EN, 29) +DEFINE_BIT(MISC_STBCAL_DQSIENMODE, 31) + +/* DDRPHY_REG_B0_PHY2 */ +DEFINE_BITFIELD(B0_PHY2_RG_RX_ARDQS_JM_SEL_B0, 7, 4) +DEFINE_BIT(B0_PHY2_RG_RX_ARDQS_JM_EN_B0, 8) +DEFINE_BITFIELD(B0_PHY2_RG_RX_ARDQS_JM_DLY_B0, 24, 16) +DEFINE_BIT(B0_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B0, 28) + +/* DDRPHY_REG_B1_PHY2 */ +DEFINE_BITFIELD(B1_PHY2_RG_RX_ARDQS_JM_SEL_B1, 7, 4) +DEFINE_BIT(B1_PHY2_RG_RX_ARDQS_JM_EN_B1, 8) +DEFINE_BITFIELD(B1_PHY2_RG_RX_ARDQS_JM_DLY_B1, 24, 16) +DEFINE_BIT(B1_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B1, 28) + +/* DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL */ +DEFINE_BIT(MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT, 0) +DEFINE_BIT(MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN, 1) +DEFINE_BITFIELD(MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN, 11, 8) +DEFINE_BITFIELD(MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN, 15, 12) + +/* DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL */ +DEFINE_BIT(MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT, 0) +DEFINE_BIT(MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN, 1) +DEFINE_BITFIELD(MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN, 11, 8) +DEFINE_BITFIELD(MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN, 15, 12) + +/* DDRPHY_REG_B0_RXDVS0 */ +DEFINE_BIT(B0_RXDVS0_R_RX_RANKINSEL_B0, 0) +DEFINE_BITFIELD(B0_RXDVS0_R_RX_RANKINCTL_B0, 7, 4) +DEFINE_BIT(B0_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B0, 9) +DEFINE_BIT(B0_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B0, 19) +DEFINE_BIT(B0_RXDVS0_R_HWRESTORE_ENA_B0, 22) +DEFINE_BIT(B0_RXDVS0_R_HWSAVE_MODE_ENA_B0, 24) +DEFINE_BIT(B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0, 28) +DEFINE_BIT(B0_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B0, 29) +DEFINE_BIT(B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0, 31) + +/* DDRPHY_REG_B1_RXDVS0 */ +DEFINE_BIT(B1_RXDVS0_R_RX_RANKINSEL_B1, 0) +DEFINE_BITFIELD(B1_RXDVS0_R_RX_RANKINCTL_B1, 7, 4) +DEFINE_BIT(B1_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B1, 9) +DEFINE_BIT(B1_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B1, 19) +DEFINE_BIT(B1_RXDVS0_R_HWRESTORE_ENA_B1, 22) +DEFINE_BIT(B1_RXDVS0_R_HWSAVE_MODE_ENA_B1, 24) +DEFINE_BIT(B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1, 28) +DEFINE_BIT(B1_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B1, 29) +DEFINE_BIT(B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1, 31) + +/* DDRPHY_REG_RK_B0_RXDVS3 */ +DEFINE_BITFIELD(RK_B0_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B0, 7, 0) +DEFINE_BITFIELD(RK_B0_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B0, 15, 8) + +/* DDRPHY_REG_RK_B0_RXDVS4 */ +DEFINE_BITFIELD(RK_B0_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B0, 8, 0) +DEFINE_BITFIELD(RK_B0_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B0, 24, 16) + +/* DDRPHY_REG_RK_B0_RXDVS2 */ +DEFINE_BITFIELD(RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B0, 17, 16) +DEFINE_BITFIELD(RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B0, 19, 18) +DEFINE_BIT(RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0, 23) +DEFINE_BITFIELD(RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B0, 25, 24) +DEFINE_BITFIELD(RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B0, 27, 26) +DEFINE_BIT(RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0, 28) +DEFINE_BIT(RK_B0_RXDVS2_R_RK0_DVS_FDLY_MODE_B0, 29) +DEFINE_BITFIELD(RK_B0_RXDVS2_R_RK0_DVS_MODE_B0, 31, 30) + +/* DDRPHY_REG_RK_B0_RXDVS1 */ +DEFINE_BITFIELD(RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LAG, 15, 0) +DEFINE_BITFIELD(RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD, 31, 16) + +/* DDRPHY_REG_RK_B1_RXDVS3 */ +DEFINE_BITFIELD(RK_B1_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B1, 7, 0) +DEFINE_BITFIELD(RK_B1_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B1, 15, 8) + +/* DDRPHY_REG_RK_B1_RXDVS4 */ +DEFINE_BITFIELD(RK_B1_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B1, 8, 0) +DEFINE_BITFIELD(RK_B1_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B1, 24, 16) + +/* DDRPHY_REG_RK_B1_RXDVS2 */ +DEFINE_BITFIELD(RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B1, 17, 16) +DEFINE_BITFIELD(RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B1, 19, 18) +DEFINE_BIT(RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1, 23) +DEFINE_BITFIELD(RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B1, 25, 24) +DEFINE_BITFIELD(RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B1, 27, 26) +DEFINE_BIT(RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1, 28) +DEFINE_BIT(RK_B1_RXDVS2_R_RK0_DVS_FDLY_MODE_B1, 29) +DEFINE_BITFIELD(RK_B1_RXDVS2_R_RK0_DVS_MODE_B1, 31, 30) + +/* DDRPHY_REG_RK_B1_RXDVS1 */ +DEFINE_BITFIELD(RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LAG, 15, 0) +DEFINE_BITFIELD(RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LEAD, 31, 16) + +/* DDRPHY_REG_MISC_CG_CTRL1 */ +DEFINE_BITFIELD(MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL, 31, 0) + +/* DDRPHY_REG_B0_RXDVS1 */ +DEFINE_BIT(B0_RXDVS1_F_LEADLAG_TRACK_B0, 15) +DEFINE_BIT(B0_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B0, 17) + +/* DDRPHY_REG_B1_RXDVS1 */ +DEFINE_BIT(B1_RXDVS1_F_LEADLAG_TRACK_B1, 15) +DEFINE_BIT(B1_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B1, 17) + +/* DRAMC_REG_DLLFRZ_CTRL */ +DEFINE_BIT(DLLFRZ_CTRL_INPUTRXTRACK_BLOCK, 0) +DEFINE_BIT(DLLFRZ_CTRL_DLLFRZ_MON_PBREF_OPT, 1) +DEFINE_BIT(DLLFRZ_CTRL_DLLFRZ_BLOCKLONG, 2) +DEFINE_BIT(DLLFRZ_CTRL_DLLFRZ, 7) +DEFINE_BIT(DLLFRZ_CTRL_UPDBYWR, 8) + +/* DDRPHY_REG_MISC_RG_DFS_CTRL */ +DEFINE_BIT(MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL, 0) +DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DPY_RXDLY_TRACK_EN, 2) +DEFINE_BITFIELD(MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM, 7, 4) +DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE, 8) +DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM_LATCH, 9) +DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DR_SRAM_LOAD, 10) +DEFINE_BITFIELD(MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL, 17, 16) +DEFINE_BIT(MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN, 18) +DEFINE_BIT(MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN, 19) +DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DR_SHU_EN, 23) +DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN, 24) + +/* DDRPHY_REG_MISC_CTRL4 */ +DEFINE_BIT(MISC_CTRL4_R_OPT2_MPDIV_CG, 0) +DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_MCK, 1) +DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_DQM, 2) +DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_DQS, 3) +DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_DQ, 4) +DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_DQSIEN, 5) +DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_CMD, 6) +DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_CLK, 7) +DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_CS, 8) + +/* DDRPHY_REG_MISC_CTRL3 */ +DEFINE_BITFIELD(MISC_CTRL3_ARPI_CG_CMD_OPT, 1, 0) +DEFINE_BITFIELD(MISC_CTRL3_ARPI_CG_CLK_OPT, 3, 2) +DEFINE_BIT(MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT, 4) +DEFINE_BIT(MISC_CTRL3_ARPI_CG_MCK_CA_OPT, 5) +DEFINE_BIT(MISC_CTRL3_ARPI_CG_MCTL_CA_OPT, 6) +DEFINE_BITFIELD(MISC_CTRL3_ARPI_CG_DQ_OPT, 17, 16) +DEFINE_BITFIELD(MISC_CTRL3_ARPI_CG_DQS_OPT, 19, 18) +DEFINE_BIT(MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT, 20) +DEFINE_BIT(MISC_CTRL3_ARPI_CG_MCK_DQ_OPT, 21) +DEFINE_BIT(MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT, 22) +DEFINE_BIT(MISC_CTRL3_R_DDRPHY_COMB_CG_IG, 26) +DEFINE_BIT(MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG, 27) + +/* DDRPHY_REG_MISC_CG_CTRL5 */ +DEFINE_BIT(MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN, 16) +DEFINE_BIT(MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN, 17) +DEFINE_BIT(MISC_CG_CTRL5_R_CA_DLY_DCM_EN, 18) +DEFINE_BIT(MISC_CG_CTRL5_R_DQ1_PI_DCM_EN, 20) +DEFINE_BIT(MISC_CG_CTRL5_R_DQ0_PI_DCM_EN, 21) +DEFINE_BIT(MISC_CG_CTRL5_R_CA_PI_DCM_EN, 22) + +/* DRAMC_REG_RX_CG_SET0 */ +DEFINE_BIT(RX_CG_SET0_RDATCKAR, 30) +DEFINE_BIT(RX_CG_SET0_RDYCKAR, 31) + +/* DRAMC_REG_SREF_DPD_CTRL */ +DEFINE_BIT(SREF_DPD_CTRL_LPSM_BYPASS_B, 7) +DEFINE_BIT(SREF_DPD_CTRL_CLR_EN, 9) +DEFINE_BIT(SREF_DPD_CTRL_SELFREF_AUTOSAVE_EN, 10) +DEFINE_BIT(SREF_DPD_CTRL_SREF_PRD_OPT, 11) +DEFINE_BIT(SREF_DPD_CTRL_SREF_CG_OPT, 12) +DEFINE_BIT(SREF_DPD_CTRL_SRFPD_DIS, 13) +DEFINE_BITFIELD(SREF_DPD_CTRL_SREFDLY, 19, 16) +DEFINE_BIT(SREF_DPD_CTRL_SREF_HW_EN, 22) +DEFINE_BIT(SREF_DPD_CTRL_CMDCKAR, 26) +DEFINE_BIT(SREF_DPD_CTRL_GT_SYNC_MASK, 29) +DEFINE_BIT(SREF_DPD_CTRL_DAT_SYNC_MASK, 30) +DEFINE_BIT(SREF_DPD_CTRL_PHY_SYNC_MASK, 31) + +/* DRAMC_REG_DCM_CTRL0 */ +DEFINE_BIT(DCM_CTRL0_BCLKAR, 2) + +/* DRAMC_REG_TX_CG_SET0 */ +DEFINE_BIT(TX_CG_SET0_SELPH_4LCG_DIS, 0) +DEFINE_BIT(TX_CG_SET0_SELPH_CG_DIS, 1) +DEFINE_BIT(TX_CG_SET0_DWCLKRUN, 2) +DEFINE_BIT(TX_CG_SET0_WDATA_CG_DIS, 3) +DEFINE_BIT(TX_CG_SET0_TX_ATK_CLKRUN, 4) +DEFINE_BIT(TX_CG_SET0_PSELAR, 31) + +/* DRAMC_REG_SCSMCTRL_CG */ +DEFINE_BIT(SCSMCTRL_CG_SCARB_SM_CGAR, 30) +DEFINE_BIT(SCSMCTRL_CG_SCSM_CGAR, 31) + +/* DRAMC_REG_TX_TRACKING_SET0 */ +DEFINE_BIT(TX_TRACKING_SET0_TX_TRACKING_OPT, 15) +DEFINE_BIT(TX_TRACKING_SET0_SW_UP_TX_NOW_CASE, 16) +DEFINE_BIT(TX_TRACKING_SET0_TXUIPI_CAL_CGAR, 17) +DEFINE_BIT(TX_TRACKING_SET0_SHU_PRELOAD_TX_START, 18) +DEFINE_BIT(TX_TRACKING_SET0_SHU_PRELOAD_TX_HW, 19) +DEFINE_BIT(TX_TRACKING_SET0_HMRRSEL_CGAR, 21) +DEFINE_BIT(TX_TRACKING_SET0_RDDQSOSC_CGAR, 22) + +/* DRAMC_REG_ZQ_SET0 */ +DEFINE_BITFIELD(ZQ_SET0_ZQCSOP, 7, 0) +DEFINE_BITFIELD(ZQ_SET0_ZQCSAD, 15, 8) +DEFINE_BITFIELD(ZQ_SET0_ZQCS_MASK_SEL, 18, 16) +DEFINE_BIT(ZQ_SET0_ZQCS_MASK_SEL_CGAR, 19) +DEFINE_BIT(ZQ_SET0_ZQMASK_CGAR, 20) +DEFINE_BIT(ZQ_SET0_ZQCSMASK_OPT, 21) +DEFINE_BIT(ZQ_SET0_ZQCSMASK, 29) +DEFINE_BIT(ZQ_SET0_ZQCSDUAL, 30) + +/* DRAMC_REG_ACTIMING_CTRL */ +DEFINE_BIT(ACTIMING_CTRL_SEQCLKRUN3, 0) +DEFINE_BIT(ACTIMING_CTRL_SEQCLKRUN2, 1) +DEFINE_BIT(ACTIMING_CTRL_SEQCLKRUN, 2) +DEFINE_BIT(ACTIMING_CTRL_REFNA_OPT, 6) +DEFINE_BIT(ACTIMING_CTRL_REFBW_FREN, 8) +DEFINE_BIT(ACTIMING_CTRL_CLKWITRFC, 9) +DEFINE_BIT(ACTIMING_CTRL_TMRRICHKDIS, 21) +DEFINE_BIT(ACTIMING_CTRL_TMRRIBYRK_DIS, 22) +DEFINE_BIT(ACTIMING_CTRL_MRRIOPT, 23) +DEFINE_BIT(ACTIMING_CTRL_FASTW2R, 24) + +/* DRAMC_REG_CLKAR */ +DEFINE_BITFIELD(CLKAR_REQQUE_PACG_DIS, 14, 0) +DEFINE_BIT(CLKAR_DCMREF_OPT, 24) +DEFINE_BIT(CLKAR_REQQUECLKRUN, 27) + +/* DRAMC_REG_DRAMC_PD_CTRL */ +DEFINE_BIT(DRAMC_PD_CTRL_DCMEN, 0) +DEFINE_BIT(DRAMC_PD_CTRL_DCMEN2, 1) +DEFINE_BIT(DRAMC_PD_CTRL_DCMENNOTRFC, 2) +DEFINE_BIT(DRAMC_PD_CTRL_PHYGLUECLKRUN, 3) +DEFINE_BIT(DRAMC_PD_CTRL_COMBPHY_CLKENSAME, 5) +DEFINE_BIT(DRAMC_PD_CTRL_MIOCKCTRLOFF, 6) +DEFINE_BIT(DRAMC_PD_CTRL_PG_DCM_OPT, 9) +DEFINE_BIT(DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 12) +DEFINE_BIT(DRAMC_PD_CTRL_TCKFIXON, 13) +DEFINE_BIT(DRAMC_PD_CTRL_PHYCLKDYNGEN, 30) +DEFINE_BIT(DRAMC_PD_CTRL_COMBCLKCTRL, 31) + +/* DRAMC_REG_TEST2_A3 */ +DEFINE_BIT(TEST2_A3_ADRDECEN_TARKMODE, 5) +DEFINE_BIT(TEST2_A3_TESTAUDPAT, 7) +DEFINE_BIT(TEST2_A3_TESTCLKRUN, 8) +DEFINE_BIT(TEST2_A3_PAT_SHIFT_SW_EN, 11) +DEFINE_BIT(TEST2_A3_TEST2_PAT_SHIFT, 15) +DEFINE_BIT(TEST2_A3_TEST_AID_EN, 16) +DEFINE_BIT(TEST2_A3_HFIDPAT, 17) +DEFINE_BIT(TEST2_A3_AUTO_GEN_PAT, 18) +DEFINE_BIT(TEST2_A3_TEST2WREN2_HW_EN, 28) +DEFINE_BIT(TEST2_A3_TEST1, 29) +DEFINE_BIT(TEST2_A3_TEST2R, 30) +DEFINE_BIT(TEST2_A3_TEST2W, 31) + +/* DRAMC_REG_DVFS_CTRL0 */ +DEFINE_BIT(DVFS_CTRL0_R_DRAMC_CHA, 0) +DEFINE_BIT(DVFS_CTRL0_SHU_PHYRST_SEL, 1) +DEFINE_BIT(DVFS_CTRL0_R_DVFS_SREF_OPT, 5) +DEFINE_BIT(DVFS_CTRL0_HWSET_WLRL, 8) +DEFINE_BIT(DVFS_CTRL0_MR13_SHU_EN, 9) +DEFINE_BIT(DVFS_CTRL0_VRCG_EN, 10) +DEFINE_BIT(DVFS_CTRL0_DVFS_RXFIFOST_SKIP, 13) +DEFINE_BIT(DVFS_CTRL0_DVFS_NOQUEFLUSH_EN, 15) +DEFINE_BIT(DVFS_CTRL0_DVFS_CKE_OPT, 16) +DEFINE_BIT(DVFS_CTRL0_DVFS_CG_OPT, 19) +DEFINE_BIT(DVFS_CTRL0_SCARB_PRI_OPT, 20) +DEFINE_BIT(DVFS_CTRL0_R_DMDVFSMRW_EN, 21) +DEFINE_BIT(DVFS_CTRL0_MRWWOPRA, 22) +DEFINE_BIT(DVFS_CTRL0_DVFS_SYNC_MASK, 27) + +/* DDRPHY_REG_MISC_DUTYSCAN1 */ +DEFINE_BIT(MISC_DUTYSCAN1_REG_SW_RST, 0) +DEFINE_BIT(MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 1) +DEFINE_BIT(MISC_DUTYSCAN1_RX_MIOCK_JIT_EN, 2) +DEFINE_BIT(MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 3) +DEFINE_BIT(MISC_DUTYSCAN1_EYESCAN_DQ_SYNC_EN, 8) +DEFINE_BIT(MISC_DUTYSCAN1_EYESCAN_NEW_DQ_SYNC_EN, 9) +DEFINE_BIT(MISC_DUTYSCAN1_EYESCAN_DQS_SYNC_EN, 10) +DEFINE_BIT(MISC_DUTYSCAN1_EYESCAN_DQS_OPT, 11) +DEFINE_BIT(MISC_DUTYSCAN1_DQSERRCNT_DIS, 14) + +/* DDRPHY_REG_SHU_B0_DQ8 */ +DEFINE_BITFIELD(SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0, 14, 0) +DEFINE_BIT(SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0, 15) +DEFINE_BIT(SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 19) +DEFINE_BIT(SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 20) +DEFINE_BIT(SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 21) +DEFINE_BIT(SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 22) +DEFINE_BIT(SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 23) +DEFINE_BIT(SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 24) +DEFINE_BIT(SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 26) +DEFINE_BIT(SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 27) +DEFINE_BIT(SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 28) +DEFINE_BIT(SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 29) +DEFINE_BIT(SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 30) +DEFINE_BIT(SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 31) + +/* DDRPHY_REG_SHU_B1_DQ8 */ +DEFINE_BITFIELD(SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1, 14, 0) +DEFINE_BIT(SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1, 15) +DEFINE_BIT(SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 19) +DEFINE_BIT(SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 20) +DEFINE_BIT(SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 21) +DEFINE_BIT(SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 22) +DEFINE_BIT(SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 23) +DEFINE_BIT(SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 24) +DEFINE_BIT(SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 26) +DEFINE_BIT(SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 27) +DEFINE_BIT(SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 28) +DEFINE_BIT(SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 29) +DEFINE_BIT(SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 30) +DEFINE_BIT(SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 31) + +/* DRAMC_REG_DDRCOMMON0 */ +DEFINE_BIT(DDRCOMMON0_DISSTOP26M, 0) +DEFINE_BIT(DDRCOMMON0_TRCDEARLY, 3) +DEFINE_BIT(DDRCOMMON0_BK8EN, 8) +DEFINE_BIT(DDRCOMMON0_LPDDR4EN, 19) +DEFINE_BIT(DDRCOMMON0_LPDDR5EN, 20) + +/* DRAMC_REG_RX_SET0 */ +DEFINE_BIT(RX_SET0_RDATRST, 0) +DEFINE_BIT(RX_SET0_PRE_DLE_VLD_OPT, 1) +DEFINE_BITFIELD(RX_SET0_DATLAT_PDLE_TH, 4, 2) +DEFINE_BIT(RX_SET0_SMRR_UPD_OLD, 6) +DEFINE_BIT(RX_SET0_DM4TO1MODE, 31) + +/* DRAMC_REG_REFCTRL0 */ +DEFINE_BITFIELD(REFCTRL0_PBREF_BK_REFA_NUM, 2, 0) +DEFINE_BIT(REFCTRL0_PBREF_BK_REFA_ENA, 3) +DEFINE_BIT(REFCTRL0_DMPGVLD_IG, 8) +DEFINE_BIT(REFCTRL0_KEEP_PBREF_OPT, 9) +DEFINE_BIT(REFCTRL0_KEEP_PBREF, 10) +DEFINE_BITFIELD(REFCTRL0_DISBYREFNUM, 14, 12) +DEFINE_BIT(REFCTRL0_PBREF_DISBYREFNUM, 16) +DEFINE_BIT(REFCTRL0_PBREF_DISBYRATE, 17) +DEFINE_BITFIELD(REFCTRL0_REF_PREGATE_CNT, 27, 24) +DEFINE_BIT(REFCTRL0_REFDIS, 29) + +/* DRAMC_REG_REFCTRL1 */ +DEFINE_BIT(REFCTRL1_PB2AB_OPT, 0) +DEFINE_BIT(REFCTRL1_REFPENDINGINT_OPT1, 3) +DEFINE_BIT(REFCTRL1_REF_QUE_AUTOSAVE_EN, 5) +DEFINE_BIT(REFCTRL1_REFPEND_OPT1, 6) +DEFINE_BIT(REFCTRL1_REFPEND_OPT2, 7) +DEFINE_BIT(REFCTRL1_REFPB2AB_IGZQCS, 8) +DEFINE_BIT(REFCTRL1_REFRATE_MON_CLR, 11) +DEFINE_BIT(REFCTRL1_REF_OVERHEAD_PBR2PB_ENA, 13) +DEFINE_BIT(REFCTRL1_REF_OVERHEAD_RATE_REFAL_ENA, 14) +DEFINE_BIT(REFCTRL1_REF_OVERHEAD_RATE_REFPB_ENA, 15) +DEFINE_BIT(REFCTRL1_REF_OVERHEAD_SLOW_REFAL_ENA, 24) +DEFINE_BIT(REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA, 25) +DEFINE_BIT(REFCTRL1_REF_OVERHEAD_ALL_REFAL_ENA, 26) +DEFINE_BIT(REFCTRL1_REF_OVERHEAD_ALL_REFPB_ENA, 27) + +/* DRAMC_REG_REFCTRL2 */ +DEFINE_BITFIELD(REFCTRL2_MR4INT_TH, 4, 0) +DEFINE_BITFIELD(REFCTRL2_REF_OVERHEAD_RATE, 31, 16) + +/* DRAMC_REG_DRAMCTRL */ +DEFINE_BIT(DRAMCTRL_CTOREQ_HPRI_OPT, 0) +DEFINE_BIT(DRAMCTRL_ADRDECEN, 2) +DEFINE_BIT(DRAMCTRL_ADRBIT3DEC, 3) +DEFINE_BIT(DRAMCTRL_ALL_BLOCK_CTO_ALE_DBG_EN, 8) +DEFINE_BIT(DRAMCTRL_SELFREF_BLOCK_CTO_ALE_DBG_EN, 9) +DEFINE_BIT(DRAMCTRL_DVFS_BLOCK_CTO_ALE_DBG_EN, 10) +DEFINE_BIT(DRAMCTRL_AG0MWR, 12) +DEFINE_BIT(DRAMCTRL_DYNMWREN, 13) +DEFINE_BIT(DRAMCTRL_PREALL_OPTION, 19) +DEFINE_BIT(DRAMCTRL_REQQUE_THD_EN, 26) +DEFINE_BIT(DRAMCTRL_SHORTQ_OPT, 31) + +/* DRAMC_REG_ARBCTL */ +DEFINE_BITFIELD(ARBCTL_MAXPENDCNT, 7, 0) +DEFINE_BIT(ARBCTL_WDATACNTDIS, 9) + +/* DRAMC_REG_DRAM_CLK_CTRL */ +DEFINE_BIT(DRAM_CLK_CTRL_CLK_EN, 0) + +/* DRAMC_REG_RKCFG */ +DEFINE_BIT(RKCFG_MRS2RK, 10) +DEFINE_BIT(RKCFG_CKE2RANK, 12) + +/* DRAMC_REG_CKECTRL */ +DEFINE_BIT(CKECTRL_CKE2RANK_OPT3, 1) +DEFINE_BIT(CKECTRL_CKE1FIXON, 4) +DEFINE_BIT(CKECTRL_CKE1FIXOFF, 5) +DEFINE_BIT(CKECTRL_CKEFIXON, 6) +DEFINE_BIT(CKECTRL_CKEFIXOFF, 7) +DEFINE_BIT(CKECTRL_CKE2RANK_OPT5, 8) +DEFINE_BIT(CKECTRL_CKE2RANK_OPT6, 9) +DEFINE_BIT(CKECTRL_CKE2RANK_OPT7, 10) +DEFINE_BIT(CKECTRL_CKE2RANK_OPT8, 11) +DEFINE_BIT(CKECTRL_CKETIMER_SEL, 13) +DEFINE_BIT(CKECTRL_FASTWAKE_SEL, 14) +DEFINE_BIT(CKECTRL_CKEWAKE_SEL, 15) +DEFINE_BIT(CKECTRL_CKEPBDIS, 22) +DEFINE_BIT(CKECTRL_CKELCKFIX, 23) +DEFINE_BIT(CKECTRL_CKE2RANK_OPT2, 24) +DEFINE_BIT(CKECTRL_CKE2RANK_OPT, 25) +DEFINE_BIT(CKECTRL_RUNTIMEMRRCKEFIX, 27) +DEFINE_BIT(CKECTRL_RUNTIMEMRRMIODIS, 28) +DEFINE_BIT(CKECTRL_CKEON, 31) + +/* DRAMC_REG_SCHEDULER_COM */ +DEFINE_BIT(SCHEDULER_COM_RWOFOEN, 0) +DEFINE_BIT(SCHEDULER_COM_RWHPRICTL, 4) +DEFINE_BIT(SCHEDULER_COM_RWSPLIT, 5) +DEFINE_BIT(SCHEDULER_COM_MWHPRIEN, 6) +DEFINE_BIT(SCHEDULER_COM_DISRDPHASE1, 8) +DEFINE_BIT(SCHEDULER_COM_PBR2PBR_OPT, 9) + +/* DRAMC_REG_PERFCTL0 */ +DEFINE_BIT(PERFCTL0_EBG_EN, 0) +DEFINE_BIT(PERFCTL0_RWHPRIEN, 8) +DEFINE_BIT(PERFCTL0_RWLLATEN, 9) +DEFINE_BIT(PERFCTL0_RWAGEEN, 10) +DEFINE_BIT(PERFCTL0_EMILLATEN, 11) +DEFINE_BIT(PERFCTL0_WFLUSHEN, 14) +DEFINE_BIT(PERFCTL0_REORDER_MODE, 18) +DEFINE_BIT(PERFCTL0_REORDEREN, 19) + +/* DRAMC_REG_HW_MRR_FUN */ +DEFINE_BIT(HW_MRR_FUN_TMRR_ENA, 0) +DEFINE_BIT(HW_MRR_FUN_TRCDMRR_EN, 1) +DEFINE_BIT(HW_MRR_FUN_TRPMRR_EN, 2) +DEFINE_BIT(HW_MRR_FUN_MANTMRR_EN, 3) +DEFINE_BIT(HW_MRR_FUN_TR2MRR_ENA, 4) +DEFINE_BIT(HW_MRR_FUN_R2MRRHPRICTL, 5) +DEFINE_BIT(HW_MRR_FUN_MRR_HW_HIPRI, 11) + +/* DRAMC_REG_MPC_OPTION */ +DEFINE_BIT(MPC_OPTION_MPCRKEN, 17) + +/* DRAMC_REG_MPC_CTRL */ +DEFINE_BIT(MPC_CTRL_MPC_BLOCKALE_OPT, 0) +DEFINE_BIT(MPC_CTRL_MPC_BLOCKALE_OPT1, 1) +DEFINE_BIT(MPC_CTRL_MPC_BLOCKALE_OPT2, 2) +DEFINE_BIT(MPC_CTRL_ZQ_BLOCKALE_OPT, 3) +DEFINE_BIT(MPC_CTRL_REFR_BLOCKEN, 5) +DEFINE_BIT(MPC_CTRL_RTMRW_HPRI_EN, 6) +DEFINE_BIT(MPC_CTRL_RTSWCMD_HPRI_EN, 7) + +/* DRAMC_REG_HMR4 */ +DEFINE_BIT(HMR4_HMR4_TOG_OPT, 1) +DEFINE_BIT(HMR4_SPDR_MR4_OPT, 2) +DEFINE_BIT(HMR4_HMR4_BYTEMODE_EN, 5) +DEFINE_BIT(HMR4_MR4INT_LIMITEN, 6) +DEFINE_BIT(HMR4_REFR_PERIOD_OPT, 7) +DEFINE_BIT(HMR4_REFRDIS, 8) +DEFINE_BIT(HMR4_REFRCNT_OPT, 9) + +/* DRAMC_REG_RK_TEST2_A1 */ +DEFINE_BITFIELD(RK_TEST2_A1_TEST2_BASE, 31, 3) + +/* DRAMC_REG_TEST2_A2 */ +DEFINE_BITFIELD(TEST2_A2_TEST2_OFF, 31, 4) + +/* DRAMC_REG_TEST2_A4 */ +DEFINE_BITFIELD(TEST2_A4_TESTAUDINC, 4, 0) +DEFINE_BIT(TEST2_A4_TESTSSOPAT, 6) +DEFINE_BIT(TEST2_A4_TESTSSOXTALKPAT, 7) +DEFINE_BITFIELD(TEST2_A4_TESTAUDINIT, 12, 8) +DEFINE_BIT(TEST2_A4_TESTAUDBITINV, 14) +DEFINE_BIT(TEST2_A4_TESTAUDMODE, 15) +DEFINE_BIT(TEST2_A4_TESTXTALKPAT, 16) +DEFINE_BIT(TEST2_A4_TEST_REQ_LEN1, 17) +DEFINE_BITFIELD(TEST2_A4_TESTAGENTRK, 25, 24) +DEFINE_BITFIELD(TEST2_A4_TESTAGENTRKSEL, 30, 28) + +/* DRAMC_REG_CMD_DEC_CTRL0 */ +DEFINE_BIT(CMD_DEC_CTRL0_SELPH_CMD_CG_DIS, 4) +DEFINE_BITFIELD(CMD_DEC_CTRL0_RKMODE, 10, 8) + +/* DRAMC_REG_MISCTL0 */ +DEFINE_BIT(MISCTL0_REFP_ARBMASK_PBR2PBR_ENA, 0) +DEFINE_BIT(MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS, 1) +DEFINE_BITFIELD(MISCTL0_PG_WAKEUP_OPT, 15, 14) +DEFINE_BIT(MISCTL0_PAGDIS, 17) +DEFINE_BIT(MISCTL0_REFA_ARB_EN2, 19) +DEFINE_BIT(MISCTL0_PBC_ARB_E1T, 23) +DEFINE_BIT(MISCTL0_PBC_ARB_EN, 24) +DEFINE_BIT(MISCTL0_EMIPREEN, 27) +DEFINE_BIT(MISCTL0_REFP_ARB_EN2, 31) + +/* DRAMC_REG_SCSMCTRL */ +DEFINE_BIT(SCSMCTRL_SC_PG_UPD_OPT, 0) +DEFINE_BIT(SCSMCTRL_SC_PG_MAN_DIS, 1) + +/* DRAMC_REG_SHUCTRL1 */ +DEFINE_BITFIELD(SHUCTRL1_FC_PRDCNT, 7, 0) +DEFINE_BITFIELD(SHUCTRL1_CKFSPE_PRDCNT, 15, 8) +DEFINE_BITFIELD(SHUCTRL1_CKFSPX_PRDCNT, 23, 16) +DEFINE_BITFIELD(SHUCTRL1_VRCGEN_PRDCNT, 31, 24) + +/* DRAMC_REG_DVFS_TIMING_CTRL1 */ +DEFINE_BITFIELD(DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT, 7, 0) +DEFINE_BITFIELD(DVFS_TIMING_CTRL1_DMSHU_CNT, 21, 16) + +/* DRAMC_REG_REFPEND1 */ +DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH0, 3, 0) +DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH1, 7, 4) +DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH2, 11, 8) +DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH3, 15, 12) +DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH4, 19, 16) +DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH5, 23, 20) +DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH6, 27, 24) +DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH7, 31, 28) + +/* DRAMC_REG_CBT_WLEV_CTRL1 */ +DEFINE_BITFIELD(CBT_WLEV_CTRL1_CATRAINLAT, 14, 11) +DEFINE_BITFIELD(CBT_WLEV_CTRL1_CATRAIN_INTV, 22, 15) +DEFINE_BITFIELD(CBT_WLEV_CTRL1_TCMDO1LAT, 30, 23) + +/* DRAMC_REG_TX_SET0 */ +DEFINE_BITFIELD(TX_SET0_TXRANK, 1, 0) +DEFINE_BIT(TX_SET0_TXRANKFIX, 2) +DEFINE_BIT(TX_SET0_OE_DOWNGRADE, 6) +DEFINE_BIT(TX_SET0_WPRE2T, 22) +DEFINE_BIT(TX_SET0_DRSCLR_EN, 24) +DEFINE_BIT(TX_SET0_DRSCLR_RK0_EN, 25) +DEFINE_BIT(TX_SET0_RK_SCINPUT_OPT, 30) + +/* DRAMC_REG_DQSOSCR */ +DEFINE_BIT(DQSOSCR_ARUIDQ_SW, 7) +DEFINE_BIT(DQSOSCR_SREF_TXUI_RELOAD_OPT, 23) +DEFINE_BIT(DQSOSCR_DQSOSCRDIS, 24) +DEFINE_BIT(DQSOSCR_R_DMDQS2DQ_FILT_OPT, 26) +DEFINE_BIT(DQSOSCR_SREF_TXPI_RELOAD_OPT, 27) +DEFINE_BIT(DQSOSCR_DQSOSC_CALEN, 31) + +/* DRAMC_REG_DUMMY_RD */ +DEFINE_BIT(DUMMY_RD_DUMMY_RD_SW, 4) +DEFINE_BIT(DUMMY_RD_DMY_WR_DBG, 6) +DEFINE_BIT(DUMMY_RD_DMY_RD_DBG, 7) +DEFINE_BIT(DUMMY_RD_DRS_SELFWAKE_DMYRD_DIS, 15) +DEFINE_BITFIELD(DUMMY_RD_RANK_NUM, 17, 16) +DEFINE_BIT(DUMMY_RD_DUMMY_RD_EN, 20) +DEFINE_BIT(DUMMY_RD_SREF_DMYRD_EN, 21) +DEFINE_BIT(DUMMY_RD_DQSG_DMYRD_EN, 22) +DEFINE_BIT(DUMMY_RD_DQSG_DMYWR_EN, 23) +DEFINE_BIT(DUMMY_RD_DUMMY_RD_PA_OPT, 24) +DEFINE_BIT(DUMMY_RD_DMYRD_REORDER_DIS, 27) + +/* DRAMC_REG_DUMMY_RD_INTV */ +DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT0, 0) +DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT1, 1) +DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT2, 2) +DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT3, 3) +DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT4, 4) +DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT5, 5) +DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT6, 6) +DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT7, 7) + +/* DRAMC_REG_RK_DQSOSC */ +DEFINE_BIT(RK_DQSOSC_RK0_BYTE_MODE, 29) +DEFINE_BIT(RK_DQSOSC_DQSOSCR_RK0EN, 30) + +/* DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0 */ +DEFINE_BIT(TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT, 31) + +/* DRAMC_REG_SWCMD_CTRL1 */ +DEFINE_BIT(SWCMD_CTRL1_RDDQC_LP_ENB, 2) +DEFINE_BIT(SWCMD_CTRL1_WRFIFO_MODE2, 31) + +/* DRAMC_REG_DBG_CMDDEC_CMDSEL0 */ +DEFINE_BIT(DBG_CMDDEC_CMDSEL0_RANK0_10GBEN, 0) +DEFINE_BIT(DBG_CMDDEC_CMDSEL0_RANK1_10GBEN, 1) + +/* DRAMC_REG_DBIWR_PROTECT */ +DEFINE_BIT(DBIWR_PROTECT_DBIWR_IMP_EN, 0) +DEFINE_BIT(DBIWR_PROTECT_DBIWR_PINMUX_EN, 1) +DEFINE_BITFIELD(DBIWR_PROTECT_DBIWR_OPT_B0, 23, 16) +DEFINE_BITFIELD(DBIWR_PROTECT_DBIWR_OPT_B1, 31, 24) + +/* DDRPHY_REG_MISC_SRAM_DMA0 */ +DEFINE_BIT(MISC_SRAM_DMA0_SW_DMA_FIRE, 0) +DEFINE_BIT(MISC_SRAM_DMA0_SW_MODE, 1) +DEFINE_BIT(MISC_SRAM_DMA0_APB_WR_MODE, 2) +DEFINE_BIT(MISC_SRAM_DMA0_SRAM_WR_MODE, 3) +DEFINE_BITFIELD(MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM, 7, 4) +DEFINE_BITFIELD(MISC_SRAM_DMA0_SW_SHU_LEVEL_APB, 11, 8) +DEFINE_BITFIELD(MISC_SRAM_DMA0_PENABLE_LAT_WR, 15, 14) +DEFINE_BIT(MISC_SRAM_DMA0_KEEP_SRAM_ARB_ENA, 16) +DEFINE_BIT(MISC_SRAM_DMA0_KEEP_APB_ARB_ENA, 17) +DEFINE_BIT(MISC_SRAM_DMA0_DMA_TIMER_EN, 18) +DEFINE_BIT(MISC_SRAM_DMA0_SW_STEP_EN_MODE, 23) +DEFINE_BITFIELD(MISC_SRAM_DMA0_APB_SLV_SEL, 29, 28) + +/* DDRPHY_MD32_REG_SSPM_MCLK_DIV */ +DEFINE_BIT(SSPM_MCLK_DIV_MCLK_DCM_EN, 8) + +/* DDRPHY_REG_CA_CMD7 */ +DEFINE_BIT(CA_CMD7_RG_TX_ARCLKB_PULL_DN, 0) +DEFINE_BIT(CA_CMD7_RG_TX_ARCLKB_PULL_UP, 1) +DEFINE_BIT(CA_CMD7_RG_TX_ARCLK_PULL_DN, 2) +DEFINE_BIT(CA_CMD7_RG_TX_ARCLK_PULL_UP, 3) +DEFINE_BIT(CA_CMD7_RG_TX_ARCS0_PULL_DN, 4) +DEFINE_BIT(CA_CMD7_RG_TX_ARCS0_PULL_UP, 5) +DEFINE_BIT(CA_CMD7_RG_TX_ARCMD_PULL_DN, 6) +DEFINE_BIT(CA_CMD7_RG_TX_ARCMD_PULL_UP, 7) +DEFINE_BIT(CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y, 16) + +/* DDRPHY_REG_B0_DQ7 */ +DEFINE_BIT(B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0, 0) +DEFINE_BIT(B0_DQ7_RG_TX_ARDQS0B_PULL_UP_B0, 1) +DEFINE_BIT(B0_DQ7_RG_TX_ARDQS0_PULL_DN_B0, 2) +DEFINE_BIT(B0_DQ7_RG_TX_ARDQS0_PULL_UP_B0, 3) +DEFINE_BIT(B0_DQ7_RG_TX_ARDQM0_PULL_DN_B0, 4) +DEFINE_BIT(B0_DQ7_RG_TX_ARDQM0_PULL_UP_B0, 5) +DEFINE_BIT(B0_DQ7_RG_TX_ARDQ_PULL_DN_B0, 6) +DEFINE_BIT(B0_DQ7_RG_TX_ARDQ_PULL_UP_B0, 7) +DEFINE_BIT(B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y, 16) + +/* DDRPHY_REG_B1_DQ7 */ +DEFINE_BIT(B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1, 0) +DEFINE_BIT(B1_DQ7_RG_TX_ARDQS0B_PULL_UP_B1, 1) +DEFINE_BIT(B1_DQ7_RG_TX_ARDQS0_PULL_DN_B1, 2) +DEFINE_BIT(B1_DQ7_RG_TX_ARDQS0_PULL_UP_B1, 3) +DEFINE_BIT(B1_DQ7_RG_TX_ARDQM0_PULL_DN_B1, 4) +DEFINE_BIT(B1_DQ7_RG_TX_ARDQM0_PULL_UP_B1, 5) +DEFINE_BIT(B1_DQ7_RG_TX_ARDQ_PULL_DN_B1, 6) +DEFINE_BIT(B1_DQ7_RG_TX_ARDQ_PULL_UP_B1, 7) +DEFINE_BIT(B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y, 16) + +/* DDRPHY_REG_B0_DQ11 */ +DEFINE_BIT(B0_DQ11_DMY_DQ11_B0, 0) + +/* DDRPHY_REG_B1_DQ11 */ +DEFINE_BIT(B1_DQ11_DMY_DQ11_B1, 0) + +/* DDRPHY_REG_MISC_SRAM_DMA1 */ +DEFINE_BITFIELD(MISC_SRAM_DMA1_SPM_RESTORE_STEP_EN, 16, 0) +DEFINE_BIT(MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS, 19) +DEFINE_BITFIELD(MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL, 23, 20) + +/* DDRPHY_REG_MISC_CG_CTRL7 */ +DEFINE_BIT(MISC_CG_CTRL7_CK_BFE_DCM_EN, 11) +DEFINE_BIT(MISC_CG_CTRL7_ARMCTL_CK_OUT_CG_SEL, 16) + +/* DDRPHY_REG_MISC_DVFSCTL2 */ +DEFINE_BIT(MISC_DVFSCTL2_RG_TOPCK_FMEM_CK_BLOCK_DURING_DFS, 3) +DEFINE_BIT(MISC_DVFSCTL2_RG_DLL_SHUFFLE, 4) +DEFINE_BIT(MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE, 5) +DEFINE_BIT(MISC_DVFSCTL2_RG_MRW_AFTER_DFS, 8) +DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_CDC_OPTION, 9) +DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_DLL_CHA, 12) +DEFINE_BIT(MISC_DVFSCTL2_R_CDC_MUX_SEL_OPTION, 13) +DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_PARK_N, 14) +DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_OPTION, 15) +DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL, 29) +DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_SYNC_MODULE_RST_SEL, 31) + +/* DDRPHY_REG_MISC_DVFSCTL3 */ +DEFINE_BIT(MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK, 4) +DEFINE_BIT(MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_MCLK, 5) +DEFINE_BIT(MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_BCLK, 6) +DEFINE_BIT(MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_BCLK, 7) +DEFINE_BITFIELD(MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI, 9, 8) +DEFINE_BITFIELD(MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE, 11, 10) +DEFINE_BITFIELD(MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_MCLK, 17, 12) +DEFINE_BITFIELD(MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK, 27, 22) +DEFINE_BITFIELD(MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK, 31, 28) + +/* DDRPHY_REG_MISC_CLK_CTRL */ +DEFINE_BIT(MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN, 0) +DEFINE_BIT(MISC_CLK_CTRL_DVFS_CLK_MEM_SEL, 1) +DEFINE_BITFIELD(MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL, 10, 9) +DEFINE_BITFIELD(MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE, 13, 12) + +/* DDRPHY_REG_MISC_SHU_OPT */ +DEFINE_BIT(MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN, 0) +DEFINE_BITFIELD(MISC_SHU_OPT_R_DQB0_SHU_PHDET_SPM_EN, 3, 2) +DEFINE_BIT(MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN, 8) +DEFINE_BITFIELD(MISC_SHU_OPT_R_DQB1_SHU_PHDET_SPM_EN, 11, 10) +DEFINE_BIT(MISC_SHU_OPT_R_CA_SHU_PHY_GATING_RESETB_SPM_EN, 16) +DEFINE_BITFIELD(MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN, 19, 18) + +/* DRAMC_REG_SHU_SELPH_CA1 */ +DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_CS, 2, 0) +DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_CKE, 6, 4) +DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_ODT, 10, 8) +DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_RESET, 14, 12) +DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_WE, 18, 16) +DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_CAS, 22, 20) +DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_RAS, 26, 24) +DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_CS1, 30, 28) + +/* DRAMC_REG_SHU_SELPH_CA2 */ +DEFINE_BITFIELD(SHU_SELPH_CA2_TXDLY_BA0, 2, 0) +DEFINE_BITFIELD(SHU_SELPH_CA2_TXDLY_BA1, 6, 4) +DEFINE_BITFIELD(SHU_SELPH_CA2_TXDLY_BA2, 10, 8) +DEFINE_BITFIELD(SHU_SELPH_CA2_TXDLY_CKE1, 26, 24) + +/* DRAMC_REG_SHU_SELPH_CA3 */ +DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA0, 2, 0) +DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA1, 6, 4) +DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA2, 10, 8) +DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA3, 14, 12) +DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA4, 18, 16) +DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA5, 22, 20) +DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA6, 26, 24) +DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA7, 30, 28) + +/* DRAMC_REG_SHU_SELPH_CA4 */ +DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA8, 2, 0) +DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA9, 6, 4) +DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA10, 10, 8) +DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA11, 14, 12) +DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA12, 18, 16) +DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA13, 22, 20) +DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA14, 26, 24) +DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA15, 30, 28) + +/* DRAMC_REG_SHU_SELPH_CA5 */ +DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_CS, 2, 0) +DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_CKE, 6, 4) +DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_ODT, 10, 8) +DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_RESET, 14, 12) +DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_WE, 18, 16) +DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_CAS, 22, 20) +DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_RAS, 26, 24) +DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_CS1, 30, 28) + +/* DRAMC_REG_SHU_SELPH_CA6 */ +DEFINE_BITFIELD(SHU_SELPH_CA6_DLY_BA0, 2, 0) +DEFINE_BITFIELD(SHU_SELPH_CA6_DLY_BA1, 6, 4) +DEFINE_BITFIELD(SHU_SELPH_CA6_DLY_BA2, 10, 8) +DEFINE_BITFIELD(SHU_SELPH_CA6_DLY_CKE1, 26, 24) + +/* DRAMC_REG_SHU_SELPH_CA7 */ +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA0, 2, 0) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA1, 6, 4) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA2, 10, 8) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA3, 14, 12) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA4, 18, 16) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA5, 22, 20) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA6, 26, 24) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA7, 30, 28) + +/* DRAMC_REG_SHU_SELPH_CA8 */ +DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA8, 2, 0) +DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA9, 6, 4) +DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA10, 10, 8) +DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA11, 14, 12) +DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA12, 18, 16) +DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA13, 22, 20) +DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA14, 26, 24) +DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA15, 30, 28) + +/* DDRPHY_REG_SHU_MISC_DRVING2 */ +DEFINE_BITFIELD(SHU_MISC_DRVING2_CMDDRVN1, 4, 0) +DEFINE_BITFIELD(SHU_MISC_DRVING2_CMDDRVP1, 9, 5) +DEFINE_BITFIELD(SHU_MISC_DRVING2_CMDDRVN2, 14, 10) +DEFINE_BITFIELD(SHU_MISC_DRVING2_CMDDRVP2, 19, 15) +DEFINE_BITFIELD(SHU_MISC_DRVING2_DQDRVN1, 24, 20) +DEFINE_BITFIELD(SHU_MISC_DRVING2_DQDRVP1, 29, 25) +DEFINE_BIT(SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN, 31) + +/* DDRPHY_REG_SHU_MISC_IMPCAL1 */ +DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE, 2, 0) +DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPDRVP, 8, 4) +DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPDRVN, 16, 12) +DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE, 19, 17) +DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPCALCNT, 27, 20) +DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPCAL_CALICNT, 31, 28) + +/* DDRPHY_REG_SHU_CA_CMD12 */ +DEFINE_BITFIELD(SHU_CA_CMD12_RG_RIMP_REV, 7, 0) +DEFINE_BITFIELD(SHU_CA_CMD12_RG_RIMP_VREF_SEL_ODTN, 14, 8) +DEFINE_BITFIELD(SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVN, 22, 16) +DEFINE_BIT(SHU_CA_CMD12_RG_RIMP_DRV05, 23) +DEFINE_BITFIELD(SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVP, 30, 24) +DEFINE_BIT(SHU_CA_CMD12_RG_RIMP_UNTERM_EN, 31) + +/* DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1 */ +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVP_UPD_DIS, 0) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVN_UPD_DIS, 1) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_ODTN_UPD_DIS, 2) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVP_UPD_DIS, 4) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVN_UPD_DIS, 5) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_ODTN_UPD_DIS, 6) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS, 8) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS, 9) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS, 10) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVP_UPD_DIS, 12) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVN_UPD_DIS, 13) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_ODTN_UPD_DIS, 14) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVP_UPD_DIS, 16) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVN_UPD_DIS, 17) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_ODTN_UPD_DIS, 18) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVP_UPD_DIS, 20) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVN_UPD_DIS, 21) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_ODTN_UPD_DIS, 22) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVP_UPD_DIS, 28) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVN_UPD_DIS, 29) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_ODTN_UPD_DIS, 30) + +/* DDRPHY_REG_SHU_MISC_DRVING6 */ +DEFINE_BITFIELD(SHU_MISC_DRVING6_IMP_TXDLY_CMD, 5, 0) + +/* DRAMC_REG_SHU_COMMON0 */ +DEFINE_BIT(SHU_COMMON0_FREQDIV4, 0) +DEFINE_BIT(SHU_COMMON0_FDIV2, 1) +DEFINE_BIT(SHU_COMMON0_DM64BITEN, 4) +DEFINE_BIT(SHU_COMMON0_BL4, 10) +DEFINE_BIT(SHU_COMMON0_BC4OTF, 12) + +/* DRAMC_REG_SHU_ACTIMING_CONF */ +DEFINE_BITFIELD(SHU_ACTIMING_CONF_SCINTV, 5, 0) +DEFINE_BITFIELD(SHU_ACTIMING_CONF_REFBW_FR, 25, 16) +DEFINE_BIT(SHU_ACTIMING_CONF_TREFBWIG, 31) + +/* DRAMC_REG_SHU_DCM_CTRL0 */ +DEFINE_BIT(SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 7) +DEFINE_BITFIELD(SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT, 10, 8) +DEFINE_BITFIELD(SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL, 15, 12) +DEFINE_BITFIELD(SHU_DCM_CTRL0_APHYPI_CKCGL_CNT, 19, 16) +DEFINE_BITFIELD(SHU_DCM_CTRL0_APHYPI_CKCGH_CNT, 23, 20) +DEFINE_BIT(SHU_DCM_CTRL0_FASTWAKE2, 29) +DEFINE_BIT(SHU_DCM_CTRL0_FASTWAKE, 31) + +/* DRAMC_REG_SHU_CONF0 */ +DEFINE_BITFIELD(SHU_CONF0_DMPGTIM, 6, 0) +DEFINE_BIT(SHU_CONF0_ADVPREEN, 7) +DEFINE_BIT(SHU_CONF0_PBREFEN, 8) +DEFINE_BITFIELD(SHU_CONF0_REFTHD, 15, 12) + +/* DRAMC_REG_SHU_MATYPE */ +DEFINE_BITFIELD(SHU_MATYPE_MATYPE, 1, 0) + +/* DRAMC_REG_SHU_SCHEDULER */ +DEFINE_BIT(SHU_SCHEDULER_DUALSCHEN, 2) + +/* DRAMC_REG_SHU_TX_SET0 */ +DEFINE_BITFIELD(SHU_TX_SET0_DQOE_CNT, 3, 0) +DEFINE_BIT(SHU_TX_SET0_DQOE_OPT, 4) +DEFINE_BITFIELD(SHU_TX_SET0_TXUPD_SEL, 7, 6) +DEFINE_BITFIELD(SHU_TX_SET0_TXUPD_W2R_SEL, 10, 8) +DEFINE_BIT(SHU_TX_SET0_DBIWR, 12) +DEFINE_BIT(SHU_TX_SET0_WDATRGO, 13) +DEFINE_BIT(SHU_TX_SET0_WPST1P5T, 15) +DEFINE_BITFIELD(SHU_TX_SET0_OE_EXT2UI, 24, 22) +DEFINE_BITFIELD(SHU_TX_SET0_DQS2DQ_FILT_PITHRD, 30, 25) + +/* DDRPHY_REG_MISC_SHU_STBCAL1 */ +DEFINE_BIT(MISC_SHU_STBCAL1_STB_UPDMASK_EN, 11) +DEFINE_BITFIELD(MISC_SHU_STBCAL1_STB_UPDMASKCYC, 15, 12) +DEFINE_BIT(MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL, 16) +DEFINE_BITFIELD(MISC_SHU_STBCAL1_STB_PI_TRACKING_RATIO, 25, 20) + +/* DDRPHY_REG_MISC_SHU_STBCAL */ +DEFINE_BITFIELD(MISC_SHU_STBCAL_DMSTBLAT, 3, 0) +DEFINE_BITFIELD(MISC_SHU_STBCAL_PICGLAT, 6, 4) +DEFINE_BIT(MISC_SHU_STBCAL_DQSG_MODE, 8) +DEFINE_BIT(MISC_SHU_STBCAL_DQSIEN_PICG_MODE, 9) + +/* DDRPHY_REG_MISC_SHU_RANKCTL */ +DEFINE_BITFIELD(MISC_SHU_RANKCTL_RANKINCTL_RXDLY, 3, 0) +DEFINE_BIT(MISC_SHU_RANKCTL_RANK_RXDLY_OPT, 4) +DEFINE_BIT(MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN, 15) +DEFINE_BITFIELD(MISC_SHU_RANKCTL_RANKINCTL_STB, 19, 16) +DEFINE_BITFIELD(MISC_SHU_RANKCTL_RANKINCTL, 23, 20) +DEFINE_BITFIELD(MISC_SHU_RANKCTL_RANKINCTL_ROOT1, 27, 24) +DEFINE_BITFIELD(MISC_SHU_RANKCTL_RANKINCTL_PHY, 31, 28) + +/* DRAMC_REG_SHU_MISC */ +DEFINE_BITFIELD(SHU_MISC_REQQUE_MAXCNT, 3, 0) +DEFINE_BITFIELD(SHU_MISC_DCMDLYREF, 18, 16) +DEFINE_BIT(SHU_MISC_DAREFEN, 30) + +/* DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL */ +DEFINE_BITFIELD(MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT, 2, 0) +DEFINE_BITFIELD(MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT, 6, 4) + +/* DDRPHY_REG_MISC_SHU_RODTENSTB */ +DEFINE_BIT(MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN, 0) +DEFINE_BIT(MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE, 1) +DEFINE_BIT(MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL, 3) +DEFINE_BIT(MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE, 4) +DEFINE_BIT(MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME, 5) +DEFINE_BITFIELD(MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET, 11, 8) +DEFINE_BITFIELD(MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET, 15, 12) +DEFINE_BITFIELD(MISC_SHU_RODTENSTB_RODTENSTB_EXT, 31, 16) + +/* DDRPHY_REG_MISC_SHU_RODTENSTB1 */ +DEFINE_BITFIELD(MISC_SHU_RODTENSTB1_RODTENCGEN_HEAD, 5, 4) +DEFINE_BITFIELD(MISC_SHU_RODTENSTB1_RODTENCGEN_TAIL, 7, 6) + +/* DDRPHY_REG_MISC_SHU_RX_SELPH_MODE */ +DEFINE_BITFIELD(MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE, 1, 0) +DEFINE_BITFIELD(MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE, 5, 4) +DEFINE_BITFIELD(MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE, 7, 6) + +/* DDRPHY_REG_MISC_SHU_RDAT1 */ +DEFINE_BIT(MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT, 0) +DEFINE_BIT(MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT, 1) +DEFINE_BIT(MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT, 2) + +/* DRAMC_REG_SHURK_CKE_CTRL */ +DEFINE_BITFIELD(SHURK_CKE_CTRL_CKE_DBE_CNT, 3, 0) + +/* DDRPHY_REG_MISC_SHU_DQSG_RETRY1 */ +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_SW_RESET, 0) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_SW_EN, 1) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_DDR1866_PLUS, 2) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_ONCE, 3) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_3TIMES, 4) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_1RANK, 5) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_BY_RANK, 6) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_DM4BYTE, 7) +DEFINE_BITFIELD(MISC_SHU_DQSG_RETRY1_RETRY_DQSIENLAT, 11, 8) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_STBENCMP_ALLBYTE, 12) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN, 13) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE, 14) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_CMP_DATA, 15) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_ALE_BLOCK_MASK, 20) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_RDY_SEL_DLE, 21) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_USE_NON_EXTEND, 22) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_USE_CG_GATING, 23) +DEFINE_BITFIELD(MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM, 25, 24) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_RANKSEL_FROM_PHY, 28) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_PA_DISABLE, 29) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_STBEN_RESET_MSK, 30) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_USE_BURST_MODE, 31) + +/* DRAMC_REG_SHU_HWSET_MR13 */ +DEFINE_BITFIELD(SHU_HWSET_MR13_HWSET_MR13_MRSMA, 12, 0) +DEFINE_BITFIELD(SHU_HWSET_MR13_HWSET_MR13_OP, 23, 16) + +/* DRAMC_REG_SHU_HWSET_VRCG */ +DEFINE_BITFIELD(SHU_HWSET_VRCG_HWSET_VRCG_MRSMA, 12, 0) +DEFINE_BITFIELD(SHU_HWSET_VRCG_HWSET_VRCG_OP, 23, 16) +DEFINE_BITFIELD(SHU_HWSET_VRCG_VRCGDIS_PRDCNT, 31, 24) + +/* DRAMC_REG_SHU_HWSET_MR2 */ +DEFINE_BITFIELD(SHU_HWSET_MR2_HWSET_MR2_MRSMA, 12, 0) +DEFINE_BITFIELD(SHU_HWSET_MR2_HWSET_MR2_OP, 23, 16) + +/* DDRPHY_REG_MISC_SHU_DVFSDLL */ +DEFINE_BIT(MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL, 0) +DEFINE_BIT(MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL, 1) +DEFINE_BITFIELD(MISC_SHU_DVFSDLL_R_DLL_IDLE, 10, 4) +DEFINE_BITFIELD(MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE, 22, 16) + +/* DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL */ +DEFINE_BIT(SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN, 0) + +/* DRAMC_REG_SHU_ACTIM1 */ +DEFINE_BITFIELD(SHU_ACTIM1_TRPAB, 3, 0) +DEFINE_BITFIELD(SHU_ACTIM1_TMRWCKEL, 7, 4) +DEFINE_BITFIELD(SHU_ACTIM1_TRP, 11, 8) +DEFINE_BITFIELD(SHU_ACTIM1_TRAS, 21, 16) +DEFINE_BITFIELD(SHU_ACTIM1_TRC, 28, 24) + +/* DRAMC_REG_SHU_ACTIM3 */ +DEFINE_BITFIELD(SHU_ACTIM3_TRFCPB, 7, 0) +DEFINE_BITFIELD(SHU_ACTIM3_MANTMRR, 11, 8) +DEFINE_BITFIELD(SHU_ACTIM3_TR2MRR, 15, 12) +DEFINE_BITFIELD(SHU_ACTIM3_TRFC, 23, 16) +DEFINE_BITFIELD(SHU_ACTIM3_TWTR_L, 29, 24) + +/* DRAMC_REG_SHU_ACTIM2 */ +DEFINE_BITFIELD(SHU_ACTIM2_TXP, 3, 0) +DEFINE_BITFIELD(SHU_ACTIM2_TMRRI, 8, 4) +DEFINE_BITFIELD(SHU_ACTIM2_TRTP, 14, 12) +DEFINE_BITFIELD(SHU_ACTIM2_TR2W, 21, 16) +DEFINE_BITFIELD(SHU_ACTIM2_TFAW, 28, 24) + +/* DRAMC_REG_SHU_ACTIM0 */ +DEFINE_BITFIELD(SHU_ACTIM0_TWTR, 5, 0) +DEFINE_BITFIELD(SHU_ACTIM0_TWR, 15, 8) +DEFINE_BITFIELD(SHU_ACTIM0_TRRD, 18, 16) +DEFINE_BITFIELD(SHU_ACTIM0_TRCD, 27, 24) +DEFINE_BITFIELD(SHU_ACTIM0_CKELCKCNT, 31, 28) + +/* DRAMC_REG_SHU_ACTIM5 */ +DEFINE_BITFIELD(SHU_ACTIM5_TR2PD, 6, 0) +DEFINE_BITFIELD(SHU_ACTIM5_TWTPD, 14, 8) +DEFINE_BITFIELD(SHU_ACTIM5_TPBR2PBR, 23, 16) +DEFINE_BITFIELD(SHU_ACTIM5_TPBR2ACT, 29, 28) + +/* DRAMC_REG_SHU_ACTIM6 */ +DEFINE_BITFIELD(SHU_ACTIM6_TZQLAT2, 4, 0) +DEFINE_BITFIELD(SHU_ACTIM6_TMRD, 11, 8) +DEFINE_BITFIELD(SHU_ACTIM6_TMRW, 15, 12) +DEFINE_BITFIELD(SHU_ACTIM6_TW2MRW, 25, 20) +DEFINE_BITFIELD(SHU_ACTIM6_TR2MRW, 31, 26) + +/* DRAMC_REG_SHU_ACTIM4 */ +DEFINE_BITFIELD(SHU_ACTIM4_TXREFCNT, 9, 0) +DEFINE_BITFIELD(SHU_ACTIM4_TMRR2MRW, 15, 10) +DEFINE_BITFIELD(SHU_ACTIM4_TMRR2W, 21, 16) +DEFINE_BITFIELD(SHU_ACTIM4_TZQCS, 31, 24) + +/* DRAMC_REG_SHU_CKECTRL */ +DEFINE_BIT(SHU_CKECTRL_TPDE_05T, 0) +DEFINE_BIT(SHU_CKECTRL_TPDX_05T, 1) +DEFINE_BITFIELD(SHU_CKECTRL_TPDE, 14, 12) +DEFINE_BITFIELD(SHU_CKECTRL_TPDX, 18, 16) +DEFINE_BITFIELD(SHU_CKECTRL_TCKEPRD, 22, 20) +DEFINE_BITFIELD(SHU_CKECTRL_TCKESRX, 25, 24) + +/* DRAMC_REG_SHU_ACTIM_XRT */ +DEFINE_BITFIELD(SHU_ACTIM_XRT_XRTR2R, 4, 0) +DEFINE_BITFIELD(SHU_ACTIM_XRT_XRTR2W, 13, 8) +DEFINE_BITFIELD(SHU_ACTIM_XRT_XRTW2R, 19, 16) +DEFINE_BITFIELD(SHU_ACTIM_XRT_XRTW2W, 28, 24) + +/* DRAMC_REG_SHU_AC_TIME_05T */ +DEFINE_BIT(SHU_AC_TIME_05T_TRC_05T, 0) +DEFINE_BIT(SHU_AC_TIME_05T_TRFCPB_05T, 1) +DEFINE_BIT(SHU_AC_TIME_05T_TRFC_05T, 2) +DEFINE_BIT(SHU_AC_TIME_05T_TPBR2PBR_05T, 3) +DEFINE_BIT(SHU_AC_TIME_05T_TXP_05T, 4) +DEFINE_BIT(SHU_AC_TIME_05T_TRTP_05T, 5) +DEFINE_BIT(SHU_AC_TIME_05T_TRCD_05T, 6) +DEFINE_BIT(SHU_AC_TIME_05T_TRP_05T, 7) +DEFINE_BIT(SHU_AC_TIME_05T_TRPAB_05T, 8) +DEFINE_BIT(SHU_AC_TIME_05T_TRAS_05T, 9) +DEFINE_BIT(SHU_AC_TIME_05T_TWR_M05T, 10) +DEFINE_BIT(SHU_AC_TIME_05T_TRRD_05T, 12) +DEFINE_BIT(SHU_AC_TIME_05T_TFAW_05T, 13) +DEFINE_BIT(SHU_AC_TIME_05T_TCKEPRD_05T, 14) +DEFINE_BIT(SHU_AC_TIME_05T_TR2PD_05T, 15) +DEFINE_BIT(SHU_AC_TIME_05T_TWTPD_M05T, 16) +DEFINE_BIT(SHU_AC_TIME_05T_TMRRI_05T, 17) +DEFINE_BIT(SHU_AC_TIME_05T_TMRWCKEL_05T, 18) +DEFINE_BIT(SHU_AC_TIME_05T_BGTRRD_05T, 19) +DEFINE_BIT(SHU_AC_TIME_05T_BGTCCD_05T, 20) +DEFINE_BIT(SHU_AC_TIME_05T_BGTWTR_M05T, 21) +DEFINE_BIT(SHU_AC_TIME_05T_TR2W_05T, 22) +DEFINE_BIT(SHU_AC_TIME_05T_TWTR_M05T, 23) +DEFINE_BIT(SHU_AC_TIME_05T_XRTR2W_05T, 24) +DEFINE_BIT(SHU_AC_TIME_05T_TMRD_05T, 25) +DEFINE_BIT(SHU_AC_TIME_05T_TMRW_05T, 26) +DEFINE_BIT(SHU_AC_TIME_05T_TMRR2MRW_05T, 27) +DEFINE_BIT(SHU_AC_TIME_05T_TW2MRW_05T, 28) +DEFINE_BIT(SHU_AC_TIME_05T_TR2MRW_05T, 29) +DEFINE_BIT(SHU_AC_TIME_05T_TPBR2ACT_05T, 30) +DEFINE_BIT(SHU_AC_TIME_05T_XRTW2R_M05T, 31) + +/* DRAMC_REG_SHU_AC_DERATING0 */ +DEFINE_BIT(SHU_AC_DERATING0_ACDERATEEN, 0) +DEFINE_BITFIELD(SHU_AC_DERATING0_TRRD_DERATE, 18, 16) +DEFINE_BITFIELD(SHU_AC_DERATING0_TRCD_DERATE, 27, 24) + +/* DRAMC_REG_SHU_AC_DERATING1 */ +DEFINE_BITFIELD(SHU_AC_DERATING1_TRPAB_DERATE, 3, 0) +DEFINE_BITFIELD(SHU_AC_DERATING1_TRP_DERATE, 11, 8) +DEFINE_BITFIELD(SHU_AC_DERATING1_TRAS_DERATE, 21, 16) +DEFINE_BITFIELD(SHU_AC_DERATING1_TRC_DERATE, 28, 24) + +/* DRAMC_REG_SHU_AC_DERATING_05T */ +DEFINE_BIT(SHU_AC_DERATING_05T_TRC_05T_DERATE, 0) +DEFINE_BIT(SHU_AC_DERATING_05T_TRCD_05T_DERATE, 6) +DEFINE_BIT(SHU_AC_DERATING_05T_TRP_05T_DERATE, 7) +DEFINE_BIT(SHU_AC_DERATING_05T_TRPAB_05T_DERATE, 8) +DEFINE_BIT(SHU_AC_DERATING_05T_TRAS_05T_DERATE, 9) +DEFINE_BIT(SHU_AC_DERATING_05T_TRRD_05T_DERATE, 12) + +/* DRAMC_REG_REFCTRL3 */ +DEFINE_BITFIELD(REFCTRL3_REF_DERATING_EN, 15, 0) + +/* DDRPHY_REG_MISC_SHU_RK_DQSCTL */ +DEFINE_BITFIELD(MISC_SHU_RK_DQSCTL_DQSINCTL, 3, 0) + +/* DDRPHY_REG_MISC_SHU_ODTCTRL */ +DEFINE_BIT(MISC_SHU_ODTCTRL_RODTEN, 0) +DEFINE_BIT(MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 1) +DEFINE_BITFIELD(MISC_SHU_ODTCTRL_RODT_LAT, 7, 4) +DEFINE_BIT(MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN, 15) +DEFINE_BITFIELD(MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT, 25, 24) +DEFINE_BIT(MISC_SHU_ODTCTRL_FIXRODT, 27) +DEFINE_BIT(MISC_SHU_ODTCTRL_RODTEN_OPT, 29) +DEFINE_BIT(MISC_SHU_ODTCTRL_RODTE2, 30) +DEFINE_BIT(MISC_SHU_ODTCTRL_RODTE, 31) + +/* DDRPHY_REG_SHU_MISC_RANK_SEL_STB */ +DEFINE_BIT(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0) +DEFINE_BIT(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 1) +DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 3, 2) +DEFINE_BIT(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 4) +DEFINE_BIT(SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 5) +DEFINE_BIT(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 7) +DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, 11, 8) +DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 19, 16) +DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 23, 20) +DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, 27, 24) +DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, 31, 28) + +/* DDRPHY_REG_MISC_SHU_RDAT */ +DEFINE_BITFIELD(MISC_SHU_RDAT_DATLAT, 4, 0) +DEFINE_BITFIELD(MISC_SHU_RDAT_DATLAT_DSEL, 12, 8) +DEFINE_BITFIELD(MISC_SHU_RDAT_DATLAT_DSEL_PHY, 20, 16) + +/* DRAMC_REG_SHU_TX_RANKCTL */ +DEFINE_BITFIELD(SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, 3, 0) +DEFINE_BITFIELD(SHU_TX_RANKCTL_TXRANKINCTL, 7, 4) +DEFINE_BITFIELD(SHU_TX_RANKCTL_TXRANKINCTL_ROOT, 11, 8) + +/* DRAMC_REG_BYPASS_FSPOP */ +DEFINE_BIT(BYPASS_FSPOP_BPFSP_OPT, 16) + +/* DDRPHY_MD32_REG_LPIF_FSM_CFG_1 */ +DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL, 0) +DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND, 1) +DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR, 2) +DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND, 3) +DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW, 4) +DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW_2ND, 5) +DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL, 6) +DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL_2ND, 7) + +/* DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0 */ +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_PHYPLL_EN, 3, 2) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_DPY_DLL_EN, 5, 4) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_DPY_2ND_DLL_EN, 7, 6) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_DPY_DLL_CK_EN, 9, 8) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_DPY_VREF_EN, 11, 10) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN, 17, 16) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN, 21, 20) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW, 23, 22) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN, 25, 24) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW, 27, 26) + +/* DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1 */ +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_1_DMY_EN_MOD_SEL, 13, 12) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_1_DMYRD_INTV_SEL, 15, 14) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_1_DMYRD_EN, 17, 16) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_1_TX_TRACKING_RETRY_EN, 21, 20) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL, 29, 22) + +/* DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3 */ +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_3_DPY_MCK8X_EN, 1, 0) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_3_DPY_MIDPI_EN, 3, 2) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_3_DPY_PI_RESETB_EN, 5, 4) + +/* DDRPHY_MD32_REG_LPIF_FSM_OUT_CTRL_0 */ +DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_EN, 1) +DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_EN, 2) +DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_2ND_DLL_EN, 3) +DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_CK_EN, 4) +DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_VREF_EN, 5) +DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_SHU_EN, 10) +DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_MODE_SW, 11) + +/* DDRPHY_REG_CLRPLL0 */ +DEFINE_BIT(CLRPLL0_RG_RCLRPLL_EN, 31) + +/* DDRPHY_MD32_REG_LPIF_DFD_DBUG_0 */ +DEFINE_BIT(LPIF_DFD_DBUG_0_LPIF_DFD_DEBUG_ISO_EN, 0) + +/* DDRPHY_REG_MISC_DMA_DEBUG0 */ +DEFINE_BIT(MISC_DMA_DEBUG0_SRAM_DONE, 16) +DEFINE_BIT(MISC_DMA_DEBUG0_APB_DONE, 17) +DEFINE_BIT(MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK, 29) +DEFINE_BIT(MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK, 30) + +/* DDRPHY_MD32_REG_LPIF_STATUS_4 */ +DEFINE_BITFIELD(LPIF_STATUS_4_SHU_EN_ACK, 15, 14) + +/* DRAMC_REG_MRR_STATUS2 */ +DEFINE_BITFIELD(MRR_STATUS2_DVFS_STATE, 31, 24) + +/* DDRPHY_REG_SHU_MISC_RDSEL_TRACK */ +DEFINE_BITFIELD(SHU_MISC_RDSEL_TRACK_DMDATLAT_I, 4, 0) +DEFINE_BIT(SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK, 6) +DEFINE_BIT(SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN, 7) +DEFINE_BITFIELD(SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG, 19, 8) +DEFINE_BITFIELD(SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS, 31, 20) + +/* DDRPHY_REG_MISC_SHU_PHY_RX_CTRL */ +DEFINE_BIT(MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN, 8) +DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET, 11, 9) +DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET, 15, 14) +DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD, 18, 16) +DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL, 22, 20) +DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 26, 24) +DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL, 30, 28) + +/* DDRPHY_REG_MISC_SHU_RANK_SEL_LAT */ +DEFINE_BITFIELD(MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 3, 0) +DEFINE_BITFIELD(MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 7, 4) +DEFINE_BITFIELD(MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 11, 8) + +/* DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY */ +DEFINE_BITFIELD(SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 3, 0) +DEFINE_BITFIELD(SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 7, 4) +DEFINE_BITFIELD(SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 19, 16) +DEFINE_BITFIELD(SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 23, 20) + +/* DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY */ +DEFINE_BITFIELD(SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 6, 0) + +/* DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY */ +DEFINE_BITFIELD(SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 3, 0) +DEFINE_BITFIELD(SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 7, 4) +DEFINE_BITFIELD(SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 19, 16) +DEFINE_BITFIELD(SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 23, 20) + +/* DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY */ +DEFINE_BITFIELD(SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 6, 0) + +/* DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY */ +DEFINE_BITFIELD(SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 2, 0) +DEFINE_BITFIELD(SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 6, 4) +DEFINE_BITFIELD(SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 18, 16) +DEFINE_BITFIELD(SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 22, 20) + +/* DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY */ +DEFINE_BITFIELD(SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 2, 0) +DEFINE_BITFIELD(SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 6, 4) +DEFINE_BITFIELD(SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 18, 16) +DEFINE_BITFIELD(SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 22, 20) + +/* DRAMC_REG_SHU_RX_CG_SET0 */ +DEFINE_BIT(SHU_RX_CG_SET0_DLE_LAST_EXTEND3, 0) +DEFINE_BIT(SHU_RX_CG_SET0_READ_START_EXTEND3, 1) +DEFINE_BIT(SHU_RX_CG_SET0_DLE_LAST_EXTEND2, 2) +DEFINE_BIT(SHU_RX_CG_SET0_READ_START_EXTEND2, 3) +DEFINE_BIT(SHU_RX_CG_SET0_DLE_LAST_EXTEND1, 4) +DEFINE_BIT(SHU_RX_CG_SET0_READ_START_EXTEND1, 5) + +/* DDRPHY_REG_MISC_SHU_RK_DQSCAL */ +DEFINE_BITFIELD(MISC_SHU_RK_DQSCAL_DQSIENLLMT, 6, 0) +DEFINE_BIT(MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 7) +DEFINE_BITFIELD(MISC_SHU_RK_DQSCAL_DQSIENHLMT, 14, 8) +DEFINE_BIT(MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 15) + +/* DDRPHY_REG_SHU_R0_B0_INI_UIPI */ +DEFINE_BITFIELD(SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 6, 0) +DEFINE_BITFIELD(SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 15, 8) + +/* DDRPHY_REG_SHU_R0_B1_INI_UIPI */ +DEFINE_BITFIELD(SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 6, 0) +DEFINE_BITFIELD(SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 15, 8) + +/* DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI */ +DEFINE_BITFIELD(SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 6, 0) +DEFINE_BITFIELD(SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 15, 8) +DEFINE_BITFIELD(SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 31, 24) + +/* DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI */ +DEFINE_BITFIELD(SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 6, 0) +DEFINE_BITFIELD(SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 15, 8) +DEFINE_BITFIELD(SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 31, 24) + +/* DDRPHY_REG_SHU_R0_B0_DQ0 */ +DEFINE_BITFIELD(SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 2, 0) +DEFINE_BITFIELD(SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 6, 4) +DEFINE_BITFIELD(SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 13, 8) +DEFINE_BITFIELD(SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 21, 16) +DEFINE_BITFIELD(SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 29, 24) +DEFINE_BIT(SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 30) +DEFINE_BIT(SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 31) + +/* DDRPHY_REG_SHU_R0_B1_DQ0 */ +DEFINE_BITFIELD(SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 2, 0) +DEFINE_BITFIELD(SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 6, 4) +DEFINE_BITFIELD(SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 13, 8) +DEFINE_BITFIELD(SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 21, 16) +DEFINE_BITFIELD(SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 29, 24) +DEFINE_BIT(SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 30) +DEFINE_BIT(SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 31) + +/* DRAMC_REG_SHU_APHY_TX_PICG_CTRL */ +DEFINE_BITFIELD(SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, 3, 0) +DEFINE_BITFIELD(SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, 6, 4) +DEFINE_BITFIELD(SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, 10, 8) +DEFINE_BITFIELD(SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT, 15, 12) +DEFINE_BIT(SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 31) + +/* DRAMC_REG_SHURK_APHY_TX_PICG_CTRL */ +DEFINE_BITFIELD(SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 2, 0) +DEFINE_BITFIELD(SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 6, 4) + +/* DRAMC_REG_SHU_NEW_XRW2W_CTRL */ +DEFINE_BITFIELD(SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, 18, 16) +DEFINE_BITFIELD(SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, 26, 24) +DEFINE_BIT(SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 31) + +/* DRAMC_REG_SHU_SELPH_DQS0 */ +DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_DQS0, 2, 0) +DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_DQS1, 6, 4) +DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_DQS2, 10, 8) +DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_DQS3, 14, 12) +DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_OEN_DQS0, 18, 16) +DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_OEN_DQS1, 22, 20) +DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_OEN_DQS2, 26, 24) +DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_OEN_DQS3, 30, 28) + +/* DRAMC_REG_SHURK_SELPH_DQ0 */ +DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_DQ0, 2, 0) +DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_DQ1, 6, 4) +DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_DQ2, 10, 8) +DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_DQ3, 14, 12) +DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 18, 16) +DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 22, 20) +DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 26, 24) +DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 30, 28) + +/* DRAMC_REG_SHURK_SELPH_DQ1 */ +DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_DQM0, 2, 0) +DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_DQM1, 6, 4) +DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_DQM2, 10, 8) +DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_DQM3, 14, 12) +DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 18, 16) +DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 22, 20) +DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 26, 24) +DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 30, 28) + +/* DRAMC_REG_SHURK_SELPH_DQ2 */ +DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_DQ0, 3, 0) +DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_DQ1, 7, 4) +DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_DQ2, 11, 8) +DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_DQ3, 15, 12) +DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_OEN_DQ0, 19, 16) +DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_OEN_DQ1, 23, 20) +DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_OEN_DQ2, 27, 24) +DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_OEN_DQ3, 31, 28) + +/* DRAMC_REG_SHURK_SELPH_DQ3 */ +DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_DQM0, 3, 0) +DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_DQM1, 7, 4) +DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_DQM2, 11, 8) +DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_DQM3, 15, 12) +DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_OEN_DQM0, 19, 16) +DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_OEN_DQM1, 23, 20) +DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_OEN_DQM2, 27, 24) +DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_OEN_DQM3, 31, 28) + +/* DRAMC_REG_SHURK_DQS2DQ_CAL1 */ +DEFINE_BITFIELD(SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 10, 0) +DEFINE_BITFIELD(SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 26, 16) + +/* DRAMC_REG_SHURK_DQS2DQ_CAL2 */ +DEFINE_BITFIELD(SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 10, 0) +DEFINE_BITFIELD(SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 26, 16) + +/* DRAMC_REG_SHURK_DQS2DQ_CAL5 */ +DEFINE_BITFIELD(SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 10, 0) +DEFINE_BITFIELD(SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 26, 16) + +/* DRAMC_REG_SHURK_PI */ +DEFINE_BITFIELD(SHURK_PI_RK0_ARPI_DQ_B1, 5, 0) +DEFINE_BITFIELD(SHURK_PI_RK0_ARPI_DQ_B0, 13, 8) +DEFINE_BITFIELD(SHURK_PI_RK0_ARPI_DQM_B1, 21, 16) +DEFINE_BITFIELD(SHURK_PI_RK0_ARPI_DQM_B0, 29, 24) + +/* DDRPHY_REG_SHU_R0_B0_TXDLY0 */ +DEFINE_BITFIELD(SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 7, 0) +DEFINE_BITFIELD(SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 15, 8) +DEFINE_BITFIELD(SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 23, 16) +DEFINE_BITFIELD(SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 31, 24) + +/* DDRPHY_REG_SHU_R0_B0_TXDLY1 */ +DEFINE_BITFIELD(SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 7, 0) +DEFINE_BITFIELD(SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 15, 8) +DEFINE_BITFIELD(SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 23, 16) +DEFINE_BITFIELD(SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 31, 24) + +/* DDRPHY_REG_SHU_R0_B0_TXDLY3 */ +DEFINE_BITFIELD(SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 7, 0) +DEFINE_BITFIELD(SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 23, 16) +DEFINE_BITFIELD(SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 31, 24) + +/* DDRPHY_REG_SHU_R0_B1_TXDLY0 */ +DEFINE_BITFIELD(SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 7, 0) +DEFINE_BITFIELD(SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 15, 8) +DEFINE_BITFIELD(SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 23, 16) +DEFINE_BITFIELD(SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 31, 24) + +/* DDRPHY_REG_SHU_R0_B1_TXDLY1 */ +DEFINE_BITFIELD(SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 7, 0) +DEFINE_BITFIELD(SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 15, 8) +DEFINE_BITFIELD(SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 23, 16) +DEFINE_BITFIELD(SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 31, 24) + +/* DDRPHY_REG_SHU_R0_B1_TXDLY3 */ +DEFINE_BITFIELD(SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 7, 0) +DEFINE_BITFIELD(SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 23, 16) +DEFINE_BITFIELD(SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 31, 24) + +/* DRAMC_REG_SHU_SREF_CTRL */ +DEFINE_BITFIELD(SHU_SREF_CTRL_CKEHCMD, 5, 4) +DEFINE_BITFIELD(SHU_SREF_CTRL_SREF_CK_DLY, 29, 28) + +/* DRAMC_REG_SHU_HMR4_DVFS_CTRL0 */ +DEFINE_BITFIELD(SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 15, 8) +DEFINE_BITFIELD(SHU_HMR4_DVFS_CTRL0_REFRCNT, 27, 16) + +/* DDRPHY_REG_SHU_B0_DQ5 */ +DEFINE_BITFIELD(SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 5, 0) +DEFINE_BIT(SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0, 6) +DEFINE_BITFIELD(SHU_B0_DQ5_RG_ARPI_FB_B0, 13, 8) +DEFINE_BITFIELD(SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0, 18, 16) +DEFINE_BIT(SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0, 19) +DEFINE_BITFIELD(SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0, 23, 20) +DEFINE_BITFIELD(SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0, 31, 29) + +/* DDRPHY_REG_SHU_B1_DQ5 */ +DEFINE_BITFIELD(SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1, 5, 0) +DEFINE_BIT(SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1, 6) +DEFINE_BITFIELD(SHU_B1_DQ5_RG_ARPI_FB_B1, 13, 8) +DEFINE_BITFIELD(SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1, 18, 16) +DEFINE_BIT(SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1, 19) +DEFINE_BITFIELD(SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1, 23, 20) +DEFINE_BITFIELD(SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1, 31, 29) + +/* DDRPHY_REG_SHU_R0_B0_RXDLY0 */ +DEFINE_BITFIELD(SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 7, 0) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 15, 8) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 23, 16) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 31, 24) + +/* DDRPHY_REG_SHU_R0_B0_RXDLY1 */ +DEFINE_BITFIELD(SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 7, 0) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 15, 8) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 23, 16) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 31, 24) + +/* DDRPHY_REG_SHU_R0_B0_RXDLY2 */ +DEFINE_BITFIELD(SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 7, 0) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 15, 8) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 23, 16) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 31, 24) + +/* DDRPHY_REG_SHU_R0_B0_RXDLY3 */ +DEFINE_BITFIELD(SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 7, 0) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 15, 8) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 23, 16) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 31, 24) + +/* DDRPHY_REG_SHU_R0_B0_RXDLY4 */ +DEFINE_BITFIELD(SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 7, 0) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 15, 8) + +/* DDRPHY_REG_SHU_R0_B0_RXDLY5 */ +DEFINE_BITFIELD(SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 8, 0) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 24, 16) + +/* DDRPHY_REG_SHU_R0_B1_RXDLY0 */ +DEFINE_BITFIELD(SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 7, 0) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 15, 8) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 23, 16) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 31, 24) + +/* DDRPHY_REG_SHU_R0_B1_RXDLY1 */ +DEFINE_BITFIELD(SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 7, 0) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 15, 8) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 23, 16) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 31, 24) + +/* DDRPHY_REG_SHU_R0_B1_RXDLY2 */ +DEFINE_BITFIELD(SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 7, 0) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 15, 8) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 23, 16) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 31, 24) + +/* DDRPHY_REG_SHU_R0_B1_RXDLY3 */ +DEFINE_BITFIELD(SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 7, 0) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 15, 8) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 23, 16) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 31, 24) + +/* DDRPHY_REG_SHU_R0_B1_RXDLY4 */ +DEFINE_BITFIELD(SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 7, 0) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 15, 8) + +/* DDRPHY_REG_SHU_R0_B1_RXDLY5 */ +DEFINE_BITFIELD(SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 8, 0) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 24, 16) + +/* DDRPHY_REG_B0_DQ4 */ +DEFINE_BITFIELD(B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0, 6, 0) +DEFINE_BITFIELD(B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0, 14, 8) +DEFINE_BITFIELD(B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0, 21, 16) +DEFINE_BITFIELD(B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0, 29, 24) + +/* DDRPHY_REG_B1_DQ4 */ +DEFINE_BITFIELD(B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1, 6, 0) +DEFINE_BITFIELD(B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1, 14, 8) +DEFINE_BITFIELD(B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1, 21, 16) +DEFINE_BITFIELD(B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1, 29, 24) + +/* DDRPHY_REG_SHU_R0_CA_CMD0 */ +DEFINE_BITFIELD(SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY, 2, 0) +DEFINE_BITFIELD(SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY, 6, 4) +DEFINE_BITFIELD(SHU_R0_CA_CMD0_RG_ARPI_CS, 13, 8) +DEFINE_BITFIELD(SHU_R0_CA_CMD0_RG_ARPI_CMD, 21, 16) +DEFINE_BITFIELD(SHU_R0_CA_CMD0_RG_ARPI_CLK, 29, 24) +DEFINE_BIT(SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA, 30) +DEFINE_BIT(SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA, 31) + +/* DRAMC_REG_SHU_SELPH_DQS1 */ +DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_DQS0, 3, 0) +DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_DQS1, 7, 4) +DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_DQS2, 11, 8) +DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_DQS3, 15, 12) +DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_OEN_DQS0, 19, 16) +DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_OEN_DQS1, 23, 20) +DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_OEN_DQS2, 27, 24) +DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_OEN_DQS3, 31, 28) + +/* DDRPHY_REG_MISC_RX_AUTOK_CFG0 */ +DEFINE_BIT(MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN, 3) + +/* DDRPHY_REG_SHU_CA_CMD8 */ +DEFINE_BIT(SHU_CA_CMD8_R_RMRODTEN_CG_IG_CA, 20) +DEFINE_BIT(SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA, 21) +DEFINE_BIT(SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA, 26) +DEFINE_BIT(SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA, 27) +DEFINE_BIT(SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA, 28) +DEFINE_BIT(SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA, 29) +DEFINE_BIT(SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA, 30) +DEFINE_BIT(SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA, 31) + +/* DRAMC_REG_MRR_BIT_MUX1 */ +DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT0_SEL, 4, 0) +DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT1_SEL, 12, 8) +DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT2_SEL, 20, 16) +DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT3_SEL, 28, 24) + +/* DRAMC_REG_MRR_BIT_MUX2 */ +DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT4_SEL, 4, 0) +DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT5_SEL, 12, 8) +DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT6_SEL, 20, 16) +DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT7_SEL, 28, 24) + +/* DRAMC_REG_MRR_BIT_MUX3 */ +DEFINE_BITFIELD(MRR_BIT_MUX3_MRR_BIT8_SEL, 4, 0) +DEFINE_BITFIELD(MRR_BIT_MUX3_MRR_BIT9_SEL, 12, 8) +DEFINE_BITFIELD(MRR_BIT_MUX3_MRR_BIT10_SEL, 20, 16) +DEFINE_BITFIELD(MRR_BIT_MUX3_MRR_BIT11_SEL, 28, 24) + +/* DRAMC_REG_MRR_BIT_MUX4 */ +DEFINE_BITFIELD(MRR_BIT_MUX4_MRR_BIT12_SEL, 4, 0) +DEFINE_BITFIELD(MRR_BIT_MUX4_MRR_BIT13_SEL, 12, 8) +DEFINE_BITFIELD(MRR_BIT_MUX4_MRR_BIT14_SEL, 20, 16) +DEFINE_BITFIELD(MRR_BIT_MUX4_MRR_BIT15_SEL, 28, 24) + +/* DDRPHY_REG_MISC_DQ_SE_PINMUX_CTRL0 */ +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ0, 3, 0) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ1, 7, 4) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ2, 11, 8) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ3, 15, 12) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ4, 19, 16) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ5, 23, 20) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ6, 27, 24) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ7, 31, 28) + +/* DDRPHY_REG_MISC_DQ_SE_PINMUX_CTRL1 */ +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ8, 3, 0) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ9, 7, 4) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ10, 11, 8) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ11, 15, 12) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ12, 19, 16) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ13, 23, 20) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ14, 27, 24) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ15, 31, 28) + +/* DRAMC_REG_SA_RESERVE */ +DEFINE_BIT(SA_RESERVE_SINGLE_RANK, 0) +DEFINE_BITFIELD(SA_RESERVE_MODE_RK1, 27, 24) +DEFINE_BITFIELD(SA_RESERVE_MODE_RK0, 31, 28) + +/* DRAMC_REG_SWCMD_CTRL0 */ +DEFINE_BITFIELD(SWCMD_CTRL0_MRSOP, 7, 0) +DEFINE_BITFIELD(SWCMD_CTRL0_MRSMA, 20, 8) +DEFINE_BITFIELD(SWCMD_CTRL0_MRSRK, 25, 24) +DEFINE_BIT(SWCMD_CTRL0_SWTRIG_ZQ_RK, 30) + +/* DRAMC_REG_DRAMC_IRQ_EN */ +DEFINE_BIT(DRAMC_IRQ_EN_MR4INT_EN, 0) +DEFINE_BITFIELD(DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV, 31, 18) + +/* DDRPHY_REG_CA_TX_MCK */ +DEFINE_BITFIELD(CA_TX_MCK_R_DMRESETB_DRVP_FRPHY, 25, 21) +DEFINE_BITFIELD(CA_TX_MCK_R_DMRESETB_DRVN_FRPHY, 30, 26) +DEFINE_BIT(CA_TX_MCK_R_DMRESET_FRPHY_OPT, 31) + +/* DDRPHY_REG_MISC_IMPCAL */ +DEFINE_BIT(MISC_IMPCAL_DRVCGWREF, 2) +DEFINE_BIT(MISC_IMPCAL_DQDRVSWUPD, 3) +DEFINE_BIT(MISC_IMPCAL_IMPSRCEXT, 4) +DEFINE_BIT(MISC_IMPCAL_IMPBINARY, 5) +DEFINE_BIT(MISC_IMPCAL_DRV_ECO_OPT, 10) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_CHGDRV_ECO_OPT, 11) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_SM_ECO_OPT, 12) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_ECO_OPT, 13) +DEFINE_BIT(MISC_IMPCAL_DIS_SUS_CH1_DRV, 14) +DEFINE_BIT(MISC_IMPCAL_DIS_SUS_CH0_DRV, 15) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_DRVUPDOPT, 17) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV, 19) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_HWSAVE_EN, 20) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_CALI_ENN, 21) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_CALI_ENP, 22) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_CALI_EN, 23) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_IMPPDN, 24) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_IMPPDP, 25) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_NEW_OLD_SL, 26) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_SWVALUE_EN, 29) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_EN, 30) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_HW, 31) + +/* DDRPHY_REG_SHU_B0_DLL2 */ +DEFINE_BITFIELD(SHU_B0_DLL2_RG_ARDQ_REV_B0, 31, 0) + +/* DDRPHY_REG_SHU_B1_DLL2 */ +DEFINE_BITFIELD(SHU_B1_DLL2_RG_ARDQ_REV_B1, 31, 0) + +/* DDRPHY_REG_SHU_CA_DLL2 */ +DEFINE_BITFIELD(SHU_CA_DLL2_RG_ARCMD_REV, 31, 0) + +/* DRAMC_REG_DRAMC_DBG_SEL1 */ +DEFINE_BITFIELD(DRAMC_DBG_SEL1_DEBUG_SEL_0, 15, 0) + +/* DRAMC_REG_SWCMD_CTRL2 */ +DEFINE_BITFIELD(SWCMD_CTRL2_RTSWCMD_AGE, 9, 0) + +/* DRAMC_REG_RTMRW_CTRL0 */ +DEFINE_BITFIELD(RTMRW_CTRL0_RTMRW_AGE, 24, 15) + +/* DRAMC_REG_REF_BOUNCE1 */ +DEFINE_BITFIELD(REF_BOUNCE1_REFRATE_DEBOUNCE_COUNT, 7, 0) +DEFINE_BITFIELD(REF_BOUNCE1_REFRATE_DEBOUNCE_TH, 12, 8) +DEFINE_BIT(REF_BOUNCE1_REFRATE_DEBOUNCE_OPT, 13) +DEFINE_BITFIELD(REF_BOUNCE1_REFRATE_DEBOUNCE_DIS, 31, 16) + +/* DRAMC_REG_REFPEND2 */ +DEFINE_BITFIELD(REFPEND2_MPENDREFCNT_TH8, 3, 0) + +/* DRAMC_REG_RTSWCMD_CNT */ +DEFINE_BITFIELD(RTSWCMD_CNT_RTSWCMD_CNT, 31, 0) + +/* DDRPHY_REG_B0_DLL_ARPI4 */ +DEFINE_BIT(B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B0, 8) +DEFINE_BIT(B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B0, 9) + +/* DDRPHY_REG_B1_DLL_ARPI4 */ +DEFINE_BIT(B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B1, 8) +DEFINE_BIT(B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B1, 9) + +/* DDRPHY_REG_CA_DLL_ARPI4 */ +DEFINE_BIT(CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CA_CA, 8) +DEFINE_BIT(CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CLK_CA, 9) + +/* DDRPHY_REG_MISC_DDR_RESERVE */ +DEFINE_BITFIELD(MISC_DDR_RESERVE_WDT_CONF_ISO_CNT, 7, 0) +DEFINE_BIT(MISC_DDR_RESERVE_WDT_SM_CLR, 24) +DEFINE_BIT(MISC_DDR_RESERVE_WDT_LITE_EN, 25) + +/* DDRPHY_REG_MISC_CTRL6 */ +DEFINE_BIT(MISC_CTRL6_RG_PHDET_EN_SHU_OPT, 0) +DEFINE_BIT(MISC_CTRL6_RG_ADA_MCK8X_EN_SHU_OPT, 1) + +/* DRAMC_REG_REF_BOUNCE2 */ +DEFINE_BITFIELD(REF_BOUNCE2_PRE_MR4INT_TH, 4, 0) + +/* DRAMC_REG_SHU_REF0 */ +DEFINE_BITFIELD(SHU_REF0_MPENDREF_CNT, 2, 0) + +/* DRAMC_REG_ZQ_SET1 */ +DEFINE_BIT(ZQ_SET1_ZQCALDISB, 30) + +/* DRAMC_REG_TX_RETRY_SET0 */ +DEFINE_BIT(TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK, 0) +DEFINE_BIT(TX_RETRY_SET0_XSR_TX_RETRY_EN, 2) +DEFINE_BIT(TX_RETRY_SET0_XSR_TX_RETRY_SW_EN, 4) + +/* DRAMC_REG_SPCMDRESP */ +DEFINE_BIT(SPCMDRESP_MRR_RESPONSE, 1) +DEFINE_BIT(SPCMDRESP_RDDQC_RESPONSE, 7) +DEFINE_BIT(SPCMDRESP_TX_RETRY_DONE_RESPONSE, 15) + +/* DDRPHY_REG_SHU_B0_VREF */ +DEFINE_BIT(SHU_B0_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B0, 16) +DEFINE_BIT(SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0, 22) + +/* DDRPHY_REG_SHU_B1_VREF */ +DEFINE_BIT(SHU_B1_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B1, 16) +DEFINE_BIT(SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1, 22) + +/* DDRPHY_REG_SHU_B0_PHY_VREF_SEL */ +DEFINE_BITFIELD(RG_RX_ARDQ_VREF_SEL_LB_B0, 6, 0) +DEFINE_BITFIELD(RG_RX_ARDQ_VREF_SEL_UB_B0, 14, 8) + +/* DDRPHY_REG_SHU_B1_PHY_VREF_SEL */ +DEFINE_BITFIELD(RG_RX_ARDQ_VREF_SEL_LB_B1, 6, 0) +DEFINE_BITFIELD(RG_RX_ARDQ_VREF_SEL_UB_B1, 14, 8) + +/* DDRPHY_REG_SHU_MISC_DRVING1 */ +DEFINE_BITFIELD(SHU_MISC_DRVING1_DQDRVN2, 4, 0) +DEFINE_BITFIELD(SHU_MISC_DRVING1_DQDRVP2, 9, 5) +DEFINE_BITFIELD(SHU_MISC_DRVING1_DQSDRVN1, 14, 10) +DEFINE_BITFIELD(SHU_MISC_DRVING1_DQSDRVP1, 19, 15) +DEFINE_BITFIELD(SHU_MISC_DRVING1_DQSDRVN2, 24, 20) +DEFINE_BITFIELD(SHU_MISC_DRVING1_DQSDRVP2, 29, 25) +DEFINE_BIT(SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK, 30) +DEFINE_BIT(SHU_MISC_DRVING1_DIS_IMPCAL_HW, 31) + +/* DRAMC_REG_SHU_ZQ_SET0 */ +DEFINE_BITFIELD(SHU_ZQ_SET0_ZQCSCNT, 15, 0) +DEFINE_BITFIELD(SHU_ZQ_SET0_TZQLAT, 31, 27) + +/* DRAMC_REG_DCM_SUB_CTRL */ +DEFINE_BIT(DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING, 1) +DEFINE_BIT(DCM_SUB_CTRL_SUBCLK_CTRL_TX_AUTOK, 12) + +/* DDRPHY_REG_B0_PHY3 */ +DEFINE_BIT(B0_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B0, 28) + +/* DDRPHY_REG_B1_PHY3 */ +DEFINE_BIT(B1_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B1, 28) + +/* DRAMC_REG_CBT_WLEV_CTRL5 */ +DEFINE_BITFIELD(CBT_WLEV_CTRL5_NEW_CBT_PAT_INTV, 11, 4) + +/* DRAMC_REG_CBT_WLEV_CTRL0 */ +DEFINE_BIT(CBT_WLEV_CTRL0_BYTEMODECBTEN, 2) +DEFINE_BIT(CBT_WLEV_CTRL0_WRITE_LEVEL_EN, 3) +DEFINE_BIT(CBT_WLEV_CTRL0_DQSOEAOEN, 4) +DEFINE_BIT(CBT_WLEV_CTRL0_CBT_WLEV_DQS_TRIG, 7) +DEFINE_BITFIELD(CBT_WLEV_CTRL0_CBT_WLEV_DQS_SEL, 11, 8) +DEFINE_BITFIELD(CBT_WLEV_CTRL0_WLEV_DQSPAT_LAT, 19, 12) +DEFINE_BITFIELD(CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN, 29, 26) +DEFINE_BIT(CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE, 30) + +/* DRAMC_REG_SHU_LP5_CMD */ +DEFINE_BIT(SHU_LP5_CMD_LP5_CMD1TO2EN, 0) + +/* DDRPHY_REG_SHU_R0_CA_TXDLY0 */ +DEFINE_BITFIELD(SHU_R0_CA_TXDLY0_TX_ARCA0_DLY, 7, 0) +DEFINE_BITFIELD(SHU_R0_CA_TXDLY0_TX_ARCA1_DLY, 15, 8) +DEFINE_BITFIELD(SHU_R0_CA_TXDLY0_TX_ARCA2_DLY, 23, 16) +DEFINE_BITFIELD(SHU_R0_CA_TXDLY0_TX_ARCA3_DLY, 31, 24) + +/* DDRPHY_REG_SHU_R0_CA_TXDLY1 */ +DEFINE_BITFIELD(SHU_R0_CA_TXDLY1_TX_ARCA4_DLY, 7, 0) +DEFINE_BITFIELD(SHU_R0_CA_TXDLY1_TX_ARCA5_DLY, 15, 8) +DEFINE_BITFIELD(SHU_R0_CA_TXDLY1_TX_ARCA6_DLY, 23, 16) +DEFINE_BITFIELD(SHU_R0_CA_TXDLY1_TX_ARCA7_DLY, 31, 24) + +/* DRAMC_REG_CBT_WLEV_CTRL4 */ +DEFINE_BITFIELD(CBT_WLEV_CTRL4_CBT_TXDQ_B0, 7, 0) +DEFINE_BITFIELD(CBT_WLEV_CTRL4_CBT_TXDQ_B1, 15, 8) + +/* DRAMC_REG_CBT_WLEV_CTRL3 */ +DEFINE_BITFIELD(CBT_WLEV_CTRL3_DQSBX_G, 17, 14) + +/* DRAMC_REG_SWCMD_EN */ +DEFINE_BIT(SWCMD_EN_RDDQCEN, 5) +DEFINE_BIT(SWCMD_EN_MRWEN, 11) +DEFINE_BIT(SWCMD_EN_MRREN, 12) +DEFINE_BIT(SWCMD_EN_ZQCEN_SWTRIG, 16) +DEFINE_BIT(SWCMD_EN_ZQLATEN_SWTRIG, 17) +DEFINE_BIT(SWCMD_EN_WCK2DQI_START_SWTRIG, 18) + +/* DRAMC_REG_SPCMDRESP3 */ +DEFINE_BIT(SPCMDRESP3_ZQC_SWTRIG_RESPONSE, 1) +DEFINE_BIT(SPCMDRESP3_ZQLAT_SWTRIG_RESPONSE, 2) +DEFINE_BIT(SPCMDRESP3_WCK2DQI_START_SWTRIG_RESPONSE, 3) + +/* DDRPHY_REG_SHU_B0_RANK_SELPH_UI_DLY */ +DEFINE_BITFIELD(SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B0, 18, 16) +DEFINE_BITFIELD(SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B0, 22, 20) + +/* DDRPHY_REG_SHU_B1_RANK_SELPH_UI_DLY */ +DEFINE_BITFIELD(SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B1, 18, 16) +DEFINE_BITFIELD(SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B1, 22, 20) + +/* DRAMC_REG_RDDQCGOLDEN */ +DEFINE_BITFIELD(RDDQCGOLDEN_MR20_GOLDEN, 7, 0) +DEFINE_BITFIELD(RDDQCGOLDEN_MR15_GOLDEN, 15, 8) +DEFINE_BITFIELD(RDDQCGOLDEN_MR40_GOLDEN, 23, 16) +DEFINE_BITFIELD(RDDQCGOLDEN_MR32_GOLDEN, 31, 24) + +/* DDRPHY_REG_MISC_JMETER */ +DEFINE_BIT(MISC_JMETER_JMTR_EN, 0) + +/* DDRPHY_REG_MISC_DUTY_TOGGLE_CNT */ +DEFINE_BITFIELD(MISC_DUTY_TOGGLE_CNT_TOGGLE_CNT, 31, 0) + +/* DDRPHY_REG_MISC_DUTY_DQS0_ERR_CNT */ +DEFINE_BITFIELD(MISC_DUTY_DQS0_ERR_CNT_DQS0_ERR_CNT, 31, 0) + +/* DDRPHY_REG_DVFS_STATUS */ +DEFINE_BITFIELD(DVFS_STATUS_OTHER_SHU_GP, 17, 16) + +/* DDRPHY_REG_SHU_MISC_DRVING3 */ +DEFINE_BITFIELD(SHU_MISC_DRVING3_DQODTN2, 4, 0) +DEFINE_BITFIELD(SHU_MISC_DRVING3_DQODTP2, 9, 5) +DEFINE_BITFIELD(SHU_MISC_DRVING3_DQSODTN, 14, 10) +DEFINE_BITFIELD(SHU_MISC_DRVING3_DQSODTP, 19, 15) +DEFINE_BITFIELD(SHU_MISC_DRVING3_DQSODTN2, 24, 20) +DEFINE_BITFIELD(SHU_MISC_DRVING3_DQSODTP2, 29, 25) + +/* DDRPHY_REG_SHU_MISC_DRVING4 */ +DEFINE_BITFIELD(SHU_MISC_DRVING4_CMDODTN1, 4, 0) +DEFINE_BITFIELD(SHU_MISC_DRVING4_CMDODTP1, 9, 5) +DEFINE_BITFIELD(SHU_MISC_DRVING4_CMDODTN2, 14, 10) +DEFINE_BITFIELD(SHU_MISC_DRVING4_CMDODTP2, 19, 15) +DEFINE_BITFIELD(SHU_MISC_DRVING4_DQODTN1, 24, 20) +DEFINE_BITFIELD(SHU_MISC_DRVING4_DQODTP1, 29, 25) + +/* DDRPHY_REG_MISC_SHU_DRVING8 */ +DEFINE_BITFIELD(MISC_SHU_DRVING8_CS_DRVN, 4, 0) +DEFINE_BITFIELD(MISC_SHU_DRVING8_CS_DRVP, 12, 8) + +/* DDRPHY_REG_MISC_PHY_RGS_CMD */ +DEFINE_BIT(MISC_PHY_RGS_CMD_RGS_RIMPCALOUT, 24) + +/* DDRPHY_REG_SHU_CA_TXDUTY */ +DEFINE_BITFIELD(SHU_CA_TXDUTY_DA_TX_ARCLK_DUTY_DLY, 13, 8) + +/* DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY */ +DEFINE_BITFIELD(SHU_B0_TXDUTY_DA_TX_ARDQ_DUTY_DLY_B0, 5, 0) +DEFINE_BITFIELD(SHU_B0_TXDUTY_DA_TX_ARDQS_DUTY_DLY_B0, 13, 8) +DEFINE_BITFIELD(SHU_B0_TXDUTY_DA_TX_ARDQM_DUTY_DLY_B0, 21, 16) +DEFINE_BITFIELD(SHU_B0_TXDUTY_DA_TX_ARWCK_DUTY_DLY_B0, 29, 24) + +/* DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3 */ +DEFINE_BITFIELD(TEST2_A3_TESTCNT, 3, 0) + +/* DRAMC_REG_SHU_DQSOSC_SET0 */ +DEFINE_BIT(SHU_DQSOSC_SET0_DQSOSCENDIS, 0) +DEFINE_BITFIELD(SHU_DQSOSC_SET0_DQSOSC_PRDCNT, 13, 4) +DEFINE_BITFIELD(SHU_DQSOSC_SET0_DQSOSCENCNT, 31, 16) + +/* DRAMC_REG_SHURK_DQSOSC */ +DEFINE_BITFIELD(SHURK_DQSOSC_DQSOSC_BASE_RK0, 15, 0) +DEFINE_BITFIELD(SHURK_DQSOSC_DQSOSC_BASE_RK0_B1, 31, 16) + +/* DRAMC_REG_SHU_DQSOSCR */ +DEFINE_BITFIELD(SHU_DQSOSCR_DQSOSCRCNT, 7, 0) + +/* DRAMC_REG_SHURK_DQSOSC_THRD */ +DEFINE_BITFIELD(SHURK_DQSOSC_THRD_DQSOSCTHRD_INC, 11, 0) +DEFINE_BITFIELD(SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC, 27, 16) + +/* DRAMC_REG_SHU_FREQ_RATIO_SET0 */ +DEFINE_BITFIELD(SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3, 7, 0) +DEFINE_BITFIELD(SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2, 15, 8) +DEFINE_BITFIELD(SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1, 23, 16) +DEFINE_BITFIELD(SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0, 31, 24) + +/* DRAMC_REG_SHU_FREQ_RATIO_SET1 */ +DEFINE_BITFIELD(SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO7, 7, 0) +DEFINE_BITFIELD(SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO6, 15, 8) +DEFINE_BITFIELD(SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO5, 23, 16) +DEFINE_BITFIELD(SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO4, 31, 24) + +/* DRAMC_REG_SHU_FREQ_RATIO_SET2 */ +DEFINE_BITFIELD(SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO9, 23, 16) +DEFINE_BITFIELD(SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO8, 31, 24) + +/* DDRPHY_REG_SHU_MISC_PRE_TDQSCK */ +DEFINE_BIT(SHU_MISC_PRE_TDQSCK_PRECAL_DISABLE, 0) + +/* DDRPHY_REG_MISC_PRE_TDQSCK1 */ +DEFINE_BIT(MISC_PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL, 22) +DEFINE_BIT(MISC_PRE_TDQSCK1_TDQSCK_REG_DVFS, 25) +DEFINE_BIT(MISC_PRE_TDQSCK1_TDQSCK_PRECAL_HW, 26) + +/* DRAMC_REG_MISC_STATUSA */ +DEFINE_BIT(MISC_STATUSA_REQQ_EMPTY, 2) +DEFINE_BITFIELD(MISC_STATUSA_REFRESH_QUEUE_CNT, 27, 24) + +/* DRAMC_REG_TEST2_A0 */ +DEFINE_BITFIELD(TEST2_A0_TEST2_PAT1, 7, 0) +DEFINE_BITFIELD(TEST2_A0_TEST2_PAT0, 15, 8) +DEFINE_BIT(TEST2_A0_LOOP_NV_END, 16) +DEFINE_BIT(TEST2_A0_ERR_BREAK_EN, 17) +DEFINE_BIT(TEST2_A0_TA2_LOOP_EN, 18) +DEFINE_BITFIELD(TEST2_A0_LOOP_CNT_INDEX, 23, 20) + +/* DRAMC_REG_TESTRPT */ +DEFINE_BITFIELD(TESTRPT_TESTSTAT, 22, 20) + +/* DRAMC_REG_MRR_STATUS */ +DEFINE_BITFIELD(MRR_STATUS_MRR_SW_REG, 31, 16) + +/* DRAMC_REG_SPCMDRESP */ +DEFINE_BIT(SPCMDRESP_MRW_RESPONSE, 0) + +/* DRAMC_REG_MISC_STATUSA */ +DEFINE_BITFIELD(MISC_STATUSA_REFRESH_RATE, 12, 8) + +/* DDRPHY_REG_SHU_CA_CMD0 */ +DEFINE_BIT(SHU_CA_CMD0_R_LP4Y_WDN_MODE_CLK, 31) + +/* DDRPHY_REG_SHU_B0_DQ0 */ +DEFINE_BIT(SHU_B0_DQ0_R_LP4Y_WDN_MODE_DQS0, 31) + +/* DDRPHY_REG_SHU_B1_DQ0 */ +DEFINE_BIT(SHU_B1_DQ0_R_LP4Y_WDN_MODE_DQS1, 31) + +#endif //__SOC_MEDIATEK_MT8192_DRAMC_MACRO_DEF_H__ \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/44699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc64fb6c60d57184c4a2f9febe765b5cb69b39ae Gerrit-Change-Number: 44699 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

10 37

Change in coreboot[master]: soc/mediatek/mt8192: Add DDR mode register init
by CK HU (Code Review) 31 Dec '20

31 Dec '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44711 to review the following change. Change subject: soc/mediatek/mt8192: Add DDR mode register init ...................................................................... soc/mediatek/mt8192: Add DDR mode register init Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: If200f4dcef0b1d0b7e901d4ae6e667b1f75156f5 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_dvfs.c M src/soc/mediatek/mt8192/dramc_pi_basic_api.c 3 files changed, 414 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/44711/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index bf819ec..f42ae75 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -16,7 +16,7 @@ verstage-y += ../common/uart.c romstage-y += ../common/cbmem.c -romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c dramc_utility.c +romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c dramc_utility.c dramc_dvfs.c romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8192/dramc_dvfs.c b/src/soc/mediatek/mt8192/dramc_dvfs.c new file mode 100644 index 0000000..ce24829 --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_dvfs.c @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> + +void enable_dfs_hw_mode_clk(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl3, + MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI, 0x3, + MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_clk_ctrl, + MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN, 0x1, + MISC_CLK_CTRL_DVFS_CLK_MEM_SEL, 0x1, + MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE, 0x0, + MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL, 0x1); + } +} + +void dramc_dfs_direct_jump_rg_mode(const struct ddr_cali *cali, u8 shu_level) +{ + u8 shu_ack = 0; + u8 tmp_level = 0; + u8 pll_mode = *(cali->pll_mode); + u32 *shu_ack_reg = &mtk_dpm->status_4; + + if (pll_mode == PHYPLL_MODE) { + dramc_dbg("Disable CLRPLL\n"); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.clrpll0, CLRPLL0_RG_RCLRPLL_EN, 0); + } else { + dramc_dbg("Disable PHYPLL\n"); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 0); + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + shu_ack |= (0x1 << chn); + + if (pll_mode == PHYPLL_MODE) { + dramc_dbg("Jump to CLRPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, shu_ack); + } else { + dramc_dbg("Jump to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, shu_ack); + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN, 1); + + if (shu_level == DRAM_DFS_SHU0) + tmp_level = shu_level; + else + tmp_level = 1; + + if (pll_mode == PHYPLL_MODE) { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL, tmp_level); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN, 1); + } + dramc_dbg("Enable CLRPLL\n"); + } else { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL, tmp_level); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN, 1); + } + dramc_dbg("Enable PHYPLL\n"); + } + udelay(1); + + if (pll_mode == PHYPLL_MODE) + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.clrpll0, CLRPLL0_RG_RCLRPLL_EN, 1); + else + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 1); + + udelay(20); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SHU_EN, 1); + while ((READ32_BITFIELD(shu_ack_reg, LPIF_STATUS_4_SHU_EN_ACK) & shu_ack) != shu_ack) + dramc_dbg("wait shu_en ack.\n"); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SHU_EN, 0); + + if (pll_mode == PHYPLL_MODE) + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 0); + else + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.clrpll0, CLRPLL0_RG_RCLRPLL_EN, 0); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN, 0); + + dramc_dbg("Shuffle flow complete\n"); + + pll_mode = !pll_mode; + *(cali->pll_mode) = pll_mode; +} + diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 091b21b..adabb80 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -110,6 +110,75 @@ set_dqO1_pinmux_mapping(cali); } +static void dramc_init_default_mr_value(const struct ddr_cali *cali) +{ + struct mr_values *mr_value = cali->mr_value; + dram_freq_grp freq_group = cali->freq_group; + u8 highest_freq = get_highest_freq_group(); + + mr_value->mr01[FSP_0] = 0x26; + mr_value->mr01[FSP_1] = 0x56; + mr_value->mr02[FSP_0] = 0x1a; + mr_value->mr02[FSP_1] = 0x1a; + + mr_value->mr03[FSP_0] = 0x30 | 0x4; + mr_value->mr03[FSP_1] = 0x30 | 0x4; + mr_value->mr03[FSP_1] |= 0x2; + + mr_value->mr04[RANK_0] = 0x3; + mr_value->mr04[RANK_1] = 0x3; + + mr_value->mr21[FSP_0] = 0x0; + mr_value->mr21[FSP_1] = 0x0; + mr_value->mr51[FSP_0] = 0x0; + mr_value->mr51[FSP_1] = 0x0; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + for (u8 rk = 0; rk < RANK_MAX; rk++) { + mr_value->mr23[chn][rk] = 0x3f; + for (u8 fsp = 0; fsp < FSP_MAX; fsp++) { + mr_value->mr14[chn][rk][fsp] = (fsp == FSP_0) ? 0x5d : 0x18; + mr_value->mr12[chn][rk][fsp] = (fsp == FSP_0) ? 0x5d : 0x1b; + } + } + + mr_value->mr01[FSP_0] &= 0x8F; + mr_value->mr01[FSP_1] &= 0x8F; + + if (highest_freq == DDRFREQ_2133) { + mr_value->mr01[FSP_0] |= (0x7 << 4); + mr_value->mr01[FSP_1] |= (0x7 << 4); + } else { + mr_value->mr01[FSP_0] |= (0x5 << 4); + mr_value->mr01[FSP_1] |= (0x5 << 4); + } + + switch (freq_group) { + case DDRFREQ_400: + mr_value->mr02[FSP_0] = 0x12; + break; + case DDRFREQ_600: + case DDRFREQ_800: + mr_value->mr02[FSP_0] = 0x12; + break; + case DDRFREQ_933: + mr_value->mr02[FSP_0] = 0x1b; + break; + case DDRFREQ_1200: + mr_value->mr02[FSP_0] = 0x24; + break; + case DDRFREQ_1600: + mr_value->mr02[FSP_1] = 0x2d; + break; + case DDRFREQ_2133: + mr_value->mr02[FSP_1] = 0x3f; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } +} + static void sv_algorithm_assistance_lp4_800(void) { SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rdsel_track, @@ -3702,6 +3771,235 @@ } } +static void dramc_power_on_sequence(const struct ddr_cali *cali) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, + MISC_CTRL1_R_DMDA_RRESETB_I, 0x0); + cke_fix_onoff(cali, chn, RANK_MAX, CKE_FIXOFF); + udelay(200); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, + MISC_CTRL1_R_DMDA_RRESETB_I, 0x1); + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, + DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 1); + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, + DRAMC_PD_CTRL_TCKFIXON, 1); + mdelay(2); + cke_fix_onoff(cali, chn, RANK_MAX, CKE_FIXON); + udelay(2); + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, + DRAMC_PD_CTRL_TCKFIXON, 0); + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, + DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 0); + } +} + +static void dramc_zq_calibration(const struct ddr_cali *cali, u8 chn, u8 rank) +{ + const u32 timeout = 100; + + struct reg_bak regs_bak[] = { + {&ch[chn].ao.swcmd_en}, + {&ch[chn].ao.swcmd_ctrl0}, + {&ch[chn].ao.dramc_pd_ctrl}, + {&ch[chn].ao.ckectrl}, + }; + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 1); + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, DRAMC_PD_CTRL_TCKFIXON, 1); + udelay(1); + cke_fix_onoff(cali, chn, rank, CKE_FIXON); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_SWTRIG_ZQ_RK, rank); + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_ZQCEN_SWTRIG, 1); + if (!wait_us(timeout, READ32_BITFIELD(&ch[chn].nao.spcmdresp3, + SPCMDRESP3_ZQC_SWTRIG_RESPONSE))) { + dramc_err("ZQCAL Start fail (time out)\n"); + return; + } + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_ZQCEN_SWTRIG, 0); + + udelay(1); + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_ZQLATEN_SWTRIG, 1); + if (!wait_us(timeout, READ32_BITFIELD(&ch[chn].nao.spcmdresp3, + SPCMDRESP3_ZQLAT_SWTRIG_RESPONSE))) { + dramc_err("ZQCAL Latch fail (time out)\n"); + return; + } + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_ZQLATEN_SWTRIG, 0); + + udelay(1); + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); +} + +void dramc_mode_reg_write_by_rank(const struct ddr_cali *cali, + u8 chn, u8 rank, u8 mr_idx, u8 value) +{ + u32 bk_bak, ckectrl_bak; + dramc_info("MRW CH%d RK%d MR%d = %#x\n", chn, rank, mr_idx, value); + + bk_bak = READ32_BITFIELD(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK); + ckectrl_bak = read32(&ch[chn].ao.ckectrl); + + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank); + cke_fix_onoff(cali, chn, rank, CKE_FIXON); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSMA, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSOP, value); + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRWEN, 1); + while (READ32_BITFIELD(&ch[chn].nao.spcmdresp, SPCMDRESP_MRW_RESPONSE) == 0) + udelay(1); + + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRWEN, 0); + write32(&ch[chn].ao.ckectrl, ckectrl_bak); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, bk_bak); +} + +void cbt_switch_freq(const struct ddr_cali *cali, cbt_freq freq) +{ + static u8 _cur_freq = CBT_UNKNOWN_FREQ; + + /* if frequency is same to last, do nothing */ + if (_cur_freq == freq) + return; + _cur_freq = freq; + + enable_dfs_hw_mode_clk(); + + if (freq == CBT_LOW_FREQ) + dramc_dfs_direct_jump_rg_mode(cali, DRAM_DFS_SHU1); + else + dramc_dfs_direct_jump_rg_mode(cali, DRAM_DFS_SHU0); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_clk_ctrl, + MISC_CLK_CTRL_DVFS_CLK_MEM_SEL, 0, + MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN, 0); +} + +static void dramc_mode_reg_init(const struct ddr_cali *cali) +{ + u8 chn; + u8 set_mrsrk; + u8 operate_fsp = get_fsp(cali); + struct mr_values *mr_value = cali->mr_value; + + u32 bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + dramc_power_on_sequence(cali); + + if (get_fsp(cali) == FSP_1) { + for (chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + cbt_switch_freq(cali, CBT_LOW_FREQ); + for (chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + } + + for (chn = 0; chn < CHANNEL_MAX; chn++) { + for (u8 rk = 0; rk < cali->support_ranks; rk++) { + dramc_dbg("ModeRegInit CH%u RK%u\n", chn, rk); + for (u8 fsp = FSP_0; fsp < FSP_MAX; fsp++) { + if (fsp == FSP_0) { + dramc_dbg("FSP0\n"); + mr_value->mr13[rk] = BIT(4) | BIT(3); + mr_value->mr22[fsp] = 0x38; + mr_value->mr11[fsp] = 0x0; + } else { + dramc_dbg("FSP1\n"); + mr_value->mr13[rk] |= 0x40; + + if (cali->cbt_mode[rk] == CBT_NORMAL_MODE) + mr_value->mr11[fsp] = 0x3 | 0x40; + else + mr_value->mr11[fsp] = 0x3 | 0x20; + + if (rk == RANK_0) + mr_value->mr22[fsp] = 0x4; + else + mr_value->mr22[fsp] = 0x2c; + } + + dramc_mode_reg_write_by_rank(cali, chn, rk, 13, + mr_value->mr13[rk]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 12, + mr_value->mr12[chn][rk][fsp]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 1, + mr_value->mr01[fsp]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 2, + mr_value->mr02[fsp]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 11, + mr_value->mr11[fsp]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 21, + mr_value->mr21[fsp]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 51, + mr_value->mr51[fsp]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 22, + mr_value->mr22[fsp]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 14, + mr_value->mr14[chn][rk][fsp]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 3, + mr_value->mr03[fsp]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 4, + mr_value->mr04[rk]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 3, + mr_value->mr03[fsp]); + } + + dramc_zq_calibration(cali, chn, rk); + + if (operate_fsp == FSP_0) + mr_value->mr13[rk] &= 0x3f; + else + mr_value->mr13[rk] |= 0xc0; + } + + if (cali->support_ranks == DUAL_RANK_DDR) + set_mrsrk = 0x3; + else + set_mrsrk = RANK_0; + + dramc_mode_reg_write_by_rank(cali, chn, set_mrsrk, 13, mr_value->mr13[RANK_0]); + + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr13, + SHU_HWSET_MR13_HWSET_MR13_OP, mr_value->mr13[RANK_0] | BIT(3), + SHU_HWSET_MR13_HWSET_MR13_MRSMA, 13); + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_vrcg, + SHU_HWSET_VRCG_HWSET_VRCG_OP, mr_value->mr13[RANK_0] | BIT(3), + SHU_HWSET_VRCG_HWSET_VRCG_MRSMA, 13); + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr2, + SHU_HWSET_MR2_HWSET_MR2_OP, mr_value->mr02[operate_fsp], + SHU_HWSET_MR2_HWSET_MR2_MRSMA, 2); + } + + if (operate_fsp == FSP_1) { + for (chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + cbt_switch_freq(cali, CBT_HIGH_FREQ); + for (chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + } + + for (chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, RANK_0); + + dramc_set_broadcast(bc_bak); +} + static void set_cke2rank_independent(void) { for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { @@ -3792,6 +4090,7 @@ dramc_reset_delay_chain_before_calibration(); dramc_8_phase_cal(cali); dramc_duty_calibration(cali->params); + dramc_mode_reg_init(cali); } static void dramc_before_calibration(const struct ddr_cali *cali) @@ -3870,6 +4169,7 @@ void dfs_init_for_calibration(const struct ddr_cali *cali) { + dramc_init_default_mr_value(cali); dramc_init(cali); dramc_before_calibration(cali); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If200f4dcef0b1d0b7e901d4ae6e667b1f75156f5 Gerrit-Change-Number: 44711 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 21

Change in coreboot[master]: soc/mediatek/mt8192: Do dramc duty calibration
by CK HU (Code Review) 31 Dec '20

31 Dec '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44710 to review the following change. Change subject: soc/mediatek/mt8192: Do dramc duty calibration ...................................................................... soc/mediatek/mt8192: Do dramc duty calibration Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I317451e41774e983c07566dc71c7ba8833c7f55e --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c 2 files changed, 84 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44710/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index b5b262b..091b21b 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -3791,6 +3791,7 @@ dramc_setting(cali); dramc_reset_delay_chain_before_calibration(); dramc_8_phase_cal(cali); + dramc_duty_calibration(cali->params); } static void dramc_before_calibration(const struct ddr_cali *cali) diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c index 22a2545..e1f3d67 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -579,3 +579,86 @@ for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) write32(regs_bak[i].addr, regs_bak[i].value); } + +static void duty_delay_reg_convert(s8 duty_delay, u8 *delay) +{ + u8 delay_tmp; + + if (duty_delay < 0) + delay_tmp = -duty_delay; + else if (duty_delay > 0) + delay_tmp = duty_delay + (1 << 5); + else + delay_tmp = 0; + + *delay = delay_tmp; +} + +static void dramc_duty_set_clk_delay_cell(u8 chn, const s8* duty_delay) +{ + u8 delay_tmp; + + duty_delay_reg_convert(duty_delay[0], &delay_tmp); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_txduty, + SHU_CA_TXDUTY_DA_TX_ARCLK_DUTY_DLY, delay_tmp); +} + +static void dramc_duty_set_dqs_delay_cell(u8 chn, const s8* duty_delay) +{ + u8 dqs; + u8 delay_tmp[DQS_NUMBER]; + + for (dqs = 0; dqs < DQS_NUMBER; dqs++) { + duty_delay_reg_convert(duty_delay[dqs], &(delay_tmp[dqs])); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty, + SHU_B0_TXDUTY_DA_TX_ARDQS_DUTY_DLY_B0, delay_tmp[dqs]); + } +} + + +static void dramc_duty_set_wck_delay_cell(u8 chn, const s8* duty_delay) +{ + u8 dqs; + u8 delay_tmp[DQS_NUMBER]; + + for (dqs = 0; dqs < DQS_NUMBER; dqs++) { + duty_delay_reg_convert(duty_delay[dqs], &(delay_tmp[dqs])); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty, + SHU_B0_TXDUTY_DA_TX_ARWCK_DUTY_DLY_B0, delay_tmp[dqs]); + } +} + +static void dramc_duty_set_dqdqm_delay_cell(u8 chn, + const s8* duty_delay, u8 k_type) +{ + u8 dqs; + u8 delay_tmp[DQS_NUMBER]; + + for (dqs = 0; dqs < DQS_NUMBER; dqs++) { + duty_delay_reg_convert(duty_delay[dqs], &(delay_tmp[dqs])); + + if (k_type == DutyScan_K_DQ) + SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty, + SHU_B0_TXDUTY_DA_TX_ARDQ_DUTY_DLY_B0, delay_tmp[dqs]); + else if (k_type == DutyScan_K_DQM) + SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty, + SHU_B0_TXDUTY_DA_TX_ARDQM_DUTY_DLY_B0, delay_tmp[dqs]); + } +} + +void dramc_duty_calibration(const struct sdram_params *params) +{ + u32 bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + dramc_duty_set_clk_delay_cell(chn, params->duty_clk_delay[chn]); + dramc_duty_set_dqs_delay_cell(chn, params->duty_dqs_delay[chn]); + dramc_duty_set_wck_delay_cell(chn, params->duty_wck_delay[chn]); + dramc_duty_set_dqdqm_delay_cell(chn, params->duty_dqm_delay[chn], + DutyScan_K_DQM); + dramc_duty_set_dqdqm_delay_cell(chn, params->duty_dq_delay[chn], + DutyScan_K_DQ); + } + + dramc_set_broadcast(bc_bak); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I317451e41774e983c07566dc71c7ba8833c7f55e Gerrit-Change-Number: 44710 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

6 19

Change in coreboot[master]: soc/mediatek/mt8192: Add dramc 8 phase calibration
by CK HU (Code Review) 31 Dec '20

31 Dec '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44709 to review the following change. Change subject: soc/mediatek/mt8192: Add dramc 8 phase calibration ...................................................................... soc/mediatek/mt8192: Add dramc 8 phase calibration Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Ib4ccaa8d43b8382cbc64cf82de86ad1ac16cb89a --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c 2 files changed, 344 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/44709/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index fb250ab..b5b262b 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -3790,6 +3790,7 @@ { dramc_setting(cali); dramc_reset_delay_chain_before_calibration(); + dramc_8_phase_cal(cali); } static void dramc_before_calibration(const struct ddr_cali *cali) diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c index 38a8048..22a2545 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -236,3 +236,346 @@ dramc_set_broadcast(bc_bak); } +static void dramc_phy_reset(u8 chn) +{ + SET32_BITFIELDS(&ch[chn].ao.rx_set0, RX_SET0_RDATRST, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0, + B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0, + B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0); + udelay(1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 1, + B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 1, + B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 0); + SET32_BITFIELDS(&ch[chn].ao.rx_set0, RX_SET0_RDATRST, 0); +} + +static int dramc_8_phase_cal_find_best_dly(u8 phase_sm, u8 ph_dly, u8 ph_dly_back, + u8 *dqs_level, u8 *ph_dly_final, u8 *ph_dly_loop_break) +{ + u8 early_break_cnt = 5; + static u8 loop_cnt = 0; + static u16 r0 = 0xffff, r180 = 0xffff, r_tmp = 0xffff, p_tmp = 0xffff; + static s16 err_code = 0x7fff, err_code_min = 0x7fff; + u16 dqs_dly = 0, jm_dly_start = 0, jm_dly_end = 512, jm_dly_step = 1; + u32 sample_cnt, ones_cnt[DQS_NUMBER]; + + dramc_dbg("8PH dly = %d\n", ph_dly); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq1, + SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0, ph_dly); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq1, + SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1, ph_dly); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1, + SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA, ph_dly); + + for (dqs_dly = jm_dly_start; dqs_dly < jm_dly_end; dqs_dly += jm_dly_step) { + /* Set DQS delay */ + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_phy2, + B0_PHY2_RG_RX_ARDQS_JM_DLY_B0, dqs_dly); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_phy2, + B1_PHY2_RG_RX_ARDQS_JM_DLY_B1, dqs_dly); + dramc_phy_reset(0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_REG_SW_RST, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_REG_SW_RST, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 1); + udelay(10); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 0); + sample_cnt = READ32_BITFIELD(&ch[0].phy_nao.misc_duty_toggle_cnt, + MISC_DUTY_TOGGLE_CNT_TOGGLE_CNT); + ones_cnt[0] = READ32_BITFIELD(&ch[0].phy_nao.misc_duty_dqs0_err_cnt, + MISC_DUTY_DQS0_ERR_CNT_DQS0_ERR_CNT); + + if (ones_cnt[0] < (sample_cnt / 2)) { + if (*dqs_level == 0xff) + dramc_dbg("[L] %d, %8d\n", dqs_dly, ones_cnt[0]); + *dqs_level = 0; + } else { + if (*dqs_level == 0) { + *dqs_level = 1; + dramc_dbg("[H] %d, %8d\n", dqs_dly, ones_cnt[0]); + + if (phase_sm == DQS_8PH_DEGREE_0) { + r0 = dqs_dly; + dramc_dbg("R0 = %d\n", r0); + break; + } else if (phase_sm == DQS_8PH_DEGREE_180) { + r180 = dqs_dly; + if (r180 > r0) { + r_tmp = r0 + ((r180 - r0) >> 2); + dramc_dbg("R = %d, R180 = %d\n", r_tmp, r180); + break; + } else { + *dqs_level = 0xff; + } + } else if (phase_sm == DQS_8PH_DEGREE_45) { + p_tmp = dqs_dly; + dramc_dbg("p_tmp =%d, R0 = %d\n", p_tmp, r0); + if (p_tmp > r0) { + if (r_tmp > p_tmp) + err_code = r_tmp - p_tmp; + else + err_code = p_tmp - r_tmp; + + if (err_code == 0) { + *ph_dly_final = ph_dly; + *ph_dly_loop_break = 1; + } else if (err_code < err_code_min) { + err_code_min = err_code; + *ph_dly_final = ph_dly; + loop_cnt = 0; + } else if (err_code >= err_code_min) { + loop_cnt++; + if (loop_cnt > early_break_cnt) + *ph_dly_loop_break = 1; + } + + dramc_dbg("diff (P-R) = %d, min = %d, break count = %d\n", + err_code, err_code_min, loop_cnt); + break; + } else { + *dqs_level = 0xff; + } + } else { + dramc_dbg("phase_sm err!\n"); + } + } + } + + } + + if ((*dqs_level == 0xff) || (*dqs_level == 0)) { + *ph_dly_final = ph_dly_back; + dramc_dbg("8-Phase SM_%d is fail (to Default)!\n", phase_sm); + return 0; + } else if (*ph_dly_loop_break == 1) + return -1; + + return -2; +} + +static void dramc_8_phase_cal_set_best_dly(const struct ddr_cali *cali, u8 ph_dly_back) +{ + u8 dqsien_pi = 0; + u8 phase_sm, ph_dly = 0, ph_start = 0, ph_end = 0, ph_dly_final = 0xff; + u8 ph_dly_loop_break = 0; + + for (phase_sm = DQS_8PH_DEGREE_0; phase_sm < DQS_8PH_DEGREE_MAX; phase_sm++) { + switch (phase_sm) { + case DQS_8PH_DEGREE_0: + dqsien_pi = 16; + ph_start = 0; + ph_end = 1; + break; + case DQS_8PH_DEGREE_180: + dqsien_pi = 48; + ph_start = 0; + ph_end = 1; + break; + case DQS_8PH_DEGREE_45: + dqsien_pi = 24; + ph_start = 0; + ph_end = 32; + break; + default: + dramc_dbg("phase_sm err!\n"); + break; + } + + dramc_dbg("8-Phase SM_%d, 8PH_dly (%d~%d), DQSIEN PI = %d, 8PH_Dly = %d\n", + phase_sm, ph_start, ph_end, dqsien_pi, ph_dly_back); + + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[rk].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, dqsien_pi); + + for (ph_dly = ph_start; ph_dly < ph_end; ph_dly++) { + u8 dqs_level = 0xff; + int ret = dramc_8_phase_cal_find_best_dly(phase_sm, ph_dly, + ph_dly_back, &dqs_level, + &ph_dly_final, &ph_dly_loop_break); + if (ret == 0) + goto final_found; + if (ph_dly_loop_break == 1) + break; + } + } + +final_found: + dramc_dbg("8 phase calibration ph_dly_final = %d\n", ph_dly_final); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq1, + SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0, ph_dly_final); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq1, + SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1, ph_dly_final); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd1, + SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA, ph_dly_final); + } +} + +void dramc_8_phase_cal(const struct ddr_cali *cali) +{ + u8 ph_dly_back = 0; + dram_freq_grp freq_group = cali->freq_group; + + if (freq_group < DDRFREQ_2133) { + dramc_dbg("Freq %d < 2133, do not need do 8-Phase\n", get_frequency(cali)); + return; + } + + struct reg_bak regs_bak[] = { + {&ch[0].phy_ao.misc_dutyscan1}, + {&ch[0].phy_ao.dvs_b[0].b0_dq6}, + {&ch[0].phy_ao.dvs_b[1].b0_dq6}, + {&ch[0].phy_ao.dvs_b[0].b0_dq5}, + {&ch[0].phy_ao.dvs_b[1].b0_dq5}, + {&ch[0].phy_ao.dvs_b[0].b0_dq3}, + {&ch[0].phy_ao.dvs_b[1].b0_dq3}, + {&ch[0].phy_ao.misc_ctrl1}, + {&ch[0].phy_ao.misc_ctrl4}, + {&ch[0].phy_ao.dvs_b[0].b0_phy2}, + {&ch[0].phy_ao.dvs_b[1].b0_phy2}, + {&ch[0].phy_ao.byte[0].shu_b0_dll_arpi2}, + {&ch[0].phy_ao.byte[1].shu_b0_dll_arpi2}, + {&ch[0].phy_ao.byte[0].shu_b0_dq11}, + {&ch[0].phy_ao.byte[1].shu_b0_dq11}, + {&ch[0].phy_ao.shu_ca_cmd11}, + {&ch[0].phy_ao.misc_stbcal}, + {&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_dqsien_pi_dly}, + {&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_dqsien_pi_dly}, + {&ch[0].phy_ao.misc_jmeter}, + {&ch[0].phy_ao.misc_shu_stbcal}, + {&ch[0].phy_ao.shu_ca_dll1}, + {&ch[0].phy_ao.byte[0].shu_b0_dll1}, + {&ch[0].phy_ao.byte[1].shu_b0_dll1}, + {&ch[0].phy_ao.dvs_b[0].b0_dq2}, + {&ch[0].phy_ao.dvs_b[1].b0_dq2}, + {&ch[0].phy_ao.ca_cmd2}, + {&ch[0].phy_ao.byte[0].shu_b0_dq13}, + {&ch[0].phy_ao.byte[1].shu_b0_dq13}, + {&ch[0].phy_ao.shu_ca_cmd13}, + {&ch[1].phy_ao.shu_ca_dll1}, + {&ch[1].phy_ao.byte[0].shu_b0_dll1}, + {&ch[1].phy_ao.byte[1].shu_b0_dll1}, + {&ch[1].phy_ao.dvs_b[0].b0_dq2}, + {&ch[1].phy_ao.dvs_b[1].b0_dq2}, + {&ch[1].phy_ao.ca_cmd2}, + {&ch[1].phy_ao.byte[0].shu_b0_dq13}, + {&ch[1].phy_ao.byte[1].shu_b0_dq13}, + {&ch[1].phy_ao.shu_ca_cmd13}, + }; + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq2, + B0_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B0, 0, + B0_DQ2_RG_TX_ARDQS_OE_TIE_EN_B0, 1, + B0_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B0, 0, + B0_DQ2_RG_TX_ARWCK_OE_TIE_EN_B0, 1, + B0_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B0, 0, + B0_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B0, 1, + B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0, 0, + B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0, 1, + B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0, 0, + B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0, 0xff); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq2, + B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1, 0, + B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1, 1, + B1_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B1, 0, + B1_DQ2_RG_TX_ARWCK_OE_TIE_EN_B1, 1, + B1_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B1, 0, + B1_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B1, 1, + B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1, 0, + B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1, 1, + B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1, 0, + B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1, 0xff); + SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA, 0, + CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA, 1, + CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA, 0, + CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq13, + SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0, 0, + SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq13, + SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1, 0, + SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd13, + SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA, 0, + SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA, 1); + } + + ph_dly_back = READ32_BITFIELD(&ch[0].phy_ao.byte[0].shu_b0_dq1, + SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal, + MISC_SHU_STBCAL_STBCALEN, 0x0, + MISC_SHU_STBCAL_STB_SELPHCALEN, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq11, + SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq11, + SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd11, + SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA, 0); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1, + SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 0x0, + SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dll1, + SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, 0x0, + SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dll1, + SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, 0x0, + SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1, 0x0); + } + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMDQSIENCG_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi2, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi2, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl4, MISC_CTRL4_R_OPT2_CG_DQSIEN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal, MISC_STBCAL_DQSIENCG_NORMAL_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq6, + B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq6, + B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_EYESCAN_DQS_SYNC_EN, 0x1, + MISC_DUTYSCAN1_EYESCAN_NEW_DQ_SYNC_EN, 0x1, + MISC_DUTYSCAN1_EYESCAN_DQ_SYNC_EN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq3, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq3, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_phy2, B0_PHY2_RG_RX_ARDQS_JM_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_phy2, B1_PHY2_RG_RX_ARDQS_JM_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_jmeter, MISC_JMETER_JMTR_EN, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_phy2, B0_PHY2_RG_RX_ARDQS_JM_SEL_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_phy2, B1_PHY2_RG_RX_ARDQS_JM_SEL_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, MISC_DUTYSCAN1_RX_MIOCK_JIT_EN, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, MISC_DUTYSCAN1_DQSERRCNT_DIS, 0); + + dramc_8_phase_cal_set_best_dly(cali, ph_dly_back); + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4ccaa8d43b8382cbc64cf82de86ad1ac16cb89a Gerrit-Change-Number: 44709 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: Update initial settings of dramc
by CK HU (Code Review) 31 Dec '20

31 Dec '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44708 to review the following change. Change subject: soc/mediatek/mt8192: Update initial settings of dramc ...................................................................... soc/mediatek/mt8192: Update initial settings of dramc Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I08326cd1e6f7415d3a91d1591678e1b2c52c6781 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c 2 files changed, 624 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/44708/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 5ca000f..fb250ab 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -3085,6 +3085,571 @@ } } +static void replace_dv_init(const struct ddr_cali *cali) +{ + bool is_4266; + u8 dq_hyst_sel = 0x1, ca_hyst_sel = 0x1; + u8 dq_cap_sel = 0x18, ca_cap_sel = 0x18; + u8 dq_bw_sel_b0 = 0, dq_bw_sel_b1 = 0, ca_bw_sel_ca = 0, clk_bw_sel_ca = 0; + + dram_freq_grp freq_group = cali->freq_group; + + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, + B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, + B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_rxdvs0, + B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0, 0, + B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_rxdvs0, + B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1, 0, + B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1, 0); + + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) { + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].rk[rk].rk_b0_rxdvs2, + RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0, 0, + RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0, 0, + RK_B0_RXDVS2_R_RK0_DVS_MODE_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].rk[rk].rk_b0_rxdvs2, + RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1, 0, + RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1, 0, + RK_B1_RXDVS2_R_RK0_DVS_MODE_B1, 0); + } + + SET32_BITFIELDS(&ch[0].ao.cbt_wlev_ctrl1, CBT_WLEV_CTRL1_CATRAINLAT, 0); + SET32_BITFIELDS(&ch[0].ao.swcmd_ctrl1, SWCMD_CTRL1_WRFIFO_MODE2, 0); + + u32 bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + + switch (freq_group) { + case DDRFREQ_400: + case DDRFREQ_600: + case DDRFREQ_800: + case DDRFREQ_933: + dq_cap_sel = 0x18; + ca_cap_sel = 0x18; + break; + case DDRFREQ_1200: + dq_cap_sel = 0x14; + ca_cap_sel = 0x14; + break; + case DDRFREQ_1600: + dq_cap_sel = 0x4; + ca_cap_sel = 0x4; + break; + case DDRFREQ_2133: + dq_cap_sel = 0x2; + ca_cap_sel = 0x2; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + if (freq_group <= DDRFREQ_933) { + dq_hyst_sel = 0x1; + ca_hyst_sel = 0x1; + } else { + dq_hyst_sel = 0x0; + ca_hyst_sel = 0x0; + } + + if (freq_group <= DDRFREQ_1200) + clk_bw_sel_ca = 1; + + is_4266 = freq_group >= DDRFREQ_2133; + if (is_4266) { + dq_bw_sel_b0 = 1; + dq_bw_sel_b1 = 1; + ca_bw_sel_ca = 1; + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq6, + SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0, dq_hyst_sel, + SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0, dq_cap_sel); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq6, + SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1, dq_hyst_sel, + SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1, dq_cap_sel); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd6, + SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA, ca_hyst_sel, + SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA, ca_cap_sel); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq2, + SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0, is_4266, + SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0, is_4266, + SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0, 0, + SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq2, + SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1, is_4266, + SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1, is_4266, + SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1, 0, + SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd2, + SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA, is_4266, + SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA, is_4266, + SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA, 0, + SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_rx_pipe_ctrl, + SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN, 0x0); + write32(&ch[chn].phy_ao.misc_dbg_irq_ctrl1, 0x0); + write32(&ch[chn].phy_ao.misc_dbg_irq_ctrl4, 0x0); + write32(&ch[chn].phy_ao.misc_dbg_irq_ctrl7, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rx_cg_ctrl, + MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY, 0, + MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY, 2, + MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT, 0, + MISC_SHU_RX_CG_CTRL_RX_DCM_OPT, 0); + SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_MR4INT_LIMITEN, 0); + SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFPEND_OPT1, 0); + SET32_BITFIELDS(&ch[chn].ao.refctrl3, REFCTRL3_REF_DERATING_EN, 0); + SET32_BITFIELDS(&ch[chn].ao.dramc_irq_en, + DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV, 0x3fff, + DRAMC_IRQ_EN_MR4INT_EN, 0x0); + SET32_BITFIELDS(&ch[chn].ao.shu_conf0, SHU_CONF0_PBREFEN, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.ca_tx_mck, + CA_TX_MCK_R_DMRESET_FRPHY_OPT, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2, + MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, MISC_IMPCAL_IMPBINARY, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq10, + SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0, 0x1, + SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq10, + SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1, 0x1, + SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq8, + SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 1, + SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq8, + SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 1, + SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dll2, + SHU_B0_DLL2_RG_ARDQ_REV_B0, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dll2, + SHU_B1_DLL2_RG_ARDQ_REV_B1, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll2, + SHU_CA_DLL2_RG_ARCMD_REV, 0x1); + SET32_BITFIELDS(&ch[chn].ao.dummy_rd, DUMMY_RD_DQSG_DMYRD_EN, 0); + SET32_BITFIELDS(&ch[chn].ao.dramc_dbg_sel1, + DRAMC_DBG_SEL1_DEBUG_SEL_0, 0x1e); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl2, SWCMD_CTRL2_RTSWCMD_AGE, 0x20); + SET32_BITFIELDS(&ch[chn].ao.rtmrw_ctrl0, RTMRW_CTRL0_RTMRW_AGE, 0x20); + SET32_BITFIELDS(&ch[chn].ao.dllfrz_ctrl, + DLLFRZ_CTRL_DLLFRZ, 0, + DLLFRZ_CTRL_DLLFRZ_MON_PBREF_OPT, 0); + SET32_BITFIELDS(&ch[chn].ao.mpc_ctrl, + MPC_CTRL_RTSWCMD_HPRI_EN, 1, + MPC_CTRL_RTMRW_HPRI_EN, 1); + SET32_BITFIELDS(&ch[chn].ao.hw_mrr_fun, + HW_MRR_FUN_R2MRRHPRICTL, 0, + HW_MRR_FUN_TR2MRR_ENA, 0); + SET32_BITFIELDS(&ch[chn].ao.actiming_ctrl, + ACTIMING_CTRL_REFNA_OPT, 1, + ACTIMING_CTRL_SEQCLKRUN3, 1); + SET32_BITFIELDS(&ch[chn].ao.ckectrl, CKECTRL_RUNTIMEMRRCKEFIX, 1); + SET32_BITFIELDS(&ch[chn].ao.dvfs_ctrl0, + DVFS_CTRL0_DVFS_SYNC_MASK, 0, + DVFS_CTRL0_R_DVFS_SREF_OPT, 1); + SET32_BITFIELDS(&ch[chn].ao.dvfs_timing_ctrl1, + DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT, 1); + SET32_BITFIELDS(&ch[chn].ao.hmr4, + HMR4_REFRCNT_OPT, 1, + HMR4_REFR_PERIOD_OPT, 0, + HMR4_SPDR_MR4_OPT, 1, + HMR4_HMR4_TOG_OPT, 0); + SET32_BITFIELDS(&ch[chn].ao.rx_set0, RX_SET0_SMRR_UPD_OLD, 0); + SET32_BITFIELDS(&ch[chn].ao.dramctrl, DRAMCTRL_SHORTQ_OPT, 1); + SET32_BITFIELDS(&ch[chn].ao.misctl0, + MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS, 1); + SET32_BITFIELDS(&ch[chn].ao.perfctl0, PERFCTL0_EBG_EN, 0); + SET32_BITFIELDS(&ch[chn].ao.clkar, + CLKAR_REQQUECLKRUN, 1, + CLKAR_REQQUE_PACG_DIS, 0x7fff); + SET32_BITFIELDS(&ch[chn].ao.refctrl0, + REFCTRL0_PBREF_BK_REFA_ENA, 0, + REFCTRL0_PBREF_BK_REFA_NUM, 0); + SET32_BITFIELDS(&ch[chn].ao.refctrl1, + REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA, 0); + SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFPB2AB_IGZQCS, 0); + SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFPENDINGINT_OPT1, 1); + SET32_BITFIELDS(&ch[chn].ao.ref_bounce1, + REF_BOUNCE1_REFRATE_DEBOUNCE_TH, 5); + SET32_BITFIELDS(&ch[chn].ao.refpend2, REFPEND2_MPENDREFCNT_TH8, 8); + SET32_BITFIELDS(&ch[chn].ao.scsmctrl, SCSMCTRL_SC_PG_MAN_DIS, 0); + SET32_BITFIELDS(&ch[chn].ao.scsmctrl_cg, + SCSMCTRL_CG_SCSM_CGAR, 1, + SCSMCTRL_CG_SCARB_SM_CGAR, 1); + SET32_BITFIELDS(&ch[chn].ao.rtswcmd_cnt, + RTSWCMD_CNT_RTSWCMD_CNT, 0x30); + SET32_BITFIELDS(&ch[chn].ao.dramc_irq_en, + DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV, 0x3fff); + SET32_BITFIELDS(&ch[chn].ao.shu_dcm_ctrl0, + SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 1); + SET32_BITFIELDS(&ch[chn].ao.shu_hmr4_dvfs_ctrl0, + SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x1ff, + SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 0); + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_vrcg, + SHU_HWSET_VRCG_VRCGDIS_PRDCNT, 11); + SET32_BITFIELDS(&ch[chn].ao.shu_misc, SHU_MISC_REQQUE_MAXCNT, 2); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dll_arpi4, + B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B0, 1, + B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dll_arpi4, + B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B1, 1, + B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.ca_dll_arpi4, + CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CLK_CA, 1, + CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CA_CA, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd11, + CA_CMD11_RG_RRESETB_DRVN, 0xa, + CA_CMD11_RG_RRESETB_DRVP, 0xa); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL, 0x1f); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl9, + MISC_CG_CTRL9_RG_MCK4X_O_FB_CK_CG_OFF, 0, + MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_O_OFF, 0, + MISC_CG_CTRL9_RG_MCK4X_O_OPENLOOP_MODE_EN, 0, + MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF, 0, + MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF, 0, + MISC_CG_CTRL9_RG_MCK4X_Q_OPENLOOP_MODE_EN, 0, + MISC_CG_CTRL9_RG_MCK4X_I_FB_CK_CG_OFF, 0, + MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF, 0, + MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN, 0, + MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2, + MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE, 1, + MISC_DVFSCTL2_RG_DLL_SHUFFLE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl3, + MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK, 0x10, + MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE, 1, + MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI, 3, + MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_BCLK, 1, + MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ddr_reserve, + MISC_DDR_RESERVE_WDT_CONF_ISO_CNT, 0xf); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_imp_ctrl1, + MISC_IMP_CTRL1_RG_RIMP_SUS_ECO_OPT, 1, + MISC_IMP_CTRL1_IMP_ABN_LAT_CLR, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV, 1, + MISC_IMPCAL_IMPCAL_DRVUPDOPT, 1, + MISC_IMPCAL_IMPBINARY, 1, + MISC_IMPCAL_DQDRVSWUPD, 1, + MISC_IMPCAL_DRVCGWREF, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_EYESCAN_DQS_OPT, 1, + MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfs_emi_clk, + MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl0, + MISC_CTRL0_IDLE_DCM_CHB_CDC_ECO_OPT, 0, + MISC_CTRL0_IMPCAL_CDC_ECO_OPT, 1, + MISC_CTRL0_IMPCAL_LP_ECO_OPT, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl4, + MISC_CTRL4_R_OPT2_CG_CS, 0, + MISC_CTRL4_R_OPT2_CG_CLK, 0, + MISC_CTRL4_R_OPT2_CG_CMD, 0, + MISC_CTRL4_R_OPT2_CG_DQSIEN, 0, + MISC_CTRL4_R_OPT2_CG_DQ, 0, + MISC_CTRL4_R_OPT2_CG_DQS, 0, + MISC_CTRL4_R_OPT2_CG_DQM, 0, + MISC_CTRL4_R_OPT2_CG_MCK, 0, + MISC_CTRL4_R_OPT2_MPDIV_CG, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl6, + MISC_CTRL6_RG_ADA_MCK8X_EN_SHU_OPT, 1, + MISC_CTRL6_RG_PHDET_EN_SHU_OPT, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rx_autok_cfg0, + MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq1, + SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0, 1, + SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0, 1, + SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq1, + SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1, 1, + SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1, 1, + SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq10, + SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0, 1, + SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0, 1, + SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq10, + SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1, 1, + SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1, 1, + SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq11, + SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0, dq_bw_sel_b0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq11, + SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1, dq_bw_sel_b1); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd11, + SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA, ca_bw_sel_ca); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd10, + SHU_CA_CMD10_RG_RX_ARCLK_BW_SEL_CA, clk_bw_sel_ca); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd1, + SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA, 1, + SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd8, + SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA, 1, + SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA, 1, + SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA, 1, + SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA, 1, + SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA, 1, + SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA, 1, + SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA, 1, + SHU_CA_CMD8_R_RMRODTEN_CG_IG_CA, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_REV, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_impedamce_upd_dis1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_ODTN_UPD_DIS, 1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVN_UPD_DIS, 1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVP_UPD_DIS, 1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_ODTN_UPD_DIS, 1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVN_UPD_DIS, 1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVP_UPD_DIS, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rx_cg_ctrl, + MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY, 0, + MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY, 2, + MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT, 0, + MISC_SHU_RX_CG_CTRL_RX_DCM_OPT, 0); + } + + dramc_set_broadcast(bc_bak); +} + +static void rx_picg_setting(const struct ddr_cali *cali) +{ + u8 talk_lat = (get_div_mode(cali) == DIV4_MODE) ? 1: 0; + + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal, + MISC_SHU_STBCAL_STBCALEN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal, + MISC_SHU_STBCAL_STB_SELPHCALEN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal1, + MISC_STBCAL1_STBCNT_SHU_RST_EN, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal2, + MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal, + MISC_SHU_STBCAL_DQSIEN_PICG_MODE, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rx_in_gate_en_ctrl, + MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rx_in_buff_en_ctrl, + MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal2, + MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN, 0); + for (u8 rk = 0; rk < cali->support_ranks; rk++) + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[rk].misc_shu_rk_dqsien_picg_ctrl, + MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT, talk_lat, + MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rx_in_buff_en_ctrl, + MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN, 0, + MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN, 0, + MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rx_in_gate_en_ctrl, + MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN, 0, + MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN, 0, + MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN, 0); +} + +static void dqs_stb_settings(void) +{ + u32 dqsien_mode = 1; + + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal, + MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE, dqsien_mode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq10, + SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0, dqsien_mode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq10, + SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1, dqsien_mode); +} + +static void rodt_settings(const struct ddr_cali *cali) +{ + u8 vref_sel; + u8 odt_onoff = get_odt_state(cali); + if (get_odt_state(cali) == ODT_ON) + vref_sel = 0x2c; + else + vref_sel = 0x37; + + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, + B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, + B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_vref, + SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0, !odt_onoff); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_vref, + SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1, !odt_onoff); + + for (u8 rk = 0; rk < cali->support_ranks; rk++) { + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[rk].shu_b0_phy_vref_sel, + RG_RX_ARDQ_VREF_SEL_LB_B0, vref_sel, + RG_RX_ARDQ_VREF_SEL_UB_B0, vref_sel); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[rk].shu_b0_phy_vref_sel, + RG_RX_ARDQ_VREF_SEL_LB_B1, vref_sel, + RG_RX_ARDQ_VREF_SEL_UB_B1, vref_sel); + } + + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_vref, + SHU_B0_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_vref, + SHU_B1_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_odtctrl, MISC_SHU_ODTCTRL_RODTEN, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, SHU_B0_DQ7_R_DMRODTEN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, SHU_B1_DQ7_R_DMRODTEN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rodtenstb, + MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN, 1, + MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL, 1, + MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13, + SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0, !odt_onoff); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13, + SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1, !odt_onoff); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd13, + SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA, !odt_onoff); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13, + SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0, 0, + SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq14, + SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13, + SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1, 0, + SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq14, + SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1, 0); +} + +void dramc_cmd_UI_delay_setting(u8 chn, u8 value) +{ + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca7, + SHU_SELPH_CA7_DLY_RA0, value, + SHU_SELPH_CA7_DLY_RA1, value, + SHU_SELPH_CA7_DLY_RA2, value, + SHU_SELPH_CA7_DLY_RA3, value, + SHU_SELPH_CA7_DLY_RA4, value, + SHU_SELPH_CA7_DLY_RA5, value, + SHU_SELPH_CA7_DLY_RA6, value); + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca5, SHU_SELPH_CA5_DLY_CKE, value); + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca6, SHU_SELPH_CA6_DLY_CKE1, value); +} + +void cbt_delay_ca_clk(u8 chn, u8 rank, s32 delay) +{ + if (delay < 0) + /* Set CLK delay */ + SET32_BITFIELDS(&ch[chn].phy_ao.ca_rk[rank].shu_r0_ca_cmd0, + SHU_R0_CA_CMD0_RG_ARPI_CMD, 0, + SHU_R0_CA_CMD0_RG_ARPI_CLK, -delay, + SHU_R0_CA_CMD0_RG_ARPI_CS, -delay); + else + /* Set CA output delay */ + SET32_BITFIELDS(&ch[chn].phy_ao.ca_rk[rank].shu_r0_ca_cmd0, + SHU_R0_CA_CMD0_RG_ARPI_CMD, delay, + SHU_R0_CA_CMD0_RG_ARPI_CLK, 0, + SHU_R0_CA_CMD0_RG_ARPI_CS, 0); +} + +static void set_mck_8x_low_pwr_option(void) +{ + u32 mck_8x_mode = 1; + + SET32_BITFIELDS(&ch[0].phy_ao.misc_lp_ctrl, + MISC_LP_CTRL_RG_SC_ARPI_RESETB_8X_SEQ_LP_SEL, mck_8x_mode, + MISC_LP_CTRL_RG_ADA_MCK8X_8X_SEQ_LP_SEL, mck_8x_mode, + MISC_LP_CTRL_RG_AD_MCK8X_8X_SEQ_LP_SEL, mck_8x_mode, + MISC_LP_CTRL_RG_MIDPI_EN_8X_SEQ_LP_SEL, mck_8x_mode, + MISC_LP_CTRL_RG_MIDPI_CKDIV4_EN_8X_SEQ_LP_SEL, mck_8x_mode, + MISC_LP_CTRL_RG_MCK8X_CG_SRC_LP_SEL, mck_8x_mode, + MISC_LP_CTRL_RG_MCK8X_CG_SRC_AND_LP_SEL, mck_8x_mode); +} + +static void update_initial_settings(const struct ddr_cali *cali) +{ + u8 ca_pi = 0, ca_ui = 1; + u8 fsp = get_fsp(cali); + dram_freq_grp freq_group = get_freq_group(cali); + + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl3, MISC_CTRL3_ARPI_CG_CLK_OPT, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl4, MISC_CTRL4_R_OPT2_CG_CLK, 0); + + replace_dv_init(cali); + + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd14, + SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA, 0xC0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 0x0); + + rx_picg_setting(cali); + dramc_sw_impedance_save_register(cali); + dqs_stb_settings(); + rodt_settings(cali); + SET32_BITFIELDS(&ch[0].ao.shu_tx_set0, SHU_TX_SET0_DBIWR, 0x0); + + dramc_cmd_UI_delay_setting(CHANNEL_A, ca_ui); + SET32_BITFIELDS(&ch[0].ao.shu_selph_ca5, + SHU_SELPH_CA5_DLY_CS, 0x1, + SHU_SELPH_CA5_DLY_CS1, 0x1); + + for (u8 rk = 0; rk < cali->support_ranks; rk++) + cbt_delay_ca_clk(CHANNEL_A, rk, ca_pi); + + SET32_BITFIELDS(&ch[0].ao.refctrl1, REFCTRL1_REF_OVERHEAD_PBR2PB_ENA, 0x1); + SET32_BITFIELDS(&ch[0].ao.misctl0, MISCTL0_REFP_ARBMASK_PBR2PBR_ENA, 0x1); + SET32_BITFIELDS(&ch[0].ao.scheduler_com, SCHEDULER_COM_PBR2PBR_OPT, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_tx_set0, SHU_TX_SET0_WPST1P5T, fsp); + SET32_BITFIELDS(&ch[0].ao.dummy_rd, + DUMMY_RD_DMYRD_REORDER_DIS, 0x1, + DUMMY_RD_SREF_DMYRD_EN, 0x1); + SET32_BITFIELDS(&ch[0].ao.dramctrl, + DRAMCTRL_ALL_BLOCK_CTO_ALE_DBG_EN, 0x0, + DRAMCTRL_DVFS_BLOCK_CTO_ALE_DBG_EN, 0x1, + DRAMCTRL_SELFREF_BLOCK_CTO_ALE_DBG_EN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal2, MISC_STBCAL2_DQSGCNT_BYP_REF, 1); + + if (freq_group <= DDRFREQ_800) + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl, + MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 0); + else if (freq_group <= DDRFREQ_1200) + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl, + MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 1); + else + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl, + MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 2); + + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMARPIDQ_SW, 1); + SET32_BITFIELDS(&ch[0].phy_ao.ca_tx_mck, + CA_TX_MCK_R_DMRESETB_DRVP_FRPHY, 0xa, + CA_TX_MCK_R_DMRESETB_DRVN_FRPHY, 0xa); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rank_sel_lat, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 0x3, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 0x3, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 0x3); + set_mck_8x_low_pwr_option(); +} + static void dramc_setting(const struct ddr_cali *cali) { dram_freq_grp freq_group = cali->freq_group; @@ -3111,6 +3676,7 @@ return; } + update_initial_settings(cali); dramc_set_broadcast(DRAMC_BROADCAST_OFF); } diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c index 04ff5d7..38a8048 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -178,3 +178,61 @@ write32(&ch[chn].phy_ao.misc_impcal, impcal_bak); dramc_set_broadcast(bc_bak); } + +void dramc_sw_impedance_save_register(const struct ddr_cali *cali) +{ + u8 ca_term, dq_term; + u32 bc_bak = dramc_get_broadcast(); + u32 result[ODT_MAX][IMP_DRV_MAX] = {0}; + + ca_term = get_odt_state(cali); + dq_term = (get_freq_group(cali) < DDRFREQ_2133) ? ODT_OFF : ODT_ON; + + memcpy(result, &cali->impedance.result, sizeof(result)); + + dramc_set_broadcast(DRAMC_BROADCAST_ON); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_drving1, + SHU_MISC_DRVING1_DQDRVP2, result[dq_term][DRVP], + SHU_MISC_DRVING1_DQDRVN2, result[dq_term][DRVN]); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_drving2, + SHU_MISC_DRVING2_DQDRVP1, result[dq_term][DRVP], + SHU_MISC_DRVING2_DQDRVN1, result[dq_term][DRVN]); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_drving3, + SHU_MISC_DRVING3_DQODTP2, result[dq_term][ODTP], + SHU_MISC_DRVING3_DQODTN2, result[dq_term][ODTN]); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_drving4, + SHU_MISC_DRVING4_DQODTP1, result[dq_term][ODTP], + SHU_MISC_DRVING4_DQODTN1, result[dq_term][ODTN]); + + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_drving1, + SHU_MISC_DRVING1_DQSDRVP2, result[dq_term][DRVP], + SHU_MISC_DRVING1_DQSDRVN2, result[dq_term][DRVN]); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_drving1, + SHU_MISC_DRVING1_DQSDRVP1, result[dq_term][DRVP], + SHU_MISC_DRVING1_DQSDRVN1, result[dq_term][DRVN]); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_drving3, + SHU_MISC_DRVING3_DQSODTP2, result[dq_term][ODTP], + SHU_MISC_DRVING3_DQSODTN2, result[dq_term][ODTN]); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_drving3, + SHU_MISC_DRVING3_DQSODTP, result[dq_term][ODTP], + SHU_MISC_DRVING3_DQSODTN, result[dq_term][ODTN]); + + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_drving2, + SHU_MISC_DRVING2_CMDDRVP2, result[ca_term][DRVP], + SHU_MISC_DRVING2_CMDDRVN2, result[ca_term][DRVN]); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_drving2, + SHU_MISC_DRVING2_CMDDRVP1, result[ca_term][DRVP], + SHU_MISC_DRVING2_CMDDRVN1, result[ca_term][DRVN]); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_drving4, + SHU_MISC_DRVING4_CMDODTP2, result[ca_term][ODTP], + SHU_MISC_DRVING4_CMDODTN2, result[ca_term][ODTN]); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_drving4, + SHU_MISC_DRVING4_CMDODTP1, result[ca_term][ODTP], + SHU_MISC_DRVING4_CMDODTN1, result[ca_term][ODTN]); + + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_drving8, MISC_SHU_DRVING8_CS_DRVP, 0xF); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_drving8, MISC_SHU_DRVING8_CS_DRVN, 0x14); + + dramc_set_broadcast(bc_bak); +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/44708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08326cd1e6f7415d3a91d1591678e1b2c52c6781 Gerrit-Change-Number: 44708 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020