coreboot-gerrit September 2020

coreboot-gerrit@coreboot.org

1 participants
2629 discussions

Change in coreboot[master]: soc/ti/am335x/header.c: Add missing include
by HAOUAS Elyes (Code Review) 03 Feb '21

03 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44738 ) Change subject: soc/ti/am335x/header.c: Add missing include ...................................................................... soc/ti/am335x/header.c: Add missing include Use of 'offsetof' needs stddef. Change-Id: Ie250b20f464909649b2bd038dbb757d5df637486 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/ti/am335x/header.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44738/1 diff --git a/src/soc/ti/am335x/header.c b/src/soc/ti/am335x/header.c index 9edfdd0..9ed9937 100644 --- a/src/soc/ti/am335x/header.c +++ b/src/soc/ti/am335x/header.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <stddef.h> #include <stdint.h> #include <symbols.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/44738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie250b20f464909649b2bd038dbb757d5df637486 Gerrit-Change-Number: 44738 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/pcengines/apu2: Remove gpio1_ and gpio2_ references
by Kyösti Mälkki (Code Review) 01 Feb '21

01 Feb '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42521 ) Change subject: mb/pcengines/apu2: Remove gpio1_ and gpio2_ references ...................................................................... mb/pcengines/apu2: Remove gpio1_ and gpio2_ references The banks are one after each other in the ACPIMMIO space. Also there is space for more banks and existing ASL also takes advantage of this property. Change-Id: I348ba43a76287be5b24012ae3dfc28ed783da9c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/pcengines/apu2/gpio_ftns.c 1 file changed, 8 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/42521/1 diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c index c249c2d..03eddce 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.c +++ b/src/mainboard/pcengines/apu2/gpio_ftns.c @@ -10,27 +10,20 @@ static u32 gpio_read_wrapper(u32 iomux_gpio) { u32 gpio = iomux_gpio << 2; + if (gpio >= 0x300) + die("Invalid GPIO"); - if (gpio < 0x100) - return gpio0_read32(gpio & 0xff); - else if (gpio >= 0x100 && gpio < 0x200) - return gpio1_read32(gpio & 0xff); - else if (gpio >= 0x200 && gpio < 0x300) - return gpio2_read32(gpio & 0xff); + return gpio0_read32(gpio & 0x3ff); - die("Invalid GPIO"); } static void gpio_write_wrapper(u32 iomux_gpio, u32 setting) { u32 gpio = iomux_gpio << 2; + if (gpio >= 0x300) + die("Invalid GPIO"); - if (gpio < 0x100) - gpio0_write32(gpio & 0xff, setting); - else if (gpio >= 0x100 && gpio < 0x200) - gpio1_write32(gpio & 0xff, setting); - else if (gpio >= 0x200 && gpio < 0x300) - gpio2_write32(gpio & 0xff, setting); + gpio0_write32(gpio & 0x3ff, setting); } void configure_gpio(u32 gpio, u8 iomux_ftn, u32 setting) @@ -70,9 +63,9 @@ * One SPD file contains all 4 options, determine which index to * read here, then call into the standard routines. */ - if (gpio1_read8(0x02) & BIT0) + if (read_gpio(GPIO_49)) index |= BIT0; - if (gpio1_read8(0x06) & BIT0) + if (read_gpio(GPIO_50)) index |= BIT1; return index; -- To view, visit https://review.coreboot.org/c/coreboot/+/42521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I348ba43a76287be5b24012ae3dfc28ed783da9c7 Gerrit-Change-Number: 42521 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

5 29

Change in coreboot[master]: cpu/x86/name/name.c: Clean up includes
by HAOUAS Elyes (Code Review) 01 Feb '21

01 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44315 ) Change subject: cpu/x86/name/name.c: Clean up includes ...................................................................... cpu/x86/name/name.c: Clean up includes Change-Id: I49615434b140601ce599b4a63aa42c82874bd0f7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/x86/name/name.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44315/1 diff --git a/src/cpu/x86/name/name.c b/src/cpu/x86/name/name.c index a7d2c70..d4f50b6 100644 --- a/src/cpu/x86/name/name.c +++ b/src/cpu/x86/name/name.c @@ -2,8 +2,8 @@ #include <string.h> #include <arch/cpu.h> -#include <device/device.h> #include <cpu/x86/name.h> +#include <stdint.h> void fill_processor_name(char *processor_name) { -- To view, visit https://review.coreboot.org/c/coreboot/+/44315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49615434b140601ce599b4a63aa42c82874bd0f7 Gerrit-Change-Number: 44315 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/google/dedede/variants/drawcia/variant.c: Remove unused <bootstate.h>
by HAOUAS Elyes (Code Review) 01 Feb '21

01 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45815 ) Change subject: mb/google/dedede/variants/drawcia/variant.c: Remove unused <bootstate.h> ...................................................................... mb/google/dedede/variants/drawcia/variant.c: Remove unused <bootstate.h> Change-Id: I38d115f2c405128a8d80aec48d2d9d3f25867151 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/dedede/variants/drawcia/variant.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/45815/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/variant.c b/src/mainboard/google/dedede/variants/drawcia/variant.c index 88e9de7..321d165 100644 --- a/src/mainboard/google/dedede/variants/drawcia/variant.c +++ b/src/mainboard/google/dedede/variants/drawcia/variant.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootstate.h> #include <fw_config.h> #include <sar.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38d115f2c405128a8d80aec48d2d9d3f25867151 Gerrit-Change-Number: 45815 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/samsung/exynos5250/include/soc/cpu.h: Add missing include
by HAOUAS Elyes (Code Review) 01 Feb '21

01 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44737 ) Change subject: soc/samsung/exynos5250/include/soc/cpu.h: Add missing include ...................................................................... soc/samsung/exynos5250/include/soc/cpu.h: Add missing include Use of 'KiB' needs <commonlib/bsd/helpers.h> Change-Id: Ia6ba36fd4b0364cc9984523f0add859869068727 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/samsung/exynos5250/include/soc/cpu.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/44737/1 diff --git a/src/soc/samsung/exynos5250/include/soc/cpu.h b/src/soc/samsung/exynos5250/include/soc/cpu.h index aa5a2e8..6d5c18a 100644 --- a/src/soc/samsung/exynos5250/include/soc/cpu.h +++ b/src/soc/samsung/exynos5250/include/soc/cpu.h @@ -3,6 +3,7 @@ #ifndef CPU_SAMSUNG_EXYNOS5250_CPU_H #define CPU_SAMSUNG_EXYNOS5250_CPU_H +#include <commonlib/bsd/helpers.h> #include <symbols.h> /* Base address registers */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6ba36fd4b0364cc9984523f0add859869068727 Gerrit-Change-Number: 44737 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: soc/amd/stoneyridge/acpi: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 01 Feb '21

01 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45690 ) Change subject: soc/amd/stoneyridge/acpi: Convert to ASL 2.0 syntax ...................................................................... soc/amd/stoneyridge/acpi: Convert to ASL 2.0 syntax Change-Id: Ife9bb37817815beec6dad4bc791abba4d91abe00 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/stoneyridge/acpi/cpu.asl M src/soc/amd/stoneyridge/acpi/pci_int.asl M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl M src/soc/amd/stoneyridge/acpi/sleepstates.asl M src/soc/amd/stoneyridge/acpi/usb.asl 5 files changed, 403 insertions(+), 345 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/45690/1 diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl index b2322ea..ca5f249 100644 --- a/src/soc/amd/stoneyridge/acpi/cpu.asl +++ b/src/soc/amd/stoneyridge/acpi/cpu.asl @@ -21,7 +21,7 @@ /* Return a package containing enabled processor entries */ Method (PPKG) { - If (LGreaterEqual (\PCNT, 4)) { + If (\PCNT >= 4) { Return (Package () { \_SB.P000, @@ -29,7 +29,7 @@ \_SB.P002, \_SB.P003 }) - } ElseIf (LGreaterEqual (\PCNT, 2)) { + } ElseIf (\PCNT>= 2) { Return (Package () { \_SB.P000, diff --git a/src/soc/amd/stoneyridge/acpi/pci_int.asl b/src/soc/amd/stoneyridge/acpi/pci_int.asl index 0f3d882..b0bd57b 100644 --- a/src/soc/amd/stoneyridge/acpi/pci_int.asl +++ b/src/soc/amd/stoneyridge/acpi/pci_int.asl @@ -133,9 +133,9 @@ Method(_STA, 0) { if (PIRA) { - Return(0x0b) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTA._STA) */ @@ -145,14 +145,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTA._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKA\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRA, IRQN) - Return(IRQB) + IRQN = 1 << PIRA + Return (IRQB) } /* Method(_SB.INTA._CRS) */ Method(_SRS, 1) { @@ -162,9 +162,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRA) + PIRA = Local0 } /* End Method(_SB.INTA._SRS) */ } /* End Device(INTA) */ @@ -174,9 +174,9 @@ Method(_STA, 0) { if (PIRB) { - Return(0x0b) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTB._STA) */ @@ -186,14 +186,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTB._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKB\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRB, IRQN) - Return(IRQB) + IRQN = 1 << PIRB + Return (IRQB) } /* Method(_SB.INTB._CRS) */ Method(_SRS, 1) { @@ -203,9 +203,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRB) + PIRB = Local0 } /* End Method(_SB.INTB._SRS) */ } /* End Device(INTB) */ @@ -215,9 +215,9 @@ Method(_STA, 0) { if (PIRC) { - Return(0x0b) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTC._STA) */ @@ -227,14 +227,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTC._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKC\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRC, IRQN) - Return(IRQB) + IRQN = 1 << PIRC + Return (IRQB) } /* Method(_SB.INTC._CRS) */ Method(_SRS, 1) { @@ -244,9 +244,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRC) + PIRC = Local0 } /* End Method(_SB.INTC._SRS) */ } /* End Device(INTC) */ @@ -256,9 +256,9 @@ Method(_STA, 0) { if (PIRD) { - Return(0x0b) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTD._STA) */ @@ -268,14 +268,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTD._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKD\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRD, IRQN) - Return(IRQB) + IRQN = 1 << PIRD + Return (IRQB) } /* Method(_SB.INTD._CRS) */ Method(_SRS, 1) { @@ -285,9 +285,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRD) + PIRD = Local0 } /* End Method(_SB.INTD._SRS) */ } /* End Device(INTD) */ @@ -297,9 +297,9 @@ Method(_STA, 0) { if (PIRE) { - Return(0x0b) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTE._STA) */ @@ -309,14 +309,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTE._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKE\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRE, IRQN) - Return(IRQB) + IRQN = 1 << PIRE + Return (IRQB) } /* Method(_SB.INTE._CRS) */ Method(_SRS, 1) { @@ -326,9 +326,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRE) + PIRE = Local0 } /* End Method(_SB.INTE._SRS) */ } /* End Device(INTE) */ @@ -338,9 +338,9 @@ Method(_STA, 0) { if (PIRF) { - Return(0x0b) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTF._STA) */ @@ -350,14 +350,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) + Return (PITF) } /* Method(_SB.INTF._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKF\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRF, IRQN) - Return(IRQB) + IRQN = 1 << PIRF + Return (IRQB) } /* Method(_SB.INTF._CRS) */ Method(_SRS, 1) { @@ -367,9 +367,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRF) + PIRF = Local0 } /* End Method(_SB.INTF._SRS) */ } /* End Device(INTF) */ @@ -379,9 +379,9 @@ Method(_STA, 0) { if (PIRG) { - Return(0x0b) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTG._STA) */ @@ -391,14 +391,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTG._CRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKG\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRG, IRQN) - Return(IRQB) + IRQN = 1 << PIRG + Return (IRQB) } /* Method(_SB.INTG._CRS) */ Method(_SRS, 1) { @@ -408,9 +408,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRG) + PIRG= Local0 } /* End Method(_SB.INTG._SRS) */ } /* End Device(INTG) */ @@ -420,9 +420,9 @@ Method(_STA, 0) { if (PIRH) { - Return(0x0b) /* sata is invisible */ + Return (0x0b) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTH._STA) */ @@ -432,14 +432,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTH._CRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKH\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRH, IRQN) - Return(IRQB) + IRQN = 1 << PIRH + Return (IRQB) } /* Method(_SB.INTH._CRS) */ Method(_SRS, 1) { @@ -449,8 +449,8 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRH) + PIRH = Local0 } /* End Method(_SB.INTH._SRS) */ } /* End Device(INTH) */ diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 1820f7a..f302b04 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -9,14 +9,14 @@ Method(_OSC,4) { /* Check for proper PCI/PCIe UUID */ - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) } Else { CreateDWordField(Arg3,0,CDW1) - Or(CDW1,4,CDW1) // Unrecognized UUID - Return(Arg3) + CDW1 |= 4 // Unrecognized UUID + Return (Arg3) } } @@ -104,12 +104,12 @@ * 32bit (0x00000000 - TOM1) will wrap and give the same * result as 64bit (0x100000000 - TOM1). */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + MM1B = TOM1 + Local0 = 0x10000000 << 4 + Local0 -= TOM1 + MM1L = Local0 - Return(CRES) /* note to change the Name buffer */ + Return (CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ /* @@ -142,8 +142,8 @@ CreateWordField(F1BF, 0, F1SZ) CreateByteField(F1BF, 2, F1DA) - Store(3, F1SZ) - Store(\PWRS, F1DA) + F1SZ = 3 + F1DA= \PWRS \_SB.ALIB(1, F1BF) @@ -151,23 +151,23 @@ Method(OSFL, 0){ - if (LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ + if (OSVR != Ones) {Return (OSVR)} /* OS version was already detected */ if (CondRefOf(\_OSI)) { - Store(1, OSVR) /* Assume some form of XP */ + OSVR = 1 /* Assume some form of XP */ if (\_OSI("Windows 2006")) /* Vista */ { - Store(2, OSVR) + OSVR = 2 } } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ + If (WCMP(\_OS,"Linux")) { + OSVR = 3 /* Linux */ } Else { - Store(4, OSVR) /* Gotta be WinCE */ + OSVR = 4 /* Gotta be WinCE */ } } - Return(OSVR) + Return (OSVR) } OperationRegion(SMIC, SystemMemory, 0xfed80000, 0x80000) @@ -356,74 +356,75 @@ { Acquire(FDAS, 0xffff) - if(LEqual(Arg1, 0)) { + if (Arg1 == 0) { Switch(ToInteger(Arg0)) { Case(Package() {5, 15, 24}) { - Store(One, PG1A) + PG1A = One } Case(Package() {6, 7, 8, 11, 12, 18}) { - Store(One, PG2_) + PG2_ = One } } /* put device into D0 */ Switch(ToInteger(Arg0)) { Case(5) { - Store(0x00, I0TD) - Store(One, I0PD) - Store(I0DS, Local0) - while(LNotEqual(Local0,0x7)) { - Store(I0DS, Local0) + I0TD = 0x00 + I0PD = One + Local0 = I0DS + while(Local0 != 0x7) { + Local0 = I0DS } } Case(6) { - Store(0x00, I1TD) - Store(One, I1PD) - Store(I1DS, Local0) - while(LNotEqual(Local0,0x7)) { - Store(I1DS, Local0) + I1TD = 0x00 + I1PD = One + Local0 = I1DS + while(Local0 != 0x7) { + Local0 = I1DS } } Case(7) { - Store(0x00, I2TD) - Store(One, I2PD) - Store(I2DS, Local0) - while(LNotEqual(Local0,0x7)) { - Store(I2DS, Local0) + I2TD = 0x00 + I2PD = One + Local0 = I2DS + while(Local0 != 0x7) { + Local0 = I2DS } } - Case(8) {Store(0x00, I3TD) - Store(One, I3PD) - Store(I3DS, Local0) - while(LNotEqual(Local0,0x7)) { - Store(I3DS, Local0) + Case(8) { + I3TD = 0x00 + I3PD = One + Local0 = I3DS + while(Local0 != 0x7) { + Local0 = I3DS } } Case(11) { - Store(0x00, U0TD) - Store(One, U0PD) - Store(U0DS, Local0) - while(LNotEqual(Local0,0x7)) { - Store(U0DS, Local0) + U0TD = 0x00 + U0PD = One + Local0 = U0DS + while(Local0 != 0x7) { + Local0 = U0DS } } Case(12) { - Store(0x00, U1TD) - Store(One, U1PD) - Store(U1DS, Local0) - while(LNotEqual(Local0,0x7)) { - Store(U1DS, Local0) + U1TD = 0x00 + U1PD = One + Local0 = U1DS + while(Local0 != 0x7) { + Local0 = U1DS } } /* todo Case(15) { STD0()} */ /* SATA */ Case(18) { U2D0()} /* EHCI */ Case(23) { U3D0()} /* XHCI */ Case(24) { /* SD */ - Store(0x00, SDTD) - Store(One, SDPD) - Store(SDDS, Local0) - while(LNotEqual(Local0,0x7)) { - Store(SDDS, Local0) + SDTD = 0x00 + SDPD = One + Local0 = SDDS + while(Local0 != 0x7) { + Local0 = SDDS } } } @@ -432,77 +433,78 @@ Switch(ToInteger(Arg0)) { Case(5) { - Store(Zero, I0PD) - Store(I0DS, Local0) - while(LNotEqual(Local0,0x0)) { - Store(I0DS, Local0) + I0PD = Zero + Local0 = I0DS + while(Local0 != 0x0) { + Local0 = I0DS } - Store(0x03, I0TD) + I0TD = 0x03 } Case(6) { - Store(Zero, I1PD) - Store(I1DS, Local0) - while(LNotEqual(Local0,0x0)) { - Store(I1DS, Local0) + I1PD = Zero + Local0 = I1DS + while(Local0 != 0x0) { + Local0 = I1DS } - Store(0x03, I1TD) + I1TD = 0x03 } - Case(7) { - Store(Zero, I2PD) - Store(I2DS, Local0) - while(LNotEqual(Local0,0x0)) { - Store(I2DS, Local0) + Case(7) { + I2PD = Zero + Local0 = I2DS + while(Local0 != 0x0) { + Local0 = I2DS } - Store(0x03, I2TD)} + I2TD = 0x03 + } Case(8) { - Store(Zero, I3PD) - Store(I3DS, Local0) - while(LNotEqual(Local0,0x0)) { - Store(I3DS, Local0) + I3PD = Zero + Local0 = I3DS + while(Local0 != 0x0) { + Local0 = I3DS } - Store(0x03, I3TD) + I3TD = 0x03 } Case(11) { - Store(Zero, U0PD) - Store(U0DS, Local0) - while(LNotEqual(Local0,0x0)) { - Store(U0DS, Local0) + U0PD = Zero + Local0 = U0DS + while(Local0 != 0x0) { + Local0 = U0DS } - Store(0x03, U0TD) + U0TD = 0x03 } Case(12) { - Store(Zero, U1PD) - Store(U1DS, Local0) - while(LNotEqual(Local0,0x0)) { - Store(U1DS, Local0) + U1PD = Zero + Local0 = U1DS + while(Local0 != 0x0) { + Local0 = U1DS } - Store(0x03, U1TD) + U1TD = 0x03 } /* todo Case(15) { STD3()} */ /* SATA */ Case(18) { U2D3()} /* EHCI */ Case(23) { U3D3()} /* XHCI */ Case(24) { /* SD */ - Store(Zero, SDPD) - Store(SDDS, Local0) - while(LNotEqual(Local0,0x0)) { - Store(SDDS, Local0) + SDPD = Zero + Local0 = SDDS + while(Local0 != 0x0) { + Local0 = SDDS } - Store(0x03, SDTD) + SDTD = 0x03 } } /* Turn off Power */ - if(LEqual(I0TD, 3)) { - if(LEqual(SATD, 3)) { - if(LEqual(SDTD, 3)) { Store(Zero, PG1A) } + if (I0TD == 3) { + if (SATD == 3) { + if (SDTD == 3) { PG1A = Zero } } } - if(LEqual(I1TD, 3)) { - if(LEqual(I2TD, 3)) { - if(LEqual(I3TD, 3)) { - if(LEqual(U0TD, 3)) { - if(LEqual(U1TD, 3)) { - if(LEqual(U2TD, 3)) { - Store(Zero, PG2_) + if (I1TD == 3) { + if (I2TD == 3) { + if (I3TD == 3) { + if (U0TD == 3) { + if (U1TD == 3) { + if (U2TD == 3) { + PG2_ = Zero } } } @@ -515,53 +517,53 @@ Method(FPTS,0, Serialized) /* FCH _PTS */ { - if(LEqual(\XHCE, one)) { - if(LNotEqual(U3TD, 0x03)) { + if (\XHCE == one) { + if (U3TD != 0x03) { FDDC(23, 3) } } - if(LNotEqual(U2TD, 0x03)) { + if (U2TD != 0x03) { FDDC(18, 3) } } Method(FWAK,0, Serialized) /* FCH _WAK */ { - if(LEqual(\XHCE, one)) { - if(LEqual(U3TD, 0x03)) { + if (\XHCE == one) { + if (U3TD == 0x03) { FDDC(23, 0) } } - if(LEqual(U2TD, 0x03)) { + if (U2TD == 0x03) { FDDC(18, 0) } - if(LEqual(\UT0E, zero)) { - if(LNotEqual(U0TD, 0x03)) { + if (\UT0E == zero) { + if (U0TD != 0x03) { FDDC(11, 3) } } - if(LEqual(\UT1E, zero)) { - if(LNotEqual(U1TD, 0x03)) { + if (\UT1E == zero) { + if (U1TD != 0x03) { FDDC(12, 3) } } - if(LEqual(\IC0E, zero)) { - if(LNotEqual(I0TD, 0x03)) { + if (\IC0E == zero) { + if (I0TD != 0x03) { FDDC(5, 3) } } - if(LEqual(\IC1E, zero)) { - if(LNotEqual(I1TD, 0x03)) { + if (\IC1E == zero) { + if (I1TD != 0x03) { FDDC(6, 3) } } - if(LEqual(\IC2E, zero)) { - if(LNotEqual(I2TD, 0x03)) { + if (\IC2E == zero) { + if (I2TD != 0x03) { FDDC(7, 3) } } - if(LEqual(\IC3E, zero)) { - if(LNotEqual(I3TD, 0x03)) { + if (\IC3E == zero) { + if (I3TD != 0x03) { FDDC(8, 3) } } @@ -574,20 +576,20 @@ */ Method(PWGC,2, Serialized) { - And (PGA3, 0xdf, Local0) /* do SwUsb3SlpShutdown below */ - if(Arg1) { - Or(Arg0, Local0, Local0) + Local0 = PGA3 & 0xdf /* do SwUsb3SlpShutdown below */ + if (Arg1) { + Local0 |= Arg0 } else { - Not(Arg0, Local1) - And(Local1, Local0, Local0) + Local1 = ~Arg0 + Local0 &= Local1 } Store(Local0, PGA3) - if(LEqual(Arg0, 0x20)) { /* if SwUsb3SlpShutdown */ - Store(PGA3, Local0) - And(Arg0, Local0, Local0) - while(LNot(Local0)) { /* wait SwUsb3SlpShutdown to complete */ - Store(PGA3, Local0) - And(Arg0, Local0, Local0) + if (Arg0 == 0x20) { /* if SwUsb3SlpShutdown */ + Local0 = PGA3 + Local0 &= Arg0 + while(!Local0) { /* wait SwUsb3SlpShutdown to complete */ + Local0 = PGA3 + Local0 &= Arg0 } } } diff --git a/src/soc/amd/stoneyridge/acpi/sleepstates.asl b/src/soc/amd/stoneyridge/acpi/sleepstates.asl index 88c6efc..03d28bb 100644 --- a/src/soc/amd/stoneyridge/acpi/sleepstates.asl +++ b/src/soc/amd/stoneyridge/acpi/sleepstates.asl @@ -3,25 +3,25 @@ /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ Name(SSFG, 0x09) If (CONFIG(HAVE_ACPI_RESUME)) { - Store(0x0D, SSFG) + SSFG = 0x0D } If (CONFIG(DISABLE_ACPI_HIBERNATE)) { - Store(And(SSFG, 0xF7), SSFG) + SSFG &= 0xF7 } /* Supported sleep states: */ Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ -If (And(SSFG, 0x01)) { +If (SSFG & 0x01) { Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ } -If (And(SSFG, 0x02)) { +If (SSFG & 0x02) { Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ } -If (And(SSFG, 0x04)) { +If (SSFG & 0x04) { Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ } -If (And(SSFG, 0x08)) { +If (SSFG & 0x08) { Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ } diff --git a/src/soc/amd/stoneyridge/acpi/usb.asl b/src/soc/amd/stoneyridge/acpi/usb.asl index 3c62b33..bf39c94 100644 --- a/src/soc/amd/stoneyridge/acpi/usb.asl +++ b/src/soc/amd/stoneyridge/acpi/usb.asl @@ -67,10 +67,10 @@ Return(XHD0) } Method(_ON) { - Store(0x01, XHD0) + XHD0 = 0x01 } Method(_OFF) { - Store(0x00, XHD0) + XHD0 = 0x00 } } PowerResource(P3U3, 0, 0) { @@ -78,10 +78,10 @@ Return(XHD3) } Method(_ON) { - Store(0x01, XHD3) + XHD3 = 0x01 } Method(_OFF) { - Store(0x00, XHD3) + XHD3 = 0x00 } } @@ -92,10 +92,10 @@ Return(EHD0) } Method(_ON) { - Store(0x01, EHD0) + EHD0 = 0x01 } Method(_OFF) { - Store(0x00, EHD0) + EHD0 = 0x00 } } PowerResource(P3U2, 0, 0) { @@ -103,10 +103,10 @@ Return(EHD3) } Method(_ON) { - Store(0x01, EHD3) + EHD3 = 0x01 } Method(_OFF) { - Store(0x00, EHD3) + EHD3 = 0x00 } } } @@ -121,33 +121,33 @@ Method(U2D3,0, Serialized) { - if (LNotEqual(EH10, Zero)) { - Store (EH10, EHBA) - Store (One, EHME) - Store (ESIM, SSIM) + if (EH10 != Zero) { + EHBA = EH10 + EHME = One + SSIM = ESIM } - if (LEqual(E_PS, 3)) { - Store (Zero, RQTY) - Store (One, RQ18) + if (E_PS == 3) { + RQTY = Zero + RQ18 = One - Store (U2SR, Local0) + Local0 = U2SR while (Local0) { - Store (U2SR, Local0) + Local0 = U2SR } - Store (Zero, U2PD) + U2PD = Zero - Store (U2DS, Local0) - while (LNotEqual(Local0, Zero)) { - Store (U2DS, Local0) + Local0 = U2DS + while (Local0 != Zero) { + Local0 = U2DS } - Store (0x03,U2TD) + U2TD = 0x03 - if (LEqual(U3TD, 0x03)) { /* Shutdown USB2 PLL */ + if (U3TD == 0x03) { /* Shutdown USB2 PLL */ PWGC (0x40, 0) - Store (One, U2RP) + U2RP = One } } } @@ -155,115 +155,115 @@ Method(U2D0,0, Serialized) { PWGC (0x40, 1) - Store (Zero, U2RP) - Store (0x00,U2TD) + U2RP = Zero + U2TD = 0x00 - Store (Zero, U2TD) - Store (One, U2PD) + U2TD = Zero + U2PD = One - Store (U2DS, Local0) - while (LNotEqual(Local0,0x7)) { - Store (U2DS, Local0) + Local0 = U2DS + while (Local0 != 0x7) { + Local0 = U2DS } - Store (One, RQTY) - Store (One, RQ18) - Store (U2SR, Local0) - while (LNot(Local0)) { - Store (U2SR, Local0) + RQTY = One + RQ18 = One + Local0 = U2SR + while (!Local0) { + Local0 = U2SR } - Store (EHID, EH2C) + EH2C = EHID - if (LNotEqual(EH10, Zero)) { - Store (EH10, EHBA) - Store (One, EHME) - Store (SSIM, ESIM) + if (EH10 != Zero) { + EHBA = EH10 + EHME = One + ESIM = SSIM } - Store (ES54, EH54) - Store (ES64, EH64) + EH54 = ES54 + EH64 = ES64 } Method(LXFW,3, Serialized) //Load Xhci FirmWare { - Store (One, FWLM) /* Firmware Load Mode */ - Store (Arg0, ROAM) /* ROM/RAM */ - Store (Arg1, UA04) - Store (Arg2, UA08) - Store (One, FPLS) /* Firmware Preload Start */ - Store (FPLC, Local0) /* Firmware Preload Complete */ - while (LNot(Local0)) { - Store (FPLC, Local0) + FWLM = One /* Firmware Load Mode */ + ROAM = Arg0 /* ROM/RAM */ + UA04 = Arg1 + UA08 = Arg2 + FPLS = One /* Firmware Preload Start */ + Local0 = FPLC /* Firmware Preload Complete */ + while (!Local0) { + Local0 = FPLC } - Store (Zero, FPLS) + FPLS = Zero } Method(U3D3,0, Serialized) { - if (LEqual(U_PS, 3)) { + if (U_PS == 3) { X0_S () - Or (PGA3, 0x20, PGA3) /* SwUsb3SlpShutdown */ - And (PGA3, 0x20, Local0) - while (LNot(Local0)) { /* wait for it to complete */ - And (PGA3, 0x20, Local0) + PGA3 |= 0x20 /* SwUsb3SlpShutdown */ + Local0 = PGA3 & 0x20 + while (!Local0) { /* wait for it to complete */ + Local0 = PGA3 & 0x20 } - Store (One, UD3P) /* U3P_D3Cold_PWRDN */ + UD3P = One /* U3P_D3Cold_PWRDN */ - Store (Zero, U3PD) /* PwrOnDev */ - Store (U3DS, Local0) + U3PD = Zero /* PwrOnDev */ + Local0 = U3DS while (Local0) { /* RstBState, RefClkOkState, PwrRstBState */ - Store (U3DS, Local0) + Local0 = U3DS } - Store (0x3, U3TD) /* TargetedDeviceState */ + U3TD = 0x3 /* TargetedDeviceState */ - Store (One, U3RP) /* USB3_RefClk_Pwdn */ + U3RP = One /* USB3_RefClk_Pwdn */ - if (Lequal(U2TD, 0x3)) { /* If EHCI targeted in D3cold */ - And (PGA3, 0x9f, PGA3) /* SwUsb2S5RstB */ - Store (One, U2RP) /* USB2_RefClk_Pwdn */ + if (U2TD == 0x3) { /* If EHCI targeted in D3cold */ + PGA3 &= 0x9f /* SwUsb2S5RstB */ + U2RP = One /* USB2_RefClk_Pwdn */ } - Store (Zero, U3PG) /* XhcPwrGood */ - Store (One, U3PS) /* Usb3PowerSel */ + U3PG = Zero /* XhcPwrGood */ + U3PS = One /* Usb3PowerSel */ } } Method(U3D0,0, Serialized) { - Store (Zero, U3PS) /* Usb3PowerSel */ - Store (One, U3PG) /* XhcPwrGood */ + U3PS = Zero /* Usb3PowerSel */ + U3PG = One /* XhcPwrGood */ - Store (Zero, U2RP) - Store (Zero, U3RP) + U2RP = Zero + U3RP = Zero - And (PGA3, 0xdf, Local0) - Or (Local0, 0x40, Local0) - Store (Local0, PGA3) /* SwUsb2S5RstB */ + Local0 = PGA3 & 0xdf + Local0 |= 0x40 + PGA3 = Local0 /* SwUsb2S5RstB */ - Store (Zero, U3TD) /* TargetedDeviceState */ - Store (One, U3PD) /* PwrOnDev */ + U3TD = Zero /* TargetedDeviceState */ + U3PD = One /* PwrOnDev */ - Store (U3DS, Local0) /* wait for RstBState, RefClkOkState, PwrRstBState */ - while (LNot(Lequal(Local0, 0x7))) { - Store (U3DS, Local0) + Local0 = U3DS /* wait for RstBState, RefClkOkState, PwrRstBState */ + while (Local0 != 0x7) { + Local0 = U3DS } - Store (U3PY, Local0) /* USB3 PHY Lock */ - while (LNot(Local0)) { - Store (U3PY, Local0) + Local0 = U3PY /* USB3 PHY Lock */ + while (!Local0) { + Local0 = U3PY } - Store (Zero, U3PR) /* U3P_RESTORE_RESET */ + U3PR = Zero /* U3P_RESTORE_RESET */ - Store (AUSS, Local0) /* AutoSizeStart */ - if (LNotEqual(Local0,1)) { - Store(One, AUSS) + Local0 = AUSS /* AutoSizeStart */ + if (Local0 != 1) { + AUSS = One } - Store (AUSS, Local0) - while (LNotEqual(Local0,1)) { - Store (AUSS, Local0) + Local0 = AUSS + while (Local0 != 1) { + Local0 = AUSS } LXFW (1, FW00, FW01) @@ -271,9 +271,9 @@ X0_R () - Store (One, U3PR) /* U3P_RESTORE_RESET */ - Store (Zero, UD3P) /* U3P_D3Cold_PWRDN */ - Store (One, U3TD) /* TargetedDeviceState */ + U3PR = One /* U3P_RESTORE_RESET */ + UD3P = Zero /* U3P_D3Cold_PWRDN */ + U3TD = One /* TargetedDeviceState */ } Name (SVBF, Buffer (0x1000) {0}) /* length from FchCarrizo.asl, new fields */ @@ -313,66 +313,122 @@ Method(X0_S,0) { - Store (XH2C, XHID) - Store (0x00000000, IDEX) Store (DATA, S000) - Store (0x00000004, IDEX) Store (DATA, S004) - Store (0x00000008, IDEX) Store (DATA, S008) - Store (0x0000000c, IDEX) Store (DATA, S00C) - Store (0x00000018, IDEX) Store (DATA, S018) - Store (0x0000001c, IDEX) Store (DATA, S01C) - Store (0x00000020, IDEX) Store (DATA, S020) - Store (0x00000030, IDEX) Store (DATA, S030) - Store (0x00000118, IDEX) Store (DATA, S118) - Store (0x00000158, IDEX) Store (DATA, S158) - Store (0x00000198, IDEX) Store (DATA, S198) - Store (0x000001d8, IDEX) Store (DATA, S1D8) - Store (0x00000300, IDEX) Store (DATA, S300) - Store (0x00000304, IDEX) Store (DATA, S304) - Store (0x00000308, IDEX) Store (DATA, S308) - Store (0x0000030c, IDEX) Store (DATA, S30C) - Store (0x00000310, IDEX) Store (DATA, S310) - Store (0x40000028, IDEX) Store (DATA, S428) - Store (0x40000038, IDEX) Store (DATA, S438) - Store (0x4000003c, IDEX) Store (DATA, S43C) - Store (0x40000058, IDEX) Store (DATA, S458) - Store (0x40000068, IDEX) Store (DATA, S468) - Store (0x4000006c, IDEX) Store (DATA, S46C) - Store (0x40000070, IDEX) Store (DATA, S470) - Store (0x40000080, IDEX) Store (DATA, S480) - Store (0x40000084, IDEX) Store (DATA, S484) - Store (0x40000088, IDEX) Store (DATA, S488) - Store (0x4000008c, IDEX) Store (DATA, S48C) + XHID = XH2C + IDEX = Zero + S000 = DATA + IDEX = 0x00000004 + S004 = DATA + IDEX = 0x00000008 + S008 = DATA + IDEX = 0x0000000C + S00C = DATA + IDEX = 0x00000018 + S018 = DATA + IDEX = 0x0000001C + S01C = DATA + IDEX = 0x00000020 + S020 = DATA + IDEX = 0x00000030 + S030 = DATA + IDEX = 0x00000118 + S118 = DATA + IDEX = 0x00000158 + S158 = DATA + IDEX = 0x00000198 + S198 = DATA + IDEX = 0x000001D8 + S1D8 = DATA + IDEX = 0x00000300 + S300 = DATA + IDEX = 0x00000304 + S304 = DATA + IDEX = 0x00000308 + S308 = DATA + IDEX = 0x0000030C + S30C = DATA + IDEX = 0x00000310 + S310 = DATA + IDEX = 0x40000028 + S428 = DATA + IDEX = 0x40000038 + S438 = DATA + IDEX = 0x4000003C + S43C = DATA + IDEX = 0x40000058 + S458 = DATA + IDEX = 0x40000068 + S468 = DATA + IDEX = 0x4000006C + S46C = DATA + IDEX = 0x40000070 + S470 = DATA + IDEX = 0x40000080 + S480 = DATA + IDEX = 0x40000084 + S484 = DATA + IDEX = 0x40000088 + S488 = DATA + IDEX = 0x4000008C + S48C = DATA } Method(X0_R,0) { - Store (XHID, XH2C) - Store (0x00000000, IDEX) Store (S000, DATA) - Store (0x00000004, IDEX) Store (S004, DATA) - Store (0x00000008, IDEX) Store (S008, DATA) - Store (0x0000000c, IDEX) Store (S00C, DATA) - Store (0x00000018, IDEX) Store (S018, DATA) - Store (0x0000001c, IDEX) Store (S01C, DATA) - Store (0x00000020, IDEX) Store (S020, DATA) - Store (0x00000030, IDEX) Store (S030, DATA) - Store (0x00000118, IDEX) Store (S118, DATA) - Store (0x00000158, IDEX) Store (S158, DATA) - Store (0x00000198, IDEX) Store (S198, DATA) - Store (0x000001d8, IDEX) Store (S1D8, DATA) - Store (0x00000300, IDEX) Store (S300, DATA) - Store (0x00000304, IDEX) Store (S304, DATA) - Store (0x00000308, IDEX) Store (S308, DATA) - Store (0x0000030c, IDEX) Store (S30C, DATA) - Store (0x00000310, IDEX) Store (S310, DATA) - Store (0x40000028, IDEX) Store (S428, DATA) - Store (0x40000038, IDEX) Store (S438, DATA) - Store (0x4000003c, IDEX) Store (S43C, DATA) - Store (0x40000058, IDEX) Store (S458, DATA) - Store (0x40000068, IDEX) Store (S468, DATA) - Store (0x4000006c, IDEX) Store (S46C, DATA) - Store (0x40000070, IDEX) Store (S470, DATA) - Store (0x40000080, IDEX) Store (S480, DATA) - Store (0x40000084, IDEX) Store (S484, DATA) - Store (0x40000088, IDEX) Store (S488, DATA) - Store (0x4000008c, IDEX) Store (S48C, DATA) + XH2C = XHID + IDEX = Zero + DATA = S000 + IDEX = 0x000000004 + DATA = S004 + IDEX = 0x000000008 + DATA = S008 + IDEX = 0x00000000C + DATA = S00C + IDEX = 0x000000018 + DATA = S018 + IDEX = 0x00000001C + DATA = S01C + IDEX = 0x000000020 + DATA = S020 + IDEX = 0x00000030 + DATA = S030 + IDEX = 0x00000118 + DATA = S118 + IDEX = 0x00000158 + DATA = S158 + IDEX = 0x00000198 + DATA = S198 + IDEX = 0x000001D8 + DATA = S1D8 + IDEX = 0x00000300 + DATA = S300 + IDEX = 0x00000304 + DATA = S304 + IDEX = 0x00000308 + DATA = S308 + IDEX = 0x0000030C + DATA = S30C + IDEX = 0x00000310 + DATA = S310 + IDEX = 0x40000028 + DATA = S428 + IDEX = 0x40000038 + DATA = S438 + IDEX = 0x4000003C + DATA = S43C + IDEX = 0x40000058 + DATA = S458 + IDEX = 0x40000068 + DATA = S468 + IDEX = 0x4000006C + DATA = S46C + IDEX = 0x40000070 + DATA = S470 + IDEX = 0x40000080 + DATA = S480 + IDEX = 0x40000084 + DATA = S484 + IDEX = 0x40000088 + DATA = S488 + IDEX = 0x4000008C + DATA = S48C } -- To view, visit https://review.coreboot.org/c/coreboot/+/45690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife9bb37817815beec6dad4bc791abba4d91abe00 Gerrit-Change-Number: 45690 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: src: Remove unused include <cpu/x86/smm.h>
by HAOUAS Elyes (Code Review) 31 Jan '21

31 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43993 ) Change subject: src: Remove unused include <cpu/x86/smm.h> ...................................................................... src: Remove unused include <cpu/x86/smm.h> Change-Id: I866d9f72c866f22ec1b72ed90900ca11be98e267 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/baytrail/acpi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/skylake/romstage/romstage.c 3 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/43993/1 diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 458e2d5..5a0f210 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -7,7 +7,6 @@ #include <arch/smp/mpspec.h> #include <cbmem.h> #include <console/console.h> -#include <cpu/x86/smm.h> #include <types.h> #include <cpu/x86/msr.h> #include <cpu/intel/turbo.h> diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index c76c8d2..eb6bad7 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -6,7 +6,6 @@ #include <arch/smp/mpspec.h> #include <cbmem.h> #include <device/pci_ops.h> -#include <cpu/x86/smm.h> #include <console/console.h> #include <types.h> #include <string.h> diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 99f444a..9ae854d 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -4,7 +4,6 @@ #include <arch/symbols.h> #include <assert.h> #include <cpu/x86/msr.h> -#include <cpu/x86/smm.h> #include <cbmem.h> #include <console/console.h> #include <device/pci_def.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/43993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866d9f72c866f22ec1b72ed90900ca11be98e267 Gerrit-Change-Number: 43993 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/mediatek/mt8192: Implement dram all channel calibration
by CK HU (Code Review) 28 Jan '21

28 Jan '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44715 to review the following change. Change subject: soc/mediatek/mt8192: Implement dram all channel calibration ...................................................................... soc/mediatek/mt8192: Implement dram all channel calibration Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I62cc654d5a6b861f72eec66e09d24483b993f0e4 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 358 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44715/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 1a5f242..8362c05 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -4031,6 +4031,51 @@ dramc_set_broadcast(bc_bak); } +static void move_dramc_delay(const struct ddr_cali* cali, reg_transfer *ui, + reg_transfer *mck, s8 shift_ui) +{ + s32 sum; + u8 ui_offset = ui->offset, ui_width = 4, mck_offset = mck->offset, mck_width = 3; + u32 *ui_reg = ui->addr, *mck_reg = mck->addr; + + u32 tmp_ui, tmp_mck, ui_mask, mck_mask; + u8 div_shift = get_mck2ui_div_shift(cali); + + ui_mask = (BIT(ui_width) - 1); + mck_mask = (BIT(mck_width) - 1); + tmp_ui = ((read32(ui_reg) >> ui_offset) & ui_mask) & (~(1 << div_shift)); + tmp_mck = (read32(mck_reg) >> mck_offset) & mck_mask; + + sum = (tmp_mck << div_shift) + tmp_ui + shift_ui; + + if (sum < 0) { + tmp_ui = 0; + tmp_mck = 0; + } else { + tmp_mck = sum >> div_shift; + tmp_ui = sum - (tmp_mck << div_shift); + } + + clrsetbits32(ui_reg, ui_mask << ui_offset, tmp_ui << ui_offset); + clrsetbits32(mck_reg, mck_mask << mck_offset, tmp_mck << mck_offset); +} + +void shift_dq_ui(const struct ddr_cali* cali, u8 rk, s8 shift_ui) +{ + u8 chn = cali->chn; + reg_transfer ui_regs[] = {{&ch[chn].ao.shu_rk[rk].shurk_selph_dq3, 0}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq3, 4}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq2, 0}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq2, 4}}; + reg_transfer mck_regs[] = {{&ch[chn].ao.shu_rk[rk].shurk_selph_dq1, 0}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq1, 4}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq0, 0}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq0, 4}}; + + for (u8 idx = 0; idx < ARRAY_SIZE(ui_regs); idx++) + move_dramc_delay(cali, &ui_regs[idx], &mck_regs[idx], shift_ui); +} + static void ddr_update_ac_timing(const struct ddr_cali *cali) { u8 table_idx; @@ -4407,3 +4452,255 @@ dramc_before_calibration(cali); } +void tx_picg_setting(const struct ddr_cali *cali) +{ + u32 dqs_oen_final, dq_oen_final; + u16 dqs_oen_2t[2], dqs_oen_05t[2], dqs_oen_delay[2]; + u16 dq_oen_2t[2], dq_oen_05t[2], dq_oen_delay[2]; + u16 comb_tx_sel[2]; + u16 shift_dqs_div[2], shift_dq_div[2]; + u16 comb_tx_picg_cnt; + u8 div_ratio; + + comb_tx_picg_cnt = 3; + if (get_div_mode(cali) == DIV8_MODE) { + shift_dqs_div[0] = 10; + shift_dqs_div[1] = 6; + shift_dq_div[0] = 8; + shift_dq_div[1] = 4; + div_ratio = 3; + } else { + shift_dqs_div[0] = 2; + shift_dqs_div[1] = 0; + shift_dq_div[0] = 0; + shift_dq_div[1] = 0; + div_ratio = 2; + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + dqs_oen_2t[0] = READ32_BITFIELD(&ch[chn].ao.shu_selph_dqs0, + SHU_SELPH_DQS0_TXDLY_OEN_DQS0); + dqs_oen_05t[0] = READ32_BITFIELD(&ch[chn].ao.shu_selph_dqs1, + SHU_SELPH_DQS1_DLY_OEN_DQS0); + dqs_oen_delay[0] = (dqs_oen_2t[0] << div_ratio) + dqs_oen_05t[0]; + dqs_oen_2t[1] = READ32_BITFIELD(&ch[chn].ao.shu_selph_dqs0, + SHU_SELPH_DQS0_TXDLY_OEN_DQS1); + dqs_oen_05t[1] = READ32_BITFIELD(&ch[chn].ao.shu_selph_dqs1, + SHU_SELPH_DQS1_DLY_OEN_DQS1); + dqs_oen_delay[1] = (dqs_oen_2t[1] << div_ratio) + dqs_oen_05t[1]; + + dqs_oen_final = (dqs_oen_delay[0] > dqs_oen_delay[1]) ? + dqs_oen_delay[1]: dqs_oen_delay[0]; + dqs_oen_final += 1; + + comb_tx_sel[0] = (dqs_oen_final > shift_dqs_div[0]) ? + ((dqs_oen_final - shift_dqs_div[0]) >> div_ratio) : 0; + + if (get_div_mode(cali) == DIV4_MODE) + comb_tx_sel[1] = 0; + else + comb_tx_sel[1] = (dqs_oen_final > shift_dqs_div[1]) ? + ((dqs_oen_final - shift_dqs_div[1]) >> div_ratio): 0; + + SET32_BITFIELDS(&ch[chn].ao.shu_aphy_tx_picg_ctrl, + SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, comb_tx_sel[0], + SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, comb_tx_sel[1], + SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, comb_tx_picg_cnt); + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) { + dq_oen_2t[0] = READ32_BITFIELD(&ch[chn].ao.shu_rk[rk].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0); + dq_oen_05t[0] = READ32_BITFIELD(&ch[chn].ao.shu_rk[rk].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_OEN_DQ0); + dq_oen_delay[0] = (dq_oen_2t[0] << div_ratio) + dq_oen_05t[0]; + dq_oen_2t[1] = READ32_BITFIELD(&ch[chn].ao.shu_rk[rk].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1); + dq_oen_05t[1] = READ32_BITFIELD(&ch[chn].ao.shu_rk[rk].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_OEN_DQ1); + dq_oen_delay[1] = (dq_oen_2t[1] << div_ratio) + dq_oen_05t[1]; + + dq_oen_final = (dq_oen_delay[0] > dq_oen_delay[1]) ? + dq_oen_delay[1] : dq_oen_delay[0]; + dq_oen_final += 1; + + comb_tx_sel[0] = (dq_oen_final > shift_dq_div[0]) ? + ((dq_oen_final - shift_dq_div[0]) >> div_ratio) : 0; + + if (get_div_mode(cali) == DIV4_MODE) + comb_tx_sel[1] = 0; + else + comb_tx_sel[1] = (dq_oen_final > shift_dq_div[1]) ? + ((dq_oen_final - shift_dq_div[1]) >> div_ratio): 0; + + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rk].shurk_aphy_tx_picg_ctrl, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, comb_tx_sel[0], + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, comb_tx_sel[1]); + } + } +} + +void xrtrtr_shu_setting(const struct ddr_cali *cali) +{ + dram_freq_grp freq_group = get_freq_group(cali); + u8 rk_sel_ui_minus = 0, rk_sel_mck_minus = 0; + + if (freq_group == DDRFREQ_400) + rk_sel_mck_minus = 1; + else if (freq_group >= DDRFREQ_1600) + rk_sel_ui_minus = 2; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_rank_sel_stb, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, rk_sel_mck_minus, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, rk_sel_ui_minus, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 0x1, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0x1); +} + +void freq_jump_ratio_calculation(const struct ddr_cali *cali) +{ + u32 src_freq, dst_freq, src_shu, dst_shu, jump_ratio_index; + u16 jump_ratio[12] = {0}; + + jump_ratio_index = 0; + src_freq = get_frequency(cali); + src_shu = get_shu(cali); + + if (src_freq != 400) { + for (dst_shu = DRAM_DFS_SHU0; dst_shu < DRAM_DFS_SHU_MAX; dst_shu++) { + dst_freq = get_frequency_by_shu(dst_shu); + jump_ratio[jump_ratio_index] = DIV_ROUND_CLOSEST(dst_freq * 32, src_freq); + + dramc_dbg("Jump_RATIO [%d]: 0x%x\tFreq %d -> %d\tDDR%d -> DDR%d\n", + jump_ratio_index, jump_ratio[jump_ratio_index], + src_shu, dst_shu, src_freq << 1, dst_freq << 1); + jump_ratio_index++; + } + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.shu_freq_ratio_set0, + SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0, jump_ratio[0], + SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1, jump_ratio[1], + SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2, jump_ratio[2], + SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3, jump_ratio[3]); + SET32_BITFIELDS(&ch[chn].ao.shu_freq_ratio_set1, + SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO4, jump_ratio[4], + SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO5, jump_ratio[5], + SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO6, jump_ratio[6], + SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO7, jump_ratio[7]); + SET32_BITFIELDS(&ch[chn].ao.shu_freq_ratio_set2, + SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO8, jump_ratio[8], + SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO9, jump_ratio[9]); + } +} + +void dramc_hmr4_presetting(const struct ddr_cali* cali) +{ + for (u8 chn = CHANNEL_A; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_REFR_PERIOD_OPT, 1); + SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_REFRCNT_OPT, 0); + SET32_BITFIELDS(&ch[chn].ao.shu_hmr4_dvfs_ctrl0, + SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x80); + + if (get_cbt_mode(cali) == CBT_BYTE_MODE1) + SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_HMR4_BYTEMODE_EN, 1); + else + SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_HMR4_BYTEMODE_EN, 0); + + SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFRATE_MON_CLR, 0); + SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFRATE_MON_CLR, 1); + SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFRATE_MON_CLR, 0); + } +} + +void dramc_enable_perbank_refresh(bool en) +{ + if (en) { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.refctrl0, + REFCTRL0_PBREF_BK_REFA_ENA, 1, + REFCTRL0_PBREF_BK_REFA_NUM, 2); + SET32_BITFIELDS(&ch[chn].ao.refctrl0, + REFCTRL0_KEEP_PBREF, 0, + REFCTRL0_KEEP_PBREF_OPT, 1); + SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFPB2AB_IGZQCS, 1); + } + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].ao.shu_conf0, SHU_CONF0_PBREFEN, en); +} + +void dramc_modified_refresh_mode(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.refpend1, + REFPEND1_MPENDREFCNT_TH0, 2, + REFPEND1_MPENDREFCNT_TH1, 2, + REFPEND1_MPENDREFCNT_TH2, 4, + REFPEND1_MPENDREFCNT_TH3, 5, + REFPEND1_MPENDREFCNT_TH4, 5, + REFPEND1_MPENDREFCNT_TH5, 3, + REFPEND1_MPENDREFCNT_TH6, 3, + REFPEND1_MPENDREFCNT_TH7, 3); + SET32_BITFIELDS(&ch[chn].ao.refctrl1, + REFCTRL1_REFPEND_OPT1, 1, + REFCTRL1_REFPEND_OPT2, 1); + SET32_BITFIELDS(&ch[chn].ao.shu_ref0, SHU_REF0_MPENDREF_CNT, 4); + } +} + +void dramc_cke_debounce(const struct ddr_cali* cali) +{ + if (get_freq_group(cali) < DDRFREQ_2133) + return; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + for (u8 rk = 0; rk < cali->support_ranks; rk++) + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rk].shurk_cke_ctrl, + SHURK_CKE_CTRL_CKE_DBE_CNT, 15); +} + +void dramc_hw_dqsosc(const struct ddr_cali* cali, u8 chn) +{ + SET32_BITFIELDS(&ch[chn].ao.tx_freq_ratio_old_mode0, + TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT, 1); + SET32_BITFIELDS(&ch[chn].ao.tx_tracking_set0, + TX_TRACKING_SET0_SHU_PRELOAD_TX_HW, 1, + TX_TRACKING_SET0_SHU_PRELOAD_TX_START, 0, + TX_TRACKING_SET0_SW_UP_TX_NOW_CASE, 0); + + SET32_BITFIELDS(&ch[chn].ao.mpc_ctrl, MPC_CTRL_MPC_BLOCKALE_OPT, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMARPIDQ_SW, 0); + SET32_BITFIELDS(&ch[chn].ao.dcm_sub_ctrl, DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING, 1); + SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_ARUIDQ_SW, 1); + SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSCRDIS, 0); + SET32_BITFIELDS(&ch[chn].ao.rk[0].rk_dqsosc, RK_DQSOSC_DQSOSCR_RK0EN, 1); + if (cali->support_ranks == DUAL_RANK_DDR) + SET32_BITFIELDS(&ch[chn].ao.rk[1].rk_dqsosc, RK_DQSOSC_DQSOSCR_RK0EN, 1); + SET32_BITFIELDS(&ch[chn].ao.tx_set0, TX_SET0_DRSCLR_RK0_EN, 1); + SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSC_CALEN, 1); +} + +void apply_write_dbi_power_improve(bool en) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].ao.dbiwr_protect, + DBIWR_PROTECT_DBIWR_OPT_B1, 0, + DBIWR_PROTECT_DBIWR_OPT_B0, 0, + DBIWR_PROTECT_DBIWR_PINMUX_EN, 0, + DBIWR_PROTECT_DBIWR_IMP_EN, en); +} + +void dramc_write_dbi_onoff(u8 onoff) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].ao.shu_tx_set0, SHU_TX_SET0_DBIWR, onoff); + dramc_info("DramC Write-DBI %s\n", (onoff == DBI_ON) ? "on" : "off"); +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 3273f28..11ec636 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -6,6 +6,16 @@ #include <soc/pll_common.h> #include <soc/mt6359p.h> +static void dramc_write_shift_mck_write_DBI(const struct ddr_cali *cali, s8 shift_value) +{ + u8 div_shift = 0; + s8 ui_move = 0; + + div_shift = get_mck2ui_div_shift(cali); + ui_move = shift_value * (s8)(1 << div_shift); + shift_dq_ui(cali, cali->rank, ui_move); +} + static void dramc_ac_timing_optimize(const struct ddr_cali* cali) { u8 rf_group = 0, cab_id = 0; @@ -208,8 +218,57 @@ cali->density = max_density; } +static void dramc_calibration_single_channel(struct ddr_cali *cali, u8 chn) +{ + cali->chn = chn; + SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); +} + static void dramc_calibration_all_channels(struct ddr_cali *cali) { + u8 chn_bak, rank_bak; + dbi_mode w_dbi = get_write_dbi(cali); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + dramc_calibration_single_channel(cali, chn); + + if (w_dbi == DBI_ON) { + chn_bak = cali->chn; + rank_bak = cali->rank; + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + for (u8 rank = RANK_0; rank < RANK_MAX; rank++) { + cali->chn = chn; + cali->rank = rank; + dramc_write_shift_mck_write_DBI(cali, -1); + } + cali->chn = chn_bak; + cali->rank = rank_bak; + apply_write_dbi_power_improve(true); + } + + dramc_write_dbi_onoff(w_dbi); + + tx_picg_setting(cali); + if (cali->support_ranks == DUAL_RANK_DDR) + xrtrtr_shu_setting(cali); + freq_jump_ratio_calculation(cali); + + dramc_hmr4_presetting(cali); + dramc_enable_perbank_refresh(true); + dramc_modified_refresh_mode(); + dramc_cke_debounce(cali); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + dramc_hw_dqsosc(cali, chn); } static void mem_pll_init(void) @@ -296,6 +355,7 @@ if (first_freq_k) dramc_load_shuffle_to_dramc(cali.shu, DRAM_DFS_SHU1); - first_freq_k= false; + first_freq_k = false; + dramc_info("frequency %d calibration finish\n", get_frequency(&cali)); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/44715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62cc654d5a6b861f72eec66e09d24483b993f0e4 Gerrit-Change-Number: 44715 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

6 13

Change in coreboot[master]: sb/amd/cimx/sb800/acpi: Convert 'pcie.asl' to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 27 Jan '21

27 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45874 ) Change subject: sb/amd/cimx/sb800/acpi: Convert 'pcie.asl' to ASL 2.0 syntax ...................................................................... sb/amd/cimx/sb800/acpi: Convert 'pcie.asl' to ASL 2.0 syntax Change-Id: Ic817c261a3be8d5ee333982873996aa35778a192 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/cimx/sb800/acpi/pcie.asl 1 file changed, 72 insertions(+), 72 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45874/1 diff --git a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl index a2d7f12..9f6a934 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl @@ -138,18 +138,18 @@ { \_SB.CIRQ() } - Store(Arg0, PMOD) + PMOD = Arg0 } Method(CIRQ, 0x00, NotSerialized){ - Store(0, PIRA) - Store(0, PIRB) - Store(0, PIRC) - Store(0, PIRD) - Store(0, PIRE) - Store(0, PIRF) - Store(0, PIRG) - Store(0, PIRH) + PIRA = 0 + PIRB = 0 + PIRC = 0 + PIRD = 0 + PIRE = 0 + PIRF = 0 + PIRG = 0 + PIRH = 0 } Name(IRQB, ResourceTemplate(){ @@ -170,27 +170,27 @@ Method(_STA, 0) { if (PIRA) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTA._STA) */ Method(_DIS ,0) { /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - Store(0, PIRA) + PIRA = 0 } /* End Method(_SB.INTA._DIS) */ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTA._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKA\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRA, IRQN) - Return(IRQB) + IRQN = 1 << PIRA + Return (IRQB) } /* Method(_SB.INTA._CRS) */ Method(_SRS, 1) { @@ -200,9 +200,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRA) + PIRA = Local0 } /* End Method(_SB.INTA._SRS) */ } /* End Device(INTA) */ @@ -212,27 +212,27 @@ Method(_STA, 0) { if (PIRB) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTB._STA) */ Method(_DIS ,0) { /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - Store(0, PIRB) + PIRB = 0 } /* End Method(_SB.INTB._DIS) */ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTB._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKB\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRB, IRQN) - Return(IRQB) + IRQN = 1 << PIRB + Return (IRQB) } /* Method(_SB.INTB._CRS) */ Method(_SRS, 1) { @@ -242,9 +242,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRB) + PIRB = Local0 } /* End Method(_SB.INTB._SRS) */ } /* End Device(INTB) */ @@ -254,15 +254,15 @@ Method(_STA, 0) { if (PIRC) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTC._STA) */ Method(_DIS ,0) { /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - Store(0, PIRC) + PIRC = 0 } /* End Method(_SB.INTC._DIS) */ Method(_PRS ,0) { @@ -273,8 +273,8 @@ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKC\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRC, IRQN) - Return(IRQB) + IRQN = 1 << PIRC + Return (IRQB) } /* Method(_SB.INTC._CRS) */ Method(_SRS, 1) { @@ -284,9 +284,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRC) + PIRC = Local0 } /* End Method(_SB.INTC._SRS) */ } /* End Device(INTC) */ @@ -296,27 +296,27 @@ Method(_STA, 0) { if (PIRD) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTD._STA) */ Method(_DIS ,0) { /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - Store(0, PIRD) + PIRD = 0 } /* End Method(_SB.INTD._DIS) */ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTD._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKD\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRD, IRQN) - Return(IRQB) + IRQN = 1 << PIRD + Return (IRQB) } /* Method(_SB.INTD._CRS) */ Method(_SRS, 1) { @@ -326,9 +326,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRD) + PIRD = Local0 } /* End Method(_SB.INTD._SRS) */ } /* End Device(INTD) */ @@ -338,27 +338,27 @@ Method(_STA, 0) { if (PIRE) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTE._STA) */ Method(_DIS ,0) { /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - Store(0, PIRE) + PIRE = 0 } /* End Method(_SB.INTE._DIS) */ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTE._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKE\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRE, IRQN) - Return(IRQB) + IRQN = 1 << PIRE + Return (IRQB) } /* Method(_SB.INTE._CRS) */ Method(_SRS, 1) { @@ -368,9 +368,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRE) + PIRE Local0 } /* End Method(_SB.INTE._SRS) */ } /* End Device(INTE) */ @@ -380,27 +380,27 @@ Method(_STA, 0) { if (PIRF) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTF._STA) */ Method(_DIS ,0) { /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - Store(0, PIRF) + PIRF = 0 } /* End Method(_SB.INTF._DIS) */ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) + Return (PITF) } /* Method(_SB.INTF._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKF\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRF, IRQN) - Return(IRQB) + IRQN = 1 << PIRF + Return (IRQB) } /* Method(_SB.INTF._CRS) */ Method(_SRS, 1) { @@ -410,9 +410,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRF) + PIRF = Local0 } /* End Method(_SB.INTF._SRS) */ } /* End Device(INTF) */ @@ -422,27 +422,27 @@ Method(_STA, 0) { if (PIRG) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTG._STA) */ Method(_DIS ,0) { /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - Store(0, PIRG) + PIRG = 0 } /* End Method(_SB.INTG._DIS) */ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTG._CRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKG\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRG, IRQN) - Return(IRQB) + IRQN = 1 << PIRG + Return (IRQB) } /* Method(_SB.INTG._CRS) */ Method(_SRS, 1) { @@ -452,9 +452,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRG) + PIRG = Local0 } /* End Method(_SB.INTG._SRS) */ } /* End Device(INTG) */ @@ -464,27 +464,27 @@ Method(_STA, 0) { if (PIRH) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTH._STA) */ Method(_DIS ,0) { /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - Store(0, PIRH) + PIRH = 0 } /* End Method(_SB.INTH._DIS) */ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTH._CRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKH\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRH, IRQN) - Return(IRQB) + IRQN = 1 << PIRH + Return (IRQB) } /* Method(_SB.INTH._CRS) */ Method(_SRS, 1) { @@ -494,9 +494,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRH) + PIRH = Local0 } /* End Method(_SB.INTH._SRS) */ } /* End Device(INTH) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic817c261a3be8d5ee333982873996aa35778a192 Gerrit-Change-Number: 45874 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: [WIP] cpu/x86/mpinit: Serialize microcode updates for HT threads
by Patrick Rudolph (Code Review) 25 Jan '21

25 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44904 ) Change subject: [WIP] cpu/x86/mpinit: Serialize microcode updates for HT threads ...................................................................... [WIP] cpu/x86/mpinit: Serialize microcode updates for HT threads Update microcode using a core specific semaphore. The SDM and most of the BWGs suggest doing this. Change-Id: I89a01f6ff94e7d35f1feded3ddb0c43caf7c6c5d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/mp_init.c M src/cpu/x86/sipi_vector.S 2 files changed, 74 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44904/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 5807831..4c4de09 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -25,6 +25,7 @@ #include <symbols.h> #include <timer.h> #include <thread.h> +#include <lib.h> #include <security/intel/stm/SmmStm.h> @@ -97,6 +98,9 @@ uint32_t msr_count; uint32_t c_handler; atomic_t ap_count; + uint32_t microcode_lock_ht; /* 1 special microcode locking for Intel HT CPUs */ + uint32_t apic_core_id_mask; + uint32_t hyperthreading_lock[CONFIG_MAX_CPUS/2]; } __packed; /* This also needs to match the assembly code for saved MSR encoding. */ @@ -216,6 +220,31 @@ sp->stack_top = ALIGN_DOWN((uintptr_t)&_estack, CONFIG_STACK_SIZE); /* Adjust the stack top to take into account cpu_info. */ sp->stack_top -= sizeof(struct cpu_info); + sp->microcode_lock_ht = !!(cpuid_edx(1) & CPUID_FEAURE_HTT); + if (sp->microcode_lock_ht) { + struct cpuid_result result; + unsigned int core_ids, apic_ids, threads; + + apic_ids = 1; + if (cpuid_eax(0) >= 1) + apic_ids = (cpuid_ebx(1) >> 16) & 0xff; + if (apic_ids == 0) + apic_ids = 1; + + core_ids = 1; + if (cpuid_eax(0) >= 4) { + result = cpuid_ext(4, 0); + core_ids += (result.eax >> 26) & 0x3f; + } + + threads = (apic_ids / core_ids); + + sp->apic_core_id_mask = 1UL << log2_ceil(core_ids); + sp->apic_core_id_mask <<= log2_ceil(threads); + } else { + sp->apic_core_id_mask = 0; + } + memset(sp->hyperthreading_lock, 0, sizeof(sp->hyperthreading_lock)); } #define NUM_FIXED_MTRRS 11 diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index ba1ecb7..abf0549 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -3,6 +3,7 @@ #include <cpu/x86/cr.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/msr.h> +#include <cpu/x86/lapic_def.h> #include <arch/ram_segs.h> /* The SIPI vector is responsible for initializing the APs in the system. It @@ -33,6 +34,12 @@ .long 0 ap_count: .long 0 +apic_core_id_mask: +.long 0 +hyperthreading_lock: +.space CONFIG_MAX_CPUS/2 +microcode_lock_ht: +.long 0 #define CR0_CLEAR_FLAGS_CACHE_ENABLE (CR0_CD | CR0_NW) #define CR0_SET_FLAGS (CR0_CLEAR_FLAGS_CACHE_ENABLE | CR0_PE) @@ -115,6 +122,35 @@ test %edx, %edx jnz microcode_done + /* Determine if Hyper-Threading semaphore should be used */ + cmpl $0, microcode_lock_ht + je load_microcode + + /* Get this CPU's LAPIC ID */ + movl $(LOCAL_APIC_ADDR | LAPIC_ID), %esi + movl (%esi), %ecx + shr $24, %ecx + + movl apic_core_id_mask, %eax + andl %eax, %ecx +1: + bt $0, %eax + jc 1f + shr $1, %eax + shr $1, %ecx + jmp 1b +1: + /* ecx now contains the core ID */ + movl $(hyperthreading_lock), %ebx + shl $2, %ecx + addl %ecx, %ebx + +lock_ht_semaphore: + /* Lock the core specific semaphore */ + lock bts $0, (%ebx) + jc lock_ht_semaphore + jmp load_microcode + /* Determine if parallel microcode loading is allowed. */ cmpl $0xffffffff, microcode_lock je load_microcode @@ -136,6 +172,15 @@ wrmsr popa + /* Determine if Hyper-Threading semaphore should be used */ + cmpl $0, microcode_lock_ht + jne 1f + + xor %eax, %eax + mov %eax, (%ebx) + je microcode_done + +1: /* Unconditionally unlock microcode loading. */ cmpl $0xffffffff, microcode_lock je microcode_done -- To view, visit https://review.coreboot.org/c/coreboot/+/44904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89a01f6ff94e7d35f1feded3ddb0c43caf7c6c5d Gerrit-Change-Number: 44904 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 15

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2020