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Change in coreboot[master]: mb/samsung/stumpy: Do not overwrite pei_data
by Angel Pons (Code Review) 08 Feb '21

08 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43035 ) Change subject: mb/samsung/stumpy: Do not overwrite pei_data ...................................................................... mb/samsung/stumpy: Do not overwrite pei_data Most of the values are already set in northbridge code. Change-Id: I59864d93d0da121a9cf1f354b563e083b000207d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/samsung/stumpy/early_init.c 1 file changed, 19 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/43035/1 diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index f079482..db9a65a 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -99,50 +99,26 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xa0, 0x00,0xa4,0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1333, - .usb_port_config = { - { 1, 0, 0x0080 }, /* P0: Front port (OC0) */ - { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ - { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ - { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ - { 1, 2, 0x0080 }, /* P4: Front port (OC2) */ - { 0, 0, 0x0000 }, /* P5: Empty */ - { 0, 0, 0x0000 }, /* P6: Empty */ - { 0, 0, 0x0000 }, /* P7: Empty */ - { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ - { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ - { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */ - { 0, 4, 0x0000 }, /* P11: Empty */ - { 1, 6, 0x0040 }, /* P12: Back port (OC6) */ - { 1, 5, 0x0040 }, /* P13: Back port (OC5) */ - }, + pei_data->system_type = 0; /* 0 Mobile, 1 Desktop/Server */ + pei_data->spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }; + pei_data->max_ddr3_freq = 1333; + + pei_data->usb_port_config = { + { 1, 0, 0x0080 }, /* P0: Front port (OC0) */ + { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ + { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ + { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ + { 1, 2, 0x0080 }, /* P4: Front port (OC2) */ + { 0, 0, 0x0000 }, /* P5: Empty */ + { 0, 0, 0x0000 }, /* P6: Empty */ + { 0, 0, 0x0000 }, /* P7: Empty */ + { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ + { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ + { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */ + { 0, 4, 0x0000 }, /* P11: Empty */ + { 1, 6, 0x0040 }, /* P12: Back port (OC6) */ + { 1, 5, 0x0040 }, /* P13: Back port (OC5) */ }; - *pei_data = pei_data_template; } void mainboard_get_spd(spd_raw_data *spd, bool id_only) -- To view, visit https://review.coreboot.org/c/coreboot/+/43035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59864d93d0da121a9cf1f354b563e083b000207d Gerrit-Change-Number: 43035 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/emeraldlake2: Do not overwrite pei_data
by Angel Pons (Code Review) 08 Feb '21

08 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43034 ) Change subject: mb/intel/emeraldlake2: Do not overwrite pei_data ...................................................................... mb/intel/emeraldlake2: Do not overwrite pei_data Most of the values are already set in northbridge code. Change-Id: Id36bcb41b2f8c2efc91f91ba40ac23541ee804d9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/emeraldlake2/early_init.c 1 file changed, 19 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/43034/1 diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index 119346e..38e6ffc 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -49,50 +49,26 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb_port_config = { - { 1, 0, 0x0040 }, /* P0: Front port (OC0) */ - { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ - { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ - { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ - { 1, 2, 0x0040 }, /* P4: Front port (OC2) */ - { 0, 0, 0x0000 }, /* P5: Empty */ - { 0, 0, 0x0000 }, /* P6: Empty */ - { 0, 0, 0x0000 }, /* P7: Empty */ - { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ - { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ - { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */ - { 0, 4, 0x0000 }, /* P11: Empty */ - { 1, 6, 0x0040 }, /* P12: Back port (OC6) */ - { 1, 5, 0x0040 }, /* P13: Back port (OC5) */ - }, + pei_data->system_type = 0; /* 0 Mobile, 1 Desktop/Server */ + pei_data->spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }; + pei_data->max_ddr3_freq = 1600; + + pei_data->usb_port_config = { + { 1, 0, 0x0040 }, /* P0: Front port (OC0) */ + { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ + { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ + { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ + { 1, 2, 0x0040 }, /* P4: Front port (OC2) */ + { 0, 0, 0x0000 }, /* P5: Empty */ + { 0, 0, 0x0000 }, /* P6: Empty */ + { 0, 0, 0x0000 }, /* P7: Empty */ + { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ + { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ + { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */ + { 0, 4, 0x0000 }, /* P11: Empty */ + { 1, 6, 0x0040 }, /* P12: Back port (OC6) */ + { 1, 5, 0x0040 }, /* P13: Back port (OC5) */ }; - *pei_data = pei_data_template; } const struct southbridge_usb_port mainboard_usb_ports[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/43034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id36bcb41b2f8c2efc91f91ba40ac23541ee804d9 Gerrit-Change-Number: 43034 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/dcp847ske: Do not overwrite pei_data
by Angel Pons (Code Review) 08 Feb '21

08 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43033 ) Change subject: mb/intel/dcp847ske: Do not overwrite pei_data ...................................................................... mb/intel/dcp847ske: Do not overwrite pei_data Most of the values are already set in northbridge code. Change-Id: Ib865eee601fef52b5bed9c31bcf2404d161445f2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/dcp847ske/romstage.c 1 file changed, 5 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43033/1 diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index e81b4b6..72c869d 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -12,39 +12,14 @@ #if !CONFIG(USE_NATIVE_RAMINIT) void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xa0, 0x00, 0xa2, 0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 0, - .gbe_enable = 1, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1333, - .usb_port_config = { + pei_data->system_type = 0; /* 0 Mobile, 1 Desktop/Server */ + pei_data->spd_addresses = { 0xa0, 0x00, 0xa2, 0x00 }; + pei_data->max_ddr3_freq = 1333; + + pei_data->usb_port_config = { #define USB_CONFIG(enabled, current, ocpin) { enabled, ocpin, 0x040 * current } #include "usb.h" - }, }; - *pei_data = pei_data_template; } int mainboard_should_reset_usb(int s3resume) -- To view, visit https://review.coreboot.org/c/coreboot/+/43033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib865eee601fef52b5bed9c31bcf2404d161445f2 Gerrit-Change-Number: 43033 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/x220: Do not overwrite pei_data
by Angel Pons (Code Review) 08 Feb '21

08 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43032 ) Change subject: mb/lenovo/x220: Do not overwrite pei_data ...................................................................... mb/lenovo/x220: Do not overwrite pei_data Most of the values are already set in northbridge code. Change-Id: Iab4d255f09095fd6fa92c0468a266ff01790fe7c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/lenovo/x220/early_init.c 1 file changed, 20 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/43032/1 diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index 5f0ad45..17c910b 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -11,51 +11,27 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xa0, 0x00,0xa2,0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .gbe_enable = 1, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1333, - .usb_port_config = { - { 1, 0, 0x0040 }, - { 1, 1, 0x0080 }, - { 1, 3, 0x0080 }, - { 1, 3, 0x0080 }, - { 1, 0, 0x0080 }, - { 1, 0, 0x0080 }, - { 1, 2, 0x0040 }, - { 1, 2, 0x0040 }, - { 1, 6, 0x0080 }, - { 1, 5, 0x0080 }, - { 1, 6, 0x0080 }, - { 1, 6, 0x0080 }, - { 1, 7, 0x0080 }, - { 1, 6, 0x0080 }, - }, + pei_data->system_type = 0; /* 0 Mobile, 1 Desktop/Server */ + pei_data->ec_present = 1; + pei_data->spd_addresses = { 0xa0, 0x00, 0xa2, 0x00 }; + pei_data->max_ddr3_freq = 1333; + + pei_data->usb_port_config = { + { 1, 0, 0x0040 }, + { 1, 1, 0x0080 }, + { 1, 3, 0x0080 }, + { 1, 3, 0x0080 }, + { 1, 0, 0x0080 }, + { 1, 0, 0x0080 }, + { 1, 2, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 6, 0x0080 }, + { 1, 5, 0x0080 }, + { 1, 6, 0x0080 }, + { 1, 6, 0x0080 }, + { 1, 7, 0x0080 }, + { 1, 6, 0x0080 }, }; - *pei_data = pei_data_template; } void mainboard_get_spd(spd_raw_data *spd, bool id_only) -- To view, visit https://review.coreboot.org/c/coreboot/+/43032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab4d255f09095fd6fa92c0468a266ff01790fe7c Gerrit-Change-Number: 43032 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/roda/rv11: Do not overwrite pei_data
by Angel Pons (Code Review) 08 Feb '21

08 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43031 ) Change subject: mb/roda/rv11: Do not overwrite pei_data ...................................................................... mb/roda/rv11: Do not overwrite pei_data Most of the values are already set in northbridge code. Change-Id: I5b8986fdaddbd04ee02b71dc6120d00573a5279e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/roda/rv11/variants/rv11/early_init.c M src/mainboard/roda/rv11/variants/rw11/early_init.c 2 files changed, 56 insertions(+), 106 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/43031/1 diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c index ada4b9f..c733d48 100644 --- a/src/mainboard/roda/rv11/variants/rv11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c @@ -8,60 +8,35 @@ void mainboard_fill_pei_data(struct pei_data *const pei_data) { - const struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .gbe_enable = 1, - .ddr3lv_support = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* Enabled / OC PIN / Length */ - { 1, 0, 0x0040 }, /* P00: 1st USB3 (OC #0) */ - { 1, 4, 0x0040 }, /* P01: 2nd USB3 (OC #4) */ - { 1, 1, 0x0080 }, /* P02: 1st Multibay USB3 (OC #1) */ - { 1, 2, 0x0080 }, /* P03: 2nd Multibay USB3 (OC #2) */ - { 1, 8, 0x0040 }, /* P04: MiniPCIe 1 USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P05: MiniPCIe 2 USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P06: MiniPCIe 3 USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P07: GPS USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P08: MiniPCIe 4 USB2 (no OC) */ - { 1, 3, 0x0040 }, /* P09: Express Card USB2 (OC #3) */ - { 1, 8, 0x0040 }, /* P10: SD card reader USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P11: Sensors Hub? USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P12: Touch Screen USB2 (no OC) */ - { 1, 5, 0x0040 }, /* P13: reserved? USB2 (OC #5) */ - }, - .usb3 = { - .mode = 3, /* Smart Auto? */ - .hs_port_switch_mask = 0xf, /* All four ports. */ - .preboot_support = 1, /* preOS driver? */ - .xhci_streams = 1, /* Enable. */ - }, - .pcie_init = 1, + pei_data->system_type = 0; /* 0 Mobile, 1 Desktop/Server */ + pei_data->ec_present = 1; + pei_data->spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 }; + pei_data->max_ddr3_freq = 1600; + + pei_data->usb_port_config = { + /* Enabled / OC PIN / Length */ + { 1, 0, 0x0040 }, /* P00: 1st USB3 (OC #0) */ + { 1, 4, 0x0040 }, /* P01: 2nd USB3 (OC #4) */ + { 1, 1, 0x0080 }, /* P02: 1st Multibay USB3 (OC #1) */ + { 1, 2, 0x0080 }, /* P03: 2nd Multibay USB3 (OC #2) */ + { 1, 8, 0x0040 }, /* P04: MiniPCIe 1 USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P05: MiniPCIe 2 USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P06: MiniPCIe 3 USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P07: GPS USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P08: MiniPCIe 4 USB2 (no OC) */ + { 1, 3, 0x0040 }, /* P09: Express Card USB2 (OC #3) */ + { 1, 8, 0x0040 }, /* P10: SD card reader USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P11: Sensors Hub? USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P12: Touch Screen USB2 (no OC) */ + { 1, 5, 0x0040 }, /* P13: reserved? USB2 (OC #5) */ }; - *pei_data = pei_data_template; + + pei_data->usb3 = { + .mode = 3, /* Smart Auto? */ + .hs_port_switch_mask = 0xf, /* All four ports. */ + .preboot_support = 1, /* preOS driver? */ + .xhci_streams = 1, /* Enable. */ + }; } const struct southbridge_usb_port mainboard_usb_ports[] = { diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c index f56a5e4..eafd3b9 100644 --- a/src/mainboard/roda/rv11/variants/rw11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c @@ -38,60 +38,35 @@ void mainboard_fill_pei_data(struct pei_data *const pei_data) { - const struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0xA2, 0xA4, 0xA6 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .gbe_enable = 1, - .ddr3lv_support = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 0, - .dimm_channel1_disabled = 0, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* Enabled / OC PIN / Length */ - { 1, 0, 0x0080 }, /* P00: 1st (left) USB3 (OC #0) */ - { 1, 0, 0x0080 }, /* P01: 2nd (left) USB3 (OC #0) */ - { 1, 1, 0x0080 }, /* P02: 1st Multibay USB3 (OC #1) */ - { 1, 1, 0x0080 }, /* P03: 2nd Multibay USB3 (OC #1) */ - { 1, 8, 0x0040 }, /* P04: MiniPCIe 1 USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P05: MiniPCIe 2 USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P06: USB Hub x4 USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P07: MiniPCIe 4 USB2 (no OC) */ - { 1, 8, 0x0080 }, /* P08: SD card reader USB2 (no OC) */ - { 1, 4, 0x0080 }, /* P09: 3rd (right) USB2 (OC #4) */ - { 1, 5, 0x0040 }, /* P10: 4th (right) USB2 (OC #5) */ - { 1, 8, 0x0040 }, /* P11: 3rd Multibay USB2 (no OC) */ - { 1, 8, 0x0080 }, /* P12: misc internal USB2 (no OC) */ - { 1, 6, 0x0080 }, /* P13: misc internal USB2 (OC #6) */ - }, - .usb3 = { - .mode = 3, /* Smart Auto? */ - .hs_port_switch_mask = 0xf, /* All four ports. */ - .preboot_support = 1, /* preOS driver? */ - .xhci_streams = 1, /* Enable. */ - }, - .pcie_init = 1, + pei_data->system_type = 0; /* 0 Mobile, 1 Desktop/Server */ + pei_data->ec_present = 1; + pei_data->spd_addresses = { 0xA0, 0xA2, 0xA4, 0xA6 }; + pei_data->max_ddr3_freq = 1600; + + pei_data->usb_port_config = { + /* Enabled / OC PIN / Length */ + { 1, 0, 0x0080 }, /* P00: 1st (left) USB3 (OC #0) */ + { 1, 0, 0x0080 }, /* P01: 2nd (left) USB3 (OC #0) */ + { 1, 1, 0x0080 }, /* P02: 1st Multibay USB3 (OC #1) */ + { 1, 1, 0x0080 }, /* P03: 2nd Multibay USB3 (OC #1) */ + { 1, 8, 0x0040 }, /* P04: MiniPCIe 1 USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P05: MiniPCIe 2 USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P06: USB Hub x4 USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P07: MiniPCIe 4 USB2 (no OC) */ + { 1, 8, 0x0080 }, /* P08: SD card reader USB2 (no OC) */ + { 1, 4, 0x0080 }, /* P09: 3rd (right) USB2 (OC #4) */ + { 1, 5, 0x0040 }, /* P10: 4th (right) USB2 (OC #5) */ + { 1, 8, 0x0040 }, /* P11: 3rd Multibay USB2 (no OC) */ + { 1, 8, 0x0080 }, /* P12: misc internal USB2 (no OC) */ + { 1, 6, 0x0080 }, /* P13: misc internal USB2 (OC #6) */ }; - *pei_data = pei_data_template; + + pei_data->usb3 = { + .mode = 3, /* Smart Auto? */ + .hs_port_switch_mask = 0xf, /* All four ports. */ + .preboot_support = 1, /* preOS driver? */ + .xhci_streams = 1, /* Enable. */ + }; } const struct southbridge_usb_port mainboard_usb_ports[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/43031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b8986fdaddbd04ee02b71dc6120d00573a5279e Gerrit-Change-Number: 43031 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/p8z77-m_pro: Do not overwrite pei_data
by Angel Pons (Code Review) 08 Feb '21

08 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43030 ) Change subject: mb/asus/p8z77-m_pro: Do not overwrite pei_data ...................................................................... mb/asus/p8z77-m_pro: Do not overwrite pei_data Most of the values are already set in northbridge code. Change-Id: I2490d63584205ff3f17ce29d7358214f3baaa09b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asus/p8z77-m_pro/early_init.c 1 file changed, 43 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/43030/1 diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index 87da010..e703e5b 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -83,79 +83,49 @@ get_option(&usb3_streams, "usb3_streams"); usb3_streams &= 0x1; /* ensure it's 0/1 only */ - struct pei_data pd = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 1, /* 0=Mobile, 1=Desktop/Server */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */ - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 0, /* Asus 2203 BIOS shows XUECA016, but no EC */ - .gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */ - .dimm_channel0_disabled = 0, /* Both DIMM enabled */ - .dimm_channel1_disabled = 0, /* Both DIMM enabled */ - .max_ddr3_freq = 1600, /* 1333=Sandy; 1600=Ivy */ - .usb_port_config = { - /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */ - { 1, 0, 0x0080 }, /* USB3 front internal header */ - { 1, 0, 0x0080 }, /* USB3 front internal header */ - { 1, 1, 0x0080 }, /* USB3 ETH top connector */ - { 1, 1, 0x0080 }, /* USB3 ETH botton connector */ - { 1, 2, 0x0080 }, /* USB2 PS2 top connector */ - { 1, 2, 0x0080 }, /* USB2 PS2 botton connector */ - { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ - { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ - { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ - { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ - { 1, 6, 0x0080 }, /* USB2 internal header (USB1112) */ - { 1, 5, 0x0080 }, /* USB2 internal header (USB1112) */ - { 0, 5, 0x0080 }, /* Unused. Asus DEBUG_PORT ??? */ - { 0, 6, 0x0080 } /* Unused. Asus DEBUG_PORT ??? */ - }, - .usb3 = { - /* 0=Disable; 1=Enable (start at USB3 speed) - * 2=Auto (start as USB2 speed until OS loads) - * 3=Smart Auto (like Auto but keep speed on reboot) - */ - usb3_mode, - /* 4 bit switch mask. 0=not switchable, 1=switchable - * Means once it's loaded the OS, it can swap ports - * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf - */ - 0xf, - usb3_drv, /* 1=Load xHCI pre-OS drv */ - /* 0=Don't use xHCI streams for better compatibility - * 1=use xHCI streams for better speed - */ - usb3_streams - }, - /* ASUS P8Z77-M PRO manual says 1.35v DIMMs are supported */ - .ddr3lv_support = 1, - /* PCIe 3.0 support. As we use Ivy Bridge, let's enable it, - * but might cause some system instability ! - */ - .pcie_init = 1, - /* Command Rate. 0=Auto; 1=1N; 2=2N. - * Leave it always at Auto for compatibility & stability - */ - .nmode = 0, - /* DDR refresh rate. 0=Auto based on DRAM's temperature; - * 1=Normal rate for speed; 2=Double rate for stability - */ - .ddr_refresh_rate_config = 0 + pei_data->system_type = 1; /* 0 Mobile, 1 Desktop/Server */ + pei_data->spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }; /* SMBus mul 2 */ + pei_data->max_ddr3_freq = 1600; + + /* ASUS P8Z77-M PRO manual says 1.35v DIMMs are supported */ + pei_data->ddr3lv_support = 1; + + pei_data->usb_port_config = { + /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */ + { 1, 0, 0x0080 }, /* USB3 front internal header */ + { 1, 0, 0x0080 }, /* USB3 front internal header */ + { 1, 1, 0x0080 }, /* USB3 ETH top connector */ + { 1, 1, 0x0080 }, /* USB3 ETH botton connector */ + { 1, 2, 0x0080 }, /* USB2 PS2 top connector */ + { 1, 2, 0x0080 }, /* USB2 PS2 botton connector */ + { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ + { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ + { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ + { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ + { 1, 6, 0x0080 }, /* USB2 internal header (USB1112) */ + { 1, 5, 0x0080 }, /* USB2 internal header (USB1112) */ + { 0, 5, 0x0080 }, /* Unused. Asus DEBUG_PORT ??? */ + { 0, 6, 0x0080 } /* Unused. Asus DEBUG_PORT ??? */ }; - /* copy the data to output PEI */ - *pei_data = pd; + pei_data->usb3 = { + /* + * 0=Disable; 1=Enable (start at USB3 speed) + * 2=Auto (start as USB2 speed until OS loads) + * 3=Smart Auto (like Auto but keep speed on reboot) + */ + usb3_mode, + /* + * 4 bit switch mask. 0=not switchable, 1=switchable + * Means once it's loaded the OS, it can swap ports + * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf + */ + 0xf, + usb3_drv, /* 1=Load xHCI pre-OS drv */ + /* + * 0=Don't use xHCI streams for better compatibility + * 1=use xHCI streams for better speed + */ + usb3_streams + }; } -- To view, visit https://review.coreboot.org/c/coreboot/+/43030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2490d63584205ff3f17ce29d7358214f3baaa09b Gerrit-Change-Number: 43030 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: mb/google/link: Do not overwrite pei_data
by Angel Pons (Code Review) 08 Feb '21

08 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43029 ) Change subject: mb/google/link: Do not overwrite pei_data ...................................................................... mb/google/link: Do not overwrite pei_data Most of the values are already set in northbridge code. Change-Id: I90af4afa2fcd103c23acb3a53d657aadc82c0703 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/link/early_init.c 1 file changed, 25 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/43029/1 diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index 8360f2a..4ab9438 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -84,58 +84,34 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .ddr3lv_support = 1, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* Empty and onboard Ports 0-7, set to un-used pin OC3 */ - { 0, 3, 0x0000 }, /* P0: Empty */ - { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */ - { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */ - { 1, 3, 0x0040 }, /* P3: SDCARD (no OC) */ - { 0, 3, 0x0000 }, /* P4: Empty */ - { 1, 3, 0x0040 }, /* P5: WWAN (no OC) */ - { 0, 3, 0x0000 }, /* P6: Empty */ - { 0, 3, 0x0000 }, /* P7: Empty */ - /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ - { 1, 4, 0x0040 }, /* P8: Camera (no OC) */ - { 1, 4, 0x0040 }, /* P9: Bluetooth (no OC) */ - { 0, 4, 0x0000 }, /* P10: Empty */ - { 0, 4, 0x0000 }, /* P11: Empty */ - { 0, 4, 0x0000 }, /* P12: Empty */ - { 0, 4, 0x0000 }, /* P13: Empty */ - }, + pei_data->system_type = 0; /* 0 Mobile, 1 Desktop/Server */ + pei_data->ec_present = 1; + pei_data->ddr3lv_support = 1; + pei_data->max_ddr3_freq = 1600; + + pei_data->usb_port_config = { + /* Empty and onboard Ports 0-7, set to un-used pin OC3 */ + { 0, 3, 0x0000 }, /* P0: Empty */ + { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */ + { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */ + { 1, 3, 0x0040 }, /* P3: SDCARD (no OC) */ + { 0, 3, 0x0000 }, /* P4: Empty */ + { 1, 3, 0x0040 }, /* P5: WWAN (no OC) */ + { 0, 3, 0x0000 }, /* P6: Empty */ + { 0, 3, 0x0000 }, /* P7: Empty */ + /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ + { 1, 4, 0x0040 }, /* P8: Camera (no OC) */ + { 1, 4, 0x0040 }, /* P9: Bluetooth (no OC) */ + { 0, 4, 0x0000 }, /* P10: Empty */ + { 0, 4, 0x0000 }, /* P11: Empty */ + { 0, 4, 0x0000 }, /* P12: Empty */ + { 0, 4, 0x0000 }, /* P13: Empty */ }; - *pei_data = pei_data_template; + /* LINK has 2 channels of memory down, so spd_data[0] and [2] both need to be populated */ - memcpy(pei_data->spd_data[0], locate_spd(), - sizeof(pei_data->spd_data[0])); - memcpy(pei_data->spd_data[2], pei_data->spd_data[0], - sizeof(pei_data->spd_data[0])); + memcpy(pei_data->spd_data[0], locate_spd(), sizeof(pei_data->spd_data[0])); + memcpy(pei_data->spd_data[2], pei_data->spd_data[0], sizeof(pei_data->spd_data[0])); } const struct southbridge_usb_port mainboard_usb_ports[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/43029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90af4afa2fcd103c23acb3a53d657aadc82c0703 Gerrit-Change-Number: 43029 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/stout: Do not overwrite pei_data
by Angel Pons (Code Review) 08 Feb '21

08 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43028 ) Change subject: mb/google/stout: Do not overwrite pei_data ...................................................................... mb/google/stout: Do not overwrite pei_data Most of the values are already set in northbridge code. Change-Id: Ic3c8d23958cb821b8c551415ebb95e934de43e0b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/stout/early_init.c 1 file changed, 28 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/43028/1 diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index e71d0ee..b9801f2 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -89,57 +89,35 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* enabled USB oc pin length */ - { 1, 0, 0x0040 }, /* P0: USB 3.0 1 (OC0) */ - { 1, 0, 0x0040 }, /* P1: USB 3.0 2 (OC0) */ - { 0, 1, 0x0000 }, /* P2: Empty */ - { 1, 1, 0x0040 }, /* P3: Camera (no OC) */ - { 1, 1, 0x0040 }, /* P4: WLAN (no OC) */ - { 1, 1, 0x0040 }, /* P5: WWAN (no OC) */ - { 0, 1, 0x0000 }, /* P6: Empty */ - { 0, 1, 0x0000 }, /* P7: Empty */ - { 0, 5, 0x0000 }, /* P8: Empty */ - { 1, 4, 0x0040 }, /* P9: USB 2.0 (AUO4) (OC4) */ - { 0, 5, 0x0000 }, /* P10: Empty */ - { 0, 5, 0x0000 }, /* P11: Empty */ - { 0, 5, 0x0000 }, /* P12: Empty */ - { 1, 5, 0x0040 }, /* P13: Bluetooth (no OC) */ - }, - .usb3 = { - .mode = XHCI_MODE, - .hs_port_switch_mask = XHCI_PORTS, - .preboot_support = XHCI_PREBOOT, - .xhci_streams = XHCI_STREAMS, - }, + pei_data->system_type = 0; /* 0 Mobile, 1 Desktop/Server */ + pei_data->ec_present = 1; + pei_data->spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 }; + pei_data->max_ddr3_freq = 1600; + + pei_data->usb_port_config = { + /* enabled USB oc pin length */ + { 1, 0, 0x0040 }, /* P0: USB 3.0 1 (OC0) */ + { 1, 0, 0x0040 }, /* P1: USB 3.0 2 (OC0) */ + { 0, 1, 0x0000 }, /* P2: Empty */ + { 1, 1, 0x0040 }, /* P3: Camera (no OC) */ + { 1, 1, 0x0040 }, /* P4: WLAN (no OC) */ + { 1, 1, 0x0040 }, /* P5: WWAN (no OC) */ + { 0, 1, 0x0000 }, /* P6: Empty */ + { 0, 1, 0x0000 }, /* P7: Empty */ + { 0, 5, 0x0000 }, /* P8: Empty */ + { 1, 4, 0x0040 }, /* P9: USB 2.0 (AUO4) (OC4) */ + { 0, 5, 0x0000 }, /* P10: Empty */ + { 0, 5, 0x0000 }, /* P11: Empty */ + { 0, 5, 0x0000 }, /* P12: Empty */ + { 1, 5, 0x0040 }, /* P13: Bluetooth (no OC) */ }; - *pei_data = pei_data_template; + + pei_data->usb3 = { + .mode = XHCI_MODE, + .hs_port_switch_mask = XHCI_PORTS, + .preboot_support = XHCI_PREBOOT, + .xhci_streams = XHCI_STREAMS, + }; } void mainboard_early_init(int s3resume) -- To view, visit https://review.coreboot.org/c/coreboot/+/43028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3c8d23958cb821b8c551415ebb95e934de43e0b Gerrit-Change-Number: 43028 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/parrot: Do not overwrite pei_data
by Angel Pons (Code Review) 08 Feb '21

08 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43027 ) Change subject: mb/google/parrot: Do not overwrite pei_data ...................................................................... mb/google/parrot: Do not overwrite pei_data Most of the values are already set in northbridge code. Change-Id: Ibad49251b88107d5fed6283d8e2ddd90927358d8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/parrot/early_init.c 1 file changed, 22 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/43027/1 diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index 3c5c363..1552550 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -52,52 +52,29 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* Empty and onboard Ports 0-7, set to un-used pin OC3 */ - { 0, 3, 0x0000 }, /* P0: Empty */ - { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */ - { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */ - { 1, 1, 0x0040 }, /* P3: Left USB 3 (OC1) */ - { 0, 3, 0x0000 }, /* P4: Empty */ - { 0, 3, 0x0000 }, /* P5: Empty */ - { 0, 3, 0x0000 }, /* P6: Empty */ - { 0, 3, 0x0000 }, /* P7: Empty */ - /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ - { 1, 4, 0x0040 }, /* P8: MiniPCIe (WLAN) (no OC) */ - { 0, 4, 0x0000 }, /* P9: Empty */ - { 1, 4, 0x0040 }, /* P10: Camera (no OC) */ - { 0, 4, 0x0000 }, /* P11: Empty */ - { 0, 4, 0x0000 }, /* P12: Empty */ - { 0, 4, 0x0000 }, /* P13: Empty */ - }, + pei_data->system_type = 0; /* 0 Mobile, 1 Desktop/Server */ + pei_data->ec_present = 1; + pei_data->spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 }; + pei_data->max_ddr3_freq = 1600; + + pei_data->usb_port_config = { + /* Empty and onboard Ports 0-7, set to un-used pin OC3 */ + { 0, 3, 0x0000 }, /* P0: Empty */ + { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */ + { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */ + { 1, 1, 0x0040 }, /* P3: Left USB 3 (OC1) */ + { 0, 3, 0x0000 }, /* P4: Empty */ + { 0, 3, 0x0000 }, /* P5: Empty */ + { 0, 3, 0x0000 }, /* P6: Empty */ + { 0, 3, 0x0000 }, /* P7: Empty */ + /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ + { 1, 4, 0x0040 }, /* P8: MiniPCIe (WLAN) (no OC) */ + { 0, 4, 0x0000 }, /* P9: Empty */ + { 1, 4, 0x0040 }, /* P10: Camera (no OC) */ + { 0, 4, 0x0000 }, /* P11: Empty */ + { 0, 4, 0x0000 }, /* P12: Empty */ + { 0, 4, 0x0000 }, /* P13: Empty */ }; - *pei_data = pei_data_template; } const struct southbridge_usb_port mainboard_usb_ports[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/43027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibad49251b88107d5fed6283d8e2ddd90927358d8 Gerrit-Change-Number: 43027 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/butterfly: Do not overwrite pei_data
by Angel Pons (Code Review) 08 Feb '21

08 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43026 ) Change subject: mb/google/butterfly: Do not overwrite pei_data ...................................................................... mb/google/butterfly: Do not overwrite pei_data Most of the values are already set in northbridge code. Change-Id: I6a50c1f38bc412bbb259c6de9fbc1801e9c14519 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/butterfly/early_init.c 1 file changed, 22 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/43026/1 diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index df51f66..04dd37b 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -77,53 +77,29 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .ddr3lv_support = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* enabled USB oc pin length */ - { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ - { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ - { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ - { 0, 0, 0x0000 }, /* P3: Empty */ - { 0, 0, 0x0000 }, /* P4: Empty */ - { 0, 0, 0x0000 }, /* P5: Empty */ - { 0, 0, 0x0000 }, /* P6: Empty */ - { 0, 0, 0x0000 }, /* P7: Empty */ - { 0, 4, 0x0000 }, /* P8: Empty */ - { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */ - { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ - { 0, 4, 0x0000 }, /* P11: Empty */ - { 0, 4, 0x0000 }, /* P12: Empty */ - { 0, 4, 0x0000 }, /* P13: Empty */ - }, - .ddr_refresh_rate_config = 2, /* Force double refresh rate */ + pei_data->system_type = 0; /* 0 Mobile, 1 Desktop/Server */ + pei_data->ec_present = 1; + pei_data->spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 }; + pei_data->max_ddr3_freq = 1600; + pei_data->ddr_refresh_rate_config = 2; /* Force double refresh rate */ + + pei_data->usb_port_config = { + /* enabled USB oc pin length */ + { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ + { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ + { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ + { 0, 0, 0x0000 }, /* P3: Empty */ + { 0, 0, 0x0000 }, /* P4: Empty */ + { 0, 0, 0x0000 }, /* P5: Empty */ + { 0, 0, 0x0000 }, /* P6: Empty */ + { 0, 0, 0x0000 }, /* P7: Empty */ + { 0, 4, 0x0000 }, /* P8: Empty */ + { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */ + { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ + { 0, 4, 0x0000 }, /* P11: Empty */ + { 0, 4, 0x0000 }, /* P12: Empty */ + { 0, 4, 0x0000 }, /* P13: Empty */ }; - *pei_data = pei_data_template; } int mainboard_should_reset_usb(int s3resume) -- To view, visit https://review.coreboot.org/c/coreboot/+/43026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a50c1f38bc412bbb259c6de9fbc1801e9c14519 Gerrit-Change-Number: 43026 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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