coreboot-gerrit September 2020

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Change in coreboot[master]: sb/amd/cimx/sb800/acpi: Convert 'smbus.asl' to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 10 Feb '21

10 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45875 ) Change subject: sb/amd/cimx/sb800/acpi: Convert 'smbus.asl' to ASL 2.0 syntax ...................................................................... sb/amd/cimx/sb800/acpi: Convert 'smbus.asl' to ASL 2.0 syntax Also, fix typo on "success". Change-Id: I6fd7056d8053f0097b5c9de6b4e2e6db38910a2e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/cimx/sb800/acpi/smbus.asl 1 file changed, 31 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/45875/1 diff --git a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl index a676893..b99da33 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl @@ -19,37 +19,37 @@ } Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ - Store (0x1E, HSTS) - Store (0xFA, Local0) - While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) { + HSTS = 0x1E + Local0 = 0xFA + While ((HSTS & 0x1E) != Zero) && (Local0 > 0)) { Stall (0x64) - Decrement (Local0) + Local0-- } Return (Local0) } Method (SWTC, 1, NotSerialized) { - Store (Arg0, Local0) - Store (0x07, Local2) - Store (One, Local1) - While (LEqual (Local1, One)) { - Store (And (HSTS, 0x1E), Local3) - If (LNotEqual (Local3, Zero)) { /* read sucess */ - If (LEqual (Local3, 0x02)) { - Store (Zero, Local2) + Local0 = Arg0 + Local2 = 0x07 + Local1 = 1 + While (Local1 == 1) { + Local3 = HSTS & 0x1E + If (Local3 != 0) { /* read success */ + If (Local3 != 0x02) { + Local2 = 0 } - Store (Zero, Local1) + Local1 = 0 } Else { - If (LLess (Local0, 0x0A)) { /* read failure */ - Store (0x10, Local2) - Store (Zero, Local1) + If (Local0 < 0x0A) { /* read failure */ + Local2 = 0x10 + Local1 = 0 } Else { Sleep (0x0A) /* 10 ms, try again */ - Subtract (Local0, 0x0A, Local0) + Local0 -= 0x0A } } } @@ -58,29 +58,29 @@ } Method (SMBR, 3, NotSerialized) { - Store (0x07, Local0) - If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) { - Store (WCLR (), Local0) /* clear SMBUS status register before read data */ - If (LEqual (Local0, Zero)) { + Local0 = 0x07 + If (Acquire (SBX0, 0xFFFF) == 0) { + Local0 = WCLR () /* clear SMBUS status register before read data */ + If (Local0 == 0) { Release (SBX0) Return (0x0) } - Store (0x1F, HSTS) - Store (Or (ShiftLeft (Arg1, One), One), HADD) - Store (Arg2, HCMD) - If (LEqual (Arg0, 0x07)) { - Store (0x48, HCNT) /* read byte */ + HSTS = 0x1F + HADD = (Arg1 << 1) | 1 + HCMD = Arg2 + If (Arg0 == 0x07) { + HCNT = 0x48 /* read byte */ } - Store (SWTC (0x03E8), Local1) /* 1000 ms */ - If (LEqual (Local1, Zero)) { - If (LEqual (Arg0, 0x07)) { - Store (DAT0, Local0) + Local1 = SWTC (0x03E8) /* 1000 ms */ + If (Local1 == 0) { + If (Arg0 == 0x07) { + Local0 = DAT0 } } Else { - Store (Local1, Local0) + Local0 = Local1 } Release (SBX0) -- To view, visit https://review.coreboot.org/c/coreboot/+/45875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fd7056d8053f0097b5c9de6b4e2e6db38910a2e Gerrit-Change-Number: 45875 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: sb/amd/*/*/acpi/: Convert 'fch.asl' to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 10 Feb '21

10 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45862 ) Change subject: sb/amd/*/*/acpi/: Convert 'fch.asl' to ASL 2.0 syntax ...................................................................... sb/amd/*/*/acpi/: Convert 'fch.asl' to ASL 2.0 syntax Change-Id: Ie413f36ef11a42a23d7d265d7a66f5e0d088892e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/agesa/hudson/acpi/fch.asl M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/amd/pi/hudson/acpi/fch.asl 3 files changed, 44 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/45862/1 diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index 321796e..ac4abdc 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -7,14 +7,14 @@ Method(_OSC,4) { /* Check for proper PCI/PCIe UUID */ - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 ==ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) } Else { CreateDWordField(Arg3,0,CDW1) - Or(CDW1,4,CDW1) // Unrecognized UUID - Return(Arg3) + CDW1 |= 4 // Unrecognized UUID + Return (Arg3) } } @@ -125,9 +125,9 @@ * result as 64bit (0x100000000 - TOM1). */ Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + Local0 = 0x10000000 << 4 + Local0 -= TOM1 + MM1L = Local0 Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ @@ -170,21 +170,21 @@ Method(OSFL, 0){ - if (LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ + if (OSVR != Ones) {Return (OSVR)} /* OS version was already detected */ if (CondRefOf(\_OSI)) { - Store(1, OSVR) /* Assume some form of XP */ + OSVR = 1 /* Assume some form of XP */ if (\_OSI("Windows 2006")) /* Vista */ { - Store(2, OSVR) + OSVR = 2 } } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ + If (WCMP(\_OS,"Linux")) { + OSVR = 3 /* Linux */ } Else { - Store(4, OSVR) /* Gotta be WinCE */ + OSVR = 4 /* Gotta be WinCE */ } } - Return(OSVR) + Return (OSVR) } diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl index 0c0150d..1c7815d 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl @@ -7,27 +7,27 @@ Method(_OSC,4) { /* Check for proper PCI/PCIe UUID */ - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If(Arg0 ==ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) } Else { CreateDWordField(Arg3,0,CDW1) - Or(CDW1,4,CDW1) // Unrecognized UUID - Return(Arg3) + CDW1 |= 4 // Unrecognized UUID + Return (Arg3) } } Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) + Return (0) } Method(_STA, 0) { /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ + Return (0x0B) /* Status is visible */ } Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ + If (PMOD){ Return (APR0) } /* APIC mode */ Return (PR0) /* PIC Mode */ } /* end _PRT */ @@ -126,12 +126,12 @@ * 32bit (0x00000000 - TOM1) will wrap and give the same * result as 64bit (0x100000000 - TOM1). */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + MM1B = TOM1 + Local0 = 0x10000000 << 4 + Local0 -= TOM1 + MM1L = Local0 - Return(CRES) /* note to change the Name buffer */ + Return (CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ /* @@ -160,8 +160,8 @@ OSFL() /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + /*if (\SBRI <= 0x13) { + * \PWDE = 0 * } */ } /* End Method(_SB._INI) */ @@ -173,10 +173,10 @@ CMTI, 8, /* Client Management Data register */ G64E, 1, - G64O, 1, - G32O, 2, + G64O, 1, + G32O, 2, , 2, - GPSL, 2, + GPSL, 2, } /* GPM Port register */ diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl index 53095e0..ca9df72 100644 --- a/src/southbridge/amd/pi/hudson/acpi/fch.asl +++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl @@ -7,14 +7,14 @@ Method(_OSC,4) { /* Check for proper PCI/PCIe UUID */ - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) } Else { CreateDWordField(Arg3,0,CDW1) - Or(CDW1,4,CDW1) // Unrecognized UUID - Return(Arg3) + CDW1 |= 4 // Unrecognized UUID + Return (Arg3) } } @@ -107,12 +107,12 @@ * 32bit (0x00000000 - TOM1) will wrap and give the same * result as 64bit (0x100000000 - TOM1). */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + MM1B = TOM1 + Local0 = 0x10000000 << 4 + Local0 -= TOM1 + MM1L = Local0 - Return(CRES) /* note to change the Name buffer */ + Return (CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ #if CONFIG(HUDSON_IMC_FWM) @@ -156,21 +156,21 @@ Method(OSFL, 0){ - if (LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ + if (OSVR != Ones) {Return(OSVR)} /* OS version was already detected */ if (CondRefOf(\_OSI)) { - Store(1, OSVR) /* Assume some form of XP */ + OSVR = 1 /* Assume some form of XP */ if (\_OSI("Windows 2006")) /* Vista */ { - Store(2, OSVR) + OSVR = 2 } } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ + If (WCMP(\_OS,"Linux")) { + OSVR = 3 /* Linux */ } Else { - Store(4, OSVR) /* Gotta be WinCE */ + OSVR = 4 /* Gotta be WinCE */ } } - Return(OSVR) + Return (OSVR) } -- To view, visit https://review.coreboot.org/c/coreboot/+/45862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie413f36ef11a42a23d7d265d7a66f5e0d088892e Gerrit-Change-Number: 45862 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: src/cpu/x86/mtrr: Convert to 96 characters line length
by HAOUAS Elyes (Code Review) 10 Feb '21

10 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44309 ) Change subject: src/cpu/x86/mtrr: Convert to 96 characters line length ...................................................................... src/cpu/x86/mtrr: Convert to 96 characters line length Change-Id: I2525c2f3cbdd7b7137c3b60ad8a44ed6ebdb8909 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/x86/mtrr/debug.c 1 file changed, 12 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/44309/1 diff --git a/src/cpu/x86/mtrr/debug.c b/src/cpu/x86/mtrr/debug.c index 4ecae06..f7eb97e 100644 --- a/src/cpu/x86/mtrr/debug.c +++ b/src/cpu/x86/mtrr/debug.c @@ -18,8 +18,8 @@ } } -static void display_mtrr_fixed_types(uint64_t msr, - uint32_t starting_address, uint32_t memory_size) +static void display_mtrr_fixed_types(uint64_t msr, uint32_t starting_address, + uint32_t memory_size) { uint32_t base_address; uint32_t index; @@ -31,25 +31,21 @@ base_address = starting_address; next_address = base_address; for (index = 0; index < 64; index += 8) { - next_address = starting_address + (memory_size * - ((index >> 3) + 1)); + next_address = starting_address + (memory_size * ((index >> 3) + 1)); next_type = (msr >> index) & MTRR_DEF_TYPE_MASK; if (next_type != type) { printk(BIOS_DEBUG, " 0x%08x - 0x%08x: %s\n", - base_address, next_address - 1, - display_mtrr_type(type)); + base_address, next_address - 1, display_mtrr_type(type)); base_address = next_address; type = next_type; } } if (base_address != next_address) - printk(BIOS_DEBUG, " 0x%08x - 0x%08x: %s\n", - base_address, next_address - 1, + printk(BIOS_DEBUG, " 0x%08x - 0x%08x: %s\n", base_address, next_address - 1, display_mtrr_type(type)); } -static void display_4k_mtrr(uint32_t msr_reg, uint32_t starting_address, - const char *name) +static void display_4k_mtrr(uint32_t msr_reg, uint32_t starting_address, const char *name) { union { uint64_t u64; @@ -61,8 +57,7 @@ display_mtrr_fixed_types(msr.u64, starting_address, 0x1000); } -static void display_16k_mtrr(uint32_t msr_reg, uint32_t starting_address, - const char *name) +static void display_16k_mtrr(uint32_t msr_reg, uint32_t starting_address, const char *name) { union { uint64_t u64; @@ -91,8 +86,7 @@ msr_t msr; msr = rdmsr(MTRR_CAP_MSR); - printk(BIOS_DEBUG, - "0x%08x%08x: IA32_MTRRCAP: %s%s%s%s%u variable MTRRs\n", + printk(BIOS_DEBUG, "0x%08x%08x: IA32_MTRRCAP: %s%s%s%s%u variable MTRRs\n", msr.hi, msr.lo, (msr.lo & MTRR_CAP_PRMRR) ? "PRMRR, " : "", (msr.lo & MTRR_CAP_SMRR) ? "SMRR, " : "", @@ -113,8 +107,7 @@ msr.u64, (msr.u64 & MTRR_DEF_TYPE_EN) ? " E," : "", (msr.u64 & MTRR_DEF_TYPE_FIX_EN) ? " FE," : "", - display_mtrr_type((uint32_t)(msr.u64 & - MTRR_DEF_TYPE_MASK))); + display_mtrr_type((uint32_t)(msr.u64 & MTRR_DEF_TYPE_MASK))); } static void display_variable_mtrr(int index, uint64_t address_mask) @@ -137,19 +130,16 @@ if (msr_m.u64 & MTRR_PHYS_MASK_VALID) { base_address = (msr_a.u64 & 0xfffffffffffff000ULL) & address_mask; - printk(BIOS_DEBUG, - "0x%016llx: PHYBASE%d: Address = 0x%016llx, %s\n", + printk(BIOS_DEBUG, "0x%016llx: PHYBASE%d: Address = 0x%016llx, %s\n", msr_a.u64, index, base_address, display_mtrr_type(msr_a.u64 & MTRR_DEF_TYPE_MASK)); mask = (msr_m.u64 & 0xfffffffffffff000ULL) & address_mask; length = (~mask & address_mask) + 1; - printk(BIOS_DEBUG, - "0x%016llx: PHYMASK%d: Length = 0x%016llx, Valid\n", + printk(BIOS_DEBUG, "0x%016llx: PHYMASK%d: Length = 0x%016llx, Valid\n", msr_m.u64, index, length); } else { printk(BIOS_DEBUG, "0x%016llx: PHYBASE%d\n", msr_a.u64, index); - printk(BIOS_DEBUG, "0x%016llx: PHYMASK%d: Disabled\n", - msr_m.u64, index); + printk(BIOS_DEBUG, "0x%016llx: PHYMASK%d: Disabled\n", msr_m.u64, index); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/44309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2525c2f3cbdd7b7137c3b60ad8a44ed6ebdb8909 Gerrit-Change-Number: 44309 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: soc/amd/stoneyridge: Move some SMI utility functions
by Kyösti Mälkki (Code Review) 10 Feb '21

10 Feb '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42989 ) Change subject: soc/amd/stoneyridge: Move some SMI utility functions ...................................................................... soc/amd/stoneyridge: Move some SMI utility functions Change-Id: I4410772a8d3f2dedbb96601d87efb23b14e5f438 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/gpio.c D src/soc/amd/stoneyridge/smi.c M src/soc/amd/stoneyridge/smi_util.c M src/soc/amd/stoneyridge/smihandler.c 5 files changed, 22 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/42989/1 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 0d7b5d1..09320b2 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -64,7 +64,6 @@ ramstage-y += pmutil.c ramstage-y += sata.c ramstage-y += memmap.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c ramstage-y += usb.c diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index a595014..bd9d1b1 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -33,11 +33,6 @@ { GPIO_69, GEVENT_17 }, }; -void soc_route_sci(uint8_t event) -{ - smi_write8(SMI_SCI_MAP(event), event); -} - void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items) { *table = gpio_event_table; diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c deleted file mode 100644 index fb6d348..0000000 --- a/src/soc/amd/stoneyridge/smi.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * Utilities for SMM setup - */ - -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <amdblocks/acpimmio.h> -#include <soc/southbridge.h> -#include <soc/smi.h> - -/** Set the EOS bit and enable SMI generation from southbridge */ -void global_smi_enable(void) -{ - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); - reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ - reg |= SMITRG0_EOS; /* Set EOS bit */ - smi_write32(SMI_REG_SMITRIG0, reg); -} diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c index 2c5085b..b65bfc0 100644 --- a/src/soc/amd/stoneyridge/smi_util.c +++ b/src/soc/amd/stoneyridge/smi_util.c @@ -5,6 +5,7 @@ */ #include <console/console.h> +#include <cpu/x86/smm.h> #include <soc/southbridge.h> #include <soc/smi.h> #include <amdblocks/acpimmio.h> @@ -56,6 +57,27 @@ smi_write32(SMI_REG_SMITRIG0, reg32); } +/** Set the EOS bit and enable SMI generation from southbridge */ +void global_smi_enable(void) +{ + uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ + reg |= SMITRG0_EOS; /* Set EOS bit */ + smi_write32(SMI_REG_SMITRIG0, reg); +} + +void southbridge_smi_set_eos(void) +{ + uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + reg |= SMITRG0_EOS; + smi_write32(SMI_REG_SMITRIG0, reg); +} + +void soc_route_sci(uint8_t event) +{ + smi_write8(SMI_SCI_MAP(event), event); +} + /** * Configure generation of SCIs. */ diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index be55458..a36ab73 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -287,10 +287,3 @@ if (smi_src & SMI_STATUS_SRC_4) process_smi_sources(SMI_REG_SMISTS4); } - -void southbridge_smi_set_eos(void) -{ - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); - reg |= SMITRG0_EOS; - smi_write32(SMI_REG_SMITRIG0, reg); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/42989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4410772a8d3f2dedbb96601d87efb23b14e5f438 Gerrit-Change-Number: 42989 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: soc/amd/picasso: Move some SMI utility functions
by Kyösti Mälkki (Code Review) 10 Feb '21

10 Feb '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42988 ) Change subject: soc/amd/picasso: Move some SMI utility functions ...................................................................... soc/amd/picasso: Move some SMI utility functions Change-Id: Ic379723c0bf6e5edf5f3d63cc11b24d0e59b5075 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/gpio.c D src/soc/amd/picasso/smi.c M src/soc/amd/picasso/smi_util.c M src/soc/amd/picasso/smihandler.c 5 files changed, 22 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/42988/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 39269e9..9a72d60 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -61,7 +61,6 @@ ramstage-y += acp.c ramstage-y += sata.c ramstage-y += memmap.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-y += uart.c ramstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c diff --git a/src/soc/amd/picasso/gpio.c b/src/soc/amd/picasso/gpio.c index c402fb5..47c005e 100644 --- a/src/soc/amd/picasso/gpio.c +++ b/src/soc/amd/picasso/gpio.c @@ -33,11 +33,6 @@ { GPIO_129, GEVENT_17 }, }; -void soc_route_sci(uint8_t event) -{ - smi_write8(SMI_SCI_MAP(event), event); -} - void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items) { *table = gpio_event_table; diff --git a/src/soc/amd/picasso/smi.c b/src/soc/amd/picasso/smi.c deleted file mode 100644 index fb6d348..0000000 --- a/src/soc/amd/picasso/smi.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * Utilities for SMM setup - */ - -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <amdblocks/acpimmio.h> -#include <soc/southbridge.h> -#include <soc/smi.h> - -/** Set the EOS bit and enable SMI generation from southbridge */ -void global_smi_enable(void) -{ - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); - reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ - reg |= SMITRG0_EOS; /* Set EOS bit */ - smi_write32(SMI_REG_SMITRIG0, reg); -} diff --git a/src/soc/amd/picasso/smi_util.c b/src/soc/amd/picasso/smi_util.c index 2c5085b..b65bfc0 100644 --- a/src/soc/amd/picasso/smi_util.c +++ b/src/soc/amd/picasso/smi_util.c @@ -5,6 +5,7 @@ */ #include <console/console.h> +#include <cpu/x86/smm.h> #include <soc/southbridge.h> #include <soc/smi.h> #include <amdblocks/acpimmio.h> @@ -56,6 +57,27 @@ smi_write32(SMI_REG_SMITRIG0, reg32); } +/** Set the EOS bit and enable SMI generation from southbridge */ +void global_smi_enable(void) +{ + uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ + reg |= SMITRG0_EOS; /* Set EOS bit */ + smi_write32(SMI_REG_SMITRIG0, reg); +} + +void southbridge_smi_set_eos(void) +{ + uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + reg |= SMITRG0_EOS; + smi_write32(SMI_REG_SMITRIG0, reg); +} + +void soc_route_sci(uint8_t event) +{ + smi_write8(SMI_SCI_MAP(event), event); +} + /** * Configure generation of SCIs. */ diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 992dc2b..a9a2b2e 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -291,10 +291,3 @@ if (smi_src & SMI_STATUS_SRC_4) process_smi_sources(SMI_REG_SMISTS4); } - -void southbridge_smi_set_eos(void) -{ - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); - reg |= SMITRG0_EOS; - smi_write32(SMI_REG_SMITRIG0, reg); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/42988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic379723c0bf6e5edf5f3d63cc11b24d0e59b5075 Gerrit-Change-Number: 42988 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: soc/amd/picasso: Move APM_CNT_SMMINFO callsite
by Kyösti Mälkki (Code Review) 10 Feb '21

10 Feb '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42987 ) Change subject: soc/amd/picasso: Move APM_CNT_SMMINFO callsite ...................................................................... soc/amd/picasso: Move APM_CNT_SMMINFO callsite Triggering SMI is not part of the semantics of global_smi_enable(). Change-Id: Id0e7723c2bb9811f80fe36c38199a01445dc1d7d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/picasso/cpu.c M src/soc/amd/picasso/smi.c 2 files changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/42987/1 diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index c42f400..6c6149f 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -85,12 +85,18 @@ smm_state->smbase = staggered_smbase; } +static void post_mp_init(void) +{ + global_smi_enable(); + apm_control(APM_CNT_SMMINFO); +} + static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, .relocation_handler = relocation_handler, - .post_mp_init = global_smi_enable, + .post_mp_init = post_mp_init, }; void mp_init_cpus(struct bus *cpu_bus) diff --git a/src/soc/amd/picasso/smi.c b/src/soc/amd/picasso/smi.c index 125dde6..fb6d348 100644 --- a/src/soc/amd/picasso/smi.c +++ b/src/soc/amd/picasso/smi.c @@ -4,7 +4,6 @@ * Utilities for SMM setup */ -#include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <amdblocks/acpimmio.h> @@ -18,6 +17,4 @@ reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ reg |= SMITRG0_EOS; /* Set EOS bit */ smi_write32(SMI_REG_SMITRIG0, reg); - - outb(APM_CNT_SMMINFO, APM_CNT); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0e7723c2bb9811f80fe36c38199a01445dc1d7d Gerrit-Change-Number: 42987 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: sb/amd/common/acpi: Convert 'sleepstates.asl' to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 10 Feb '21

10 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45861 ) Change subject: sb/amd/common/acpi: Convert 'sleepstates.asl' to ASL 2.0 syntax ...................................................................... sb/amd/common/acpi: Convert 'sleepstates.asl' to ASL 2.0 syntax Change-Id: I16919a0fd5a78d666dc7003d4e495fd41c24613d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/common/acpi/sleepstates.asl 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/45861/1 diff --git a/src/southbridge/amd/common/acpi/sleepstates.asl b/src/southbridge/amd/common/acpi/sleepstates.asl index f6afd7c..3dcf1fa 100644 --- a/src/southbridge/amd/common/acpi/sleepstates.asl +++ b/src/southbridge/amd/common/acpi/sleepstates.asl @@ -7,22 +7,22 @@ Name (SSFG, 0x09) #endif If (CONFIG(DISABLE_ACPI_HIBERNATE)) { - Store(And(SSFG, 0xF7), SSFG) + SSFG &= 0xF7 } /* Supported sleep states: */ Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ -If (And(SSFG, 0x01)) { +If (SSF & 0x01) { Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ } -If (And(SSFG, 0x02)) { +If (SSFG & 0x02) { Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ } -If (And(SSFG, 0x04)) { +If (SSFG & 0x04) { Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ } -If (And(SSFG, 0x08)) { +If (SSFG & 0x08) { Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/45861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16919a0fd5a78d666dc7003d4e495fd41c24613d Gerrit-Change-Number: 45861 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: sb/amd/{agesa,pi}hudson/acpi: Convert 'pci_int.asl' to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 10 Feb '21

10 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45876 ) Change subject: sb/amd/{agesa,pi}hudson/acpi: Convert 'pci_int.asl' to ASL 2.0 syntax ...................................................................... sb/amd/{agesa,pi}hudson/acpi: Convert 'pci_int.asl' to ASL 2.0 syntax Change-Id: I1a382eaf122e40aeaefedf88425749616a2090d9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/agesa/hudson/acpi/pci_int.asl M src/southbridge/amd/pi/hudson/acpi/pci_int.asl 2 files changed, 114 insertions(+), 114 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/45876/1 diff --git a/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl b/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl index b2898eb..86607b2 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl @@ -109,7 +109,7 @@ { \_SB.CIRQ() } - Store(Arg0, PMOD) + PMOD = Arg0 } Method(CIRQ, 0x00, NotSerialized){ @@ -133,9 +133,9 @@ Method(_STA, 0) { if (PIRA) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTA._STA) */ @@ -145,14 +145,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTA._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKA\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRA, IRQN) - Return(IRQB) + IRQN = 1 << PIRA + Return (IRQB) } /* Method(_SB.INTA._CRS) */ Method(_SRS, 1) { @@ -162,9 +162,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRA) + PIRA = Local0 } /* End Method(_SB.INTA._SRS) */ } /* End Device(INTA) */ @@ -174,9 +174,9 @@ Method(_STA, 0) { if (PIRB) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTB._STA) */ @@ -186,14 +186,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTB._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKB\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRB, IRQN) - Return(IRQB) + IRQN = 1 << PIRB + Return (IRQB) } /* Method(_SB.INTB._CRS) */ Method(_SRS, 1) { @@ -203,9 +203,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRB) + PIRB = Local0 } /* End Method(_SB.INTB._SRS) */ } /* End Device(INTB) */ @@ -215,9 +215,9 @@ Method(_STA, 0) { if (PIRC) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTC._STA) */ @@ -227,14 +227,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTC._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKC\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRC, IRQN) - Return(IRQB) + IRQN = 1 << PIRC + Return (IRQB) } /* Method(_SB.INTC._CRS) */ Method(_SRS, 1) { @@ -244,9 +244,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRC) + PIRC = Local0 } /* End Method(_SB.INTC._SRS) */ } /* End Device(INTC) */ @@ -256,9 +256,9 @@ Method(_STA, 0) { if (PIRD) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTD._STA) */ @@ -268,14 +268,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTD._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKD\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRD, IRQN) - Return(IRQB) + IRQN = 1 << PIRD + Return (IRQB) } /* Method(_SB.INTD._CRS) */ Method(_SRS, 1) { @@ -285,9 +285,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRD) + PIRD = Local0 } /* End Method(_SB.INTD._SRS) */ } /* End Device(INTD) */ @@ -297,9 +297,9 @@ Method(_STA, 0) { if (PIRE) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTE._STA) */ @@ -309,14 +309,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTE._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKE\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRE, IRQN) - Return(IRQB) + IRQN = 1 << PIRE + Return (IRQB) } /* Method(_SB.INTE._CRS) */ Method(_SRS, 1) { @@ -326,9 +326,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRE) + PIRE = Local0 } /* End Method(_SB.INTE._SRS) */ } /* End Device(INTE) */ @@ -338,9 +338,9 @@ Method(_STA, 0) { if (PIRF) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTF._STA) */ @@ -350,14 +350,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) + Return (PITF) } /* Method(_SB.INTF._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKF\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRF, IRQN) - Return(IRQB) + IRQN = 1 << PIRF + Return (IRQB) } /* Method(_SB.INTF._CRS) */ Method(_SRS, 1) { @@ -367,9 +367,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRF) + PIRF = Local0 } /* End Method(_SB.INTF._SRS) */ } /* End Device(INTF) */ @@ -379,9 +379,9 @@ Method(_STA, 0) { if (PIRG) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTG._STA) */ @@ -391,14 +391,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTG._CRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKG\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRG, IRQN) - Return(IRQB) + IRQN = 1 << PIRG + Return (IRQB) } /* Method(_SB.INTG._CRS) */ Method(_SRS, 1) { @@ -408,9 +408,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRG) + PIRG = Local0 } /* End Method(_SB.INTG._SRS) */ } /* End Device(INTG) */ @@ -420,9 +420,9 @@ Method(_STA, 0) { if (PIRH) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTH._STA) */ @@ -432,14 +432,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTH._CRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKH\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRH, IRQN) - Return(IRQB) + IRQN = 1 << PIRH + Return (IRQB) } /* Method(_SB.INTH._CRS) */ Method(_SRS, 1) { @@ -449,8 +449,8 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRH) + PIRH = Local0 } /* End Method(_SB.INTH._SRS) */ } /* End Device(INTH) */ diff --git a/src/southbridge/amd/pi/hudson/acpi/pci_int.asl b/src/southbridge/amd/pi/hudson/acpi/pci_int.asl index b2898eb..86607b2 100644 --- a/src/southbridge/amd/pi/hudson/acpi/pci_int.asl +++ b/src/southbridge/amd/pi/hudson/acpi/pci_int.asl @@ -109,7 +109,7 @@ { \_SB.CIRQ() } - Store(Arg0, PMOD) + PMOD = Arg0 } Method(CIRQ, 0x00, NotSerialized){ @@ -133,9 +133,9 @@ Method(_STA, 0) { if (PIRA) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTA._STA) */ @@ -145,14 +145,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTA._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKA\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRA, IRQN) - Return(IRQB) + IRQN = 1 << PIRA + Return (IRQB) } /* Method(_SB.INTA._CRS) */ Method(_SRS, 1) { @@ -162,9 +162,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRA) + PIRA = Local0 } /* End Method(_SB.INTA._SRS) */ } /* End Device(INTA) */ @@ -174,9 +174,9 @@ Method(_STA, 0) { if (PIRB) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTB._STA) */ @@ -186,14 +186,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTB._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKB\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRB, IRQN) - Return(IRQB) + IRQN = 1 << PIRB + Return (IRQB) } /* Method(_SB.INTB._CRS) */ Method(_SRS, 1) { @@ -203,9 +203,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRB) + PIRB = Local0 } /* End Method(_SB.INTB._SRS) */ } /* End Device(INTB) */ @@ -215,9 +215,9 @@ Method(_STA, 0) { if (PIRC) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTC._STA) */ @@ -227,14 +227,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTC._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKC\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRC, IRQN) - Return(IRQB) + IRQN = 1 << PIRC + Return (IRQB) } /* Method(_SB.INTC._CRS) */ Method(_SRS, 1) { @@ -244,9 +244,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRC) + PIRC = Local0 } /* End Method(_SB.INTC._SRS) */ } /* End Device(INTC) */ @@ -256,9 +256,9 @@ Method(_STA, 0) { if (PIRD) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTD._STA) */ @@ -268,14 +268,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTD._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKD\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRD, IRQN) - Return(IRQB) + IRQN = 1 << PIRD + Return (IRQB) } /* Method(_SB.INTD._CRS) */ Method(_SRS, 1) { @@ -285,9 +285,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRD) + PIRD = Local0 } /* End Method(_SB.INTD._SRS) */ } /* End Device(INTD) */ @@ -297,9 +297,9 @@ Method(_STA, 0) { if (PIRE) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTE._STA) */ @@ -309,14 +309,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTE._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKE\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRE, IRQN) - Return(IRQB) + IRQN = 1 << PIRE + Return (IRQB) } /* Method(_SB.INTE._CRS) */ Method(_SRS, 1) { @@ -326,9 +326,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRE) + PIRE = Local0 } /* End Method(_SB.INTE._SRS) */ } /* End Device(INTE) */ @@ -338,9 +338,9 @@ Method(_STA, 0) { if (PIRF) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTF._STA) */ @@ -350,14 +350,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) + Return (PITF) } /* Method(_SB.INTF._PRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKF\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRF, IRQN) - Return(IRQB) + IRQN = 1 << PIRF + Return (IRQB) } /* Method(_SB.INTF._CRS) */ Method(_SRS, 1) { @@ -367,9 +367,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRF) + PIRF = Local0 } /* End Method(_SB.INTF._SRS) */ } /* End Device(INTF) */ @@ -379,9 +379,9 @@ Method(_STA, 0) { if (PIRG) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTG._STA) */ @@ -391,14 +391,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTG._CRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKG\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRG, IRQN) - Return(IRQB) + IRQN = 1 << PIRG + Return (IRQB) } /* Method(_SB.INTG._CRS) */ Method(_SRS, 1) { @@ -408,9 +408,9 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRG) + PIRG = Local0 } /* End Method(_SB.INTG._SRS) */ } /* End Device(INTG) */ @@ -420,9 +420,9 @@ Method(_STA, 0) { if (PIRH) { - Return(0x0B) /* sata is invisible */ + Return (0x0B) /* sata is invisible */ } else { - Return(0x09) /* sata is disabled */ + Return (0x09) /* sata is disabled */ } } /* End Method(_SB.INTH._STA) */ @@ -432,14 +432,14 @@ Method(_PRS ,0) { /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) + Return (IRQP) } /* Method(_SB.INTH._CRS) */ Method(_CRS ,0) { /* DBGO("\\_SB\\LNKH\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRH, IRQN) - Return(IRQB) + IRQN = 1 << PIRH + Return (IRQB) } /* Method(_SB.INTH._CRS) */ Method(_SRS, 1) { @@ -449,8 +449,8 @@ /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRH) + PIRH = Local0 } /* End Method(_SB.INTH._SRS) */ } /* End Device(INTH) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a382eaf122e40aeaefedf88425749616a2090d9 Gerrit-Change-Number: 45876 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/amd/{agesa,pi}hudson/acpi: Convert 'AmdImc.asl' to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 10 Feb '21

10 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45864 ) Change subject: sb/amd/{agesa,pi}hudson/acpi: Convert 'AmdImc.asl' to ASL 2.0 syntax ...................................................................... sb/amd/{agesa,pi}hudson/acpi: Convert 'AmdImc.asl' to ASL 2.0 syntax Change-Id: Ica6998026031e1b3d7286ce74a2334237d29ac74 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl M src/southbridge/amd/pi/hudson/acpi/AmdImc.asl 2 files changed, 36 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/45864/1 diff --git a/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl b/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl index e73ccdd..d23fc4f 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl @@ -18,35 +18,35 @@ Method(WACK, 0) { - Store(0, Local0) - Store(50, Local1) - While (LAnd (LNotEqual(Local0, 0xFA), LGreater(Local1,0))) { - Store(MRG0, Local0) + Local0 = 0 + Local1 = 50 + While ((Local0 != 0xFA) && (Local1 > 0)) { + Local0 = MRG0 Sleep(10) - Decrement(Local1) + Local1-- } } //Init Method (ITZE, 0) { - Store(0, MRG0) - Store(0xB5, MRG1) - Store(0, MRG2) - Store(0x96, MSTI) + MRG0 = 0 + MRG1 = 0xB5 + MRG2 = 0 + MSTI = 0x96 WACK() - Store(0, MRG0) - Store(0, MRG1) - Store(0, MRG2) - Store(0x80, MSTI) + MRG0 = 0 + MRG1 = 0 + MRG2 = 0 + MSTI = 0x80 WACK() - Or(MRG2, 0x01, Local0) + Local0 = MRG2 | 0x01 - Store(0, MRG0) - Store(0, MRG1) - Store(Local0, MRG2) - Store(0x81, MSTI) + MRG0 = 0 + MRG1 = 0 + MRG2 = Local0 + MSTI = 0x81 WACK() } diff --git a/src/southbridge/amd/pi/hudson/acpi/AmdImc.asl b/src/southbridge/amd/pi/hudson/acpi/AmdImc.asl index e73ccdd..d23fc4f 100644 --- a/src/southbridge/amd/pi/hudson/acpi/AmdImc.asl +++ b/src/southbridge/amd/pi/hudson/acpi/AmdImc.asl @@ -18,35 +18,35 @@ Method(WACK, 0) { - Store(0, Local0) - Store(50, Local1) - While (LAnd (LNotEqual(Local0, 0xFA), LGreater(Local1,0))) { - Store(MRG0, Local0) + Local0 = 0 + Local1 = 50 + While ((Local0 != 0xFA) && (Local1 > 0)) { + Local0 = MRG0 Sleep(10) - Decrement(Local1) + Local1-- } } //Init Method (ITZE, 0) { - Store(0, MRG0) - Store(0xB5, MRG1) - Store(0, MRG2) - Store(0x96, MSTI) + MRG0 = 0 + MRG1 = 0xB5 + MRG2 = 0 + MSTI = 0x96 WACK() - Store(0, MRG0) - Store(0, MRG1) - Store(0, MRG2) - Store(0x80, MSTI) + MRG0 = 0 + MRG1 = 0 + MRG2 = 0 + MSTI = 0x80 WACK() - Or(MRG2, 0x01, Local0) + Local0 = MRG2 | 0x01 - Store(0, MRG0) - Store(0, MRG1) - Store(Local0, MRG2) - Store(0x81, MSTI) + MRG0 = 0 + MRG1 = 0 + MRG2 = Local0 + MSTI = 0x81 WACK() } -- To view, visit https://review.coreboot.org/c/coreboot/+/45864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica6998026031e1b3d7286ce74a2334237d29ac74 Gerrit-Change-Number: 45864 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: sb/amd/{agesa,pi}/hudson/acpi: Convert 'audio.asl' to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 10 Feb '21

10 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45863 ) Change subject: sb/amd/{agesa,pi}/hudson/acpi: Convert 'audio.asl' to ASL 2.0 syntax ...................................................................... sb/amd/{agesa,pi}/hudson/acpi: Convert 'audio.asl' to ASL 2.0 syntax Change-Id: I976b4c2e2aa878d8b591c3e416ffb76d7a699b39 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/agesa/hudson/acpi/audio.asl M src/southbridge/amd/pi/hudson/acpi/audio.asl 2 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/45863/1 diff --git a/src/southbridge/amd/agesa/hudson/acpi/audio.asl b/src/southbridge/amd/agesa/hudson/acpi/audio.asl index c85710f..8eb0e6d 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/audio.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/audio.asl @@ -28,11 +28,11 @@ Method (_INI, 0, NotSerialized) { - If (LEqual (OSVR, 0x03)) + If (OSVR == 0x03) { - Store (Zero, NSEN) - Store (One, NSDO) - Store (One, NSDI) + NSEN = 0 + NSDO = 1 + NSDI = 1 } } } /* end AZHD */ diff --git a/src/southbridge/amd/pi/hudson/acpi/audio.asl b/src/southbridge/amd/pi/hudson/acpi/audio.asl index c85710f..8eb0e6d 100644 --- a/src/southbridge/amd/pi/hudson/acpi/audio.asl +++ b/src/southbridge/amd/pi/hudson/acpi/audio.asl @@ -28,11 +28,11 @@ Method (_INI, 0, NotSerialized) { - If (LEqual (OSVR, 0x03)) + If (OSVR == 0x03) { - Store (Zero, NSEN) - Store (One, NSDO) - Store (One, NSDI) + NSEN = 0 + NSDO = 1 + NSDI = 1 } } } /* end AZHD */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I976b4c2e2aa878d8b591c3e416ffb76d7a699b39 Gerrit-Change-Number: 45863 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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