coreboot-gerrit September 2020

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Change in coreboot[master]: mb/kontron/ktqm77: Do not overwrite pei_data
by Angel Pons (Code Review) 08 Feb '21

08 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43025 ) Change subject: mb/kontron/ktqm77: Do not overwrite pei_data ...................................................................... mb/kontron/ktqm77: Do not overwrite pei_data Most of the values are already set in northbridge code. Change-Id: I171816ce847bea139afeb0ab56e74144cd006c6b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/kontron/ktqm77/early_init.c 1 file changed, 29 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/43025/1 diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index b8f44b5..92f169c 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -53,62 +53,36 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, /* 0 Mobile, 1 Desktop/Server */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .gbe_enable = 1, - .ddr3lv_support = 0, - /* - * 0 = leave channel enabled - * 1 = disable dimm 0 on channel - * 2 = disable dimm 1 on channel - * 3 = disable dimm 0+1 on channel - */ - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* enabled USB oc pin length */ - { 1, 0, 0x0040 }, /* P0: lower left USB 3.0 (OC0) */ - { 1, 0, 0x0040 }, /* P1: upper left USB 3.0 (OC0) */ - { 1, 0, 0x0040 }, /* P2: lower right USB 3.0 (OC0) */ - { 1, 0, 0x0040 }, /* P3: upper right USB 3.0 (OC0) */ - { 1, 0, 0x0040 }, /* P4: lower USB 2.0 (OC0) */ - { 1, 0, 0x0040 }, /* P5: upper USB 2.0 (OC0) */ - { 1, 0, 0x0040 }, /* P6: front panel USB 2.0 (OC0) */ - { 1, 0, 0x0040 }, /* P7: front panel USB 2.0 (OC0) */ - { 1, 4, 0x0040 }, /* P8: internal USB 2.0 (OC4) */ - { 1, 4, 0x0040 }, /* P9: internal USB 2.0 (OC4) */ - { 1, 4, 0x0040 }, /* P10: internal USB 2.0 (OC4) */ - { 1, 4, 0x0040 }, /* P11: internal USB 2.0 (OC4) */ - { 1, 4, 0x0040 }, /* P12: internal USB 2.0 (OC4) */ - { 1, 4, 0x0040 }, /* P13: internal USB 2.0 (OC4) */ - }, - .usb3 = { - .mode = 3, /* Smart Auto? */ - .hs_port_switch_mask = 0xf, /* All four ports. */ - .preboot_support = 1, /* preOS driver? */ - .xhci_streams = 1, /* Enable. */ - }, - .pcie_init = 1, + pei_data->system_type = 0; /* 0 Mobile, 1 Desktop/Server */ + pei_data->ec_present = 1; + pei_data->spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 }; + pei_data->max_ddr3_freq = 1600; + pei_data->pcie_init = 1; + + pei_data->usb_port_config = { + /* enabled USB oc pin length */ + { 1, 0, 0x0040 }, /* P0: lower left USB 3.0 (OC0) */ + { 1, 0, 0x0040 }, /* P1: upper left USB 3.0 (OC0) */ + { 1, 0, 0x0040 }, /* P2: lower right USB 3.0 (OC0) */ + { 1, 0, 0x0040 }, /* P3: upper right USB 3.0 (OC0) */ + { 1, 0, 0x0040 }, /* P4: lower USB 2.0 (OC0) */ + { 1, 0, 0x0040 }, /* P5: upper USB 2.0 (OC0) */ + { 1, 0, 0x0040 }, /* P6: front panel USB 2.0 (OC0) */ + { 1, 0, 0x0040 }, /* P7: front panel USB 2.0 (OC0) */ + { 1, 4, 0x0040 }, /* P8: internal USB 2.0 (OC4) */ + { 1, 4, 0x0040 }, /* P9: internal USB 2.0 (OC4) */ + { 1, 4, 0x0040 }, /* P10: internal USB 2.0 (OC4) */ + { 1, 4, 0x0040 }, /* P11: internal USB 2.0 (OC4) */ + { 1, 4, 0x0040 }, /* P12: internal USB 2.0 (OC4) */ + { 1, 4, 0x0040 }, /* P13: internal USB 2.0 (OC4) */ }; - *pei_data = pei_data_template; + + pei_data->usb3 = { + .mode = 3, /* Smart Auto? */ + .hs_port_switch_mask = 0xf, /* All four ports. */ + .preboot_support = 1, /* preOS driver? */ + .xhci_streams = 1, /* Enable. */ + }; } const struct southbridge_usb_port mainboard_usb_ports[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/43025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I171816ce847bea139afeb0ab56e74144cd006c6b Gerrit-Change-Number: 43025 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: payloads/external/FILO: Pass Libpayloads path on the clean target
by Arthur Heymans (Code Review) 07 Feb '21

07 Feb '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36461 ) Change subject: payloads/external/FILO: Pass Libpayloads path on the clean target ...................................................................... payloads/external/FILO: Pass Libpayloads path on the clean target Change-Id: If5f8f4ecce317e54cd4b5688553cc38220f6e6df Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M payloads/external/FILO/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/36461/1 diff --git a/payloads/external/FILO/Makefile b/payloads/external/FILO/Makefile index a89ea2a..ffb4e1f 100644 --- a/payloads/external/FILO/Makefile +++ b/payloads/external/FILO/Makefile @@ -44,7 +44,7 @@ $(MAKE) && $(MAKE) DESTDIR=../external/FILO/filo/build install clean: - test -d filo && $(MAKE) -C filo clean || exit 0 + test -d filo && $(MAKE) -C filo clean LIBCONFIG_PATH=../../../libpayload || exit 0 distclean: rm -rf filo -- To view, visit https://review.coreboot.org/c/coreboot/+/36461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5f8f4ecce317e54cd4b5688553cc38220f6e6df Gerrit-Change-Number: 36461 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/pineview: Move register headers into a subfolder
by Angel Pons (Code Review) 07 Feb '21

07 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45387 ) Change subject: nb/intel/pineview: Move register headers into a subfolder ...................................................................... nb/intel/pineview: Move register headers into a subfolder Move all files with register definitions into a `registers` subfolder. Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical. Change-Id: Icc3df9fa43ac3858a8b177491020295804b17aa3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/pineview/pineview.h R src/northbridge/intel/pineview/registers/host_bridge.h R src/northbridge/intel/pineview/registers/mchbar.h 3 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/45387/1 diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 03fa318..aacaad5 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -19,7 +19,7 @@ /* Device 0:0.0 PCI configuration space (Host Bridge) */ #define HOST_BRIDGE PCI_DEV(0, 0, 0) -#include "hostbridge_regs.h" +#include "registers/host_bridge.h" /* Device 0:1.0 PCI configuration space (PCI Express) */ @@ -53,7 +53,7 @@ /* As there are many registers, define them on a separate file */ -#include "mchbar_regs.h" +#include "registers/mchbar.h" /* * EPBAR - Egress Port Root Complex Register Block diff --git a/src/northbridge/intel/pineview/hostbridge_regs.h b/src/northbridge/intel/pineview/registers/host_bridge.h similarity index 88% rename from src/northbridge/intel/pineview/hostbridge_regs.h rename to src/northbridge/intel/pineview/registers/host_bridge.h index 506efcf..fbdcfea 100644 --- a/src/northbridge/intel/pineview/hostbridge_regs.h +++ b/src/northbridge/intel/pineview/registers/host_bridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __PINEVIEW_HOSTBRIDGE_REGS_H__ -#define __PINEVIEW_HOSTBRIDGE_REGS_H__ +#ifndef __PINEVIEW_REGISTERS_HOST_BRIDGE_H__ +#define __PINEVIEW_REGISTERS_HOST_BRIDGE_H__ #define EPBAR 0x40 #define MCHBAR 0x48 @@ -54,4 +54,4 @@ #define MID0 0xf8 #define DEBUP0 0xfc -#endif /* __PINEVIEW_HOSTBRIDGE_REGS_H__ */ +#endif /* __PINEVIEW_REGISTERS_HOST_BRIDGE_H__ */ diff --git a/src/northbridge/intel/pineview/mchbar_regs.h b/src/northbridge/intel/pineview/registers/mchbar.h similarity index 98% rename from src/northbridge/intel/pineview/mchbar_regs.h rename to src/northbridge/intel/pineview/registers/mchbar.h index e9cd7ce..1339135 100644 --- a/src/northbridge/intel/pineview/mchbar_regs.h +++ b/src/northbridge/intel/pineview/registers/mchbar.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PINEVIEW_MCHBAR_REGS_H__ -#define __PINEVIEW_MCHBAR_REGS_H__ +#ifndef __PINEVIEW_REGISTERS_MCHBAR_H__ +#define __PINEVIEW_REGISTERS_MCHBAR_H__ /* Indexed register helper macros */ #define Gz(r, z) ((r) + ((z) * 0x100)) @@ -562,4 +562,4 @@ #define EXTTSCS 0x3825 #define C0THRMSTS 0x3830 -#endif /* __PINEVIEW_MCHBAR_REGS_H__ */ +#endif /* __PINEVIEW_REGISTERS_MCHBAR_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc3df9fa43ac3858a8b177491020295804b17aa3 Gerrit-Change-Number: 45387 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/bd82x6x: Drop unneeded files from SMM
by Angel Pons (Code Review) 07 Feb '21

07 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42052 ) Change subject: sb/intel/bd82x6x: Drop unneeded files from SMM ...................................................................... sb/intel/bd82x6x: Drop unneeded files from SMM We also drop all `__unused` function attributes on these files. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: I37219bddd2ad9b56711508a3d28056863123d769 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/Makefile.inc M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c 3 files changed, 6 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/42052/1 diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index cf9bf50..f83d303 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -25,7 +25,7 @@ ramstage-$(CONFIG_ELOG) += elog.c -smm-y += smihandler.c me.c me_8.x.c pch.c me_common.c +smm-y += smihandler.c pch.c me_common.c romstage-y += early_smbus.c me_status.c romstage-y += early_rcba.c diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index dd3ecd7..38cdb48 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -29,7 +29,7 @@ #endif /* Get ME firmware version */ -static int __unused mkhi_get_fw_version(void) +static int mkhi_get_fw_version(void) { struct me_fw_version version; struct mkhi_header mkhi = { @@ -66,7 +66,7 @@ } /* Get ME Firmware Capabilities */ -static int __unused mkhi_get_fwcaps(void) +static int mkhi_get_fwcaps(void) { u32 rule_id = 0; struct me_fwcaps cap; @@ -109,8 +109,6 @@ return 0; } -#ifndef __SIMPLE_DEVICE__ - /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) { @@ -236,5 +234,3 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = 0x1c3a, }; - -#endif /* __SIMPLE_DEVICE__ */ diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 78f2817..5659f7a 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -34,7 +34,7 @@ name, state ? " en" : "dis"); } -static void __unused me_print_fw_version(mbp_fw_version_name *vers_name) +static void me_print_fw_version(mbp_fw_version_name *vers_name) { if (!vers_name->major_version) { printk(BIOS_ERR, "ME: mbp missing version report\n"); @@ -72,7 +72,7 @@ } /* Get ME Firmware Capabilities */ -static void __unused me_print_fwcaps(mbp_fw_caps *caps_section) +static void me_print_fwcaps(mbp_fw_caps *caps_section) { mefwcaps_sku *cap = &caps_section->fw_capabilities; if (!caps_section->available) { @@ -99,8 +99,6 @@ print_cap("Wireless LAN (WLAN)", cap->wlan); } -#ifndef __SIMPLE_DEVICE__ - /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) { @@ -242,8 +240,6 @@ .device = 0x1e3a, }; -#endif /* !__SIMPLE_DEVICE__ */ - /****************************************************************************** * */ static u32 me_to_host_words_pending(void) @@ -260,7 +256,7 @@ * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. */ -static int __unused intel_me_read_mbp(me_bios_payload *mbp_data) +static int intel_me_read_mbp(me_bios_payload *mbp_data) { mbp_header mbp_hdr; mbp_item_header mbp_item_hdr; -- To view, visit https://review.coreboot.org/c/coreboot/+/42052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37219bddd2ad9b56711508a3d28056863123d769 Gerrit-Change-Number: 42052 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/bd82x6x: Deduplicate ME finalization function
by Angel Pons (Code Review) 07 Feb '21

07 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42050 ) Change subject: sb/intel/bd82x6x: Deduplicate ME finalization function ...................................................................... sb/intel/bd82x6x: Deduplicate ME finalization function Both functions are identical, so we might as well drop one copy. Change-Id: Ifd24f01dab2b5a6b7d154a8e2b1a69c233a0e727 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/me_common.c 4 files changed, 39 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/42050/1 diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index d2a3480..7910623 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -111,57 +111,20 @@ #ifdef __SIMPLE_DEVICE__ -static void intel_me7_finalize_smm(void) -{ - struct me_hfs hfs; - u32 reg32; - u16 reg16; - - update_mei_base_address(); - - /* S3 path will have hidden this device already */ - if (!is_mei_base_address_valid()) - return; - - /* Make sure ME is in a mode that expects EOP */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); - memcpy(&hfs, &reg32, sizeof(u32)); - - /* Abort and leave device alone if not normal mode */ - if (hfs.fpt_bad || - hfs.working_state != ME_HFS_CWS_NORMAL || - hfs.operation_mode != ME_HFS_MODE_NORMAL) - return; - - /* Try to send EOP command so ME stops accepting other commands */ - mkhi_end_of_post(); - - /* Make sure IO is disabled */ - reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16); - - /* Hide the PCI device */ - RCBA32_OR(FD2, PCH_DISABLE_MEI1); -} - void intel_me_finalize_smm(void) { u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); switch (did) { case 0x1c3a8086: - intel_me7_finalize_smm(); - break; case 0x1e3a8086: - intel_me8_finalize_smm(); + me_finalize_smm(); break; default: printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); } } -#else +#else /* !__SIMPLE_DEVICE__ */ /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index a55a1f2..8fee899 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -245,6 +245,7 @@ int mkhi_end_of_post(void); void update_mei_base_address(void); bool is_mei_base_address_valid(void); +void me_finalize_smm(void); int intel_mei_setup(struct device *dev); int intel_me_extend_valid(struct device *dev); void intel_me_hide(struct device *dev); @@ -258,7 +259,6 @@ int intel_early_me_init_done(u8 status); void intel_me_finalize_smm(void); -void intel_me8_finalize_smm(void); typedef struct { u32 major_version : 16; diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 1a331e9..78f2817 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -99,44 +99,7 @@ print_cap("Wireless LAN (WLAN)", cap->wlan); } -#ifdef __SIMPLE_DEVICE__ - -void intel_me8_finalize_smm(void) -{ - struct me_hfs hfs; - u32 reg32; - u16 reg16; - - update_mei_base_address(); - - /* S3 path will have hidden this device already */ - if (!is_mei_base_address_valid()) - return; - - /* Make sure ME is in a mode that expects EOP */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); - memcpy(&hfs, &reg32, sizeof(u32)); - - /* Abort and leave device alone if not normal mode */ - if (hfs.fpt_bad || - hfs.working_state != ME_HFS_CWS_NORMAL || - hfs.operation_mode != ME_HFS_MODE_NORMAL) - return; - - /* Try to send EOP command so ME stops accepting other commands */ - mkhi_end_of_post(); - - /* Make sure IO is disabled */ - reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16); - - /* Hide the PCI device */ - RCBA32_OR(FD2, PCH_DISABLE_MEI1); -} - -#else /* !__SIMPLE_DEVICE__ */ +#ifndef __SIMPLE_DEVICE__ /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index 83e7fe6..9088d44 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -361,6 +361,41 @@ return mei_base_address && mei_base_address != (u32 *)0xfffffff0; } +void me_finalize_smm(void) +{ + struct me_hfs hfs; + u32 reg32; + u16 reg16; + + update_mei_base_address(); + + /* S3 path will have hidden this device already */ + if (!is_mei_base_address_valid()) + return; + + /* Make sure ME is in a mode that expects EOP */ + reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); + memcpy(&hfs, &reg32, sizeof(u32)); + + /* Abort and leave device alone if not normal mode */ + if (hfs.fpt_bad || + hfs.working_state != ME_HFS_CWS_NORMAL || + hfs.operation_mode != ME_HFS_MODE_NORMAL) + return; + + /* Try to send EOP command so ME stops accepting other commands */ + mkhi_end_of_post(); + + /* Make sure IO is disabled */ + reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16); + + /* Hide the PCI device */ + RCBA32_OR(FD2, PCH_DISABLE_MEI1); +} + #else /* Prepare ME for MEI messages */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd24f01dab2b5a6b7d154a8e2b1a69c233a0e727 Gerrit-Change-Number: 42050 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/bd82x6x: Relocate intel_me_finalize_smm()
by Angel Pons (Code Review) 07 Feb '21

07 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42051 ) Change subject: sb/intel/bd82x6x: Relocate intel_me_finalize_smm() ...................................................................... sb/intel/bd82x6x: Relocate intel_me_finalize_smm() This allows us to reduce the scope of three functions. Change-Id: Ib08c0eb4b01e10aa38efac434ff23a488e9e2787 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_common.c 3 files changed, 18 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42051/1 diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 7910623..dd3ecd7 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -109,22 +109,7 @@ return 0; } -#ifdef __SIMPLE_DEVICE__ - -void intel_me_finalize_smm(void) -{ - u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); - switch (did) { - case 0x1c3a8086: - case 0x1e3a8086: - me_finalize_smm(); - break; - default: - printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); - } -} - -#else /* !__SIMPLE_DEVICE__ */ +#ifndef __SIMPLE_DEVICE__ /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 8fee899..29d5749 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -243,9 +243,7 @@ void *req_data, void *rsp_data, int rsp_bytes); int mkhi_end_of_post(void); -void update_mei_base_address(void); -bool is_mei_base_address_valid(void); -void me_finalize_smm(void); +void intel_me_finalize_smm(void); int intel_mei_setup(struct device *dev); int intel_me_extend_valid(struct device *dev); void intel_me_hide(struct device *dev); @@ -258,8 +256,6 @@ int intel_early_me_uma_size(void); int intel_early_me_init_done(u8 status); -void intel_me_finalize_smm(void); - typedef struct { u32 major_version : 16; u32 minor_version : 16; diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index 9088d44..59c0b38 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -351,17 +351,17 @@ #ifdef __SIMPLE_DEVICE__ -void update_mei_base_address(void) +static inline void update_mei_base_address(void) { mei_base_address = (u32 *)(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); } -bool is_mei_base_address_valid(void) +static inline bool is_mei_base_address_valid(void) { return mei_base_address && mei_base_address != (u32 *)0xfffffff0; } -void me_finalize_smm(void) +static void me_finalize_smm(void) { struct me_hfs hfs; u32 reg32; @@ -396,6 +396,19 @@ RCBA32_OR(FD2, PCH_DISABLE_MEI1); } +void intel_me_finalize_smm(void) +{ + u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); + switch (did) { + case 0x1c3a8086: + case 0x1e3a8086: + me_finalize_smm(); + break; + default: + printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); + } +} + #else /* Prepare ME for MEI messages */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib08c0eb4b01e10aa38efac434ff23a488e9e2787 Gerrit-Change-Number: 42051 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: sb/intel/{bd82x6x,ibexpeak}: hide MEI if ME inoperable
by James (Code Review) 06 Feb '21

06 Feb '21

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39074 ) Change subject: sb/intel/{bd82x6x,ibexpeak}: hide MEI if ME inoperable ...................................................................... sb/intel/{bd82x6x,ibexpeak}: hide MEI if ME inoperable If the Management Engine is in an inoperable mode, e.g. if me_cleaner is used, hide the Management Engine Interface device so the OS doesn't try to access it. Enable the MEI in device trees of Ibex Peak, Cougar Point and Panther Point boards where they have been disabled. Change-Id: Ie4a35bf5fc196e0a02b7591cdb8633d38f0c7f3e Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/packardbell/ms2290/devicetree.cb M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/ibexpeak/me.c 11 files changed, 18 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39074/1 diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index b03e2f9..3c0d278 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -54,7 +54,7 @@ register "spi_lvscc" = "0x2005" device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 808e057..fb2876f 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -74,7 +74,9 @@ register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - device pci 16.0 off end # MEI + device pci 16.0 on # MEI + subsystemid 0x17aa 0x215f + end device pci 16.2 on # IDE/SATA subsystemid 0x17aa 0x2161 end diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 53bd16f..222825b 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -72,7 +72,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index c91b04e..314ca43 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -72,7 +72,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index ee612cd..7483c46 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -75,7 +75,7 @@ register "spi_lvscc" = "0x2005" device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 2d15d87..510fa9e 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -71,7 +71,7 @@ register "spi_lvscc" = "0x2005" device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 5ae1427..7e9d9bb 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -71,7 +71,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index bf1c171..97674d8 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -66,7 +66,9 @@ register "alt_gp_smi_en" = "0x0000" register "gen1_dec" = "0x040069" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1025 0x0379 + end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R, only management boot device pci 16.3 off end # Management Engine KT diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 15f99cd..280dcb0 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -692,6 +692,8 @@ switch (path) { case ME_S3WAKE_BIOS_PATH: + case ME_ERROR_BIOS_PATH: + case ME_DISABLE_BIOS_PATH: intel_me_hide(dev); break; @@ -717,9 +719,7 @@ */ break; - case ME_ERROR_BIOS_PATH: case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index f13ced9..88558e3 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -681,6 +681,8 @@ switch (path) { case ME_S3WAKE_BIOS_PATH: + case ME_ERROR_BIOS_PATH: + case ME_DISABLE_BIOS_PATH: intel_me_hide(dev); break; @@ -721,9 +723,7 @@ */ break; - case ME_ERROR_BIOS_PATH: case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 63dff6a..aa1c002 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -577,6 +577,8 @@ switch (path) { case ME_S3WAKE_BIOS_PATH: + case ME_ERROR_BIOS_PATH: + case ME_DISABLE_BIOS_PATH: intel_me_hide(dev); break; @@ -595,9 +597,7 @@ */ break; - case ME_ERROR_BIOS_PATH: case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4a35bf5fc196e0a02b7591cdb8633d38f0c7f3e Gerrit-Change-Number: 39074 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

6 19

Change in coreboot[master]: sb/intel/bd82x6x: Read ME MBP HWA request
by Angel Pons (Code Review) 06 Feb '21

06 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45266 ) Change subject: sb/intel/bd82x6x: Read ME MBP HWA request ...................................................................... sb/intel/bd82x6x: Read ME MBP HWA request On AMT-enabled systems, the ME can request some information about the hardware with a HWA request, which is a specific type of MBP item. Read the information provided by this item into the MBP data struct. This silences a spurious error about an unknown MBP item. Handling the HWA request is not simple, and does not appear to be necessary anyway. Change-Id: I4bddad6cbfaaad6854266d760f86c9a90705a200 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/45266/1 diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 29089a9..2290c63 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -354,6 +354,17 @@ } __packed platform_type_rule_data; typedef struct { + union { + u32 data; + struct { + u32 media_table_push : 1; + u32 reserved : 31; + } bits; + }; + u8 available; +} __packed mbp_hwa_request; + +typedef struct { mefwcaps_sku fw_capabilities; u8 available; } mbp_fw_caps; @@ -382,6 +393,7 @@ mbp_icc_profile icc_profile; tdt_state_info at_state; u32 mfsintegrity; + mbp_hwa_request hwa_request; } me_bios_payload; typedef struct { diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 96e9a51..a701315 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -320,6 +320,10 @@ case MBP_IDENT(KERNEL, MFS_FAILURE): SET_UP_COPY(mfsintegrity); + case MBP_IDENT(HWA, REQUEST): + mbp_data->hwa_request.available = 1; + SET_UP_COPY(hwa_request.data); + default: printk(BIOS_ERR, "ME: Unknown MBP item! Skipping...\n"); while (copy_size--) -- To view, visit https://review.coreboot.org/c/coreboot/+/45266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bddad6cbfaaad6854266d760f86c9a90705a200 Gerrit-Change-Number: 45266 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: sb/intel/bd82x6x: Clean up MBP item ID handling
by Angel Pons (Code Review) 06 Feb '21

06 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45263 ) Change subject: sb/intel/bd82x6x: Clean up MBP item ID handling ...................................................................... sb/intel/bd82x6x: Clean up MBP item ID handling Since this ID is only used to concatenate two values, it doesn't matter how it is defined as long as the definition is the same everywhere. Update the `MBP_MAKE_IDENT` macro to match what Lynx Point does. Also, improve some log messages to print the components of the item ID. Change-Id: I908a6973ab64b1162ec5b835c7c4ffba671d4f05 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c 2 files changed, 7 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/45263/1 diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index dc1fa48..29089a9 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -284,7 +284,7 @@ /* HWA Items */ #define MBP_HWA_REQUEST_ITEM 1 -#define MBP_MAKE_IDENT(appid, item) (((item) << 8) + (appid)) +#define MBP_MAKE_IDENT(appid, item) (((appid) << 8) | (item)) #define MBP_IDENT(appid, item) MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM) diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 6d0a82d..45e7efe 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -239,7 +239,6 @@ mbp_header mbp_hdr; mbp_item_header mbp_item_hdr; u32 me2host_pending; - u32 mbp_item_id; struct mei_csr host; me2host_pending = me_to_host_words_pending(); @@ -266,7 +265,6 @@ while (mbp_hdr.num_entries--) { u32 *copy_addr; u32 copy_size, buffer_room; - void *p; if (!me2host_pending) { printk(BIOS_ERR, "ME: no mbp data %d entries to go!\n", @@ -285,8 +283,6 @@ me2host_pending -= mbp_item_hdr.length; - mbp_item_id = MBP_MAKE_IDENT(mbp_item_hdr.app_id, (u32)mbp_item_hdr.item_id); - copy_size = mbp_item_hdr.length - 1; #define SET_UP_COPY(field) { copy_addr = (u32 *)&mbp_data->field; \ @@ -294,10 +290,10 @@ break; \ } - p = &mbp_item_hdr; - printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p)); + printk(BIOS_INFO, "ME: MBP item: app id = %u, item id = %u, length = %u\n", + mbp_item_hdr.app_id, mbp_item_hdr.item_id, mbp_item_hdr.length); - switch (mbp_item_id) { + switch (MBP_MAKE_IDENT(mbp_item_hdr.app_id, mbp_item_hdr.item_id)) { case MBP_IDENT(KERNEL, FW_VER): SET_UP_COPY(fw_version_name); @@ -325,17 +321,15 @@ SET_UP_COPY(mfsintegrity); default: - printk(BIOS_ERR, "ME: unknown mbp item id 0x%x! Skipping\n", - mbp_item_id); + printk(BIOS_WARN, "ME: Unknown MBP item! Skipping...\n"); while (copy_size--) read_cb(); continue; } if (buffer_room != copy_size) { - printk(BIOS_ERR, "ME: buffer room %d != %d copy size" - " for item 0x%x!!!\n", - buffer_room, copy_size, mbp_item_id); + printk(BIOS_ERR, "ME: buffer room %d != %d copy size!!!\n", + buffer_room, copy_size); return -1; } while (copy_size--) -- To view, visit https://review.coreboot.org/c/coreboot/+/45263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I908a6973ab64b1162ec5b835c7c4ffba671d4f05 Gerrit-Change-Number: 45263 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: sb/intel/bd82x6x/me_8.x.c: Improve ME MBP entry decoding
by Angel Pons (Code Review) 06 Feb '21

06 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45262 ) Change subject: sb/intel/bd82x6x/me_8.x.c: Improve ME MBP entry decoding ...................................................................... sb/intel/bd82x6x/me_8.x.c: Improve ME MBP entry decoding Backport the MBP macros from Lynx Point, adjusting the definitions as required. Keep the original math for now, to preserve reproducibility. Note that HWP Request isn't being handled in the current code. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: I36736bd03ca24ac3b319bf8e3d6eeb82a4104c86 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c 2 files changed, 38 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/45262/1 diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index ce1817f0..dc1fa48 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -259,6 +259,35 @@ int intel_me7_send_eop(void); int intel_me8_send_eop(void); +/* + * ME to BIOS Payload definitions + */ +#define MBP_APPID_KERNEL 1 +#define MBP_APPID_ICC 2 +#define MBP_APPID_INTEL_AT 3 +#define MBP_APPID_HWA 4 + +/* Kernel items */ +#define MBP_KERNEL_FW_VER_ITEM 1 +#define MBP_KERNEL_FW_CAP_ITEM 2 +#define MBP_KERNEL_ROM_BIST_ITEM 3 +#define MBP_KERNEL_PLAT_KEY_ITEM 4 +#define MBP_KERNEL_FW_TYPE_ITEM 5 +#define MBP_KERNEL_MFS_FAILURE_ITEM 6 + +/* ICC Items */ +#define MBP_ICC_PROFILE_ITEM 1 + +/* Intel AT items */ +#define MBP_INTEL_AT_STATE_ITEM 1 + +/* HWA Items */ +#define MBP_HWA_REQUEST_ITEM 1 + +#define MBP_MAKE_IDENT(appid, item) (((item) << 8) + (appid)) + +#define MBP_IDENT(appid, item) MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM) + typedef struct { u32 major_version : 16; u32 minor_version : 16; diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 3613fe4..6d0a82d 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -285,8 +285,7 @@ me2host_pending -= mbp_item_hdr.length; - mbp_item_id = (((u32)mbp_item_hdr.item_id) << 8) + - mbp_item_hdr.app_id; + mbp_item_id = MBP_MAKE_IDENT(mbp_item_hdr.app_id, (u32)mbp_item_hdr.item_id); copy_size = mbp_item_hdr.length - 1; @@ -299,30 +298,30 @@ printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p)); switch (mbp_item_id) { - case 0x101: + case MBP_IDENT(KERNEL, FW_VER): SET_UP_COPY(fw_version_name); - case 0x102: + case MBP_IDENT(ICC, PROFILE): SET_UP_COPY(icc_profile); - case 0x103: + case MBP_IDENT(INTEL_AT, STATE): SET_UP_COPY(at_state); - case 0x201: + case MBP_IDENT(KERNEL, FW_CAP): mbp_data->fw_caps_sku.available = 1; SET_UP_COPY(fw_caps_sku.fw_capabilities); - case 0x301: + case MBP_IDENT(KERNEL, ROM_BIST): SET_UP_COPY(rom_bist_data); - case 0x401: + case MBP_IDENT(KERNEL, PLAT_KEY): SET_UP_COPY(platform_key); - case 0x501: + case MBP_IDENT(KERNEL, FW_TYPE): mbp_data->fw_plat_type.available = 1; SET_UP_COPY(fw_plat_type.rule_data); - case 0x601: + case MBP_IDENT(KERNEL, MFS_FAILURE): SET_UP_COPY(mfsintegrity); default: -- To view, visit https://review.coreboot.org/c/coreboot/+/45262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36736bd03ca24ac3b319bf8e3d6eeb82a4104c86 Gerrit-Change-Number: 45262 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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