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Change in coreboot[master]: Documentation: Add documentation on jenkins builders
by Martin Roth (Code Review) 25 Jan '21

25 Jan '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43984 ) Change subject: Documentation: Add documentation on jenkins builders ...................................................................... Documentation: Add documentation on jenkins builders Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I54a0204e7525a25f2fd717a73007b304aac67396 --- A Documentation/community/builders.md 1 file changed, 391 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/43984/1 diff --git a/Documentation/community/builders.md b/Documentation/community/builders.md new file mode 100644 index 0000000..bc35bcc --- /dev/null +++ b/Documentation/community/builders.md @@ -0,0 +1,391 @@ +# Jenkins builder setup and configuration + +## How to set up a new jenkins builder + +### Contact a jenkins admin + +Let a jenkins admin know that you’re interested in setting up a jenkins +build system. + +For a permanent build system, this should generally be a dedicated +machine that is not generally being used for other purposes. The +coreboot builds are very intensive. + +It's also best to be aware that although we don't know of any security +issues, the jenkins-node image is run with the privileged flag which +gives the container root access to the build machine. See +[this article](https://blog.trendmicro.com/trendlabs-security-intelligence/why-ru… +about why this is discouraged. + +It's recommended that you give an admin root access on your machine so +that they can reset it in case of a failure. This is not a requirement, +as the system can just be disabled until someone is available to fix any +issues. + +Currently active Jenkins admins: +* Patrick Georgi: + * Email: [patrick@georgi-clan.de](mailto:patrick@georgi-clan.de) + * IRC: pgeorgi + + +### Build Machine requirements + +For a builder, we need a fast system with lots of threads and plenty of +RAM. The builder builds and stores the git repos and output in tmpfs +along with the ccache save area, so if there isn't enough memory, the +builds will slow down because of smaller ccache areas and can run into +"out of storage space" errors. + +#### Current Build Machines + +To give an idea of what a suitable build machine might be, currently the +coreboot project has 3 active jenkins build machines. + +* Congenialbuilder - 128 threads, 256GiB RAM + * Fastest Passing coreboot gerrit build: 4 min, 30 sec + * Slowest Passing coreboot gerrit build: 9 min, 56 sec + + +* Gleeful builder - 64 thread, 64GiB RAM + * Fastest Passing coreboot gerrit build: 6 min, 6 sec + * Slowest Passing coreboot gerrit build, 34 min + + +* Ultron (9elements) - 48 threads, 128GiB RAM + * Fastest Passing coreboot gerrit build: 6 min, 32 sec + * Slowest Passing coreboot gerrit build: 44 min + + +### Jenkins Builds + +There are a number of builds handled by the coreboot jenkins builders, +for a number of different projects - coreboot, flashrom, memtest86+, +em100, etc. Many of these have builders for their current master branch +as well as gerrit and coverity builds. + +You can see all the builds here: +[https://qa.coreboot.org/](https://qa.coreboot.org/) + +Most of the time on the builders is taken up by the coreboot master and +gerrit builds. + +* [coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/) +([Time trend](https://qa.coreboot.org/job/coreboot-gerrit/buildTimeTrend)) + + +* [coreboot master build](https://qa.coreboot.org/job/coreboot/) + ([Time trend](https://qa.coreboot.org/job/coreboot/buildTimeTrend)) + + +### Stress test the machine + +Test the machine to make sure that building won't stress the hardware +too much. Install stress-ng, then run the stress test for at least an +hour. + +On a system with 32 cores, it was tested with this command: + +``` +$ stress-ng --cpu 20 --io 6 --vm 6 --vm-bytes 1G --verify --metrics-brief -t 60m +``` + +You can watch the temperature with the sensors package or with ‘acpi -t’ +if your machine supports that. + +You can check for thermal throttling by running this command and seeing +if the values go down on any of the cores after it's been running for a +while. + +``` +$ while [ true ]; do clear; cat /proc/cpuinfo | grep 'cpu MHz' ; sleep 1; done +``` + +If the machine throttles or resets, you probably need to upgrade the +cooling system. + + +## jenkins-server docker installation + + +### Manual Installation + +If you’ve met all the above requirements, and an admin has agreed to set +up the builder in jenkins, you’re ready to go on to the next steps. + + +### Set up your network so jenkins can talk to the container + +Expose a local port through any firewalls you might have on your router. +This would generally be in the port forwarding section, and you'd just +forward a port (typically 49151) from the internet directly to the +builder’s IP address. + +You might also want to set up a port to forward to port 22 on your +machine and set up openssh so you can manage the machine remotely. + + +### Install and set up docker + +Install docker by following the directions on the docker site. These +instructions keep changing, so just check the latest information. + +[https://docs.docker.com/engine/install/](https://docs.docker.com/engine/install/) + + +#### Set up environment variables + +To make configuration and the later commands easier, these should go in +your shell's .rc file. Note that you only need to set them if you're +using something other than the default. + +``` +# Set the port used on your machine to connect to jenkins. +export COREBOOT_JENKINS_PORT=49151 + +# Set the revision of the container from docker hub +export DOCKER_COMMIT=65718760fa + +# Set the location of where the jenkins cache directory will be. +export COREBOOT_JENKINS_CACHE_DIR="/srv/docker/coreboot-builder/cache" + +# Set the name of the container +export COREBOOT_JENKINS_CONTAINER="coreboot_jenkins" +``` + +Make sure any variables needed are set in your environment before +continuing to the next step. + + +### Using the Makefile for docker installation + +From the coreboot directory, run + +``` +make -C util/docker help +``` + +This will show you the available targets and variables needed: + +``` +Commands for working with docker images: + coreboot-sdk - Build coreboot-sdk container + upload-coreboot-sdk - Upload coreboot-sdk to hub.docker.com + coreboot-jenkins-node - Build coreboot-jenkins-node container + upload-coreboot-jenkins-node - Upload coreboot-jenkins-node to hub.docker.com + doc.coreboot.org - Build doc.coreboot.org container + clean-coreboot-containers - Remove all docker coreboot containers + clean-coreboot-images - Remove all docker coreboot images + docker-clean - Remove docker coreboot containers & images + +Commands for using docker images + docker-build-coreboot - Build coreboot under coreboot-sdk + <BUILD_CMD=target> + docker-abuild - Run abuild under coreboot-sdk + <ABUILD_ARGS='-a -B'> + docker-what-jenkins-does - Run 'what-jenkins-does' target + docker-shell - Bash prompt in coreboot-jenkins-node + <USER=root or USER=coreboot> + docker-jenkins-server - Run coreboot-jenkins-node image (for server) + docker-jenkins-attach - Open shell in running jenkins server + docker-build-docs - Build the documentation + docker-livehtml-docs - Run sphinx-autobuild + +Variables: + COREBOOT_JENKINS_PORT=49151 + COREBOOT_JENKINS_CACHE_DIR=/srv/docker/coreboot-builder/cache + COREBOOT_JENKINS_CONTAINER=coreboot_jenkins + COREBOOT_IMAGE_TAG=f2741aa632f + DOCKER_COMMIT=65718760fa +``` + +### Set up the system for the jenkins builder + +As a regular user - *Not root*, run: + +``` +sudo mkdir -p ${COREBOOT_JENKINS_CACHE_DIR} +sudo mkdir -p ${COREBOOT_JENKINS_CCACHE_DIR} +sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CCACHE_DIR} +sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CACHE_DIR} +wget http://www.dediprog.com/save/78.rar/to/EM100Pro.rar +mv EM100Pro.rar ${COREBOOT_JENKINS_CACHE_DIR} +``` + +### Install the coreboot jenkins builder + +``` +make -C util/docker docker-jenkins-server +``` + +Your installation is complete on your side. + +### Tell the Admins that the machine is set up +Let the admins know that the builder is set up so they can set up the +machine profile on qa.coreboot.org. + +They need to know: +* Your external IP address or domain name. If you don’t have a static +IP, make sure you have a dynamic dns hostname configured. +* The port on your machine and firewall that’s exposed for jenkins: +`$COREBOOT_JENKINS_PORT` +* The core count of the machine. +* How much memory is available on the machine. This helps determine +the amount of memory used for ccache. + + +### First build +On the first build after a machine is reset, it will frequently take +20-25 minutes to do the entire what-jenkins-does build while the ccache +is getting filled up and the entire coreboot repo gets downloaded. As +the ccache gets populated, the build time will drop. + + +## Additional Information + + +### How to log in to the docker instance for debugging +``` + $ make -C util/docker docker-jenkins-attach + $ su coreboot + $ cd ~/slave-root/workspace + $ bash +``` + + +WARNING: This should not be used to make changes to the build system, +but just to debug issues. Changes to the build system are highly +discouraged as it leads to situations where patches can pass the build +testing on one builder and fail on another builder. Any changes that are +made in the image will be lost on the next update, so if you +accidentally change something, you can remove the containers and images +and update to get a fresh installation. + + +### How to download containers/images for a fresh installation and remove old containers + +To delete the old containers & images: + +``` +$ docker stop $COREBOOT_JENKINS_CONTAINER +$ docker rm $COREBOOT_JENKINS_CONTAINER +$ docker images # lists all existing images +$ docker rmi XXXX # Use the image ID found in the above command. +``` + +To get and run the new coreboot-jenkins image, change the value in the +`DOCKER_COMMIT` variable to the new image value. + +``` +$ make -C util/docker docker-jenkins-server +``` + +#### Getting ready to push the docker images + +Set up an account on hub.docker.com + +Get an admin to add the account to the coreboot team on hub.docker.com + +[https://hub.docker.com/u/coreboot/dashboard/teams/?team=owners](https://hub.docker.com/u/coreboot/dashboard/teams/?team=owners) + +Make sure your credentials are configured on your host machine by +running + +``` +$ docker login +``` + +This will prompt you for your docker username, password, and your email +address, and write out to ~/.docker/config.json. Without this file, you +won’t be able to push the images. + +#### Updating the Dockerfiles: + +The coreboot-sdk Dockerfile will need to be updated when any additional +dependencies are added. Both the coreboot-sdk and the +coreboot-jenkins-node Dockerfiles will need to be updated to the new +version number and git commit id anytime the toolchain is updated. Both +files are stored in the coreboot repo under coreboot/util/docker. + +Read the [dockerfile best practices](https://docs.docker.com/v1.8/articles/dockerfile_best-practices/) +page before updating the files. + +#### Rebuilding the coreboot-sdk docker image to update the toolchain: + +``` +$ make -C util/docker coreboot-sdk +``` + +This takes a relatively long time. + +#### Test the coreboot-sdk docker image: + +There are two methods of running the docker image - interactively as a +shell, or doing the build directly. Running interactively as a shell is +useful for early testing, because it allows you to update the image +(without any changes getting saved) and re-test builds. This saves the +time of having to rebuild the image for every issue you find. + +#### Running the docker image interactively: + +Run: + +``` +$ make -C util/docker docker-jenkins-server +$ make -C util/docker docker-jenkins-attach +``` + +#### Running the build directly: + +From the coreboot directory: + +``` +$ make -C util/docker docker-build-coreboot +``` + +You’ll also want to test building the other projects and payloads: +ChromeEC, flashrom, memtest86+, em100, Grub2, SeaBIOS, iPXE, coreinfo, +nvramcui, tint... + +#### Pushing the coreboot-sdk image to hub.docker.com for use: + +When you’re satisfied with the testing, push the coreboot-sdk image to +the hub.docker.com + +``` +$ make -C util/docker upload-coreboot-sdk +``` + +#### Building and pushing the coreboot-jenkins-node docker image: + +This docker image is pretty simple, so there’s not really any testing +that needs to be done. + +``` +$ make -C util/docker coreboot-jenkins-node +$ make -C util/docker upload-coreboot-jenkins-node +``` + +### Coverity Setup + +To run coverity jobs, the builder needs to have the tools available, and +to be marked as a coverity builder. + + +#### Set up the Coverity tools + +Download the Linux-64 coverity build tool and decompress it into your +cache directory as defined by the `$COREBOOT_JENKINS_CACHE_DIR` variable + +[https://scan.coverity.com/download](https://scan.coverity.com/download) + +Rename the directory from its original name +(cov-analysis-linux64-7.7.0.4) to ‘coverity’, or better, create a +symlink: + +``` +ln -s cov-analysis-linux64-7.7.0.4 coverity +``` + + +Let the admins know that the ‘coverity’ label can be added to the +builder. -- To view, visit https://review.coreboot.org/c/coreboot/+/43984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54a0204e7525a25f2fd717a73007b304aac67396 Gerrit-Change-Number: 43984 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP: soc/amd/picasso/acpi: Add power resources for UART0
by Raul Rangel (Code Review) 23 Jan '21

23 Jan '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42474 ) Change subject: WIP: soc/amd/picasso/acpi: Add power resources for UART0 ...................................................................... WIP: soc/amd/picasso/acpi: Add power resources for UART0 BUG=b:153001807 TEST=suspend and resume with trembyle Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I73c4c7325f1c31238174795b7400eb244cdf8aec --- M src/soc/amd/picasso/acpi/aoac.asl M src/soc/amd/picasso/acpi/sb_fch.asl 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/42474/1 diff --git a/src/soc/amd/picasso/acpi/aoac.asl b/src/soc/amd/picasso/acpi/aoac.asl index 6577cfc..036ebc0 100644 --- a/src/soc/amd/picasso/acpi/aoac.asl +++ b/src/soc/amd/picasso/acpi/aoac.asl @@ -140,6 +140,7 @@ AOAC_DEVICE(I2C2, 7, 0) AOAC_DEVICE(I2C3, 8, 0) AOAC_DEVICE(I2C4, 9, 5) + AOAC_DEVICE(FUR0, 11, 0) AOAC_DEVICE(FUR1, 12, 0) AOAC_DEVICE(FUR2, 16, 0) AOAC_DEVICE(FUR3, 26, 0) diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 00774fd..cb186c4 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -122,6 +122,17 @@ Return (Local0) } } + Name (_PR0, Package () { \_SB.AOAC.FUR0 }) + Name (_PR2, Package () { \_SB.AOAC.FUR0 }) + Name (_PR3, Package () { \_SB.AOAC.FUR0 }) + Method (_PS0, 0, Serialized) { + Printf("FUR0._PS0") + \_SB.AOAC.FUR0.TDS = 1 + } + Method (_PS3, 0, Serialized) { + Printf("FUR0._PS3") + \_SB.AOAC.FUR0.TDS = 3 + } } Device (FUR1) { -- To view, visit https://review.coreboot.org/c/coreboot/+/42474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73c4c7325f1c31238174795b7400eb244cdf8aec Gerrit-Change-Number: 42474 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/getac/p470/acpi: Convert 'battery.asl' to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 22 Jan '21

22 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45554 ) Change subject: mb/getac/p470/acpi: Convert 'battery.asl' to ASL 2.0 syntax ...................................................................... mb/getac/p470/acpi: Convert 'battery.asl' to ASL 2.0 syntax Change-Id: Ifcc8bf4022838056bf1fff853eb2027af684064e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/getac/p470/acpi/battery.asl 1 file changed, 81 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/45554/1 diff --git a/src/mainboard/getac/p470/acpi/battery.asl b/src/mainboard/getac/p470/acpi/battery.asl index 7924edf..33b19ae 100644 --- a/src/mainboard/getac/p470/acpi/battery.asl +++ b/src/mainboard/getac/p470/acpi/battery.asl @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Scope(\_SB) { +Scope(_SB) { Name(NIMH, "NiMH") Name(LION, "Lion") @@ -10,7 +10,7 @@ Name(_HID, EisaId("PNP0C0A")) Name(_UID, 1) - Name(_PCL, Package(){ \_SB }) + Name(_PCL, Package(){ _SB }) Name(PBST, Package() { 0x00, 0x04b0, 0x0bb8, 0x03e8 }) @@ -18,7 +18,7 @@ Method(_STA, 0) { Sleep(120) - If(\_SB.PCI0.LPCB.EC0.BAT) { + If (^^PCI0.LPCB.EC0.BAT) { Return(0x1f) } Else { Return(0x0f) @@ -45,28 +45,28 @@ }) // Is battery there? - Store(_STA(), Local0) - And(Local0, 0x10, Local0) - If(LNot(Local0)) { + Local0 = _STA () + Local0 &= 0x10 + If (!Local0) { Return (PBIF) } - Store(\_SB.PCI0.LPCB.EC0.BDC0, Index(PBIF, 1)) - Store(\_SB.PCI0.LPCB.EC0.BDV0, Index(PBIF, 4)) + PBIF [1] = ^^PCI0.LPCB.EC0.BDC0 + PBIF [4] = ^^PCI0.LPCB.EC0.BDV0 - Store(\_SB.PCI0.LPCB.EC0.BFC0, Local0) - Store(Local0, Index(PBIF, 2)) + Local0 = ^^PCI0.LPCB.EC0.BFC0 + PBIF [2] = Local0 - Divide(Local0, 10, , Local2) - Store(Local2, Index(PBIF, 5)) + Local2 = Local0 / 10 + PBIF [5] = Local2 - Divide(Local0, 20, , Local2) - Store(Local2, Index(PBIF, 6)) + Local2 = Local0 / 20 + PBIF [6] = Local2 - If(\_SB.PCI0.LPCB.EC0.BTYP) { - Store(NIMH, Index(PBIF, 11)) + If (^^PCI0.LPCB.EC0.BTYP) { + PBIF [11] = NIMH } Else { - Store(LION, Index(PBIF, 11)) + PBIF [11] = LION } Return(PBIF) @@ -75,33 +75,35 @@ /* Battery Status */ Method(_BST, 0) { - If(\_SB.PCI0.LPCB.EC0.BAT) { - Store(\_SB.PCI0.LPCB.EC0.BPV0, Index(PBST, 3)) + If (^^PCI0.LPCB.EC0.BAT) { + PBST [3] = ^^PCI0.LPCB.EC0.BPV0 - Multiply(\_SB.PCI0.LPCB.EC0.BRC0, 100, Local3) - Divide(Local3, \_SB.PCI0.LPCB.EC0.BFC0, Local3, Local0) - Multiply(\_SB.PCI0.LPCB.EC0.BFC0, Local0, Local3) - Divide(Local3, 0x64, Local3, Local0) - Increment(Local0) - Store(Local0, Index(PBST, 2)) + Local3 = ^^PCI0.LPCB.EC0.BRC0 * 0x64 + Local0 = Local3 / ^^PCI0.LPCB.EC0.BFC0 + Local3 -= (Local0 * ^^PCI0.LPCB.EC0.BFC0) + Local3 = ^^PCI0.LPCB.EC0.BFC0 * Local0 + Local0 = Local3 / 0x64 + Local3 -= (Local0 * 0x64) + Local0++ + PBST [0x02] = Local0 - Store (\_SB.PCI0.LPCB.EC0.BRC0, Local3) - Store (\_SB.PCI0.LPCB.EC0.BPR0, Local0) - And (Not (Local0), 0xFFFF, Local0) - Store (Local0, Index(PBST,1)) + Local3 = ^^PCI0.LPCB.EC0.BRC0 + Local0 = ^^PCI0.LPCB.EC0.BPR0 + Local0 = (~Local0 & 0xFFFF) + PBST [1] = Local0 // AC Power connected? - If(\_SB.PCI0.LPCB.EC0.ADP) { - If(\_SB.PCI0.LPCB.EC0.CHRG) { - Store(2, Index(PBST, 0)) + If (^^PCI0.LPCB.EC0.ADP) { + If (^^PCI0.LPCB.EC0.CHRG) { + PBST [0] = 2 } Else { - Store(0, Index(PBST, 0)) + PBST [0] = 0 } } Else { - If(LLess(Local3, 25)) { - Store(5, Index(PBST, 0)) + If (Local3 < 25) { + PBST [0] = 5 } Else { - Store(1, Index(PBST, 0)) + PBST [0] = 0 } } } @@ -115,7 +117,7 @@ Name(_HID, EisaId("PNP0C0A")) Name(_UID, 1) - Name(_PCL, Package(){ \_SB }) + Name(_PCL, Package(){ _SB }) Name(PBST, Package() { 0x00, 0x04b0, 0x0bb8, 0x03e8 }) @@ -123,7 +125,7 @@ Method(_STA, 0) { Sleep(120) - If(\_SB.PCI0.LPCB.EC0.BAT2) { + If (^^PCI0.LPCB.EC0.BAT2) { Return(0x1f) } Else { Return(0x0f) @@ -150,28 +152,28 @@ }) // Is battery there? - Store(_STA(), Local0) - And(Local0, 0x10, Local0) - If(LNot(Local0)) { + Local0 = _STA () + Local0 &= 0x10 + If (!Local0) { Return (PBIF) } - Store(\_SB.PCI0.LPCB.EC0.BDC2, Index(PBIF, 1)) - Store(\_SB.PCI0.LPCB.EC0.BDV2, Index(PBIF, 4)) + PBIF [1] = ^^PCI0.LPCB.EC0.BDC2 + PBIF [0x04] = ^^PCI0.LPCB.EC0.BDV2 - Store(\_SB.PCI0.LPCB.EC0.BFC2, Local0) - Store(Local0, Index(PBIF, 2)) + Local0 = ^^PCI0.LPCB.EC0.BFC2 + PBIF [2] = Local0 - Divide(Local0, 10, , Local2) - Store(Local2, Index(PBIF, 5)) + Local2 = Local0 / 10 + PBIF [5] = Local2 - Divide(Local0, 20, , Local2) - Store(Local2, Index(PBIF, 6)) + Local2 = Local0 / 20 + PBIF [6] = Local2 - If(\_SB.PCI0.LPCB.EC0.BTY2) { - Store(NIMH, Index(PBIF, 11)) + If (^^PCI0.LPCB.EC0.BTY2) { + PBIF [11] = NIMH } Else { - Store(LION, Index(PBIF, 11)) + PBIF [11] = LION } Return(PBIF) @@ -180,33 +182,35 @@ /* Battery Status */ Method(_BST, 0) { - If(\_SB.PCI0.LPCB.EC0.BAT2) { - Store(\_SB.PCI0.LPCB.EC0.BPV2, Index(PBST, 3)) + If (^^PCI0.LPCB.EC0.BAT2) { + PBST [0x03] = ^^PCI0.LPCB.EC0.BPV2 - Multiply(\_SB.PCI0.LPCB.EC0.BRC2, 100, Local3) - Divide(Local3, \_SB.PCI0.LPCB.EC0.BFC2, Local3, Local0) - Multiply(\_SB.PCI0.LPCB.EC0.BFC2, Local0, Local3) - Divide(Local3, 0x64, Local3, Local0) - Increment(Local0) - Store(Local0, Index(PBST, 2)) + Local3 = ^^PCI0.LPCB.EC0.BRC2 * 100 + Local0 = Local3 / ^^PCI0.LPCB.EC0.BRC2 + Local3 -= (Local0 * ^^PCI0.LPCB.EC0.BRC2) + Local3 = ^^PCI0.LPCB.EC0.BFC2 * Local0 + Local0 = Local3 / 0x64 + Local3 -= (Local0 * 0x64) + Local0++ + PBST [2] = Local0 - Store (\_SB.PCI0.LPCB.EC0.BRC2, Local3) - Store (\_SB.PCI0.LPCB.EC0.BPR2, Local0) - And (Not (Local0), 0xFFFF, Local0) - Store (Local0, Index(PBST,1)) + Local3 = ^^PCI0.LPCB.EC0.BRC2 + Local0 = ^^PCI0.LPCB.EC0.BPR2 + Local0 = (~Local0 & 0xFFFF) + PBST [One] = Local0 // AC Power connected? - If(\_SB.PCI0.LPCB.EC0.ADP) { - If(\_SB.PCI0.LPCB.EC0.CRG2) { - Store(2, Index(PBST, 0)) + If (^^PCI0.LPCB.EC0.ADP) { + If (^^PCI0.LPCB.EC0.CRG2) { + PBST [0] = 2 } Else { - Store(0, Index(PBST, 0)) + PBST [0] = 0 } } Else { - If(LLess(Local3, 25)) { - Store(5, Index(PBST, 0)) + If (Local3 < 25) { + PBST [0] = 5 } Else { - Store(1, Index(PBST, 0)) + PBST [0] = 1 } } } @@ -223,19 +227,19 @@ Name (ACST, 0x00) Method (_PSR, 0) { - If(ACFG) { - Store(ACST, Local0) + If (ACFG) { + Local0 = ACST } Else { - Store(\_SB.PCI0.LPCB.EC0.ADP, Local0) - Store(Local0, ACST) - Store(1, ACFG) + Local0 = ^^PCI0.LPCB.EC0.ADP + ACST = Local0 + ACFG = 1 } Sleep(120) Return (Local0) } Name(_PCL, Package(){ - \_SB, + _SB, BAT0, BAT1 }) -- To view, visit https://review.coreboot.org/c/coreboot/+/45554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcc8bf4022838056bf1fff853eb2027af684064e Gerrit-Change-Number: 45554 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/igd.c: Add missing "break"
by HAOUAS Elyes (Code Review) 21 Jan '21

21 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45165 ) Change subject: soc/intel/broadwell/igd.c: Add missing "break" ...................................................................... soc/intel/broadwell/igd.c: Add missing "break" Change-Id: I29dd96a7e00ddf73bb281e6fbbf256e439bce2f1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/broadwell/igd.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/45165/1 diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 41167b1..39c551d 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -467,6 +467,7 @@ dpdiv = 338; reg_em4 = 8; reg_em5 = 225; + break; default: return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29dd96a7e00ddf73bb281e6fbbf256e439bce2f1 Gerrit-Change-Number: 45165 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/mrc_cache.c: Remove unused <bootstate.h>
by HAOUAS Elyes (Code Review) 21 Jan '21

21 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45816 ) Change subject: soc/amd/picasso/mrc_cache.c: Remove unused <bootstate.h> ...................................................................... soc/amd/picasso/mrc_cache.c: Remove unused <bootstate.h> Change-Id: Ied235972d24276d7c88a2f50f192d69d24ae6e05 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/picasso/mrc_cache.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/45816/1 diff --git a/src/soc/amd/picasso/mrc_cache.c b/src/soc/amd/picasso/mrc_cache.c index ad0d964..24d86e0 100644 --- a/src/soc/amd/picasso/mrc_cache.c +++ b/src/soc/amd/picasso/mrc_cache.c @@ -3,7 +3,6 @@ #include <acpi/acpi.h> #include <assert.h> #include <boot_device.h> -#include <bootstate.h> #include <commonlib/region.h> #include <console/console.h> #include <fmap.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied235972d24276d7c88a2f50f192d69d24ae6e05 Gerrit-Change-Number: 45816 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/mediatek/mt8192: Save dramc shuffle result after calibration
by CK HU (Code Review) 19 Jan '21

19 Jan '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44714 to review the following change. Change subject: soc/mediatek/mt8192: Save dramc shuffle result after calibration ...................................................................... soc/mediatek/mt8192: Save dramc shuffle result after calibration Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Icfd0923d4bd34ebb082e00e87f262b0d908fe342 --- M src/soc/mediatek/mt8192/dramc_dvfs.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 87 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44714/1 diff --git a/src/soc/mediatek/mt8192/dramc_dvfs.c b/src/soc/mediatek/mt8192/dramc_dvfs.c index ce24829..67e2340 100644 --- a/src/soc/mediatek/mt8192/dramc_dvfs.c +++ b/src/soc/mediatek/mt8192/dramc_dvfs.c @@ -111,3 +111,85 @@ *(cali->pll_mode) = pll_mode; } +void dramc_save_result_to_shuffle(dram_dfs_shu src, dram_dfs_shu dst) +{ + u8 tmp; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_SLV_SEL, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_STEP_EN_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SRAM_WR_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_WR_MODE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_SHU_LEVEL_APB, src); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM, dst); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 1); + do { + tmp = READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_SRAM_DONE); + tmp |= (READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_APB_DONE) << 1); + dramc_dbg("wait dramc to shuffle sram done, tmp:%d.\n", tmp); + } while (tmp != 0x3); + + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_STEP_EN_MODE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_MODE, 0); + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SRAM_WR_MODE, 0); +} + +void dramc_load_shuffle_to_dramc(dram_dfs_shu src, dram_dfs_shu dst) +{ + u8 tmp; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_SLV_SEL, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_STEP_EN_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SRAM_WR_MODE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_WR_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_SHU_LEVEL_APB, dst); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM, src); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 1); + do { + tmp = READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_SRAM_DONE); + tmp |= (READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_APB_DONE)<< 1); + dramc_dbg("wait shuffle sram to dramc done.\n"); + } while (tmp != 0x3); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_STEP_EN_MODE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_MODE, 0); + } +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 5ca7bce..3273f28 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -290,6 +290,11 @@ get_dram_info_after_cal(&cali); dramc_ac_timing_optimize(&cali); + dramc_save_result_to_shuffle(DRAM_DFS_SHU0, cali.shu); + + /* for frequency switch in dramc_mode_reg_init phase */ + if (first_freq_k) + dramc_load_shuffle_to_dramc(cali.shu, DRAM_DFS_SHU1); first_freq_k= false; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfd0923d4bd34ebb082e00e87f262b0d908fe342 Gerrit-Change-Number: 44714 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

6 12

Change in coreboot[master]: soc/mediatek/mt8192: Add dramc ac timing setting
by CK HU (Code Review) 19 Jan '21

19 Jan '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44713 to review the following change. Change subject: soc/mediatek/mt8192: Add dramc ac timing setting ...................................................................... soc/mediatek/mt8192: Add dramc ac timing setting Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I10e704868e4cd36a938a669879bb1a8632e73e1a --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c A src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h 3 files changed, 1,320 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/44713/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 31e8d0e..1a5f242 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -3,6 +3,7 @@ #include <soc/gpio.h> #include <soc/dramc_pi_api.h> #include <soc/dramc_register.h> +#include <soc/dramc_ac_timing.h> #include <string.h> #include <timer.h> @@ -4030,6 +4031,206 @@ dramc_set_broadcast(bc_bak); } +static void ddr_update_ac_timing(const struct ddr_cali *cali) +{ + u8 table_idx; + struct ac_timing ac_tim; + dram_freq_grp freq_group = cali->freq_group; + + u8 rank_inctl = 0, tx_dly = 0, datlat_dsel = 0; + u8 rodt_tracking_mck = 0, root = 0, tx_rank_inctl = 0; + u8 tref_bw = 0, tfaw_05t=0, trrd_05t=0; + u16 xrtwtw = 0, xtrtrt = 0, xrtw2r = 0, xrtr2w = 0, tfaw = 0; + u16 trtw=0, trtw_05t=0, tmrr2w=0, trrd=0; + u16 phs_inctl = 0; + u32 rank_inctl_root; + + for (table_idx = 0; table_idx < AC_TIMING_NUMBER; table_idx++) + if ((ac_timing_tbl[table_idx].freq_group == freq_group) && + (ac_timing_tbl[table_idx].div_mode == get_div_mode(cali)) && + (ac_timing_tbl[table_idx].cbt_mode == get_cbt_mode(cali))) { + dramc_dbg("match AC timing table %d\n", table_idx); + break; + } + + if (table_idx == AC_TIMING_NUMBER) { + dramc_dbg("Error, no match AC timing table\n"); + return; + } + memcpy(&ac_tim, &ac_timing_tbl[table_idx], sizeof(struct ac_timing)); + + trtw = ac_tim.trtw_odt_on; + trtw_05t = ac_tim.trtw_odt_on_05T; + xrtw2r = ac_tim.xrtw2r_odt_on; + xrtr2w = ac_tim.xrtr2w_odt_on; + tfaw = ac_tim.tfaw_4266; + tfaw_05t = ac_tim.tfaw_4266_05T; + trrd = ac_tim.trrd_4266; + trrd_05t = ac_tim.trrd_4266_05T; + xtrtrt = ac_tim.xrtr2r_new_mode; + xrtwtw = ac_tim.xrtw2w_new_mode; + tmrr2w = ac_tim.tmrr2w_odt_on; + rodt_tracking_mck = 0; + trtw = trtw - rodt_tracking_mck; + xrtr2w = xrtr2w - rodt_tracking_mck; + + if (READ32_BITFIELD(&ch[0].phy_ao.shu_misc_rx_pipe_ctrl, + SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN)) + datlat_dsel = ac_tim.datlat; + else + datlat_dsel = ac_tim.datlat - 1; + + if (ac_tim.dqsinctl >= 2) { + rank_inctl_root = ac_tim.dqsinctl - 2; + } else { + dramc_info("rank_inctl_root <2, need check\n"); + rank_inctl_root = 0; + } + phs_inctl = (ac_tim.dqsinctl == 0) ? 0 : (ac_tim.dqsinctl - 1); + + if (freq_group <= DDRFREQ_800) { + if (get_div_mode(cali) == DIV4_MODE) { + tx_rank_inctl = 1; + tx_dly = 2; + } else { + tx_rank_inctl = 0; + tx_dly = 1; + } + } else { + tx_rank_inctl = 1; + tx_dly = 2; + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.shu_actim1, + SHU_ACTIM1_TRAS, ac_tim.tras, + SHU_ACTIM1_TRP, ac_tim.trp, + SHU_ACTIM1_TRPAB, ac_tim.trpab, + SHU_ACTIM1_TMRWCKEL, ac_tim.tmrwckel, + SHU_ACTIM1_TRC, ac_tim.trc); + SET32_BITFIELDS(&ch[chn].ao.shu_actim3, + SHU_ACTIM3_TRFC, ac_tim.trfc, + SHU_ACTIM3_TR2MRR, ac_tim.tr2mrr, + SHU_ACTIM3_TRFCPB, ac_tim.trfcpb); + SET32_BITFIELDS(&ch[chn].ao.shu_actim2, + SHU_ACTIM2_TXP, ac_tim.txp, + SHU_ACTIM2_TMRRI, ac_tim.tmrri, + SHU_ACTIM2_TFAW, tfaw, + SHU_ACTIM2_TR2W, trtw, + SHU_ACTIM2_TRTP, ac_tim.trtp); + SET32_BITFIELDS(&ch[chn].ao.shu_actim0, + SHU_ACTIM0_TRCD, ac_tim.trcd, + SHU_ACTIM0_TWR, ac_tim.twr, + SHU_ACTIM0_TRRD, trrd); + SET32_BITFIELDS(&ch[chn].ao.shu_actim5, + SHU_ACTIM5_TPBR2PBR, ac_tim.tpbr2pbr, + SHU_ACTIM5_TWTPD, ac_tim.twtpd, + SHU_ACTIM5_TPBR2ACT, ac_tim.tpbr2act); + SET32_BITFIELDS(&ch[chn].ao.shu_actim6, + SHU_ACTIM6_TR2MRW, ac_tim.tr2mrw, + SHU_ACTIM6_TW2MRW, ac_tim.tw2mrw, + SHU_ACTIM6_TMRD, ac_tim.tmrd, + SHU_ACTIM6_TZQLAT2, ac_tim.zqlat2, + SHU_ACTIM6_TMRW, ac_tim.tmrw); + SET32_BITFIELDS(&ch[chn].ao.shu_actim4, + SHU_ACTIM4_TMRR2MRW, ac_tim.tmrr2mrw, + SHU_ACTIM4_TMRR2W, tmrr2w, + SHU_ACTIM4_TZQCS, ac_tim.tzqcs, + SHU_ACTIM4_TXREFCNT, ac_tim.txrefcnt); + SET32_BITFIELDS(&ch[chn].ao.shu_ckectrl, SHU_CKECTRL_TCKEPRD, ac_tim.ckeprd); + SET32_BITFIELDS(&ch[chn].ao.shu_actim_xrt, + SHU_ACTIM_XRT_XRTW2W, xrtwtw, + SHU_ACTIM_XRT_XRTW2R, xrtw2r, + SHU_ACTIM_XRT_XRTR2W, xrtr2w, + SHU_ACTIM_XRT_XRTR2R, xtrtrt); + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_vrcg, + SHU_HWSET_VRCG_VRCGDIS_PRDCNT, ac_tim.vrcgdis_prdcnt); + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr2, + SHU_HWSET_MR2_HWSET_MR2_OP, ac_tim.hwset_mr2_op); + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr13, + SHU_HWSET_MR13_HWSET_MR13_OP, ac_tim.hwset_mr13_op); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TWTR_M05T, ac_tim.twtr_05T, + SHU_AC_TIME_05T_TR2W_05T, trtw_05t, + SHU_AC_TIME_05T_TWTPD_M05T, ac_tim.twtpd_05T, + SHU_AC_TIME_05T_TFAW_05T, tfaw_05t, + SHU_AC_TIME_05T_TRRD_05T, trrd_05t, + SHU_AC_TIME_05T_TWR_M05T, ac_tim.twr_05T, + SHU_AC_TIME_05T_TRAS_05T, ac_tim.tras_05T, + SHU_AC_TIME_05T_TRPAB_05T, ac_tim.trpab_05T, + SHU_AC_TIME_05T_TRP_05T, ac_tim.trp_05T, + SHU_AC_TIME_05T_TRCD_05T, ac_tim.trcd_05T, + SHU_AC_TIME_05T_TRTP_05T, ac_tim.trtp_05T, + SHU_AC_TIME_05T_TXP_05T, ac_tim.txp_05T); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TRFC_05T, ac_tim.trfc_05T, + SHU_AC_TIME_05T_TRFCPB_05T, ac_tim.trfcpb_05T, + SHU_AC_TIME_05T_TPBR2PBR_05T, ac_tim.tpbr2pbr_05T, + SHU_AC_TIME_05T_TPBR2ACT_05T, ac_tim.tpbr2act_05T, + SHU_AC_TIME_05T_TR2MRW_05T, ac_tim.tr2mrw_05T, + SHU_AC_TIME_05T_TW2MRW_05T, ac_tim.tw2mrw_05T, + SHU_AC_TIME_05T_TMRR2MRW_05T, ac_tim.tmrr2mrw_05T, + SHU_AC_TIME_05T_TMRW_05T, ac_tim.tmrw_05T, + SHU_AC_TIME_05T_TMRD_05T, ac_tim.tmrd_05T, + SHU_AC_TIME_05T_TMRWCKEL_05T, ac_tim.tmrwckel_05T, + SHU_AC_TIME_05T_TMRRI_05T, ac_tim.tmrri_05T, + SHU_AC_TIME_05T_TRC_05T, ac_tim.trc_05T); + SET32_BITFIELDS(&ch[chn].ao.shu_actim0, SHU_ACTIM0_TWTR, ac_tim.twtr); + SET32_BITFIELDS(&ch[chn].ao.shu_ckectrl, + SHU_CKECTRL_TPDE, ac_tim.tpde, + SHU_CKECTRL_TPDX, ac_tim.tpdx, + SHU_CKECTRL_TPDE_05T, ac_tim.tpde_05T, + SHU_CKECTRL_TPDX_05T, ac_tim.tpdx_05T); + SET32_BITFIELDS(&ch[chn].ao.shu_actim5, SHU_ACTIM5_TR2PD, ac_tim.trtpd); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TR2PD_05T, ac_tim.trtpd_05T); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating0, + SHU_AC_DERATING0_TRCD_DERATE, ac_tim.trcd_derate, + SHU_AC_DERATING0_TRRD_DERATE, ac_tim.trrd_derate); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating1, + SHU_AC_DERATING1_TRC_DERATE, ac_tim.trc_derate, + SHU_AC_DERATING1_TRAS_DERATE, ac_tim.tras_derate, + SHU_AC_DERATING1_TRP_DERATE, ac_tim.trp_derate, + SHU_AC_DERATING1_TRPAB_DERATE, ac_tim.trpab_derate); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating_05t, + SHU_AC_DERATING_05T_TRRD_05T_DERATE, ac_tim.trrd_derate_05T, + SHU_AC_DERATING_05T_TRAS_05T_DERATE, ac_tim.tras_derate_05T, + SHU_AC_DERATING_05T_TRPAB_05T_DERATE, ac_tim.trpab_derate_05T, + SHU_AC_DERATING_05T_TRP_05T_DERATE, ac_tim.trp_derate_05T, + SHU_AC_DERATING_05T_TRCD_05T_DERATE, ac_tim.trcd_derate_05T, + SHU_AC_DERATING_05T_TRC_05T_DERATE, ac_tim.trc_derate_05T); + SET32_BITFIELDS(&ch[chn].ao.refctrl3, REFCTRL3_REF_DERATING_EN, 0xc0); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating0, + SHU_AC_DERATING0_ACDERATEEN, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rk[0].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, ac_tim.dqsinctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rk[1].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, ac_tim.dqsinctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_odtctrl, + MISC_SHU_ODTCTRL_RODT_LAT, ac_tim.dqsinctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_PHY, ac_tim.dqsinctl, + MISC_SHU_RANKCTL_RANKINCTL_ROOT1, rank_inctl_root, + MISC_SHU_RANKCTL_RANKINCTL, rank_inctl_root); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_rank_sel_stb, + SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, phs_inctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rdat, + MISC_SHU_RDAT_DATLAT, ac_tim.datlat, + MISC_SHU_RDAT_DATLAT_DSEL, datlat_dsel, + MISC_SHU_RDAT_DATLAT_DSEL_PHY, datlat_dsel); + SET32_BITFIELDS(&ch[chn].ao.shu_actiming_conf, + SHU_ACTIMING_CONF_REFBW_FR, tref_bw); + rank_inctl = READ32_BITFIELD(&ch[0].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_RXDLY, rank_inctl); + SET32_BITFIELDS(&ch[chn].ao.shu_tx_rankctl, + SHU_TX_RANKCTL_TXRANKINCTL_ROOT, root, + SHU_TX_RANKCTL_TXRANKINCTL, tx_rank_inctl, + SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, tx_dly); + } +} + static void set_cke2rank_independent(void) { for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { @@ -4121,6 +4322,8 @@ dramc_8_phase_cal(cali); dramc_duty_calibration(cali->params); dramc_mode_reg_init(cali); + + ddr_update_ac_timing(cali); } static void dramc_before_calibration(const struct ddr_cali *cali) diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index cf199dc..5ca7bce 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -6,6 +6,151 @@ #include <soc/pll_common.h> #include <soc/mt6359p.h> +static void dramc_ac_timing_optimize(const struct ddr_cali* cali) +{ + u8 rf_group = 0, cab_id = 0; + u8 trfc, trfc_05t, trfc_pb, trfrc_pb05t, tx_ref_cnt; + + enum { + tRFCAB_130, + tRFCAB_180, + tRFCAB_280, + tRFCAB_380, + tRFCAB_NUM + }; + enum { + GRP_DDR800_DIV4_ACTIM, + GRP_DDR1200_ACTIM, + GRP_DDR1600_ACTIM, + GRP_DDR1866_ACTIM, + GRP_DDR2400_ACTIM, + GRP_DDR3200_ACTIM, + GRP_DDR4266_ACTIM, + GRP_ACTIM_NUM + }; + struct optimize_ac_time { + u8 trfc; + u8 trfc_05t; + u8 trfc_pb; + u8 trfrc_pb05t; + u16 tx_ref_cnt; + }; + + u8 density = cali->density; + dram_freq_grp freq_group = get_freq_group(cali); + + struct optimize_ac_time *ptRFCab_Opt; + struct optimize_ac_time tRFCab_Opt [GRP_ACTIM_NUM][tRFCAB_NUM] = { + [GRP_DDR800_DIV4_ACTIM] = { + {.trfc = 14, .trfc_05t = 0, .trfc_pb = 0, .trfrc_pb05t = 0, .tx_ref_cnt = 28}, + {.trfc = 24, .trfc_05t = 0, .trfc_pb = 6, .trfrc_pb05t = 0, .tx_ref_cnt = 38}, + {.trfc = 44, .trfc_05t = 0, .trfc_pb = 16, .trfrc_pb05t = 0, .tx_ref_cnt = 58}, + {.trfc = 64, .trfc_05t = 0, .trfc_pb = 26, .trfrc_pb05t = 0, .tx_ref_cnt = 78} + }, + [GRP_DDR1200_ACTIM] = { + {.trfc = 8, .trfc_05t = 0, .trfc_pb = 0, .trfrc_pb05t = 0, .tx_ref_cnt = 21}, + {.trfc = 15, .trfc_05t = 1, .trfc_pb = 2, .trfrc_pb05t = 0, .tx_ref_cnt = 29}, + {.trfc = 30, .trfc_05t = 1, .trfc_pb = 9, .trfrc_pb05t = 1, .tx_ref_cnt = 44}, + {.trfc = 45, .trfc_05t = 1, .trfc_pb = 17, .trfrc_pb05t = 0, .tx_ref_cnt = 59} + }, + [GRP_DDR1600_ACTIM] = { + {.trfc = 14, .trfc_05t = 0, .trfc_pb = 0, .trfrc_pb05t = 0, .tx_ref_cnt = 28}, + {.trfc = 24, .trfc_05t = 0, .trfc_pb = 6, .trfrc_pb05t = 0, .tx_ref_cnt = 38}, + {.trfc = 44, .trfc_05t = 0, .trfc_pb = 16, .trfrc_pb05t = 0, .tx_ref_cnt = 58}, + {.trfc = 64, .trfc_05t = 0, .trfc_pb = 26, .trfrc_pb05t = 0, .tx_ref_cnt = 78} + }, + [GRP_DDR1866_ACTIM] = { + {.trfc = 18, .trfc_05t = 1, .trfc_pb = 2, .trfrc_pb05t = 0, .tx_ref_cnt = 33}, + {.trfc = 30, .trfc_05t = 0, .trfc_pb = 9, .trfrc_pb05t = 0, .tx_ref_cnt = 44}, + {.trfc = 53, .trfc_05t = 1, .trfc_pb = 21, .trfrc_pb05t = 0, .tx_ref_cnt = 68}, + {.trfc = 77, .trfc_05t = 0, .trfc_pb = 32, .trfrc_pb05t = 1, .tx_ref_cnt = 91} + }, + [GRP_DDR2400_ACTIM] = { + {.trfc = 27, .trfc_05t = 1, .trfc_pb = 6, .trfrc_pb05t = 1, .tx_ref_cnt = 42}, + {.trfc = 42, .trfc_05t = 1, .trfc_pb = 15, .trfrc_pb05t = 1, .tx_ref_cnt = 57}, + {.trfc = 72, .trfc_05t = 1, .trfc_pb = 30, .trfrc_pb05t = 1, .tx_ref_cnt = 87}, + {.trfc = 102, .trfc_05t = 1, .trfc_pb = 45, .trfrc_pb05t = 1, .tx_ref_cnt = 117} + }, + [GRP_DDR3200_ACTIM] = { + {.trfc = 40, .trfc_05t = 0, .trfc_pb = 12, .trfrc_pb05t = 0, .tx_ref_cnt = 55}, + {.trfc = 60, .trfc_05t = 0, .trfc_pb = 24, .trfrc_pb05t = 0, .tx_ref_cnt = 75}, + {.trfc = 100, .trfc_05t = 0, .trfc_pb = 44, .trfrc_pb05t = 0, .tx_ref_cnt = 115}, + {.trfc = 140, .trfc_05t = 0, .trfc_pb = 64, .trfrc_pb05t = 0, .tx_ref_cnt = 155} + }, + [GRP_DDR4266_ACTIM] = { + {.trfc = 57, .trfc_05t = 1, .trfc_pb = 20, .trfrc_pb05t = 0, .tx_ref_cnt = 74}, + {.trfc = 84, .trfc_05t = 0, .trfc_pb = 36, .trfrc_pb05t = 0, .tx_ref_cnt = 100}, + {.trfc = 137, .trfc_05t = 1, .trfc_pb = 63, .trfrc_pb05t = 0, .tx_ref_cnt = 154}, + {.trfc = 191, .trfc_05t = 0, .trfc_pb = 89, .trfrc_pb05t = 1, .tx_ref_cnt = 207} + } + }; + + switch (density) { + case 0x0: + rf_group = tRFCAB_130; + break; + case 0x1: + case 0x2: + rf_group = tRFCAB_180; + break; + case 0x3: + case 0x4: + rf_group = tRFCAB_280; + break; + case 0x5: + case 0x6: + rf_group = tRFCAB_380; + break; + default: + die("Invalid DDR density %u\n", density); + return; + } + + switch (freq_group) { + case DDRFREQ_400: + cab_id = GRP_DDR800_DIV4_ACTIM; + break; + case DDRFREQ_600: + cab_id = GRP_DDR1200_ACTIM; + break; + case DDRFREQ_800: + cab_id = GRP_DDR1600_ACTIM; + break; + case DDRFREQ_933: + cab_id = GRP_DDR1866_ACTIM; + break; + case DDRFREQ_1200: + cab_id = GRP_DDR2400_ACTIM; + break; + case DDRFREQ_1600: + cab_id = GRP_DDR3200_ACTIM; + break; + case DDRFREQ_2133: + cab_id = GRP_DDR4266_ACTIM; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + ptRFCab_Opt = &tRFCab_Opt[cab_id][0]; + trfc = ptRFCab_Opt[rf_group].trfc; + trfc_05t = ptRFCab_Opt[rf_group].trfc_05t; + trfc_pb = ptRFCab_Opt[rf_group].trfc_pb; + trfrc_pb05t = ptRFCab_Opt[rf_group].trfrc_pb05t; + tx_ref_cnt = ptRFCab_Opt[rf_group].tx_ref_cnt; + + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.shu_actim3, SHU_ACTIM3_TRFC, trfc); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, SHU_AC_TIME_05T_TRFC_05T, trfc_05t); + SET32_BITFIELDS(&ch[chn].ao.shu_actim4, SHU_ACTIM4_TXREFCNT, tx_ref_cnt); + SET32_BITFIELDS(&ch[chn].ao.shu_actim3, SHU_ACTIM3_TRFCPB, trfc_pb); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, SHU_AC_TIME_05T_TRFCPB_05T, trfrc_pb05t); + dramc_dbg("Density (MR8 OP[5:2]) %d, TRFC %d, TRFC_05T %d, TXREFCNT %d, TRFCpb %d, TRFCpb_05T %d\n", + density, trfc, trfc_05t, tx_ref_cnt, trfc_pb, trfrc_pb05t); + } +} + static void set_vcore_voltage_for_each_freq(const struct ddr_cali *cali) { u32 vcore = get_vcore_value(cali); @@ -144,6 +289,8 @@ if (first_freq_k) get_dram_info_after_cal(&cali); + dramc_ac_timing_optimize(&cali); + first_freq_k= false; } } diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h b/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h new file mode 100644 index 0000000..717d247 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h @@ -0,0 +1,970 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__ +#define __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__ + +#include <stdint.h> +#include <sys/types.h> +#include <soc/dramc_common_mt8192.h> + +/* Normal Mode and Byte Mode */ +#define AC_TIMING_NUMBER (DDRFREQ_MAX * 2) + +struct ac_timing { + u8 cbt_mode, read_dbi; + u8 div_mode; + u16 freq_group; + u16 read_lat, write_lat; + u16 dqsinctl, datlat; + u16 tras; + u16 trp; + u16 trpab; + u16 trc; + u16 trfc; + u16 trfcpb; + u16 txp; + u16 trtp; + u16 trcd; + u16 twr; + u16 twtr; + u16 tpbr2pbr; + u16 tpbr2act; + u16 tr2mrw; + u16 tw2mrw; + u16 tmrr2mrw; + u16 tmrw; + u16 tmrd; + u16 tmrwckel; + u16 tpde; + u16 tpdx; + u16 tmrri; + u16 trrd; + u16 trrd_4266; + u16 tfaw; + u16 tfaw_4266; + u16 trtw_odt_off; + u16 trtw_odt_on; + u16 txrefcnt; + u16 tzqcs; + u16 xrtw2w_new_mode; + u16 xrtw2w_old_mode; + u16 xrtw2r_odt_on; + u16 xrtw2r_odt_off; + u16 xrtr2w_odt_on; + u16 xrtr2w_odt_off; + u16 xrtr2r_new_mode; + u16 xrtr2r_old_mode; + u16 tr2mrr; + u16 vrcgdis_prdcnt; + u16 hwset_mr2_op; + u16 hwset_mr13_op; + u16 hwset_vrcg_op; + u16 trcd_derate; + u16 trc_derate; + u16 tras_derate; + u16 trpab_derate; + u16 trp_derate; + u16 trrd_derate; + u16 trtpd; + u16 twtpd; + u16 tmrr2w_odt_off; + u16 tmrr2w_odt_on; + u16 ckeprd; + u16 ckelckcnt; + u16 zqlat2; + u16 tras_05T; + u16 trp_05T; + u16 trpab_05T; + u16 trc_05T; + u16 trfc_05T; + u16 trfcpb_05T; + u16 txp_05T; + u16 trtp_05T; + u16 trcd_05T; + u16 twr_05T; + u16 twtr_05T; + u16 tpbr2pbr_05T; + u16 tpbr2act_05T; + u16 tr2mrw_05T; + u16 tw2mrw_05T; + u16 tmrr2mrw_05T; + u16 tmrw_05T; + u16 tmrd_05T; + u16 tmrwckel_05T; + u16 tpde_05T; + u16 tpdx_05T; + u16 tmrri_05T; + u16 trrd_05T; + u16 trrd_4266_05T; + u16 tfaw_05T; + u16 tfaw_4266_05T; + u16 trtw_odt_off_05T; + u16 trtw_odt_on_05T; + u16 trcd_derate_05T; + u16 trc_derate_05T; + u16 tras_derate_05T; + u16 trpab_derate_05T; + u16 trp_derate_05T; + u16 trrd_derate_05T; + u16 trtpd_05T; + u16 twtpd_05T; +}; + +/* Normal Mode and Byte Mode for each frequency */ +static const struct ac_timing ac_timing_tbl[AC_TIMING_NUMBER] = { + { + .freq_group = DDRFREQ_2133, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 36, .write_lat = 18, .div_mode = DIV8_MODE, + .tras = 14, .tras_05T = 0, + .trp = 8, .trp_05T = 1, + .trpab = 10, .trpab_05T = 0, + .trc = 23, .trc_05T = 0, + .trfc = 137, .trfc_05T = 1, + .trfcpb = 63, .trfcpb_05T = 0, + .txp = 1, .txp_05T = 0, + .trtp = 2, .trtp_05T = 1, + .trcd = 10, .trcd_05T = 0, + .twr = 15, .twr_05T = 0, + .twtr = 10, .twtr_05T = 1, + .tpbr2pbr = 41, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 17, .tr2mrw_05T = 0, + .tw2mrw = 11, .tw2mrw_05T = 0, + .tmrr2mrw = 14, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 8, .tmrd_05T = 0, + .tmrwckel = 9, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 14, .tmrri_05T = 0, + .trrd = 4, .trrd_05T = 1, + .trrd_4266 = 3, .trrd_4266_05T = 0, + .tfaw = 13, .tfaw_05T = 1, + .tfaw_4266 = 8, .tfaw_4266_05T = 0, + .trtw_odt_off = 6, .trtw_odt_off_05T = 0, + .trtw_odt_on = 8, .trtw_odt_on_05T = 0, + .txrefcnt = 154, + .tzqcs = 46, + .xrtw2w_new_mode = 5, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 7, + .xrtr2w_odt_off = 7, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 54, + .hwset_mr2_op = 63, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 11, .trcd_derate_05T = 0, + .trc_derate = 26, .trc_derate_05T = 0, + .tras_derate = 15, .tras_derate_05T = 0, + .trpab_derate = 11, .trpab_derate_05T = 0, + .trp_derate = 9, .trp_derate_05T = 1, + .trrd_derate = 5, .trrd_derate_05T = 1, + .trtpd = 14, .trtpd_05T = 1, + .twtpd = 18, .twtpd_05T = 0, + .tmrr2w_odt_off = 10, + .tmrr2w_odt_on = 12, + .ckeprd = 3, + .ckelckcnt = 3, + .zqlat2 = 16, + .dqsinctl = 7, .datlat = 18 + }, + { + .freq_group = DDRFREQ_2133, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 40, .write_lat = 18, .div_mode = DIV8_MODE, + .tras = 14, .tras_05T = 0, + .trp = 8, .trp_05T = 1, + .trpab = 10, .trpab_05T = 0, + .trc = 23, .trc_05T = 0, + .trfc = 137, .trfc_05T = 1, + .trfcpb = 63, .trfcpb_05T = 0, + .txp = 1, .txp_05T = 0, + .trtp = 2, .trtp_05T = 1, + .trcd = 10, .trcd_05T = 0, + .twr = 16, .twr_05T = 0, + .twtr = 11, .twtr_05T = 1, + .tpbr2pbr = 41, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 18, .tr2mrw_05T = 0, + .tw2mrw = 11, .tw2mrw_05T = 0, + .tmrr2mrw = 15, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 8, .tmrd_05T = 0, + .tmrwckel = 9, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 14, .tmrri_05T = 0, + .trrd = 4, .trrd_05T = 1, + .trrd_4266 = 3, .trrd_4266_05T = 0, + .tfaw = 13, .tfaw_05T = 1, + .tfaw_4266 = 8, .tfaw_4266_05T = 0, + .trtw_odt_off = 7, .trtw_odt_off_05T = 0, + .trtw_odt_on = 9, .trtw_odt_on_05T = 0, + .txrefcnt = 154, + .tzqcs = 46, + .xrtw2w_new_mode = 5, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 8, + .xrtr2w_odt_off = 8, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 54, + .hwset_mr2_op = 63, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 11, .trcd_derate_05T = 0, + .trc_derate = 26, .trc_derate_05T = 0, + .tras_derate = 15, .tras_derate_05T = 0, + .trpab_derate = 11, .trpab_derate_05T = 0, + .trp_derate = 9, .trp_derate_05T = 1, + .trrd_derate = 5, .trrd_derate_05T = 1, + .trtpd = 15, .trtpd_05T = 1, + .twtpd = 19, .twtpd_05T = 0, + .tmrr2w_odt_off = 11, + .tmrr2w_odt_on = 13, + .ckeprd = 3, + .ckelckcnt = 3, + .zqlat2 = 16, + .dqsinctl = 7, .datlat = 18 + }, + { + .freq_group = DDRFREQ_1600, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 28, .write_lat = 14, .div_mode = DIV8_MODE, + .tras = 8, .tras_05T = 1, + .trp = 6, .trp_05T = 0, + .trpab = 7, .trpab_05T = 0, + .trc = 15, .trc_05T = 0, + .trfc = 100, .trfc_05T = 0, + .trfcpb = 44, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 1, .trtp_05T = 1, + .trcd = 7, .trcd_05T = 1, + .twr = 12, .twr_05T = 1, + .twtr = 7, .twtr_05T = 0, + .tpbr2pbr = 29, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 13, .tr2mrw_05T = 1, + .tw2mrw = 9, .tw2mrw_05T = 0, + .tmrr2mrw = 11, .tmrr2mrw_05T = 1, + .tmrw = 4, .tmrw_05T = 1, + .tmrd = 6, .tmrd_05T = 1, + .tmrwckel = 7, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 10, .tmrri_05T = 1, + .trrd = 3, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 0, + .tfaw = 8, .tfaw_05T = 0, + .tfaw_4266 = 4, .tfaw_4266_05T = 0, + .trtw_odt_off = 4, .trtw_odt_off_05T = 0, + .trtw_odt_on = 6, .trtw_odt_on_05T = 0, + .txrefcnt = 115, + .tzqcs = 34, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 5, + .xrtr2w_odt_off = 5, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 40, + .hwset_mr2_op = 45, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 8, .trcd_derate_05T = 0, + .trc_derate = 17, .trc_derate_05T = 0, + .tras_derate = 9, .tras_derate_05T = 1, + .trpab_derate = 8, .trpab_derate_05T = 0, + .trp_derate = 6, .trp_derate_05T = 1, + .trrd_derate = 4, .trrd_derate_05T = 0, + .trtpd = 12, .trtpd_05T = 0, + .twtpd = 14, .twtpd_05T = 1, + .tmrr2w_odt_off = 8, + .tmrr2w_odt_on = 10, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 12, + .dqsinctl = 5, .datlat = 15 + }, + { + .freq_group = DDRFREQ_1600, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 32, .write_lat = 14, .div_mode = DIV8_MODE, + .tras = 8, .tras_05T = 1, + .trp = 6, .trp_05T = 0, + .trpab = 7, .trpab_05T = 0, + .trc = 15, .trc_05T = 0, + .trfc = 100, .trfc_05T = 0, + .trfcpb = 44, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 1, .trtp_05T = 1, + .trcd = 7, .trcd_05T = 1, + .twr = 12, .twr_05T = 1, + .twtr = 8, .twtr_05T = 0, + .tpbr2pbr = 29, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 14, .tr2mrw_05T = 1, + .tw2mrw = 9, .tw2mrw_05T = 0, + .tmrr2mrw = 12, .tmrr2mrw_05T = 1, + .tmrw = 4, .tmrw_05T = 1, + .tmrd = 6, .tmrd_05T = 1, + .tmrwckel = 7, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 10, .tmrri_05T = 1, + .trrd = 3, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 0, + .tfaw = 8, .tfaw_05T = 0, + .tfaw_4266 = 4, .tfaw_4266_05T = 0, + .trtw_odt_off = 5, .trtw_odt_off_05T = 0, + .trtw_odt_on = 7, .trtw_odt_on_05T = 0, + .txrefcnt = 115, + .tzqcs = 34, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 6, + .xrtr2w_odt_off = 6, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 40, + .hwset_mr2_op = 45, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 8, .trcd_derate_05T = 0, + .trc_derate = 17, .trc_derate_05T = 0, + .tras_derate = 9, .tras_derate_05T = 1, + .trpab_derate = 8, .trpab_derate_05T = 0, + .trp_derate = 6, .trp_derate_05T = 1, + .trrd_derate = 4, .trrd_derate_05T = 0, + .trtpd = 13, .trtpd_05T = 0, + .twtpd = 15, .twtpd_05T = 1, + .tmrr2w_odt_off = 9, + .tmrr2w_odt_on = 11, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 12, + .dqsinctl = 5, .datlat = 15 + }, + { + .freq_group = DDRFREQ_1200, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 24, .write_lat = 12, .div_mode = DIV8_MODE, + .tras = 4, .tras_05T = 1, + .trp = 4, .trp_05T = 0, + .trpab = 5, .trpab_05T = 0, + .trc = 9, .trc_05T = 1, + .trfc = 72, .trfc_05T = 1, + .trfcpb = 30, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 1, + .trtp = 1, .trtp_05T = 0, + .trcd = 5, .trcd_05T = 1, + .twr = 9, .twr_05T = 1, + .twtr = 6, .twtr_05T = 1, + .tpbr2pbr = 20, .tpbr2pbr_05T = 1, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 12, .tr2mrw_05T = 0, + .tw2mrw = 8, .tw2mrw_05T = 0, + .tmrr2mrw = 10, .tmrr2mrw_05T = 0, + .tmrw = 4, .tmrw_05T = 0, + .tmrd = 5, .tmrd_05T = 0, + .tmrwckel = 6, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 8, .tmrri_05T = 0, + .trrd = 2, .trrd_05T = 1, + .trrd_4266 = 1, .trrd_4266_05T = 1, + .tfaw = 4, .tfaw_05T = 1, + .tfaw_4266 = 1, .tfaw_4266_05T = 1, + .trtw_odt_off = 3, .trtw_odt_off_05T = 0, + .trtw_odt_on = 6, .trtw_odt_on_05T = 0, + .txrefcnt = 87, + .tzqcs = 26, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 2, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 5, + .xrtr2w_odt_off = 5, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 31, + .hwset_mr2_op = 36, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 6, .trcd_derate_05T = 0, + .trc_derate = 10, .trc_derate_05T = 1, + .tras_derate = 5, .tras_derate_05T = 0, + .trpab_derate = 5, .trpab_derate_05T = 1, + .trp_derate = 4, .trp_derate_05T = 1, + .trrd_derate = 3, .trrd_derate_05T = 0, + .trtpd = 10, .trtpd_05T = 1, + .twtpd = 12, .twtpd_05T = 0, + .tmrr2w_odt_off = 6, + .tmrr2w_odt_on = 8, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 10, + .dqsinctl = 4, .datlat = 13 + }, + { + .freq_group = DDRFREQ_1200, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 26, .write_lat = 12, .div_mode = DIV8_MODE, + .tras = 4, .tras_05T = 1, + .trp = 4, .trp_05T = 0, + .trpab = 5, .trpab_05T = 0, + .trc = 9, .trc_05T = 1, + .trfc = 72, .trfc_05T = 1, + .trfcpb = 30, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 1, + .trtp = 1, .trtp_05T = 0, + .trcd = 5, .trcd_05T = 1, + .twr = 10, .twr_05T = 0, + .twtr = 6, .twtr_05T = 0, + .tpbr2pbr = 20, .tpbr2pbr_05T = 1, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 12, .tr2mrw_05T = 1, + .tw2mrw = 8, .tw2mrw_05T = 0, + .tmrr2mrw = 10, .tmrr2mrw_05T = 1, + .tmrw = 4, .tmrw_05T = 0, + .tmrd = 5, .tmrd_05T = 0, + .tmrwckel = 6, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 8, .tmrri_05T = 0, + .trrd = 2, .trrd_05T = 1, + .trrd_4266 = 1, .trrd_4266_05T = 1, + .tfaw = 4, .tfaw_05T = 1, + .tfaw_4266 = 1, .tfaw_4266_05T = 1, + .trtw_odt_off = 4, .trtw_odt_off_05T = 0, + .trtw_odt_on = 6, .trtw_odt_on_05T = 0, + .txrefcnt = 87, + .tzqcs = 26, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 5, + .xrtr2w_odt_off = 5, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 31, + .hwset_mr2_op = 36, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 6, .trcd_derate_05T = 0, + .trc_derate = 10, .trc_derate_05T = 1, + .tras_derate = 5, .tras_derate_05T = 0, + .trpab_derate = 5, .trpab_derate_05T = 1, + .trp_derate = 4, .trp_derate_05T = 1, + .trrd_derate = 3, .trrd_derate_05T = 0, + .trtpd = 11, .trtpd_05T = 0, + .twtpd = 13, .twtpd_05T = 0, + .tmrr2w_odt_off = 7, + .tmrr2w_odt_on = 9, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 10, + .dqsinctl = 4, .datlat = 13 + }, + { + .freq_group = DDRFREQ_933, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 20, .write_lat = 10, .div_mode = DIV8_MODE, + .tras = 1, .tras_05T = 1, + .trp = 3, .trp_05T = 0, + .trpab = 3, .trpab_05T = 1, + .trc = 5, .trc_05T = 0, + .trfc = 53, .trfc_05T = 1, + .trfcpb = 21, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 4, .trcd_05T = 1, + .twr = 8, .twr_05T = 1, + .twtr = 5, .twtr_05T = 1, + .tpbr2pbr = 14, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 10, .tr2mrw_05T = 0, + .tw2mrw = 7, .tw2mrw_05T = 0, + .tmrr2mrw = 9, .tmrr2mrw_05T = 0, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 4, .tmrd_05T = 0, + .tmrwckel = 5, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 6, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 1, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 1, .tfaw_05T = 1, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 3, .trtw_odt_off_05T = 0, + .trtw_odt_on = 5, .trtw_odt_on_05T = 0, + .txrefcnt = 68, + .tzqcs = 19, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 2, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 24, + .hwset_mr2_op = 27, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 5, .trcd_derate_05T = 0, + .trc_derate = 6, .trc_derate_05T = 1, + .tras_derate = 2, .tras_derate_05T = 0, + .trpab_derate = 4, .trpab_derate_05T = 0, + .trp_derate = 3, .trp_derate_05T = 1, + .trrd_derate = 2, .trrd_derate_05T = 0, + .trtpd = 9, .trtpd_05T = 1, + .twtpd = 10, .twtpd_05T = 1, + .tmrr2w_odt_off = 5, + .tmrr2w_odt_on = 7, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 7, + .dqsinctl = 3, .datlat = 13 + }, + { + .freq_group = DDRFREQ_933, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 22, .write_lat = 10, .div_mode = DIV8_MODE, + .tras = 1, .tras_05T = 1, + .trp = 3, .trp_05T = 0, + .trpab = 3, .trpab_05T = 1, + .trc = 5, .trc_05T = 0, + .trfc = 53, .trfc_05T = 1, + .trfcpb = 21, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 4, .trcd_05T = 1, + .twr = 8, .twr_05T = 0, + .twtr = 5, .twtr_05T = 0, + .tpbr2pbr = 14, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 10, .tr2mrw_05T = 1, + .tw2mrw = 7, .tw2mrw_05T = 0, + .tmrr2mrw = 9, .tmrr2mrw_05T = 1, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 4, .tmrd_05T = 0, + .tmrwckel = 5, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 6, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 1, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 1, .tfaw_05T = 1, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 3, .trtw_odt_off_05T = 0, + .trtw_odt_on = 5, .trtw_odt_on_05T = 0, + .txrefcnt = 68, + .tzqcs = 19, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 2, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 4, + .xrtr2w_odt_off = 4, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 24, + .hwset_mr2_op = 27, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 5, .trcd_derate_05T = 0, + .trc_derate = 6, .trc_derate_05T = 1, + .tras_derate = 2, .tras_derate_05T = 0, + .trpab_derate = 4, .trpab_derate_05T = 0, + .trp_derate = 3, .trp_derate_05T = 1, + .trrd_derate = 2, .trrd_derate_05T = 0, + .trtpd = 10, .trtpd_05T = 0, + .twtpd = 11, .twtpd_05T = 0, + .tmrr2w_odt_off = 6, + .tmrr2w_odt_on = 8, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 7, + .dqsinctl = 3, .datlat = 13 + }, + { + .freq_group = DDRFREQ_800, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 14, .write_lat = 8, .div_mode = DIV8_MODE, + .tras = 0, .tras_05T = 0, + .trp = 2, .trp_05T = 1, + .trpab = 3, .trpab_05T = 0, + .trc = 3, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 4, .trcd_05T = 0, + .twr = 7, .twr_05T = 1, + .twtr = 4, .twtr_05T = 1, + .tpbr2pbr = 11, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 8, .tr2mrw_05T = 1, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 0, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 1, + .tmrwckel = 4, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 5, .tmrri_05T = 1, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 1, .trtw_odt_off_05T = 0, + .trtw_odt_on = 4, .trtw_odt_on_05T = 0, + .txrefcnt = 58, + .tzqcs = 16, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 3, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 20, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 4, .trcd_derate_05T = 0, + .trc_derate = 4, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 1, + .trpab_derate = 3, .trpab_derate_05T = 1, + .trp_derate = 2, .trp_derate_05T = 1, + .trrd_derate = 1, .trrd_derate_05T = 1, + .trtpd = 7, .trtpd_05T = 1, + .twtpd = 9, .twtpd_05T = 1, + .tmrr2w_odt_off = 3, + .tmrr2w_odt_on = 5, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 6, + .dqsinctl = 2, .datlat = 10 + }, + { + .freq_group = DDRFREQ_800, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 16, .write_lat = 8, .div_mode = DIV8_MODE, + .tras = 0, .tras_05T = 0, + .trp = 2, .trp_05T = 1, + .trpab = 3, .trpab_05T = 0, + .trc = 3, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 4, .trcd_05T = 0, + .twr = 7, .twr_05T = 0, + .twtr = 4, .twtr_05T = 0, + .tpbr2pbr = 11, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 9, .tr2mrw_05T = 0, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 1, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 1, + .tmrwckel = 4, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 5, .tmrri_05T = 1, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 2, .trtw_odt_off_05T = 0, + .trtw_odt_on = 4, .trtw_odt_on_05T = 0, + .txrefcnt = 58, + .tzqcs = 16, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 20, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 4, .trcd_derate_05T = 0, + .trc_derate = 4, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 1, + .trpab_derate = 3, .trpab_derate_05T = 1, + .trp_derate = 2, .trp_derate_05T = 1, + .trrd_derate = 1, .trrd_derate_05T = 1, + .trtpd = 8, .trtpd_05T = 0, + .twtpd = 9, .twtpd_05T = 1, + .tmrr2w_odt_off = 4, + .tmrr2w_odt_on = 6, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 6, + .dqsinctl = 2, .datlat = 10 + }, + { + .freq_group = DDRFREQ_600, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 14, .write_lat = 8, .div_mode = DIV8_MODE, + .tras = 0, .tras_05T = 0, + .trp = 1, .trp_05T = 1, + .trpab = 2, .trpab_05T = 0, + .trc = 0, .trc_05T = 1, + .trfc = 30, .trfc_05T = 1, + .trfcpb = 9, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 3, .trcd_05T = 0, + .twr = 6, .twr_05T = 1, + .twtr = 4, .twtr_05T = 1, + .tpbr2pbr = 7, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 8, .tr2mrw_05T = 1, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 0, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 0, + .tmrwckel = 4, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 4, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 1, .trtw_odt_off_05T = 0, + .trtw_odt_on = 4, .trtw_odt_on_05T = 0, + .txrefcnt = 44, + .tzqcs = 12, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 3, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 16, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 3, .trcd_derate_05T = 0, + .trc_derate = 1, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 0, + .trpab_derate = 2, .trpab_derate_05T = 0, + .trp_derate = 1, .trp_derate_05T = 1, + .trrd_derate = 1, .trrd_derate_05T = 0, + .trtpd = 7, .trtpd_05T = 1, + .twtpd = 8, .twtpd_05T = 1, + .tmrr2w_odt_off = 3, + .tmrr2w_odt_on = 5, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 5, + .dqsinctl = 2, .datlat = 9 + }, + { + .freq_group = DDRFREQ_600, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 16, .write_lat = 8, .div_mode = DIV8_MODE, + .tras = 0, .tras_05T = 0, + .trp = 1, .trp_05T = 1, + .trpab = 2, .trpab_05T = 0, + .trc = 0, .trc_05T = 1, + .trfc = 30, .trfc_05T = 1, + .trfcpb = 9, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 3, .trcd_05T = 0, + .twr = 6, .twr_05T = 0, + .twtr = 4, .twtr_05T = 1, + .tpbr2pbr = 7, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 9, .tr2mrw_05T = 0, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 1, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 0, + .tmrwckel = 4, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 4, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 2, .trtw_odt_off_05T = 0, + .trtw_odt_on = 5, .trtw_odt_on_05T = 0, + .txrefcnt = 44, + .tzqcs = 12, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 16, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 3, .trcd_derate_05T = 0, + .trc_derate = 1, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 0, + .trpab_derate = 2, .trpab_derate_05T = 0, + .trp_derate = 1, .trp_derate_05T = 1, + .trrd_derate = 1, .trrd_derate_05T = 0, + .trtpd = 8, .trtpd_05T = 0, + .twtpd = 9, .twtpd_05T = 0, + .tmrr2w_odt_off = 4, + .tmrr2w_odt_on = 6, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 5, + .dqsinctl = 2, .datlat = 9 + }, + { + .freq_group = DDRFREQ_400, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 14, .write_lat = 8, .div_mode = DIV4_MODE, + .tras = 1, .tras_05T = 0, + .trp = 2, .trp_05T = 0, + .trpab = 3, .trpab_05T = 0, + .trc = 3, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 3, .trtp_05T = 0, + .trcd = 4, .trcd_05T = 0, + .twr = 12, .twr_05T = 0, + .twtr = 10, .twtr_05T = 0, + .tpbr2pbr = 11, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 16, .tr2mrw_05T = 0, + .tw2mrw = 13, .tw2mrw_05T = 0, + .tmrr2mrw = 14, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 0, + .tmrwckel = 8, .tmrwckel_05T = 0, + .tpde = 3, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 7, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 6, .trtw_odt_off_05T = 0, + .trtw_odt_on = 11, .trtw_odt_on_05T = 0, + .txrefcnt = 58, + .tzqcs = 16, + .xrtw2w_new_mode = 9, + .xrtw2w_old_mode = 10, + .xrtw2r_odt_on = 7, + .xrtw2r_odt_off = 5, + .xrtr2w_odt_on = 9, + .xrtr2w_odt_off = 9, + .xrtr2r_new_mode = 6, + .xrtr2r_old_mode = 8, + .tr2mrr = 8, + .vrcgdis_prdcnt = 20, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 4, .trcd_derate_05T = 0, + .trc_derate = 4, .trc_derate_05T = 0, + .tras_derate = 1, .tras_derate_05T = 0, + .trpab_derate = 3, .trpab_derate_05T = 0, + .trp_derate = 2, .trp_derate_05T = 0, + .trrd_derate = 2, .trrd_derate_05T = 0, + .trtpd = 15, .trtpd_05T = 0, + .twtpd = 15, .twtpd_05T = 0, + .tmrr2w_odt_off = 10, + .tmrr2w_odt_on = 12, + .ckeprd = 2, + .ckelckcnt = 3, + .zqlat2 = 6, + .dqsinctl = 5, .datlat = 15 + }, + { + .freq_group = DDRFREQ_400, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 16, .write_lat = 8, .div_mode = DIV4_MODE, + .tras = 1, .tras_05T = 0, + .trp = 2, .trp_05T = 0, + .trpab = 3, .trpab_05T = 0, + .trc = 3, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 3, .trtp_05T = 0, + .trcd = 4, .trcd_05T = 0, + .twr = 12, .twr_05T = 0, + .twtr = 10, .twtr_05T = 0, + .tpbr2pbr = 11, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 17, .tr2mrw_05T = 0, + .tw2mrw = 13, .tw2mrw_05T = 0, + .tmrr2mrw = 15, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 0, + .tmrwckel = 8, .tmrwckel_05T = 0, + .tpde = 3, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 7, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 7, .trtw_odt_off_05T = 0, + .trtw_odt_on = 12, .trtw_odt_on_05T = 0, + .txrefcnt = 58, + .tzqcs = 16, + .xrtw2w_new_mode = 9, + .xrtw2w_old_mode = 10, + .xrtw2r_odt_on = 6, + .xrtw2r_odt_off = 4, + .xrtr2w_odt_on = 10, + .xrtr2w_odt_off = 10, + .xrtr2r_new_mode = 6, + .xrtr2r_old_mode = 9, + .tr2mrr = 8, + .vrcgdis_prdcnt = 20, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 4, .trcd_derate_05T = 0, + .trc_derate = 4, .trc_derate_05T = 0, + .tras_derate = 1, .tras_derate_05T = 0, + .trpab_derate = 3, .trpab_derate_05T = 0, + .trp_derate = 2, .trp_derate_05T = 0, + .trrd_derate = 2, .trrd_derate_05T = 0, + .trtpd = 16, .trtpd_05T = 0, + .twtpd = 15, .twtpd_05T = 0, + .tmrr2w_odt_off = 11, + .tmrr2w_odt_on = 13, + .ckeprd = 2, + .ckelckcnt = 3, + .zqlat2 = 6, + .dqsinctl = 5, .datlat = 15 + }, +}; +#endif /* __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10e704868e4cd36a938a669879bb1a8632e73e1a Gerrit-Change-Number: 44713 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

6 56

Change in coreboot[master]: soc/mediatek/mt8192: Get DDR base information after calibration
by CK HU (Code Review) 19 Jan '21

19 Jan '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44712 to review the following change. Change subject: soc/mediatek/mt8192: Get DDR base information after calibration ...................................................................... soc/mediatek/mt8192: Get DDR base information after calibration Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Ie62948368716d309aab8149372b2b6093fc33552 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 83 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/44712/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index adabb80..31e8d0e 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -3835,6 +3835,36 @@ write32(regs_bak[i].addr, regs_bak[i].value); } +u8 dramc_mode_reg_read(u8 chn, u8 mr_idx) +{ + u8 value; + + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSMA, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRREN, 1); + + /* Wait until MRW command fired */ + while (READ32_BITFIELD(&ch[chn].nao.spcmdresp, SPCMDRESP_MRR_RESPONSE) == 0) + udelay(1); + + value = READ32_BITFIELD(&ch[chn].nao.mrr_status, MRR_STATUS_MRR_SW_REG); + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRREN, 0); + dramc_dbg("Read MR%d =%#x\n", mr_idx, value); + + return value; +} + +u8 dramc_mode_reg_read_by_rank(u8 chn, u8 rank, u8 mr_idx) +{ + u8 value = 0; + u8 rank_bak; + + rank_bak = READ32_BITFIELD(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank); + value = dramc_mode_reg_read(chn, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank_bak); + return value; +} + void dramc_mode_reg_write_by_rank(const struct ddr_cali *cali, u8 chn, u8 rank, u8 mr_idx, u8 value) { diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 355cc9d..cf199dc 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -14,6 +14,55 @@ mt6359p_buck_set_voltage(MT6359P_GPU11, vcore); } +static void get_dram_info_after_cal(struct ddr_cali *cali) +{ + u8 vendor_id, density, max_density = 0; + u32 size_Gb, max_size = 0; + + vendor_id = dramc_mode_reg_read_by_rank(CHANNEL_A, RANK_0, 5) & 0xff; + dramc_info("Vendor id is %#x\n", vendor_id); + + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) { + density = dramc_mode_reg_read_by_rank(CHANNEL_A, rk, 8) & 0xff; + dramc_dbg("MR8 %#x\n", density); + density = (density >> 2) & 0xf; + + switch (density) { + case 0x0: + size_Gb = 4; + break; + case 0x1: + size_Gb = 6; + break; + case 0x2: + size_Gb = 8; + break; + case 0x3: + size_Gb = 12; + break; + case 0x4: + size_Gb = 16; + break; + case 0x5: + size_Gb = 24; + break; + case 0x6: + size_Gb = 32; + break; + default: + size_Gb = 0; + break; + } + if (size_Gb > max_size) { + max_size = size_Gb; + max_density = density; + } + dramc_dbg("RK%d size %dGb, density:%d\n", rk, size_Gb, max_density); + } + + cali->density = max_density; +} + static void dramc_calibration_all_channels(struct ddr_cali *cali) { } @@ -91,6 +140,10 @@ dramc_calibration_all_channels(&cali); + /* only need do once for get DDR's base information */ + if (first_freq_k) + get_dram_info_after_cal(&cali); + first_freq_k= false; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/44712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie62948368716d309aab8149372b2b6093fc33552 Gerrit-Change-Number: 44712 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

7 16

Change in coreboot[master]: soc/intel/cannonlake: Add i915_gpu_controller_info
by Jeremy Soller (Code Review) 16 Jan '21

16 Jan '21

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43616 ) Change subject: soc/intel/cannonlake: Add i915_gpu_controller_info ...................................................................... soc/intel/cannonlake: Add i915_gpu_controller_info This adds the i915_gpu_controller_info struct to chip.h and implements intel_igd_get_controller_info. Due to conflicts with the GMA driver ACPI, gfx.asl had to be commented out. I believe gfx.asl should be removed, but would like to hear alternatives. Tested on system76/lemp9 - ACPI backlight control was verified. Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Change-Id: I027b5fc37527fbfcf985262c8a1a048e0363410e --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/acpi/southbridge.asl M src/soc/intel/cannonlake/chip.h A src/soc/intel/cannonlake/graphics.c 4 files changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/43616/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 96f1f97..e6d330a 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -38,6 +38,7 @@ ramstage-y += fsp_params.c ramstage-y += gspi.c ramstage-y += i2c.c +ramstage-y += graphics.c ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += me.c diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 12269d3..9cdd3b5 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -17,7 +17,7 @@ #endif /* GFX 00:02.0 */ -#include "gfx.asl" +//TODO: fix inclusion when using gma ACPI #include "gfx.asl" /* LPC 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 2923efc..3457f4d 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -5,6 +5,7 @@ #include <intelblocks/cfg.h> #include <drivers/i2c/designware/dw_i2c.h> +#include <drivers/intel/gma/gma.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -478,6 +479,9 @@ * Only override CPU flex ratio if don't want to boot with non-turbo max. */ uint8_t cpu_ratio_override; + + /* i915 struct for GMA backlight control */ + struct i915_gpu_controller_info gfx; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c new file mode 100644 index 0000000..fda4998 --- /dev/null +++ b/src/soc/intel/cannonlake/graphics.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/graphics.h> +#include <soc/ramstage.h> + +const struct i915_gpu_controller_info * +intel_igd_get_controller_info(const struct device *device) +{ + struct soc_intel_cannonlake_config *chip = device->chip_info; + return &chip->gfx; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/43616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I027b5fc37527fbfcf985262c8a1a048e0363410e Gerrit-Change-Number: 43616 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/acpi: Remove southcluster.asl
by Marc Jones (Code Review) 16 Jan '21

16 Jan '21

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45835 ) Change subject: soc/intel/xeon_sp/acpi: Remove southcluster.asl ...................................................................... soc/intel/xeon_sp/acpi: Remove southcluster.asl Remove the non-built southcluster.asl file. The asl is duplicated in iiostack.asl and uncore_irq.asl. Change-Id: I04d842880db03507adf7b2ba0e79c986c89584ca Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- D src/soc/intel/xeon_sp/acpi/southcluster.asl 1 file changed, 0 insertions(+), 235 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/45835/1 diff --git a/src/soc/intel/xeon_sp/acpi/southcluster.asl b/src/soc/intel/xeon_sp/acpi/southcluster.asl deleted file mode 100644 index effed43..0000000 --- a/src/soc/intel/xeon_sp/acpi/southcluster.asl +++ /dev/null @@ -1,235 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <soc/iomap.h> - -Name(_HID,EISAID("PNP0A08")) // PCIe -Name(_CID,EISAID("PNP0A03")) // PCI - -Name(_BBN, 0) - -Name (MCRS, ResourceTemplate() { - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00fe, 0x0000, 0xff,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xefff, 0x0000, 0xE300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xc0000-0xc3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xc4000-0xc7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xc8000-0xcbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xcc000-0xcffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000,,, OPR3) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR4) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR5) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR6) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR7) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-0xfeafffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x90000000, 0xFEAFFFFF, 0x00000000, - 0x6EB00000,,, PMEM) - - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfec00000, 0xfecfffff, 0x00000000, - 0x00100000,,, APIC) - - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed00000, 0xfedfffff, 0x00000000, - 0x00100000,,, PCHR) - - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x0000380000000000, // Range Minimum - 0x0000383FFFFFFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x0000004000000000, // Length - ,,, AddressRangeMemory, TypeStatic) -}) - -Method (_CRS, 0, Serialized) { - Return (MCRS) -} - -Method (_OSC, 4) { - /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) - { - /* Let OS control everything */ - Return (Arg3) - } - Else - { - /* Unrecognized UUID */ - CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) - Return (Arg3) - } -} - - -Name (AR00, Package() { - // [DMI0]: Legacy PCI Express Port 0 on PCI0 - Package() { 0x0000FFFF, 0, 0, 47 }, - // [BR1A]: PCI Express Port 1A on PCI0 - // [BR1B]: PCI Express Port 1B on PCI0 - Package() { 0x0001FFFF, 0, 0, 47 }, - // [BR2A]: PCI Express Port 2A on PCI0 - // [BR2B]: PCI Express Port 2B on PCI0 - // [BR2C]: PCI Express Port 2C on PCI0 - // [BR2D]: PCI Express Port 2D on PCI0 - Package() { 0x0002FFFF, 0, 0, 47 }, - // [BR3A]: PCI Express Port 3A on PCI0 - // [BR3B]: PCI Express Port 3B on PCI0 - // [BR3C]: PCI Express Port 3C on PCI0 - // [BR3D]: PCI Express Port 3D on PCI0 - Package() { 0x0003FFFF, 0, 0, 47 }, - // [CB0A]: CB3DMA on PCI0 - // [CB0E]: CB3DMA on PCI0 - Package() { 0x0004FFFF, 0, 0, 31 }, - // [CB0B]: CB3DMA on PCI0 - // [CB0F]: CB3DMA on PCI0 - Package() { 0x0004FFFF, 1, 0, 39 }, - // [CB0C]: CB3DMA on PCI0 - // [CB0G]: CB3DMA on PCI0 - Package() { 0x0004FFFF, 2, 0, 31 }, - // [CB0D]: CB3DMA on PCI0 - // [CB0H]: CB3DMA on PCI0 - Package() { 0x0004FFFF, 3, 0, 39 }, - // [IIM0]: IIOMISC on PCI0 - Package() { 0x0005FFFF, 0, 0, 16 }, - Package() { 0x0005FFFF, 1, 0, 17 }, - Package() { 0x0005FFFF, 2, 0, 18 }, - Package() { 0x0005FFFF, 3, 0, 19 }, - // [IID0]: IIODFX0 on PCI0 - Package() { 0x0006FFFF, 0, 0, 16 }, - Package() { 0x0006FFFF, 1, 0, 17 }, - Package() { 0x0006FFFF, 2, 0, 18 }, - Package() { 0x0006FFFF, 3, 0, 19 }, - // [XHCI]: xHCI controller 1 on PCH - Package() { 0x0014FFFF, 3, 0, 19 }, - // [HECI]: ME HECI on PCH - // [IDER]: ME IDE redirect on PCH - Package() { 0x0016FFFF, 0, 0, 16 }, - // [HEC2]: ME HECI2 on PCH - // [MEKT]: MEKT on PCH - Package() { 0x0016FFFF, 1, 0, 17 }, - // [GBEM]: GbE Controller VPRO - Package() { 0x0019FFFF, 0, 0, 20 }, - // [EHC2]: EHCI controller #2 on PCH - Package() { 0x001AFFFF, 2, 0, 18 }, - // [ALZA]: High definition Audio Controller - Package() { 0x001BFFFF, 0, 0, 22 }, - // [RP01]: Pci Express Port 1 on PCH - // [RP05]: Pci Express Port 5 on PCH - Package() { 0x001CFFFF, 0, 0, 16 }, - // [RP02]: Pci Express Port 2 on PCH - // [RP06]: Pci Express Port 6 on PCH - Package() { 0x001CFFFF, 1, 0, 17 }, - // [RP03]: Pci Express Port 3 on PCH - // [RP07]: Pci Express Port 7 on PCH - Package() { 0x001CFFFF, 2, 0, 18 }, - // [RP04]: Pci Express Port 4 on PCH - // [RP08]: Pci Express Port 8 on ICH - Package() { 0x001CFFFF, 3, 0, 19 }, - // [EHC1]: EHCI controller #1 on PCH - Package() { 0x001DFFFF, 2, 0, 18 }, - // [SAT1]: SATA controller 1 on PCH - // [SAT2]: SATA Host controller 2 on PCH - Package() { 0x001FFFFF, 0, 0, 16 }, - // [SMBS]: SMBus controller on PCH - // [TERM]: Thermal Subsystem on ICH - Package() { 0x001FFFFF, 2, 0, 18 }, - Package() { 0x0017FFFF, 0, 0, 20 }, - Package() { 0x0011FFFF, 0, 0, 21 }, -}) - -// Socket 0 Root bridge -Method (_PRT, 0) { - Return (AR00) -} -- To view, visit https://review.coreboot.org/c/coreboot/+/45835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04d842880db03507adf7b2ba0e79c986c89584ca Gerrit-Change-Number: 45835 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020