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Change in coreboot[master]: Chrome EC SOCs: Integrate Chrome EC check
by Paul Menzel (Code Review) 19 Feb '21

19 Feb '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42258 ) Change subject: Chrome EC SOCs: Integrate Chrome EC check ...................................................................... Chrome EC SOCs: Integrate Chrome EC check Behave the same as newer platforms. Skylake has the same code. This also adds brackets around &(gnvs->chromeos), so the it’s clear, what pointer is meant. Change-Id: I43ff551c717f598c7a65547ec49157853681314f Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/apollolake/acpi.c 3 files changed, 21 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/42258/1 diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index fe5879c..7068ac0 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -254,8 +254,13 @@ if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&gnvs->chromeos); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + } else { + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } } /* Set unknown wake source */ diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index ea67aa3..54b5521 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -229,8 +229,13 @@ if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&gnvs->chromeos); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + } else { + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } } /* Set unknown wake source */ diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 595e6a2..f9962e9 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -83,8 +83,13 @@ if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&gnvs->chromeos); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + } else { + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } } /* Set unknown wake source */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43ff551c717f598c7a65547ec49157853681314f Gerrit-Change-Number: 42258 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/*/acpi: Put braces around *else* branch
by Paul Menzel (Code Review) 19 Feb '21

19 Feb '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42257 ) Change subject: soc/intel/*/acpi: Put braces around *else* branch ...................................................................... soc/intel/*/acpi: Put braces around *else* branch From `Documentation/coding_style.md`: > This does not apply if only one branch of a conditional statement is a > single statement; in the latter case use braces in both branches: Change-Id: Idb4427f7ae9f7b99ba74f7e84aed6b8a901ca9fc Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/tigerlake/acpi.c 3 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/42257/1 diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 796e770..12ce34c 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -198,8 +198,9 @@ if (CONFIG(EC_GOOGLE_CHROMEEC)) { gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else + } else { gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } } /* Enable DPTF based on mainboard configuration */ diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 88ec5fe..250ff3b 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -292,8 +292,9 @@ if (CONFIG(EC_GOOGLE_CHROMEEC)) { gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else + } else { gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } } /* Enable DPTF based on mainboard configuration */ diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 0991134..e965c48 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -292,8 +292,9 @@ if (CONFIG(EC_GOOGLE_CHROMEEC)) { gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else + } else { gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } } /* Enable DPTF based on mainboard configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb4427f7ae9f7b99ba74f7e84aed6b8a901ca9fc Gerrit-Change-Number: 42257 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Make `acpi_create_gnvs()` static
by Paul Menzel (Code Review) 19 Feb '21

19 Feb '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42199 ) Change subject: soc/intel/cannonlake: Make `acpi_create_gnvs()` static ...................................................................... soc/intel/cannonlake: Make `acpi_create_gnvs()` static The function `acpi_create_gnvs()` is only used in this translation unit, so make it `static`. This unifies it with the Skylake version `src/soc/intel/skylake/acpi.c`. Change-Id: I8f817aa46c75332ec5a5fa77e8772ae0f0e3a366 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/soc/intel/cannonlake/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/42199/1 diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 12758e1..886cba2 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -182,7 +182,7 @@ return read32((void *)pmc_bar + IRQ_REG); } -void acpi_create_gnvs(struct global_nvs_t *gnvs) +static void acpi_create_gnvs(struct global_nvs_t *gnvs) { const struct soc_intel_cannonlake_config *config; config = config_of_soc(); -- To view, visit https://review.coreboot.org/c/coreboot/+/42199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f817aa46c75332ec5a5fa77e8772ae0f0e3a366 Gerrit-Change-Number: 42199 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: nb/intel/pineview: Drop unused `GPIO32` macro
by Angel Pons (Code Review) 18 Feb '21

18 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45423 ) Change subject: nb/intel/pineview: Drop unused `GPIO32` macro ...................................................................... nb/intel/pineview: Drop unused `GPIO32` macro It's not used, and GPIO registers are on the southbridge. Change-Id: I0b7b6edc22d461007f24618eca42091439a53d3c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/pineview/pineview.h 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/45423/1 diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 82ae3ff..48ee263 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -26,8 +26,6 @@ #define GTTADR 0x1c #define BSM 0x5c -#define GPIO32(x) *((volatile u32 *)(DEFAULT_GPIOBASE + x)) - /* * MCHBAR */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b7b6edc22d461007f24618eca42091439a53d3c Gerrit-Change-Number: 45423 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Use 133 MHz ref clock for DDR3-2400
by Angel Pons (Code Review) 18 Feb '21

18 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45503 ) Change subject: nb/intel/sandybridge: Use 133 MHz ref clock for DDR3-2400 ...................................................................... nb/intel/sandybridge: Use 133 MHz ref clock for DDR3-2400 The 100 MHz reference clock seems to be unstable when using high multipliers. Use the 133 MHz reference clock instead. Change-Id: I400e4f91776306d54d818fa249d7a845020ac37b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_native.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/45503/1 diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 6b74405..19e0e1d 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -136,7 +136,7 @@ { if (ctrl->tCK <= TCK_1200MHZ) { ctrl->tCK = TCK_1200MHZ; - ctrl->base_freq = 100; + ctrl->base_freq = 133; } else if (ctrl->tCK <= TCK_1100MHZ) { ctrl->tCK = TCK_1100MHZ; ctrl->base_freq = 100; -- To view, visit https://review.coreboot.org/c/coreboot/+/45503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I400e4f91776306d54d818fa249d7a845020ac37b Gerrit-Change-Number: 45503 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: nb/intel/sandybridge: Clean up `dram_freq` function
by Angel Pons (Code Review) 18 Feb '21

18 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45502 ) Change subject: nb/intel/sandybridge: Clean up `dram_freq` function ...................................................................... nb/intel/sandybridge: Clean up `dram_freq` function The thing that this function initializes is the MPLL (Memory PLL). So, call it by its name. Also add a missing newline in a printk, and update a comment on the callsite of this function. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I86ab643bc87253554346dfed3630eb9ddbd44eb3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_native.c 1 file changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/45502/1 diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 64a381d..6b74405 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -459,7 +459,7 @@ if (ctrl->tCK > TCK_400MHZ) { printk(BIOS_ERR, "DRAM frequency is under lowest supported frequency (400 MHz). " - "Increasing to 400 MHz as last resort"); + "Increasing to 400 MHz as last resort.\n"); ctrl->tCK = TCK_400MHZ; } @@ -467,11 +467,11 @@ u8 val2; u32 reg1 = 0; - /* Step 1 - Set target PCU frequency */ + /* Step 1 - Determine target MPLL frequency */ find_cas_tck(ctrl); /* - * The PLL will never lock if the required frequency is already set. + * The MPLL will never lock if the requested frequency is already set. * Exit early to prevent a system hang. */ reg1 = MCHBAR32(MC_BIOS_DATA); @@ -479,16 +479,16 @@ if (val2) return; - /* Step 2 - Select frequency in the MCU */ + /* Step 2 - Request MPLL frequency */ reg1 = ctrl->FRQ; if (ctrl->base_freq == 100) - reg1 |= 0x100; /* Enable 100Mhz REF clock */ + reg1 |= 0x100; /* Use 100MHz reference clock */ - reg1 |= 0x80000000; /* set running bit */ + reg1 |= (1 << 31); /* Set running bit */ MCHBAR32(MC_BIOS_REQ) = reg1; int i = 0; - printk(BIOS_DEBUG, "PLL busy... "); - while (reg1 & 0x80000000) { + printk(BIOS_DEBUG, "MPLL busy... "); + while (reg1 & (1 << 31)) { udelay(10); i++; reg1 = MCHBAR32(MC_BIOS_REQ); @@ -499,11 +499,11 @@ reg1 = MCHBAR32(MC_BIOS_DATA); val2 = (u8) reg1; if (val2 >= ctrl->FRQ) { - printk(BIOS_DEBUG, "MCU frequency is set at : %d MHz\n", + printk(BIOS_DEBUG, "MPLL frequency is set at : %d MHz\n", (1000 << 8) / ctrl->tCK); return; } - printk(BIOS_DEBUG, "PLL didn't lock. Retrying at lower frequency\n"); + printk(BIOS_DEBUG, "MPLL didn't lock. Retrying at lower frequency\n"); ctrl->tCK++; } } @@ -571,7 +571,7 @@ dram_dimm_mapping(ctrl); } - /* Set MC frequency */ + /* Set MPLL frequency */ dram_freq(ctrl); if (!fast_boot) { -- To view, visit https://review.coreboot.org/c/coreboot/+/45502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86ab643bc87253554346dfed3630eb9ddbd44eb3 Gerrit-Change-Number: 45502 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: SMBIOS: Update smbios.h
by HAOUAS Elyes (Code Review) 18 Feb '21

18 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44850 ) Change subject: SMBIOS: Update smbios.h ...................................................................... SMBIOS: Update smbios.h Type 9: add PCI Express Gen 5. add OCP NIC. add Slot Type extensions for PCIe Gen6. add support for CXL 2.0. add EDSFF slot types Type 17: add new memory device types DDR5 and LPDDR5 Change-Id: I023b901c1cb4ebe07679885a9f5e0d1e95488a30 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/smbios.h 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/44850/1 diff --git a/src/include/smbios.h b/src/include/smbios.h index 521339e..a91f6a6 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -174,6 +174,8 @@ MEMORY_TYPE_LOGICAL_NON_VOLATILE_DEVICE = 0x1f, MEMORY_TYPE_HBM = 0x20, MEMORY_TYPE_HBM2 = 0x21, + MEMORY_TYPE_DDR5 = 0x22, + MEMORY_TYPE_LPDDR5 = 0x23, } smbios_memory_type; typedef enum { @@ -664,6 +666,11 @@ SlotTypePciExpressMini52pinWithBSKO = 0x21, SlotTypePciExpressMini52pinWithoutBSKO = 0x22, SlotTypePciExpressMini76pin = 0x23, + SlotTypePciExpressGen4SFF8639 = 0x24, + SlotTypePciExpressGen5SFF8639 = 0x25, + SlotTypeOcpNic3SFF = 0x26, + SlotTypeOcpNic3LFF = 0x27, + SlotTypeOcpNicPriorTo3 = 0x28, SlotTypePC98C20 = 0xA0, SlotTypePC98C24 = 0xA1, SlotTypePC98E = 0xA2, @@ -692,7 +699,16 @@ SlotTypePciExpressGen4x2 = 0xBA, SlotTypePciExpressGen4x4 = 0xBB, SlotTypePciExpressGen4x8 = 0xBC, - SlotTypePciExpressGen4x16 = 0xBD + SlotTypePciExpressGen4x16 = 0xBD, + SlotTypePciExpressGen5 = 0xBE, + SlotTypePciExpressGen5x1 = 0xBF, + SlotTypePciExpressGen5x2 = 0xC0, + SlotTypePciExpressGen5x4 = 0xC1, + SlotTypePciExpressGen5x8 = 0xC2, + SlotTypePciExpressGen5x16 = 0xC3, + SlotTypePciExpressGen6 = 0xC4, + SlotTypeEDSFFE1 = 0xC5, + SlotTypeEDSFFE3 0xC6 }; /* System Slots - Slot Data Bus Width. */ @@ -744,6 +760,9 @@ #define SMBIOS_SLOT_HOTPLUG (1 << 1) #define SMBIOS_SLOT_SMBUS (1 << 2) #define SMBIOS_SLOT_BIFURCATION (1 << 3) +#define SMBIOS_SLOT_ASYNC (1 << 4) +#define SMBIOS_SLOT_CXL_1 (1 << 5) +#define SMBIOS_SLOT_CXL_2 (1 << 6) struct slot_peer_groups { u16 peer_seg_num; -- To view, visit https://review.coreboot.org/c/coreboot/+/44850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I023b901c1cb4ebe07679885a9f5e0d1e95488a30 Gerrit-Change-Number: 44850 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: crossgcc: Upgrade GCC to 10.1.0
by HAOUAS Elyes (Code Review) 18 Feb '21

18 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42251 ) Change subject: crossgcc: Upgrade GCC to 10.1.0 ...................................................................... crossgcc: Upgrade GCC to 10.1.0 nds32, GNAT bad constant and gnat_eh patches are integrated in upstream so we don't need them anymore. Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-10.1.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-10.1.0_gnat.patch R util/crossgcc/patches/gcc-10.1.0_libgcc.patch D util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch D util/crossgcc/patches/gcc-8.3.0_gnat_eh.patch D util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch A util/crossgcc/sum/gcc-10.1.0.tar.xz.cksum D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum 9 files changed, 2 insertions(+), 21,441 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42251/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/42251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Gerrit-Change-Number: 42251 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell: Use common MCHBAR accessor functions
by HAOUAS Elyes (Code Review) 18 Feb '21

18 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45574 ) Change subject: nb/intel/haswell: Use common MCHBAR accessor functions ...................................................................... nb/intel/haswell: Use common MCHBAR accessor functions This change the binary using "BUILD_TIMELESS=1" for lenovo/t440p baord. Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/haswell/haswell_init.c M src/northbridge/intel/haswell/Makefile.inc M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/raminit.c 8 files changed, 19 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45574/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 5f3debb..86c69f8 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -14,6 +14,7 @@ #include <cpu/intel/turbo.h> #include <cpu/x86/name.h> #include <delay.h> +#include <northbridge/intel/common/mchbar_ops.h> #include <northbridge/intel/haswell/haswell.h> #include <southbridge/intel/lynxpoint/pch.h> #include <cpu/intel/common/common.h> diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index b2fd530..8f9f33d 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -11,14 +11,17 @@ ramstage-y += acpi.c ramstage-y += minihd.c +ramstage-y += ../common/mchbar_ops.c romstage-y += memmap.c romstage-y += raminit.c romstage-y += romstage.c romstage-y += early_init.c romstage-y += report_platform.c +romstage-y += ../common/mchbar_ops.c smm-y += finalize.c +smm-y += ../common/mchbar_ops.c # We don't ship that, but booting without it is bound to fail cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index cc4487c..81ed757 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -7,6 +7,7 @@ #include <device/device.h> #include <device/pci_ops.h> #include "haswell.h" +#include <northbridge/intel/common/mchbar_ops.h> #include <southbridge/intel/lynxpoint/pch.h> unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 9db6a9d..b1fe430 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -5,6 +5,7 @@ #include <device/mmio.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <northbridge/intel/common/mchbar_ops.h> #include "haswell.h" diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 93c89ce..ebce6e9 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/pci_ops.h> +#include <northbridge/intel/common/mchbar_ops.h> + #include "haswell.h" void intel_northbridge_haswell_finalize_smm(void) @@ -17,13 +19,13 @@ pci_or_config32(HOST_BRIDGE, 0xb8, 1 << 0); /* TSEGMB */ pci_or_config32(HOST_BRIDGE, 0xbc, 1 << 0); /* TOLUD */ - MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ - MCHBAR32_OR(SAPMCTL, 1UL << 31); /* SA PM */ - MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(REQLIM, 1UL << 31); - MCHBAR32_OR(DMIVCLIM, 1UL << 31); - MCHBAR32_OR(CRDTLCK, 1 << 0); + mchbar32_set(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ + mchbar32_set(SAPMCTL, 1UL << 31); /* SA PM */ + mchbar32_set(UMAGFXCTL, 1 << 0); /* UMA GFX */ + mchbar32_set(VTDTRKLCK, 1 << 0); /* VTDTRK */ + mchbar32_set(REQLIM, 1UL << 31); + mchbar32_set(DMIVCLIM, 1UL << 31); + mchbar32_set(CRDTLCK, 1 << 0); /* Memory Controller Lockdown */ MCHBAR8(MC_LOCK) = 0x8f; diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 44ea9b9..5cacec6 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -27,22 +27,8 @@ /* * MCHBAR + * As there are many registers, define them on a separate file */ - -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) - -/* As there are many registers, define them on a separate file */ #include "registers/mchbar.h" #define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index e1c26d1..fd4a238 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -12,6 +12,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <boot/tables.h> +#include <northbridge/intel/common/mchbar_ops.h> #include "chip.h" #include "haswell.h" diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 9c6c00f..f382db5 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -16,6 +16,8 @@ #include <spd.h> #include <security/vboot/vboot_common.h> #include <commonlib/region.h> +#include <northbridge/intel/common/mchbar_ops.h> + #include "raminit.h" #include "pei_data.h" #include "haswell.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/45574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9 Gerrit-Change-Number: 45574 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/i945: Drop unneeded loop
by HAOUAS Elyes (Code Review) 18 Feb '21

18 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40369 ) Change subject: nb/i945: Drop unneeded loop ...................................................................... nb/i945: Drop unneeded loop At sdram_power_management() function, MCHBAR32(UPMC3) bit 16 is already set. Change-Id: Iefa53ceaa4fb9dd7868ea59a21d9bd11f3bf27b9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/40369/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index dad1cb2..4353a9c 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2147,7 +2147,6 @@ u16 reg16; u32 reg32; int integrated_graphics = pci_read_config16(PCI_DEV(0, 0x00, 0), GGC) & 2; - int i; reg32 = MCHBAR32(C0DRT2); reg32 &= 0xffffff00; @@ -2193,11 +2192,6 @@ MCHBAR32(UPMC3) = 0x000f06ff; - for (i = 0; i < 5; i++) { - MCHBAR32(UPMC3) &= ~(1 << 16); - MCHBAR32(UPMC3) |= (1 << 16); - } - MCHBAR32(GIPMC1) = 0x8000000c; reg16 = MCHBAR16(CPCTL); -- To view, visit https://review.coreboot.org/c/coreboot/+/40369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefa53ceaa4fb9dd7868ea59a21d9bd11f3bf27b9 Gerrit-Change-Number: 40369 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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