coreboot-gerrit September 2020

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Change in coreboot[master]: soc/mediatek/mt8192: Switch to highest DDR frequency to reduce bootup...
by CK HU (Code Review) 09 Mar '21

09 Mar '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44730 to review the following change. Change subject: soc/mediatek/mt8192: Switch to highest DDR frequency to reduce bootup time ...................................................................... soc/mediatek/mt8192: Switch to highest DDR frequency to reduce bootup time Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Ib37ecc7bf3f1776d27161948e779ed1f96ee9a0c --- M src/soc/mediatek/mt8192/dramc_dvfs.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 197 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/44730/1 diff --git a/src/soc/mediatek/mt8192/dramc_dvfs.c b/src/soc/mediatek/mt8192/dramc_dvfs.c index eb37ac3..fbb23bb 100644 --- a/src/soc/mediatek/mt8192/dramc_dvfs.c +++ b/src/soc/mediatek/mt8192/dramc_dvfs.c @@ -3,6 +3,11 @@ #include <soc/dramc_pi_api.h> #include <soc/dramc_register.h> +typedef enum { + SRAM_SHU_TYPE_LOAD, + SRAM_SHU_TYPE_RESTORE, +} sram_shu_type; + void enable_dfs_hw_mode_clk(void) { for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { @@ -17,6 +22,62 @@ } } +static void no_queue_flush_wa(bool wa_enable) +{ + u32 bc_bak = 0; + static u32 perfctl0_bak = 0; + + bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_ON); + + if (wa_enable) { + perfctl0_bak = (read32(&ch[0].ao.perfctl0) >> 10) & 0x3; + SET32_BITFIELDS(&ch[0].ao.perfctl0, + PERFCTL0_RWAGEEN, 0, + PERFCTL0_EMILLATEN, 0); + } else { + SET32_BITFIELDS(&ch[0].ao.perfctl0, + PERFCTL0_RWAGEEN, perfctl0_bak & 0x1, + PERFCTL0_EMILLATEN, (perfctl0_bak >>1) & 0x1); + } + + dramc_set_broadcast(bc_bak); +} + +static void wait_sram_shu_ack(sram_shu_type type) +{ + u8 ack_state = 0, complete = 1; + + for (u8 chn = CHANNEL_A; chn < CHANNEL_MAX; chn++) { + do { + if (type == SRAM_SHU_TYPE_LOAD) + ack_state = READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK); + else + ack_state = READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK); + } while(ack_state != complete); + } +} + +static void timing_tx_sr(u32 shu_level) +{ + u32 onoff = 0, bc_bak = 0; + + bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_ON); + + if ((shu_level == DRAM_DFS_SHU4) || (shu_level == DRAM_DFS_SHU5) || + (shu_level == DRAM_DFS_SHU6)) + onoff = 0; + else + onoff = 1; + + SET32_BITFIELDS(&ch[0].ao.refctrl1, + REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA, onoff); + dramc_set_broadcast(bc_bak); +} + void dramc_dfs_direct_jump_rg_mode(const struct ddr_cali *cali, u8 shu_level) { u8 shu_ack = 0; @@ -109,6 +170,129 @@ pll_mode = !pll_mode; *(cali->pll_mode) = pll_mode; + dramc_dbg("%s end with pll_mode:%d\n", __func__, *(cali->pll_mode)); +} + +void dramc_dfs_direct_jump_sram_shu_rg_mode(const struct ddr_cali *cali, + dram_dfs_shu shu_level) +{ + u8 shu_ack = 0; + u8 pll_mode = *(cali->pll_mode); + u32 *shu_ack_reg = &mtk_dpm->status_4; + + if (pll_mode == PHYPLL_MODE) { + dramc_dbg("Disable CLRPLL\n"); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.clrpll0, CLRPLL0_RG_RCLRPLL_EN, 0); + } else { + dramc_dbg("Disable PHYPLL\n"); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 0); + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + shu_ack |= (0x1 << chn); + + if (pll_mode == PHYPLL_MODE) + dramc_dbg("DFSDirectJump to CLRPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, shu_ack); + else + dramc_dbg("DFSDirectJump to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, shu_ack); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM_LATCH, 1); + } + + udelay(1); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM_LATCH, 0); + + if (pll_mode == PHYPLL_MODE) { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL, !pll_mode); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN, 1); + } + dramc_dbg("Enable CLRPLL\n"); + } else { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL, !pll_mode); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN, 1); + } + dramc_dbg("Enable PHYPLL\n"); + } + + udelay(1); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM, shu_level); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SRAM_LOAD, 1); + } + + wait_sram_shu_ack(SRAM_SHU_TYPE_LOAD); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SRAM_LOAD, 0); + + if (pll_mode == PHYPLL_MODE) + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.clrpll0, CLRPLL0_RG_RCLRPLL_EN, 1); + else + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 1); + + no_queue_flush_wa(true); + + udelay(20); + + dramc_dbg("SHUFFLE Start\n"); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SHU_EN, 1); + + while ((READ32_BITFIELD(shu_ack_reg, LPIF_STATUS_4_SHU_EN_ACK) != shu_ack)) + dramc_dbg("wait shu_en ack.\n"); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, MISC_RG_DFS_CTRL_RG_DR_SHU_EN, 0); + dramc_dbg("SHUFFLE End\n"); + + if (pll_mode == PHYPLL_MODE) + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 0); + else + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.clrpll0, CLRPLL0_RG_RCLRPLL_EN, 0); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE, 1); + + wait_sram_shu_ack(SRAM_SHU_TYPE_RESTORE); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE, 0); + + no_queue_flush_wa(false); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN, 0); + + timing_tx_sr(shu_level); + + dramc_dbg("Shuffle flow complete\n"); + *(cali->pll_mode) = !pll_mode; } void dvfs_settings(const struct ddr_cali *cali) diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 2bcc449..72f9a24 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -440,5 +440,18 @@ after_calib(&cali); enable_dfs_hw_mode_clk(); + if (CONFIG(MT8192_DRAM_DVFS)) { + dram_cali_seq bootup_cali_seq = CALI_SEQ5; + dram_dfs_shu bootup_shu = get_shu_save_by_k_shu(bootup_cali_seq); + + set_cali_datas(&cali, dparam, bootup_cali_seq); + set_vcore_voltage_for_each_freq(&cali); + + dramc_dfs_direct_jump_sram_shu_rg_mode(&cali, DRAM_DFS_SHU1); + dramc_dfs_direct_jump_sram_shu_rg_mode(&cali, bootup_shu); + dramc_info("switch to frequency %d to decrease the bootup time\n", + get_frequency_by_shu(bootup_shu)); + } + dramc_runtime_config(&cali); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib37ecc7bf3f1776d27161948e779ed1f96ee9a0c Gerrit-Change-Number: 44730 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

6 12

Change in coreboot[master]: soc/mediatek/mt8192: Do write leveling training
by CK HU (Code Review) 09 Mar '21

09 Mar '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44717 to review the following change. Change subject: soc/mediatek/mt8192: Do write leveling training ...................................................................... soc/mediatek/mt8192: Do write leveling training Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Icf4f5d07eb8ef1d0d99ad106f497fea5f60c8a97 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 196 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/44717/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 84acb3e..d418228 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -4096,6 +4096,191 @@ move_dramc_delay(cali, &ui_regs[idx], &mck_regs[idx], shift_ui); } +static void shift_dq_oen_ui(const struct ddr_cali* cali, u8 rk) +{ + s8 shift_ui = -1; + u8 chn = cali->chn; + reg_transfer ui_regs[] = {{&ch[chn].ao.shu_rk[rk].shurk_selph_dq3, 16}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq3, 20}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq2, 16}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq2, 20}}; + reg_transfer mck_regs[] = {{&ch[chn].ao.shu_rk[rk].shurk_selph_dq1, 16}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq1, 20}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq0, 16}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq0, 20}}; + + for (u8 idx = 0; idx < ARRAY_SIZE(ui_regs); idx++) + move_dramc_delay(cali, &ui_regs[idx], &mck_regs[idx], shift_ui); +} + +static void shift_dqs_ui(const struct ddr_cali* cali, s8 shift_ui, u8 byte) +{ + u8 idx, step; + u8 chn = cali->chn; + + if (byte == 0) { + idx = 0; + step = 2; + } else if (byte == 1) { + idx = 1; + step = 2; + } else { + idx = 0; + step = 1; + } + + reg_transfer ui_regs[] = {{&ch[chn].ao.shu_selph_dqs1, 0}, + {&ch[chn].ao.shu_selph_dqs1, 4}}; + reg_transfer mck_regs[] = {{&ch[chn].ao.shu_selph_dqs0, 0}, + {&ch[chn].ao.shu_selph_dqs0, 4}}; + for (; idx < ARRAY_SIZE(ui_regs); idx += step) + move_dramc_delay(cali, &ui_regs[idx], &mck_regs[idx], shift_ui); +} + +static void shift_dqs_oen_ui(const struct ddr_cali* cali, s8 shift_ui, u8 byte) +{ + u8 idx, step; + u8 chn = cali->chn; + + if (byte == 0) { + idx = 0; + step = 2; + } else if (byte == 1) { + idx = 1; + step = 2; + } else { + idx = 0; + step = 1; + } + + reg_transfer ui_regs[] = {{&ch[chn].ao.shu_selph_dqs1, 16}, + {&ch[chn].ao.shu_selph_dqs1, 20}}; + reg_transfer mck_regs[] = {{&ch[chn].ao.shu_selph_dqs0, 16}, + {&ch[chn].ao.shu_selph_dqs0, 20}}; + for (; idx < ARRAY_SIZE(ui_regs); idx += step) + move_dramc_delay(cali, &ui_regs[idx], &mck_regs[idx], shift_ui); +} + +static void shift_dq_ui_all_rk(const struct ddr_cali* cali) +{ + s8 shift_ui = -1; + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) + shift_dq_ui(cali, rk, shift_ui); +} + +static void shift_dq_oen_ui_all_rk(const struct ddr_cali* cali) +{ + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) + shift_dq_oen_ui(cali, rk); +} + +static void shift_dqs_wck_ui(const struct ddr_cali* cali, s8 shift_ui, u8 byte) +{ + shift_dqs_ui(cali, shift_ui, byte); + shift_dqs_oen_ui(cali, shift_ui, byte); +} + +static void write_leveling_move_dqs_instead_of_clk(const struct ddr_cali* cali) +{ + s8 shift_ui = -1; + u8 chn = cali->chn; + + shift_dq_ui_all_rk(cali); + shift_dq_oen_ui_all_rk(cali); + shift_dqs_wck_ui(cali, shift_ui, BYTE_NUM); + + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[0].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[0].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0); +} + +static void set_dram_mr_write_leveling(const struct ddr_cali* cali, bool state) +{ + u8 chn = cali->chn; + u8 rank = cali->rank; + struct mr_values *mr_value = cali->mr_value; + u8 mr02 = mr_value->mr02[get_fsp(cali)]; + + if (state) + mr02 |= 0x80; + else + mr02 &= 0x7f; + + dramc_mode_reg_write_by_rank(cali, chn, rank, 2, mr02); +} + +void dramc_write_leveling(const struct ddr_cali* cali, u8 wl_dqs_final_delay[2][2]) +{ + s8 shift_ui; + u8 chn = cali->chn; + u8 rank = cali->rank; + u16 pi_bound; + + struct reg_bak regs_bak[] = { + {&ch[chn].ao.dramc_pd_ctrl}, + {&ch[chn].ao.cbt_wlev_ctrl0}, + {&ch[chn].ao.cbt_wlev_ctrl1}, + {&ch[chn].ao.cbt_wlev_ctrl3}, + {&ch[chn].ao.cbt_wlev_ctrl5}, + {&ch[chn].phy_ao.byte[0].shu_b0_vref}, + {&ch[chn].phy_ao.byte[1].shu_b0_vref}, + {&ch[chn].phy_ao.byte[0].rk[rank].shu_b0_phy_vref_sel}, + {&ch[chn].phy_ao.byte[1].rk[rank].shu_b0_phy_vref_sel}, + {&ch[chn].ao.dramc_pd_ctrl}, + }; + + if ((cali->freq_group == DDRFREQ_400) && (rank == RANK_1)) + return; + + if (cali->freq_group == DDRFREQ_400) + pi_bound = 32; + else + pi_bound = 64; + + wl_dqs_final_delay[rank][0] = cali->params->wr_level[chn][rank][0]; + wl_dqs_final_delay[rank][1] = cali->params->wr_level[chn][rank][1]; + dramc_dbg("WRITELEVELING DQS0:%d, DQS1:%d, pi_bound:%d\n", + wl_dqs_final_delay[rank][0], wl_dqs_final_delay[rank][1], pi_bound); + + dramc_auto_refresh_switch(chn, false); + + SET32_BITFIELDS(&ch[chn].ao.tx_set0, TX_SET0_TXRANK, rank); + SET32_BITFIELDS(&ch[chn].ao.tx_set0, TX_SET0_TXRANKFIX, 1); + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + if (rank == RANK_0) + write_leveling_move_dqs_instead_of_clk(cali); + + set_dram_mr_write_leveling(cali, false); + + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, CBT_WLEV_CTRL0_WRITE_LEVEL_EN, 0); + o1_path_on_off(cali, O1_OFF); + SET32_BITFIELDS(&ch[chn].ao.tx_set0, TX_SET0_TXRANK, 0); + SET32_BITFIELDS(&ch[chn].ao.tx_set0, TX_SET0_TXRANKFIX, 0); + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); + + for (u8 byte = 0; byte < BYTE_NUM; byte++) { + dramc_dbg("Write leveling (Byte %d): %d", byte, wl_dqs_final_delay[rank][byte]); + if (wl_dqs_final_delay[rank][byte] >= pi_bound) { + shift_ui = (wl_dqs_final_delay[rank][byte] / pi_bound) * (pi_bound / 32); + shift_dqs_wck_ui(cali, shift_ui, byte); + wl_dqs_final_delay[rank][byte] %= pi_bound; + } + dramc_dbg(" => %d\n", wl_dqs_final_delay[rank][byte]); + } + + for (u8 rk = rank; rk < RANK_MAX; rk++) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rk].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_ARPI_PBYTE_B0, wl_dqs_final_delay[rank][0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rk].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_ARPI_PBYTE_B1, wl_dqs_final_delay[rank][1]); + } +} static void ddr_update_ac_timing(const struct ddr_cali *cali) { u8 table_idx; diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 214bf55..2be3962 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -220,6 +220,8 @@ static void dramc_calibration_single_channel(struct ddr_cali *cali, u8 chn) { + u8 dqs_final_delay[RANK_MAX][DQS_NUMBER]; + cali->chn = chn; SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0, @@ -233,6 +235,15 @@ } shuffle_dfs_to_fsp1(cali); + + for (u8 rank = RANK_0; rank < cali->support_ranks; rank++) { + cali->rank = rank; + dramc_dbg("Start K CH %d, RK %d\n", chn, rank); + + /* should disable the auto refresh before do write leveling */ + dramc_auto_refresh_switch(chn, false); + dramc_write_leveling(cali, dqs_final_delay); + } } static void dramc_calibration_all_channels(struct ddr_cali *cali) -- To view, visit https://review.coreboot.org/c/coreboot/+/44717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf4f5d07eb8ef1d0d99ad106f497fea5f60c8a97 Gerrit-Change-Number: 44717 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

6 13

Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss
by Brandon Breitenstein (Code Review) 05 Mar '21

05 Mar '21

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42079 ) Change subject: soc/intel/tigerlake: Add code for early tcss ...................................................................... soc/intel/tigerlake: Add code for early tcss In order for USB Type-C to be detected prior to loading Kernel PMC IPC driver is needed to communicate with PMC in order to correctly set the USB Mux settings. This patch is adding in support for early detection of both USB and Display Port. BUG=b:141608957 BRANCH=NONE TEST: built and booted TGL U RVP Change-Id: I58e66f21210d565fb8145d140d2fc7febecdd21a Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/chip.c A src/soc/intel/tigerlake/early_tcss.c A src/soc/intel/tigerlake/include/soc/early_tcss.h 5 files changed, 266 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/42079/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index fbf56b4..55c06b1 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -208,4 +208,10 @@ config PRERAM_CBMEM_CONSOLE_SIZE hex default 0xe00 + +config EARLY_TCSS + bool "Enable early TCSS" + help + Enable devices to be detected over Type-C ports during boot. + endif diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index c4f71c7..5e60114 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -31,6 +31,7 @@ ramstage-y += acpi.c ramstage-y += chip.c ramstage-y += cpu.c +ramstage-$(CONFIG_EARLY_TCSS) += early_tcss.c ramstage-y += elog.c ramstage-y += espi.c ramstage-y += finalize.c diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 00db2a4..3da5d9a 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -10,6 +10,7 @@ #include <intelblocks/itss.h> #include <intelblocks/xdci.h> #include <romstage_handoff.h> +#include <soc/early_tcss.h> #include <soc/intel/common/vbt.h> #include <soc/itss.h> #include <soc/pci_devs.h> @@ -129,6 +130,10 @@ * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + /* Check for early TCSS and connect devices */ + if (CONFIG(EARLY_TCSS)) + early_tcss_enable(); + /* Perform silicon specific init. */ fsp_silicon_init(romstage_handoff_is_resume()); diff --git a/src/soc/intel/tigerlake/early_tcss.c b/src/soc/intel/tigerlake/early_tcss.c new file mode 100644 index 0000000..942d490 --- /dev/null +++ b/src/soc/intel/tigerlake/early_tcss.c @@ -0,0 +1,206 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <bootstate.h> +#include <console/console.h> +#include <device/pci.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/pmclib.h> +#include <soc/early_tcss.h> +#include <soc/pci_devs.h> +#include <stdlib.h> + +/* send the ipc_command */ +static int send_ipc_command(uint32_t cmd, uint8_t *tcss_req, int req_size, + struct pmc_ipc_buffer *rbuf) +{ + struct pmc_ipc_buffer *wbuf = malloc(sizeof(*tcss_req)); + + /* copy the tcss_req into a buffer for ipc command */ + memcpy(wbuf, tcss_req, req_size); + + return pmc_send_ipc_cmd(cmd, wbuf, rbuf); +} + +static int send_pmc_connect_request(struct tcss_mux mux_data, + struct pmc_ipc_buffer *rbuf) +{ + union pmc_ipc_cmd tcss_cmd = { 0 }; + uint8_t tcss_req[PMC_IPC_CONN_REQ_SIZE] = { 0 }; + + tcss_cmd.cmd = PMC_IPC_USBC_CMD_ID; + tcss_cmd.subcmd = PMC_IPC_USBC_SUBCMD_ID; + + tcss_req[0] = PMC_IPC_TCSS_CONN_REQ_RES | /* Usage */ + mux_data.usb3_port << 4; + tcss_req[1] = mux_data.usb2_port | + mux_data.ufp << 4 | /* 1=UFP/0=DFP */ + mux_data.polarity << 5 | /* ORI-HSL */ + mux_data.polarity << 6 | /* ORI-SBU */ + mux_data.acc << 7; + printk(BIOS_DEBUG, "tcss_req[0]-> 0x%x\n" + "tcss_req[1]-> 0x%x\n\t", tcss_req[0], tcss_req[1]); + + tcss_cmd.len = PMC_IPC_CONN_REQ_SIZE; + + return send_ipc_command(tcss_cmd.cmd_reg, tcss_req, PMC_IPC_CONN_REQ_SIZE, rbuf); +} + +static int send_pmc_safe_mode_request(struct tcss_mux mux_data, + struct pmc_ipc_buffer *rbuf) +{ + union pmc_ipc_cmd tcss_cmd = { 0 }; + uint8_t tcss_req[PMC_IPC_SAFE_REQ_SIZE] = { 0 }; + + tcss_cmd.cmd = PMC_IPC_USBC_CMD_ID; + tcss_cmd.subcmd = PMC_IPC_USBC_SUBCMD_ID; + + tcss_req[0] = PMC_IPC_TCSS_SAFE_MODE_REQ_RES | + mux_data.usb3_port << 4; + printk(BIOS_DEBUG, "tcss_req[0]-> 0x%x\n", tcss_req[0]); + + tcss_cmd.cmd.len = PMC_IPC_SAFE_REQ_SIZE; + + return send_ipc_command(tcss_cmd.cmd_reg, tcss_req, PMC_IPC_SAFE_REQ_SIZE, rbuf); +} + +static int send_pmc_alt_mode_request(struct tcss_mux mux_data, + struct pmc_ipc_buffer *rbuf) +{ + union pmc_ipc_cmd tcss_cmd = { 0 }; + uint8_t tcss_req[PMC_IPC_ALT_REQ_SIZE] = { 0 }; + + tcss_cmd.cmd = PMC_IPC_USBC_CMD_ID; + tcss_cmd.subcmd = PMC_IPC_USBC_SUBCMD_ID; + + tcss_req[0] = PMC_IPC_TCSS_ALTMODE_REQ_RES | mux_data.usb3_port << 4; + tcss_req[1] |= PMC_IPC_DP_MODE; + + tcss_req[4] = mux_data.polarity << 1 | + mux_data.cable << 2 | + mux_data.ufp << 3 | + mux_data.polarity << 4 | + mux_data.polarity << 5; + + if (mux_data.dp_mode <= MODE_DP_PIN_F) { + switch (mux_data.dp_mode) { + case MODE_DP_PIN_A: + tcss_req[5] = 0; + break; + case MODE_DP_PIN_B: + tcss_req[5] = 1; + break; + case MODE_DP_PIN_C: + tcss_req[5] = 2; + break; + case MODE_DP_PIN_D: + tcss_req[5] = 3; + break; + case MODE_DP_PIN_E: + tcss_req[5] = 4; + break; + case MODE_DP_PIN_F: + tcss_req[5] = 5; + break; + } + } + + tcss_req[5] |= mux_data.hpd_lvl << 6; + printk(BIOS_DEBUG, "tcss_req[0]-> 0x%x\n" + "tcss_req[1]-> 0x%x\n" + "tcss_req[4]-> 0x%x\n" + "tcss_req[5]-> 0x%x\n\t", + tcss_req[0], tcss_req[1], tcss_req[4], tcss_req[5]); + + tcss_cmd.len = PMC_IPC_ALT_REQ_SIZE; + + return send_ipc_command(tcss_cmd.cmd_reg, tcss_req, PMC_IPC_ALT_REQ_SIZE, rbuf); +} + +static void update_tcss_mux(int port, struct tcss_mux mux_data) +{ + struct pmc_ipc_buffer *rbuf = malloc(sizeof(*rbuf)); + int ret = 0; + + /* Check if the mux has a USB device */ + if (mux_data.usb) { + ret = send_pmc_connect_request(mux_data, rbuf); + if (ret) { + printk(BIOS_ERR, "Port %d connect request failed\n", port); + return; + } + } + + /* check if mux has a DP device */ + if (mux_data.dp) { + + if (!mux_data.usb) { + ret = send_pmc_connect_request(mux_data, rbuf); + if (ret) { + printk(BIOS_ERR, "Port %d connect request failed\n", port); + return; + } + } + ret = send_pmc_safe_mode_request(mux_data, rbuf); + if (ret) { + printk(BIOS_ERR, "Port %d safe mode request failed\n", port); + return; + } + + ret = send_pmc_alt_mode_request(mux_data, rbuf); + } + + if (ret) + printk(BIOS_ERR, "Port %d mux set failed with error %d\n", port, ret); +} + +void early_tcss_enable(void) +{ + uint8_t num_ports; + int ret, i; + + ret = google_chromeec_get_num_pd_ports(&num_ports); + if (ret < 0) + return; + + for (i = 0; i < num_ports; i++) { + uint8_t port_map, mux_flags; + struct tcss_mux mux_data; + + ret = google_chromeec_usb_get_pd_mux_info(i, &mux_flags); + if (ret < 0) + continue; + + ret = google_chromeec_pd_get_port_info(i, &port_map); + if (ret < 0) + continue; + + ret = google_chromeec_usb_pd_control(i, &mux_data.ufp, &mux_data.acc, + &mux_data.dp_mode); + if (ret < 0) + continue; + + mux_data.usb = !!(mux_flags & USB_PD_CTRL_USB_ENABLED); + mux_data.dp = !!(mux_flags & USB_PD_CTRL_DP_ENABLED); + mux_data.cable = !!(mux_flags & USB_PD_MUX_TBT_ACTIVE_CABLE); + mux_data.polarity = !!(mux_flags & USB_PD_CTRL_POLARITY_INVERTED); + mux_data.hpd_irq = !!(mux_flags & USB_PD_CTRL_HPD_IRQ); + mux_data.hpd_lvl = !!(mux_flags & USB_PD_CTRL_HPD_LVL); + mux_data.usb2_port = port_map & 0x0F; + mux_data.usb3_port = (port_map & 0xF0) >> 4; + + printk(BIOS_DEBUG, "Port %d mux=0x%x\n" + "USB2 port = %x\n" + "USB3 port = %x\n" + "ufp = %d dbg_acc=%d\n", + i, (unsigned int)mux_flags, mux_data.usb2_port, + mux_data.usb3_port, mux_data.ufp, mux_data.acc); + + update_tcss_mux(i, mux_data); + } +} diff --git a/src/soc/intel/tigerlake/include/soc/early_tcss.h b/src/soc/intel/tigerlake/include/soc/early_tcss.h new file mode 100644 index 0000000..29b7cdd --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/early_tcss.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* PMC IPC related offsets and commands */ +#define PMC_IPC_USBC_CMD_ID 0xA7 +#define PMC_IPC_USBC_SUBCMD_ID 0x0 +#define PMC_IPC_CMD 0x0 +#define PMC_IPC_TCSS_CONN_REQ_RES 0x0 +#define PMC_IPC_TCSS_SAFE_MODE_REQ_RES 0x2 +#define PMC_IPC_TCSS_ALTMODE_REQ_RES 0x3 +#define PMC_IPC_CONN_REQ_SIZE 2 +#define PMC_IPC_ALT_REQ_SIZE 8 +#define PMC_IPC_SAFE_REQ_SIZE 1 +#define PMC_IPC_DP_MODE BIT(4) + +/* connection modes for pmc */ +enum pmc_ipc_conn_mode { + PMC_IPC_TCSS_DISCONNECT_MODE, + PMC_IPC_TCSS_USB_MODE, + PMC_IPC_TCSS_ALTERNATE_MODE, + PMC_IPC_TCSS_SAFE_MODE, + PMC_IPC_TCSS_HPD_MODE, + PMC_IPC_TCSS_TOTAL_MODES, +}; + +/* DP Mode pin definitions */ +#define MODE_DP_PIN_A BIT(0) +#define MODE_DP_PIN_B BIT(1) +#define MODE_DP_PIN_C BIT(2) +#define MODE_DP_PIN_D BIT(3) +#define MODE_DP_PIN_E BIT(4) +#define MODE_DP_PIN_F BIT(5) + +/* struct to hold all tcss_mux related variables */ +struct tcss_mux { + bool dp; /* DP connected */ + bool usb; /* USB connected */ + bool cable; /* Activ/Passive Cable */ + bool polarity; /* polarity of connected device */ + bool hpd_lvl; /* HPD Level assert */ + bool hpd_irq; /* HPD IRQ assert */ + bool ufp; + bool acc; + uint8_t dp_mode; /* DP Operation Mode */ + uint8_t usb3_port; /* USB2 Port Number */ + uint8_t usb2_port; /* USB3 Port Number */ +}; + +void early_tcss_enable(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/42079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e66f21210d565fb8145d140d2fc7febecdd21a Gerrit-Change-Number: 42079 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

7 64

Change in coreboot[master]: soc/intel/common/block/smbus: Add config to use ACPI
by Maxim Polyakov (Code Review) 03 Mar '21

03 Mar '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44865 ) Change subject: soc/intel/common/block/smbus: Add config to use ACPI ...................................................................... soc/intel/common/block/smbus: Add config to use ACPI Change-Id: Iafa7d40fc21e62f99dbdc2001ab6525a2a77ff50 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/common/block/smbus/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/44865/1 diff --git a/src/soc/intel/common/block/smbus/Kconfig b/src/soc/intel/common/block/smbus/Kconfig index fe940cc..818200e 100644 --- a/src/soc/intel/common/block/smbus/Kconfig +++ b/src/soc/intel/common/block/smbus/Kconfig @@ -3,6 +3,13 @@ help Intel Processor common SMBus support +config SOC_INTEL_COMMON_BLOCK_SMBUS_ACPI_DRIVER + bool + default n + depends on SOC_INTEL_COMMON_BLOCK_SMBUS + help + Intel Processor SMBus ACPI driver support + config SOC_INTEL_COMMON_BLOCK_TCO bool help -- To view, visit https://review.coreboot.org/c/coreboot/+/44865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafa7d40fc21e62f99dbdc2001ab6525a2a77ff50 Gerrit-Change-Number: 44865 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mb/lippert/frontrunner-af: Rename to `f14-halfboards`
by Angel Pons (Code Review) 02 Mar '21

02 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43289 ) Change subject: mb/lippert/frontrunner-af: Rename to `f14-halfboards` ...................................................................... mb/lippert/frontrunner-af: Rename to `f14-halfboards` There are two different boards inside this folder. Change-Id: I2a44af225f5e22dcee83009f0fdcb00d8a2bd1a0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- R src/mainboard/lippert/f14-halfboards/Kconfig R src/mainboard/lippert/f14-halfboards/Kconfig.name R src/mainboard/lippert/f14-halfboards/Makefile.inc R src/mainboard/lippert/f14-halfboards/OptionsIds.h R src/mainboard/lippert/f14-halfboards/acpi/routing.asl R src/mainboard/lippert/f14-halfboards/acpi/sata.asl R src/mainboard/lippert/f14-halfboards/acpi/superio.asl R src/mainboard/lippert/f14-halfboards/acpi/usb.asl R src/mainboard/lippert/f14-halfboards/acpi_tables.c R src/mainboard/lippert/f14-halfboards/board_info.txt R src/mainboard/lippert/f14-halfboards/buildOpts.c R src/mainboard/lippert/f14-halfboards/cmos.layout R src/mainboard/lippert/f14-halfboards/dsdt.asl R src/mainboard/lippert/f14-halfboards/irq_tables.c R src/mainboard/lippert/f14-halfboards/mptable.c R src/mainboard/lippert/f14-halfboards/platform_cfg.h R src/mainboard/lippert/f14-halfboards/sema.c R src/mainboard/lippert/f14-halfboards/sema.h R src/mainboard/lippert/f14-halfboards/variants/frontrunner-af/BiosCallOuts.c R src/mainboard/lippert/f14-halfboards/variants/frontrunner-af/OemCustomize.c R src/mainboard/lippert/f14-halfboards/variants/frontrunner-af/board_info.txt R src/mainboard/lippert/f14-halfboards/variants/frontrunner-af/bootblock.c R src/mainboard/lippert/f14-halfboards/variants/frontrunner-af/devicetree.cb R src/mainboard/lippert/f14-halfboards/variants/frontrunner-af/mainboard.c R src/mainboard/lippert/f14-halfboards/variants/toucan-af/BiosCallOuts.c R src/mainboard/lippert/f14-halfboards/variants/toucan-af/OemCustomize.c R src/mainboard/lippert/f14-halfboards/variants/toucan-af/board_info.txt R src/mainboard/lippert/f14-halfboards/variants/toucan-af/bootblock.c R src/mainboard/lippert/f14-halfboards/variants/toucan-af/devicetree.cb R src/mainboard/lippert/f14-halfboards/variants/toucan-af/mainboard.c 30 files changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/43289/1 diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/f14-halfboards/Kconfig similarity index 100% rename from src/mainboard/lippert/frontrunner-af/Kconfig rename to src/mainboard/lippert/f14-halfboards/Kconfig diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig.name b/src/mainboard/lippert/f14-halfboards/Kconfig.name similarity index 100% rename from src/mainboard/lippert/frontrunner-af/Kconfig.name rename to src/mainboard/lippert/f14-halfboards/Kconfig.name diff --git a/src/mainboard/lippert/frontrunner-af/Makefile.inc b/src/mainboard/lippert/f14-halfboards/Makefile.inc similarity index 100% rename from src/mainboard/lippert/frontrunner-af/Makefile.inc rename to src/mainboard/lippert/f14-halfboards/Makefile.inc diff --git a/src/mainboard/lippert/frontrunner-af/OptionsIds.h b/src/mainboard/lippert/f14-halfboards/OptionsIds.h similarity index 100% rename from src/mainboard/lippert/frontrunner-af/OptionsIds.h rename to src/mainboard/lippert/f14-halfboards/OptionsIds.h diff --git a/src/mainboard/lippert/frontrunner-af/acpi/routing.asl b/src/mainboard/lippert/f14-halfboards/acpi/routing.asl similarity index 100% rename from src/mainboard/lippert/frontrunner-af/acpi/routing.asl rename to src/mainboard/lippert/f14-halfboards/acpi/routing.asl diff --git a/src/mainboard/lippert/frontrunner-af/acpi/sata.asl b/src/mainboard/lippert/f14-halfboards/acpi/sata.asl similarity index 100% rename from src/mainboard/lippert/frontrunner-af/acpi/sata.asl rename to src/mainboard/lippert/f14-halfboards/acpi/sata.asl diff --git a/src/mainboard/lippert/frontrunner-af/acpi/superio.asl b/src/mainboard/lippert/f14-halfboards/acpi/superio.asl similarity index 100% rename from src/mainboard/lippert/frontrunner-af/acpi/superio.asl rename to src/mainboard/lippert/f14-halfboards/acpi/superio.asl diff --git a/src/mainboard/lippert/frontrunner-af/acpi/usb.asl b/src/mainboard/lippert/f14-halfboards/acpi/usb.asl similarity index 100% rename from src/mainboard/lippert/frontrunner-af/acpi/usb.asl rename to src/mainboard/lippert/f14-halfboards/acpi/usb.asl diff --git a/src/mainboard/lippert/frontrunner-af/acpi_tables.c b/src/mainboard/lippert/f14-halfboards/acpi_tables.c similarity index 100% rename from src/mainboard/lippert/frontrunner-af/acpi_tables.c rename to src/mainboard/lippert/f14-halfboards/acpi_tables.c diff --git a/src/mainboard/lippert/frontrunner-af/board_info.txt b/src/mainboard/lippert/f14-halfboards/board_info.txt similarity index 100% rename from src/mainboard/lippert/frontrunner-af/board_info.txt rename to src/mainboard/lippert/f14-halfboards/board_info.txt diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/f14-halfboards/buildOpts.c similarity index 100% rename from src/mainboard/lippert/frontrunner-af/buildOpts.c rename to src/mainboard/lippert/f14-halfboards/buildOpts.c diff --git a/src/mainboard/lippert/frontrunner-af/cmos.layout b/src/mainboard/lippert/f14-halfboards/cmos.layout similarity index 100% rename from src/mainboard/lippert/frontrunner-af/cmos.layout rename to src/mainboard/lippert/f14-halfboards/cmos.layout diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/f14-halfboards/dsdt.asl similarity index 100% rename from src/mainboard/lippert/frontrunner-af/dsdt.asl rename to src/mainboard/lippert/f14-halfboards/dsdt.asl diff --git a/src/mainboard/lippert/frontrunner-af/irq_tables.c b/src/mainboard/lippert/f14-halfboards/irq_tables.c similarity index 100% rename from src/mainboard/lippert/frontrunner-af/irq_tables.c rename to src/mainboard/lippert/f14-halfboards/irq_tables.c diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/f14-halfboards/mptable.c similarity index 100% rename from src/mainboard/lippert/frontrunner-af/mptable.c rename to src/mainboard/lippert/f14-halfboards/mptable.c diff --git a/src/mainboard/lippert/frontrunner-af/platform_cfg.h b/src/mainboard/lippert/f14-halfboards/platform_cfg.h similarity index 100% rename from src/mainboard/lippert/frontrunner-af/platform_cfg.h rename to src/mainboard/lippert/f14-halfboards/platform_cfg.h diff --git a/src/mainboard/lippert/frontrunner-af/sema.c b/src/mainboard/lippert/f14-halfboards/sema.c similarity index 100% rename from src/mainboard/lippert/frontrunner-af/sema.c rename to src/mainboard/lippert/f14-halfboards/sema.c diff --git a/src/mainboard/lippert/frontrunner-af/sema.h b/src/mainboard/lippert/f14-halfboards/sema.h similarity index 100% rename from src/mainboard/lippert/frontrunner-af/sema.h rename to src/mainboard/lippert/f14-halfboards/sema.h diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/BiosCallOuts.c b/src/mainboard/lippert/f14-halfboards/variants/frontrunner-af/BiosCallOuts.c similarity index 100% rename from src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/BiosCallOuts.c rename to src/mainboard/lippert/f14-halfboards/variants/frontrunner-af/BiosCallOuts.c diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/OemCustomize.c b/src/mainboard/lippert/f14-halfboards/variants/frontrunner-af/OemCustomize.c similarity index 100% rename from src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/OemCustomize.c rename to src/mainboard/lippert/f14-halfboards/variants/frontrunner-af/OemCustomize.c diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/board_info.txt b/src/mainboard/lippert/f14-halfboards/variants/frontrunner-af/board_info.txt similarity index 100% rename from src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/board_info.txt rename to src/mainboard/lippert/f14-halfboards/variants/frontrunner-af/board_info.txt diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c b/src/mainboard/lippert/f14-halfboards/variants/frontrunner-af/bootblock.c similarity index 100% rename from src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c rename to src/mainboard/lippert/f14-halfboards/variants/frontrunner-af/bootblock.c diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/devicetree.cb b/src/mainboard/lippert/f14-halfboards/variants/frontrunner-af/devicetree.cb similarity index 100% rename from src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/devicetree.cb rename to src/mainboard/lippert/f14-halfboards/variants/frontrunner-af/devicetree.cb diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c b/src/mainboard/lippert/f14-halfboards/variants/frontrunner-af/mainboard.c similarity index 100% rename from src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c rename to src/mainboard/lippert/f14-halfboards/variants/frontrunner-af/mainboard.c diff --git a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/BiosCallOuts.c b/src/mainboard/lippert/f14-halfboards/variants/toucan-af/BiosCallOuts.c similarity index 100% rename from src/mainboard/lippert/frontrunner-af/variants/toucan-af/BiosCallOuts.c rename to src/mainboard/lippert/f14-halfboards/variants/toucan-af/BiosCallOuts.c diff --git a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/OemCustomize.c b/src/mainboard/lippert/f14-halfboards/variants/toucan-af/OemCustomize.c similarity index 100% rename from src/mainboard/lippert/frontrunner-af/variants/toucan-af/OemCustomize.c rename to src/mainboard/lippert/f14-halfboards/variants/toucan-af/OemCustomize.c diff --git a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/board_info.txt b/src/mainboard/lippert/f14-halfboards/variants/toucan-af/board_info.txt similarity index 100% rename from src/mainboard/lippert/frontrunner-af/variants/toucan-af/board_info.txt rename to src/mainboard/lippert/f14-halfboards/variants/toucan-af/board_info.txt diff --git a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/bootblock.c b/src/mainboard/lippert/f14-halfboards/variants/toucan-af/bootblock.c similarity index 100% rename from src/mainboard/lippert/frontrunner-af/variants/toucan-af/bootblock.c rename to src/mainboard/lippert/f14-halfboards/variants/toucan-af/bootblock.c diff --git a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/devicetree.cb b/src/mainboard/lippert/f14-halfboards/variants/toucan-af/devicetree.cb similarity index 100% rename from src/mainboard/lippert/frontrunner-af/variants/toucan-af/devicetree.cb rename to src/mainboard/lippert/f14-halfboards/variants/toucan-af/devicetree.cb diff --git a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c b/src/mainboard/lippert/f14-halfboards/variants/toucan-af/mainboard.c similarity index 100% rename from src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c rename to src/mainboard/lippert/f14-halfboards/variants/toucan-af/mainboard.c -- To view, visit https://review.coreboot.org/c/coreboot/+/43289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a44af225f5e22dcee83009f0fdcb00d8a2bd1a0 Gerrit-Change-Number: 43289 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 6

Change in coreboot[master]: tests: Add lib/imd-test test case
by Jan Dabros (Code Review) 01 Mar '21

01 Mar '21

Hello Anna Karaś, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44669 to review the following change. Change subject: tests: Add lib/imd-test test case ...................................................................... tests: Add lib/imd-test test case Implement unit tests for src/lib/imd.c module. Signed-off-by: Anna Karas <aka(a)semihalf.com> Signed-off-by: Jan Dabros <jsd(a)semihalf.com> Change-Id: I9d3ab45c3da2a21c910f52a84526b60c39ff1fe7 --- M tests/lib/Makefile.inc A tests/lib/imd-test.c 2 files changed, 813 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/44669/1 diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index b66d386..3062bca 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -3,6 +3,7 @@ tests-y += string-test tests-y += b64_decode-test tests-y += hexstrtobin-test +tests-y += imd-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -13,3 +14,7 @@ hexstrtobin-test-srcs += tests/lib/hexstrtobin-test.c hexstrtobin-test-srcs += src/lib/hexstrtobin.c + +imd-test-srcs += tests/lib/imd-test.c +imd-test-srcs += tests/stubs/console.c +imd-test-srcs += src/lib/imd.c \ No newline at end of file diff --git a/tests/lib/imd-test.c b/tests/lib/imd-test.c new file mode 100644 index 0000000..01a9e19 --- /dev/null +++ b/tests/lib/imd-test.c @@ -0,0 +1,808 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <imd.h> +#include <cbmem.h> +#include <stdlib.h> +#include <stdio.h> +#include <types.h> +#include <tests/test.h> +#include <limits.h> +#include <commonlib/bsd/helpers.h> + +void *calloc(size_t nitems, size_t size); +void *memset(void * ptr, int value, size_t num); + +/* In-memory data structures. */ +struct imd_root_pointer { + uint32_t magic; + /* Relative to upper limit/offset. */ + int32_t root_offset; +} __packed; + +struct imd_entry { + uint32_t magic; + /* start is located relative to imd_root */ + int32_t start_offset; + uint32_t size; + uint32_t id; +} __packed; + +struct imd_root { + uint32_t max_entries; + uint32_t num_entries; + uint32_t flags; + uint32_t entry_align; + /* Used for fixing the size of an imd. Relative to the root. */ + int32_t max_offset; + struct imd_entry entries[0]; +} __packed; + +/* Auxiliary functions and definitions. */ + +#define CBMEM_ID_IMD_ROOT 0xff4017ff +#define CBMEM_ID_IMD_SMALL 0x53a11439 + +#define IMD_FLAG_LOCKED 1 + +const uint32_t IMD_ROOT_PTR_MAGIC = 0xc0389481; +const uint32_t IMD_ENTRY_MAGIC = ~0xc0389481; +const uint32_t SMALL_REGION_ID = CBMEM_ID_IMD_SMALL; + +#define LIMIT_SZ (LIMIT_ALIGN + 1) +#define RP_SZ sizeof(struct imd_root_pointer) +#define ROOT_SZ sizeof(struct imd_root) +#define ENTRY_SZ sizeof(struct imd_entry) +#define IMD_SZ sizeof(struct imd) +#define CURSOR_SZ sizeof(struct imd_cursor) + +#define LG_ROOT_SIZE align_up_pow2(sizeof(struct imd_root_pointer) +\ + sizeof(struct imd_root) + 3 * sizeof(struct imd_entry)) +#define LG_ENTRY_ALIGN (2 * sizeof(int32_t)) +#define LG_ENTRY_SIZE (2 * sizeof(int32_t)) +#define LG_ENTRY_ID 0xA001 + +#define SM_ROOT_SIZE LG_ROOT_SIZE +#define SM_ENTRY_ALIGN sizeof(uint32_t) +#define SM_ENTRY_SIZE sizeof(uint32_t) +#define SM_ENTRY_ID 0xB001 + +uint32_t align_up_pow2(uint32_t x) { + return (IS_POWER_OF_2(x) ? x : 1 << (32 - __builtin_clz(x - 1))); +} + +size_t max_entries(size_t root_size) { + return (root_size - RP_SZ - ROOT_SZ) / ENTRY_SZ; +} + +/* + * Mainly, we should check that imd_handle_init() aligns upper_limit properly + * for various inputs. Upper limit is the _exclusive_ address, so we expect + * ALIGN_DOWN. + */ +static void test_imd_handle_init(void **state) +{ + int i; + void *base; + struct imd imd; + uintptr_t test_inputs[] = {0, 0xDEAA, 0xF0F0F0F0, ((1ULL << 32) + 4), + ((1ULL << 60) - 100)}; + + for (i = 0; i < ARRAY_SIZE(test_inputs); i++) { + base = (void *)test_inputs[i]; + + imd_handle_init(&imd, (void *)base); + + assert_int_equal(imd.lg.limit % LIMIT_ALIGN, 0); + assert_int_equal(imd.lg.limit, ALIGN_DOWN(test_inputs[i], LIMIT_ALIGN)); + assert_ptr_equal(imd.lg.r, NULL); + + /* Small allocations not initialized */ + assert_ptr_equal(imd.sm.limit, NULL); + assert_ptr_equal(imd.sm.r, NULL); + } +} + +static void test_imd_handle_init_partial_recovery(void **state) +{ + void *base; + struct imd imd = {0}; + const struct imd_entry *entry; + struct imdr *imdr; + struct imd_root *r; + + imd_handle_init_partial_recovery(&imd); + assert_null(imd.lg.limit); + assert_null(imd.sm.limit); + + base = malloc(LIMIT_SZ); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + + imd_handle_init(&imd, (void *)(LIMIT_SZ + (uintptr_t)base)); + imd_handle_init_partial_recovery(&imd); + + assert_non_null(imd.lg.r); + assert_null(imd.sm.limit); + + assert_int_equal(0, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); + entry = imd_entry_add(&imd, SMALL_REGION_ID, LG_ENTRY_SIZE); + assert_non_null(entry); + + imd_handle_init_partial_recovery(&imd); + + assert_non_null(imd.lg.r); + assert_non_null(imd.sm.limit); + + imdr = &imd.lg; + r = (struct imd_root *) (imdr->r); + + assert_ptr_equal(((void *)r + entry->start_offset + LG_ENTRY_SIZE), imd.sm.limit); + assert_non_null(imd.sm.r); + + free(base); +} + +static void test_imd_create_empty(void **state) +{ + struct imd imd = {0}; + void *base; + struct imdr *imdr; + struct imd_root *r; + struct imd_entry *e; + + /* Expect failure, since imd handle is not initialized */ + assert_int_equal(-1, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); + base = malloc(sizeof(struct imd_root_pointer) + sizeof(struct imd_root)); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + + imd_handle_init(&imd, (void *)(LIMIT_SZ + (uintptr_t)base)); + + /* Try incorrect sizes */ + assert_int_equal(-1, imd_create_empty(&imd, sizeof(struct imd_root_pointer) + + sizeof(struct imd_root), LG_ENTRY_ALIGN)); + assert_int_equal(-1, imd_create_empty(&imd, LG_ROOT_SIZE, 2 * LG_ROOT_SIZE)); + + /* Working case */ + assert_int_equal(0, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); + + /* Only large allocation initialized with one entry for the root region */ + imdr = &imd.lg; + r = (struct imd_root *) (imdr->r); + assert_non_null(r); + + e = &r->entries[r->num_entries - 1]; + + assert_int_equal(max_entries(LG_ROOT_SIZE), r->max_entries); + assert_int_equal(1, r->num_entries); + assert_int_equal(0, r->flags); + assert_int_equal(LG_ENTRY_ALIGN, r->entry_align); + assert_int_equal(0, r->max_offset); + assert_ptr_equal(e, &r->entries); + + assert_int_equal(IMD_ENTRY_MAGIC, e->magic); + assert_int_equal(0, e->start_offset); + assert_int_equal(LG_ROOT_SIZE, e->size); + assert_int_equal(CBMEM_ID_IMD_ROOT, e->id); + + free(base); +} + +static void test_imd_create_tiered_empty(void **state) +{ + void *base; + size_t sm_region_size, lg_region_wrong_size; + struct imd imd = {0}; + struct imd_root *r; + struct imd_entry *fst_lg_entry, *snd_lg_entry, *sm_entry; + + /* Uninitialized imd handle */ + assert_int_equal(-1, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, + LG_ROOT_SIZE, SM_ENTRY_ALIGN)); + + base = malloc(LIMIT_SZ); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + + imd_handle_init(&imd, (void *)(LIMIT_SZ + (uintptr_t)base)); + + /* Too small root_size for small region */ + assert_int_equal(-1, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, + sizeof(int32_t), 2 * sizeof(int32_t))); + + /* Fail when large region doesn't have capacity for more than 1 entry */ + lg_region_wrong_size = sizeof(struct imd_root_pointer) + sizeof(struct imd_root) + + sizeof(struct imd_entry); + assert_int_equal(-1, imd_create_tiered_empty(&imd, lg_region_wrong_size, + LG_ENTRY_ALIGN, SM_ROOT_SIZE, + SM_ENTRY_ALIGN)); + + assert_int_equal(0, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, + SM_ROOT_SIZE, SM_ENTRY_ALIGN)); + + r = imd.lg.r; + + /* One entry for root_region and one for small allocations */ + assert_int_equal(2, r->num_entries); + + fst_lg_entry = &r->entries[0]; + assert_int_equal(IMD_ENTRY_MAGIC, fst_lg_entry->magic); + assert_int_equal(0, fst_lg_entry->start_offset); + assert_int_equal(LG_ROOT_SIZE, fst_lg_entry->size); + assert_int_equal(CBMEM_ID_IMD_ROOT, fst_lg_entry->id); + + sm_region_size = SM_ROOT_SIZE - RP_SZ - ROOT_SZ; + sm_region_size /= ENTRY_SZ; + sm_region_size *= SM_ENTRY_ALIGN; + sm_region_size += SM_ROOT_SIZE; + sm_region_size = ALIGN_UP(sm_region_size, LG_ENTRY_ALIGN); + + snd_lg_entry = &r->entries[1]; + assert_int_equal(IMD_ENTRY_MAGIC, snd_lg_entry->magic); + assert_int_equal(-sm_region_size, snd_lg_entry->start_offset); + assert_int_equal(CBMEM_ID_IMD_SMALL, snd_lg_entry->id); + + assert_int_equal(sm_region_size, snd_lg_entry->size); + + r = imd.sm.r; + assert_int_equal(1, r->num_entries); + + sm_entry = &r->entries[0]; + assert_int_equal(IMD_ENTRY_MAGIC, sm_entry->magic); + assert_int_equal(0, sm_entry->start_offset); + assert_int_equal(SM_ROOT_SIZE, sm_entry->size); + assert_int_equal(CBMEM_ID_IMD_ROOT, sm_entry->id); + + free(base); +} + +/* Tests for imdr_recover. */ +static void test_imd_recover(void **state) +{ + int32_t offset_copy; + uint32_t rp_magic_copy, num_entries_copy, e_magic_copy; + uint32_t size_copy, diff; + void *base; + struct imd imd = {0}; + struct imdr *imdr; + struct imd_root_pointer *rp; + struct imd_root *r; + struct imd_entry *lg_root_entry, *sm_root_entry, *ptr; + const struct imd_entry *lg_entry; + + /* Fail when the limit for lg was not set. */ + imdr = &imd.lg; + imdr->limit = (uintptr_t) NULL; + assert_int_equal(-1, imd_recover(&imd)); + + /* Set the limit for lg. */ + base = malloc(LIMIT_SZ); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + + imd_handle_init(&imd, (void *)(LIMIT_SZ + (uintptr_t)base)); + + /* Fail when the root pointer is not valid. */ + rp = (void *)imdr->limit - RP_SZ; + assert_non_null(rp); + + rp_magic_copy = rp->magic; + rp->magic = 0; + assert_int_equal(-1, imd_recover(&imd)); + rp->magic = rp_magic_copy; + + /* Set the root pointer. */ + assert_int_equal(0, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, + SM_ROOT_SIZE, SM_ENTRY_ALIGN)); + r = imd.lg.r; + assert_int_equal(2, r->num_entries); + r = imd.sm.r; + assert_int_equal(1, r->num_entries); + r = imd.lg.r; + + /* Fail if the number of entries exceeds the maximum number of entries. */ + num_entries_copy = r->num_entries; + r->num_entries = r->max_entries + 1; + assert_int_equal(-1, imd_recover(&imd)); + r->num_entries = num_entries_copy; + + /* Fail if entry align is not a power of 2. */ + r->entry_align += 1; + assert_int_equal(-1, imd_recover(&imd)); + r->entry_align--; + + + /* Fail when an entry is not valid. */ + lg_root_entry = &r->entries[0]; + e_magic_copy = lg_root_entry->magic; + lg_root_entry->magic = 0; + assert_int_equal(-1, imd_recover(&imd)); + lg_root_entry->magic = e_magic_copy; + + /* Add new entries: large and small. */ + lg_entry = imd_entry_add(&imd, LG_ENTRY_ID, LG_ENTRY_SIZE); + assert_non_null(lg_entry); + assert_int_equal(3, r->num_entries); + + assert_non_null(imd_entry_add(&imd, SM_ENTRY_ID, SM_ENTRY_SIZE)); + r = imd.sm.r; + assert_int_equal(2, r->num_entries); + r = imd.lg.r; + + /* Fail when start_addr is lower than low_limit. */ + r->max_offset = lg_entry->start_offset + sizeof(int32_t); + assert_int_equal(-1, imd_recover(&imd)); + r->max_offset = 0; + + /* Fail when start_addr is at least imdr->limit. */ + offset_copy = lg_entry->start_offset; + ptr = (struct imd_entry *)lg_entry; + ptr->start_offset = (void *)imdr->limit - (void *)r; + assert_int_equal(-1, imd_recover(&imd)); + ptr->start_offset = offset_copy; + + /* Fail when (start_addr + e->size) is higher than imdr->limit. */ + size_copy = lg_entry->size; + diff = (void *)imdr->limit - ((void *)r + lg_entry->start_offset); + ptr->size = diff + 1; + assert_int_equal(-1, imd_recover(&imd)); + ptr->size = size_copy; + + /* End of tests for imdr_recover(). */ + + /* Succeed if small region is not present. */ + sm_root_entry = &r->entries[1]; + sm_root_entry->id = 0; + assert_int_equal(0, imd_recover(&imd)); + sm_root_entry->id = SMALL_REGION_ID; + + /* Continue if small region is present. */ + assert_int_equal(0, imd_recover(&imd)); + + free(base); +} + +static void test_imd_limit_size(void **state) +{ + void *base; + struct imd imd = {0}; + size_t root_size, max_size; + struct imdr *imdr; + + max_size = align_up_pow2(RP_SZ + ROOT_SZ + 3 * ENTRY_SZ); + + assert_int_equal(-1, imd_limit_size(&imd, max_size)); + + base = malloc(LIMIT_SZ); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + imd_handle_init(&imd, (void *)(LIMIT_SZ + (uintptr_t)base)); + + imdr = &imd.lg; + root_size = align_up_pow2(RP_SZ + ROOT_SZ + 2 * ENTRY_SZ); + imdr->r = (void *)imdr->limit - root_size; + + imd_create_empty(&imd, root_size, LG_ENTRY_ALIGN); + assert_int_equal(-1, imd_limit_size(&imd, root_size - 1)); + assert_int_equal(0, imd_limit_size(&imd, max_size)); + + /* Cannot create such a big entry */ + assert_null(imd_entry_add(&imd, LG_ENTRY_ID, max_size - root_size + 1)); + + free(base); +} + +static void test_imd_lockdown(void **state) +{ + struct imd imd = {0}; + struct imdr *imdr; + struct imd_root *r_lg, *r_sm; + + assert_int_equal(-1, imd_lockdown(&imd)); + + imdr = &imd.lg; + imdr->r = malloc(ROOT_SZ); + if (imdr->r == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + + r_lg = (struct imd_root *) (imdr->r); + + assert_int_equal(0, imd_lockdown(&imd)); + assert_true(r_lg->flags & IMD_FLAG_LOCKED); + + imdr = &imd.sm; + imdr->r = malloc(ROOT_SZ); + if (imdr->r == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + r_sm = (struct imd_root *) (imdr->r); + + assert_int_equal(0, imd_lockdown(&imd)); + assert_true(r_sm->flags & IMD_FLAG_LOCKED); + + free(imd.lg.r); + free(imd.sm.r); +} + +static void test_imd_region_used(void **state) +{ + struct imd imd = {0}; + struct imd_entry *first_entry, *new_entry; + struct imdr *imdr; + struct imd_root *r; + size_t size; + void *imd_base; + void *base; + + assert_int_equal(-1, imd_region_used(&imd, &base, &size)); + + imd_base = malloc(LIMIT_SZ); + if (imd_base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + imd_handle_init(&imd, (void *)(LIMIT_SZ + (uintptr_t)imd_base)); + + assert_int_equal(-1, imd_region_used(&imd, &base, &size)); + assert_int_equal(0, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); + assert_int_equal(0, imd_region_used(&imd, &base, &size)); + + imdr = &imd.lg; + r = (struct imd_root *) (imdr->r); + first_entry = &r->entries[r->num_entries - 1]; + + assert_int_equal(r + first_entry->start_offset, (uintptr_t)base); + assert_int_equal(first_entry->size, size); + + assert_non_null(imd_entry_add(&imd, LG_ENTRY_ID, LG_ENTRY_SIZE)); + assert_int_equal(2, r->num_entries); + + assert_int_equal(0, imd_region_used(&imd, &base, &size)); + + new_entry = &r->entries[r->num_entries - 1]; + + assert_true((void *)r + new_entry->start_offset == base); + assert_int_equal(first_entry->size + new_entry->size, size); + + free(imd_base); +} + +static void test_imd_entry_add(void **state) +{ + int i; + struct imd imd = {0}; + size_t entry_size = 0; + size_t used_size; + ssize_t entry_offset; + void *base; + struct imd_root *r, *sm_r, *lg_r; + struct imd_entry *first_entry, *new_entry; +__unused struct imd_root_pointer *rp; + + /* No small region case. */ + assert_null(imd_entry_add(&imd, LG_ENTRY_ID, entry_size)); + + base = malloc(LIMIT_SZ); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + + imd_handle_init(&imd, (void *)(LIMIT_SZ + (uintptr_t)base)); + + assert_int_equal(0, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); + + r = (struct imd_root *)imd.lg.r; + first_entry = &r->entries[r->num_entries - 1]; + + /* Fail when root is locked. */ + r->flags = IMD_FLAG_LOCKED; + assert_null(imd_entry_add(&imd, LG_ENTRY_ID, entry_size)); + r->flags = 0; + + /* Fail when the maximum number of entries has been reached. */ + r->num_entries = r->max_entries; + assert_null(imd_entry_add(&imd, LG_ENTRY_ID, entry_size)); + r->num_entries = 1; + + /* Fail when entry size is 0 */ + assert_null(imd_entry_add(&imd, LG_ENTRY_ID, 0)); + + /* Fail when entry size (after alignment) overflows imd total size. */ + entry_size = 2049; + r->max_offset = -entry_size; + assert_null(imd_entry_add(&imd, LG_ENTRY_ID, entry_size)); + r->max_offset = 0; + entry_size = 2 * sizeof(int32_t); + + /* Finally succeed. */ + assert_non_null(imd_entry_add(&imd, LG_ENTRY_ID, entry_size)); + assert_int_equal(2, r->num_entries); + + new_entry = &r->entries[r->num_entries - 1]; + assert_int_equal(ENTRY_SZ, (void *)new_entry - (void *)first_entry); + + assert_int_equal(IMD_ENTRY_MAGIC, new_entry->magic); + assert_int_equal(LG_ENTRY_ID, new_entry->id); + assert_int_equal(entry_size, new_entry->size); + + used_size = ALIGN_UP(entry_size, r->entry_align); + entry_offset = first_entry->start_offset - used_size; + assert_int_equal(entry_offset, new_entry->start_offset); + + /* Use small region case. */ + imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, SM_ROOT_SIZE, + SM_ENTRY_ALIGN); + + lg_r = imd.lg.r; + sm_r = imd.sm.r; + + /* All five new entries should be added to small allocations */ + for (i = 0; i < 5; i++) { + assert_non_null(imd_entry_add(&imd, SM_ENTRY_ID, SM_ENTRY_SIZE)); + assert_int_equal(i+2, sm_r->num_entries); + assert_int_equal(2, lg_r->num_entries); + } + + /* But next should fall back on large region */ + assert_non_null(imd_entry_add(&imd, SM_ENTRY_ID, SM_ENTRY_SIZE)); + assert_int_equal(6, sm_r->num_entries); + assert_int_equal(3, lg_r->num_entries); + + /* + * Small allocation is created when occupies less than 1/4 of available + * small region. Verify this. + */ + imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, SM_ROOT_SIZE, + SM_ENTRY_ALIGN); + + assert_non_null(imd_entry_add(&imd, SM_ENTRY_ID, -sm_r->max_offset / 4 + 1)); + assert_int_equal(1, sm_r->num_entries); + assert_int_equal(3, lg_r->num_entries); + + /* Next two should go into small region */ + assert_non_null(imd_entry_add(&imd, SM_ENTRY_ID, -sm_r->max_offset / 4)); + assert_int_equal(2, sm_r->num_entries); + assert_int_equal(3, lg_r->num_entries); + + /* (1/4 * 3/4) */ + assert_non_null(imd_entry_add(&imd, SM_ENTRY_ID, -sm_r->max_offset / 16 * 3)); + assert_int_equal(3, sm_r->num_entries); + assert_int_equal(3, lg_r->num_entries); + + free(base); +} + +static void test_imd_entry_find(void **state) +{ + struct imd imd = {0}; + void *base; + + base = malloc(LIMIT_SZ); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + imd_handle_init(&imd, (void *)(LIMIT_SZ + (uintptr_t)base)); + + assert_int_equal(0, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, + SM_ROOT_SIZE, SM_ENTRY_ALIGN)); + + assert_non_null(imd_entry_add(&imd, LG_ENTRY_ID, LG_ENTRY_SIZE)); + + assert_non_null(imd_entry_find(&imd, LG_ENTRY_ID)); + assert_non_null(imd_entry_find(&imd, SMALL_REGION_ID)); + + /* Try random id, should fail */ + assert_null(imd_entry_find(&imd, 0xC001)); + + free(base); +} + +static void test_imd_entry_find_or_add(void **state) +{ + struct imd imd = {0}; + const struct imd_entry *entry; + struct imd_root *r; + void *base; + + base = malloc(LIMIT_SZ); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + imd_handle_init(&imd, (void *)(LIMIT_SZ + (uintptr_t)base)); + + assert_null(imd_entry_find_or_add(&imd, LG_ENTRY_ID, LG_ENTRY_SIZE)); + + assert_int_equal(0, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); + entry = imd_entry_find_or_add(&imd, LG_ENTRY_ID, LG_ENTRY_SIZE); + assert_non_null(entry); + + r = (struct imd_root *)imd.lg.r; + + assert_int_equal(entry->id, LG_ENTRY_ID); + assert_int_equal(2, r->num_entries); + assert_non_null(imd_entry_find_or_add(&imd, LG_ENTRY_ID, LG_ENTRY_SIZE)); + assert_int_equal(2, r->num_entries); + + free(base); +} + +static void test_imd_entry_size(void **state) +{ + struct imd_entry entry = { .size = LG_ENTRY_SIZE }; + + assert_int_equal(LG_ENTRY_SIZE, imd_entry_size(&entry)); + + entry.size = 0; + assert_int_equal(0, imd_entry_size(&entry)); +} + +static void test_imd_entry_at(void **state) +{ + struct imd imd = {0}; + struct imd_root *r; + struct imd_entry *e = NULL; + const struct imd_entry *entry; + void *base; + + base = malloc(LIMIT_SZ); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + imd_handle_init(&imd, (void *)(LIMIT_SZ + (uintptr_t)base)); + + assert_int_equal(0, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); + + /* Fail when entry is NULL */ + assert_null(imd_entry_at(&imd, e)); + + entry = imd_entry_add(&imd, LG_ENTRY_ID, LG_ENTRY_SIZE); + assert_non_null(entry); + + r = (struct imd_root *) (imd.lg.r); + assert_ptr_equal((void *)r + entry->start_offset, imd_entry_at(&imd, entry)); + + free(base); +} + +static void test_imd_entry_id(void **state) +{ + struct imd_entry entry = { .id = LG_ENTRY_ID }; + + assert_int_equal(LG_ENTRY_ID, imd_entry_id(&entry)); +} + +static void test_imd_entry_remove(void **state) +{ + void *base; + struct imd imd = {0}; + struct imd_root *r; + const struct imd_entry *fst_lg_entry, *snd_lg_entry, *fst_sm_entry; + const struct imd_entry *e = NULL; + + /* Uninitialized handle */ + assert_int_equal(-1, imd_entry_remove(&imd, e)); + + base = malloc(LIMIT_SZ); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + + imd_handle_init(&imd, (void *)(LIMIT_SZ + (uintptr_t)base)); + + assert_int_equal(0, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, + LG_ROOT_SIZE, SM_ENTRY_ALIGN)); + + r = imd.lg.r; + assert_int_equal(2, r->num_entries); + fst_lg_entry = &r->entries[0]; + snd_lg_entry = &r->entries[1]; + + /* Only last entry can be removed */ + assert_int_equal(-1, imd_entry_remove(&imd, fst_lg_entry)); + + r->flags = IMD_FLAG_LOCKED; + assert_int_equal(-1, imd_entry_remove(&imd, snd_lg_entry)); + r->flags = 0; + + r = imd.sm.r; + assert_int_equal(1, r->num_entries); + fst_sm_entry = &r->entries[0]; + + /* Fail trying to remove root entry */ + assert_int_equal(-1, imd_entry_remove(&imd, fst_sm_entry)); + assert_int_equal(1, r->num_entries); + + r = imd.lg.r; + assert_int_equal(0, imd_entry_remove(&imd, snd_lg_entry)); + assert_int_equal(1, r->num_entries); + + /* Fail trying to remove root entry */ + assert_int_equal(-1, imd_entry_remove(&imd, fst_lg_entry)); + assert_int_equal(1, r->num_entries); + + free(base); +} + +static void test_imd_cursor_init(void **state) +{ + struct imd imd = {0}; + struct imd_cursor cursor; + + assert_int_equal(-1, imd_cursor_init(NULL, NULL)); + assert_int_equal(-1, imd_cursor_init(NULL, &cursor)); + assert_int_equal(-1, imd_cursor_init(&imd, NULL)); + assert_int_equal(0, imd_cursor_init(&imd, &cursor)); + + assert_ptr_equal(cursor.imdr[0], &imd.lg); + assert_ptr_equal(cursor.imdr[1], &imd.sm); +} + +static void test_imd_cursor_next(void **state) +{ + void *base; + struct imd imd = {0}; + struct imd_cursor cursor; + struct imd_root *r; + const struct imd_entry *entry; + struct imd_entry *fst_lg_entry, *snd_lg_entry, *fst_sm_entry; + assert_int_equal(0, imd_cursor_init(&imd, &cursor)); + + cursor.current_imdr = 3; + cursor.current_entry = 0; + assert_null(imd_cursor_next(&cursor)); + + cursor.current_imdr = 0; + assert_null(imd_cursor_next(&cursor)); + + base = malloc(LIMIT_SZ); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + imd_handle_init(&imd, (void *)(LIMIT_SZ + (uintptr_t)base)); + + assert_int_equal(0, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, + SM_ROOT_SIZE, SM_ENTRY_ALIGN)); + + r = imd.lg.r; + entry = imd_cursor_next(&cursor); + assert_non_null(entry); + + fst_lg_entry = &r->entries[0]; + assert_int_equal(fst_lg_entry->id, entry->id); + assert_ptr_equal(fst_lg_entry, entry); + + entry = imd_cursor_next(&cursor); + assert_non_null(entry); + + snd_lg_entry = &r->entries[1]; + assert_int_equal(snd_lg_entry->id, entry->id); + assert_ptr_equal(snd_lg_entry, entry); + + entry = imd_cursor_next(&cursor); + assert_non_null(entry); + + r = imd.sm.r; + fst_sm_entry = &r->entries[0]; + assert_int_equal(fst_sm_entry->id, entry->id); + assert_ptr_equal(fst_sm_entry, entry); + + entry = imd_cursor_next(&cursor); + assert_null(entry); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_imd_handle_init), + cmocka_unit_test(test_imd_handle_init_partial_recovery), + cmocka_unit_test(test_imd_create_empty), + cmocka_unit_test(test_imd_create_tiered_empty), + cmocka_unit_test(test_imd_recover), + cmocka_unit_test(test_imd_limit_size), + cmocka_unit_test(test_imd_lockdown), + cmocka_unit_test(test_imd_region_used), + cmocka_unit_test(test_imd_entry_add), + cmocka_unit_test(test_imd_entry_find), + cmocka_unit_test(test_imd_entry_find_or_add), + cmocka_unit_test(test_imd_entry_size), + cmocka_unit_test(test_imd_entry_at), + cmocka_unit_test(test_imd_entry_id), + cmocka_unit_test(test_imd_entry_remove), + cmocka_unit_test(test_imd_cursor_init), + cmocka_unit_test(test_imd_cursor_next), + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/44669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d3ab45c3da2a21c910f52a84526b60c39ff1fe7 Gerrit-Change-Number: 44669 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Anna Karaś <aka(a)semihalf.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 17

Change in coreboot[master]: fix: gemini lake device id is LPC
by Name of user not set (Code Review) 01 Mar '21

01 Mar '21

coreboot(a)s.paape.io has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40755 ) Change subject: fix: gemini lake device id is LPC ...................................................................... fix: gemini lake device id is LPC Change-Id: If6a22a28f2a4ca1f984b669b00bc0c07f5588328 --- M util/inteltool/gpio.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/40755/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 471485c..e11d848 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1035,7 +1035,7 @@ case PCI_DEVICE_ID_INTEL_QM170: case PCI_DEVICE_ID_INTEL_HM170: case PCI_DEVICE_ID_INTEL_CM236: - case PCI_DEVICE_ID_INTEL_GLK: + case PCI_DEVICE_ID_INTEL_GLK_LPC: case PCI_DEVICE_ID_INTEL_APL_LPC: case PCI_DEVICE_ID_INTEL_DNV_LPC: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index a4bfdcb..475f701 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -316,7 +316,7 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C224, "C224"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C226, "C226"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, "H81"}, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK, "Gemini Lake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK_LPC, "Gemini Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_LPC, "Apollo Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_LPC, "Denverton" }, /* Intel GPUs */ diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 9f5d8aa..9eff45d 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -267,7 +267,7 @@ #define PCI_DEVICE_ID_INTEL_BAYTRAIL_GFX 0x0f31 #define CPUID_BAYTRAIL 0x30670 -#define PCI_DEVICE_ID_INTEL_GLK 0x31e8 +#define PCI_DEVICE_ID_INTEL_GLK_LPC 0x31e8 #define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8 #define PCI_DEVICE_ID_INTEL_DNV_LPC 0x19dc diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index 963a8b4..4733458 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -120,7 +120,7 @@ p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1); break; case PCI_DEVICE_ID_INTEL_APL_LPC: - case PCI_DEVICE_ID_INTEL_GLK: + case PCI_DEVICE_ID_INTEL_GLK_LPC: p2sb = pci_get_dev(sb->access, 0, 0, 0x0d, 0); break; case PCI_DEVICE_ID_INTEL_H310: -- To view, visit https://review.coreboot.org/c/coreboot/+/40755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6a22a28f2a4ca1f984b669b00bc0c07f5588328 Gerrit-Change-Number: 40755 Gerrit-PatchSet: 1 Gerrit-Owner: coreboot(a)s.paape.io Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: nb/intel/sandybridge: Clean up `dram_timing` function
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45501 ) Change subject: nb/intel/sandybridge: Clean up `dram_timing` function ...................................................................... nb/intel/sandybridge: Clean up `dram_timing` function Compute timings first, then display them. Drop unneeded comments and a double empty line before the start of the function. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I121cf9c4db76ec0ced36caf764b1a1a51e47b552 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_native.c 1 file changed, 11 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/45501/1 diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index a469910..64a381d 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -302,7 +302,6 @@ ctrl->CAS = val; } - static void dram_timing(ramctr_timing *ctrl) { /* @@ -424,42 +423,15 @@ else ctrl->CWL = get_CWL(ctrl->tCK); - printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); - - /* Find tRCD */ ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); - ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); - - /* Find tRAS */ ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); - - /* Find tWR */ ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); - - /* Find tFAW */ ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW); - - /* Find tRRD */ ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD); - - /* Find tRTP */ ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP); - - /* Find tWTR */ ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); - - /* Refresh-to-Active or Refresh-to-Refresh (tRFC) */ ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); ctrl->tREFI = get_REFI(ctrl->FRQ, ctrl->base_freq); ctrl->tMOD = get_MOD(ctrl->FRQ, ctrl->base_freq); @@ -469,6 +441,17 @@ ctrl->tXPDLL = get_XPDLL(ctrl->FRQ, ctrl->base_freq); ctrl->tXP = get_XP(ctrl->FRQ, ctrl->base_freq); ctrl->tAONPD = get_AONPD(ctrl->FRQ, ctrl->base_freq); + + printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); + printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); + printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); + printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); + printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); + printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW); + printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD); + printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP); + printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); + printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); } static void dram_freq(ramctr_timing *ctrl) -- To view, visit https://review.coreboot.org/c/coreboot/+/45501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I121cf9c4db76ec0ced36caf764b1a1a51e47b552 Gerrit-Change-Number: 45501 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: nb/intel/ironlake: Avoid casting pointers to structs
by Angel Pons (Code Review) 27 Feb '21

27 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45367 ) Change subject: nb/intel/ironlake: Avoid casting pointers to structs ...................................................................... nb/intel/ironlake: Avoid casting pointers to structs Instead, convert the struct to a union and pass in a pointer to it. Without the initialization of `reply.command`, Packard Bell MS2290 does not change. This might be due to incorrect compiler optimizations. Change-Id: I60e3dca7ad101d840759bdc0c88c50d9f07d65e2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 16 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/45367/1 diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index aa73d99..9ee2253 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1724,8 +1724,20 @@ return 0; } +union uma_reply { + struct { + u8 group_id; + u8 command; + u8 reserved; + u8 result; + u8 field2; + u8 unk3[0x48 - 4 - 1]; + }; + u32 dwords[0x48 / sizeof(u32)]; +} __packed; + /* FIXME: Add timeout. */ -static int recv_heci_message(u32 *message, u32 *message_size) +static int recv_heci_message(union uma_reply *message, u32 *message_size) { struct mei_header head; int current_position; @@ -1735,7 +1747,7 @@ u32 current_size; current_size = *message_size - current_position; if (recv_heci_packet - (&head, message + (current_position >> 2), + (&head, message->dwords + (current_position >> 2), &current_size) == -1) break; if (!current_size) @@ -1755,14 +1767,7 @@ static void send_heci_uma_message(const u64 heci_uma_addr, const unsigned int heci_uma_size) { - struct uma_reply { - u8 group_id; - u8 command; - u8 reserved; - u8 result; - u8 field2; - u8 unk3[0x48 - 4 - 1]; - } __packed reply; + union uma_reply reply; /* FIXME: recv_heci_message() does not always initialize 'reply' */ reply.command = 0; @@ -1791,7 +1796,7 @@ send_heci_message((u8 *) &msg, sizeof(msg), 0, 7); reply_size = sizeof(reply); - if (recv_heci_message((u32 *) &reply, &reply_size) == -1) + if (recv_heci_message(&reply, &reply_size) == -1) return; if (reply.command != (MKHI_SET_UMA | (1 << 7))) -- To view, visit https://review.coreboot.org/c/coreboot/+/45367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60e3dca7ad101d840759bdc0c88c50d9f07d65e2 Gerrit-Change-Number: 45367 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/poppy: Tell front sensor driver not to power it on during p...
by Sakari Ailus (Code Review) 26 Feb '21

26 Feb '21

Sakari Ailus has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45171 ) Change subject: mb/google/poppy: Tell front sensor driver not to power it on during probe ...................................................................... mb/google/poppy: Tell front sensor driver not to power it on during probe Use i2c-allow-low-power-probe boolean property to tell the driver of the front sensor to keep the device in low power state during probe. As powering on the sensor will briefly lit the privacy LED, the side effect of this patch is also that the LED remains powered off during the entire boot process. Signed-off-by: Sakari Ailus <sakari.ailus(a)linux.intel.com> Change-Id: I21946a9b0667b5c4486b96e907a14f8446617015 --- M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/45171/1 diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl index 7e20575..8a80e14 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl @@ -35,6 +35,7 @@ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "clock-frequency", 19200000 }, + Package () { "i2c-allow-low-power-probe", 1 }, } }) -- To view, visit https://review.coreboot.org/c/coreboot/+/45171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21946a9b0667b5c4486b96e907a14f8446617015 Gerrit-Change-Number: 45171 Gerrit-PatchSet: 1 Gerrit-Owner: Sakari Ailus <sakari.ailus+coreboot.org(a)linux.intel.com> Gerrit-MessageType: newchange

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