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Change in coreboot[master]: mb/asus/p2b: Migrate southbridge ACPI stuff
by Keith Hui (Code Review) 22 Mar '21

22 Mar '21

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41050 ) Change subject: mb/asus/p2b: Migrate southbridge ACPI stuff ...................................................................... mb/asus/p2b: Migrate southbridge ACPI stuff Move (remaining) ACPI stuff for both southbridge main and PM functions into one file under sb/intel/i82371eb, that is simply included from the board's \_SB scope. Also, southbridge no longer claims I/O ports 0x2e-0x2f, following the p3b-f OEM scheme, and its PM device now reports its own I/O resources. Change-Id: Ibed49a800dec19534761e5ab22a6cbb1e6bd4a5d Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p2b/dsdt.asl M src/southbridge/intel/i82371eb/acpi/i82371eb.asl 2 files changed, 85 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/41050/1 diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index c3a279d..b998ceb 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -159,79 +159,7 @@ #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl> #include <southbridge/intel/i82371eb/acpi/isabridge.asl> - /* Begin southbridge block */ - Device (PX40) - { - Name(_ADR, 0x00040000) - OperationRegion (PIRQ, PCI_Config, 0x60, 0x04) - Field (PIRQ, ByteAcc, NoLock, Preserve) - { - PIRA, 8, - PIRB, 8, - PIRC, 8, - PIRD, 8 - } - - /* PNP Motherboard Resources */ - Device (SYSR) - { - Name (_HID, EisaId ("PNP0C02")) - Name (_UID, 0x02) - Method (_CRS, 0, NotSerialized) - { - Name (BUF1, ResourceTemplate () - { - /* PM register ports */ - IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06) - /* SMBus register ports */ - IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07) - /* PIIX4E ports */ - /* Aliased DMA ports */ - IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, ) - /* Aliased PIC ports */ - IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, ) - /* Aliased timer ports */ - IO (Decode16, 0x0050, 0x0050, 0x01, 0x04, ) - IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, ) - IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B, ) - IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C, ) - IO (Decode16, 0x0091, 0x0091, 0x01, 0x03, ) - IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, ) - IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, ) - IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, ) - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, ) - IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, ) - }) - CreateWordField (BUF1, _Y06._MIN, PMLO) - CreateWordField (BUF1, _Y06._MAX, PMRL) - CreateWordField (BUF1, _Y07._MIN, SBLO) - CreateWordField (BUF1, _Y07._MAX, SBRL) - - And (\_SB.PCI0.PX43.PM00, 0xFFFE, PMLO) - And (\_SB.PCI0.PX43.SB00, 0xFFFE, SBLO) - Store (PMLO, PMRL) - Store (SBLO, SBRL) - Return (BUF1) - } - } - #include <southbridge/intel/i82371eb/acpi/i82371eb.asl> - } - Device (PX43) - { - Name (_ADR, 0x00040003) // _ADR: Address - OperationRegion (IPMU, PCI_Config, PMBA, 0x02) - Field (IPMU, ByteAcc, NoLock, Preserve) - { - PM00, 16 - } - - OperationRegion (ISMB, PCI_Config, SMBBA, 0x02) - Field (ISMB, ByteAcc, NoLock, Preserve) - { - SB00, 16 - } - } - + #include <southbridge/intel/i82371eb/acpi/i82371eb.asl> #include <superio/winbond/w83977tf/acpi/superio.asl> } } diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl index 57f347e..1e2818c 100644 --- a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl +++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl @@ -1,17 +1,60 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -/* - * Declares assorted devices that falls under this southbridge. - */ #include "southbridge/intel/i82371eb/i82371eb.h" +/* Declares assorted devices that falls under this southbridge. */ +Device (PX40) +{ + Name(_ADR, 0x00040000) + OperationRegion (PIRQ, PCI_Config, 0x60, 0x04) + Field (PIRQ, ByteAcc, NoLock, Preserve) + { + PIRA, 8, + PIRB, 8, + PIRC, 8, + PIRD, 8 + } + OperationRegion (S1XX, PCI_Config, 0xB2, 0x01) Field (S1XX, ByteAcc, NoLock, Preserve) { FXS1, 8 } + /* PNP Motherboard Resources */ + Device (SYSR) + { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x02) + Method (_CRS, 0, NotSerialized) + { + Name (BUF1, ResourceTemplate () + { + /* PIIX4E ports */ + /* Aliased DMA ports */ + IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, ) + /* Aliased PIC ports */ + /* Do not claim 0x2e-0x2f, per P3B-F vendor DSDT */ + IO (Decode16, 0x0022, 0x0022, 0x01, 0x0C, ) + IO (Decode16, 0x0030, 0x0030, 0x01, 0x10, ) + /* Aliased timer ports */ + /* Existing DSDT only reserves to 0x54 */ + IO (Decode16, 0x0044, 0x0044, 0x01, 0x10, ) + IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, ) + IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B, ) + IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C, ) + IO (Decode16, 0x0091, 0x0091, 0x01, 0x03, ) + IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, ) + IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, ) + IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, ) + /* W83977TF/EF Super I/O config ports */ + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, ) + IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, ) + }) + Return (BUF1) + } + } /* 8259-compatible Programmable Interrupt Controller */ Device (PIC) { @@ -79,3 +122,41 @@ IRQNoFlags () {13} }) } +} + +/* Power management functions allows ACPI reporting of PM and SMBus base ports. */ +Device (PX43) +{ + Name (_ADR, 0x00040003) // _ADR: Address + OperationRegion (IPMU, PCI_Config, PMBA, 0x02) + Field (IPMU, ByteAcc, NoLock, Preserve) + { + PM00, 16, + } + + OperationRegion (ISMB, PCI_Config, SMBBA, 0x02) + Field (ISMB, ByteAcc, NoLock, Preserve) + { + SB00, 16, + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF1, ResourceTemplate () + { + /* PM register ports */ + IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06) + /* SMBus register ports */ + IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07) + }) + CreateWordField (BUF1, _Y06._MIN, PMLO) + CreateWordField (BUF1, _Y06._MAX, PMRL) + CreateWordField (BUF1, _Y07._MIN, SBLO) + CreateWordField (BUF1, _Y07._MAX, SBRL) + + And (PM00, 0xFFFE, PMLO) + And (SB00, 0xFFFE, SBLO) + Store (PMLO, PMRL) + Store (SBLO, SBRL) + Return (BUF1) + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibed49a800dec19534761e5ab22a6cbb1e6bd4a5d Gerrit-Change-Number: 41050 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: drivers/generic/cbfs-serial: Update driver to read UUID from CBFS
by Name of user not set (Code Review) 21 Mar '21

21 Mar '21

Name of user not set #1002789 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44005 ) Change subject: drivers/generic/cbfs-serial: Update driver to read UUID from CBFS ...................................................................... drivers/generic/cbfs-serial: Update driver to read UUID from CBFS Modify the existing cbfs-serial driver to also read the UUID from a text file in CBFS, just as a serial number is done today. When driver is selected and a system_uuid exists in the CBFS the UUID is read from the file and populated in the SMBIOS table. Note that in order to work there must be no newline character at the end of the file, this is also true of the serial_number. Tested on a Google Tricky (Dell 3010 Chromebox). Change-Id: I140a61670cec1318c095e18815c6bc7c1bf78cd6 Signed-off-by: Chris Morgan <macromorgan(a)hotmail.com> --- M src/drivers/generic/cbfs-serial/Kconfig M src/drivers/generic/cbfs-serial/cbfs-serial.c 2 files changed, 34 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/44005/1 diff --git a/src/drivers/generic/cbfs-serial/Kconfig b/src/drivers/generic/cbfs-serial/Kconfig index 209c242..d0cce14 100644 --- a/src/drivers/generic/cbfs-serial/Kconfig +++ b/src/drivers/generic/cbfs-serial/Kconfig @@ -2,5 +2,8 @@ bool "Serial number in CBFS" default n help - Enable this option to read the board serial number from a - text file located in CBFS. + Enable this option to read the board serial number or + system UUID from a text file located in CBFS. The text + file should be named serial_number or system_uuid + respectively and include only the serial number or + UUID (with dashes) with no newline characters. diff --git a/src/drivers/generic/cbfs-serial/cbfs-serial.c b/src/drivers/generic/cbfs-serial/cbfs-serial.c index 2e3e37d..6ee3c26 100644 --- a/src/drivers/generic/cbfs-serial/cbfs-serial.c +++ b/src/drivers/generic/cbfs-serial/cbfs-serial.c @@ -4,9 +4,10 @@ #include <device/device.h> #include <smbios.h> #include <string.h> - +#include <uuid.h> #define MAX_SERIAL_LENGTH 0x100 +#define UUID_LENGTH 0x128 const char *smbios_mainboard_serial_number(void) { @@ -37,3 +38,30 @@ return serial_number; } + +void smbios_system_set_uuid(u8 *uuid) +{ + static char system_uuid[UUID_LENGTH + 1] = {0}; + struct cbfsf file; + + if (system_uuid[0] != 0) + parse_uuid(uuid, system_uuid); + + if (cbfs_boot_locate(&file, "system_uuid", NULL) == 0) { + struct region_device cbfs_region; + size_t uuid_len; + + cbfs_file_data(&cbfs_region, &file); + + uuid_len = region_device_sz(&cbfs_region); + if (uuid_len <= UUID_LENGTH) { + if (rdev_readat(&cbfs_region, system_uuid, 0, + uuid_len) == uuid_len) { + system_uuid[uuid_len] = 0; + parse_uuid(uuid, system_uuid); + } + } + } + + parse_uuid(uuid, system_uuid); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I140a61670cec1318c095e18815c6bc7c1bf78cd6 Gerrit-Change-Number: 44005 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002789 Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: [WIP] AGESA,binaryPI boards: Drop invalid MP table files
by Kyösti Mälkki (Code Review) 17 Mar '21

17 Mar '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38313 ) Change subject: [WIP] AGESA,binaryPI boards: Drop invalid MP table files ...................................................................... [WIP] AGESA,binaryPI boards: Drop invalid MP table files If we spot any error in the file, treat it as untested and broken copy-paste. Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/bettong/Kconfig D src/mainboard/amd/bettong/mptable.c M src/mainboard/amd/db-ft3b-lc/Kconfig D src/mainboard/amd/db-ft3b-lc/mptable.c M src/mainboard/amd/gardenia/Kconfig D src/mainboard/amd/gardenia/mptable.c M src/mainboard/amd/inagua/Kconfig D src/mainboard/amd/inagua/mptable.c M src/mainboard/amd/lamar/Kconfig D src/mainboard/amd/lamar/mptable.c M src/mainboard/amd/olivehill/Kconfig D src/mainboard/amd/olivehill/mptable.c M src/mainboard/amd/olivehillplus/Kconfig D src/mainboard/amd/olivehillplus/mptable.c M src/mainboard/amd/parmer/Kconfig D src/mainboard/amd/parmer/mptable.c M src/mainboard/amd/persimmon/Kconfig D src/mainboard/amd/persimmon/mptable.c M src/mainboard/amd/south_station/Kconfig D src/mainboard/amd/south_station/mptable.c M src/mainboard/amd/thatcher/Kconfig D src/mainboard/amd/thatcher/mptable.c M src/mainboard/amd/union_station/Kconfig D src/mainboard/amd/union_station/mptable.c M src/mainboard/asrock/e350m1/Kconfig D src/mainboard/asrock/e350m1/mptable.c M src/mainboard/asrock/imb-a180/Kconfig D src/mainboard/asrock/imb-a180/mptable.c M src/mainboard/asus/am1i-a/Kconfig D src/mainboard/asus/am1i-a/mptable.c M src/mainboard/asus/f2a85-m/Kconfig D src/mainboard/asus/f2a85-m/mptable.c M src/mainboard/bap/ode_e20XX/Kconfig D src/mainboard/bap/ode_e20XX/mptable.c M src/mainboard/bap/ode_e21XX/Kconfig D src/mainboard/bap/ode_e21XX/mptable.c M src/mainboard/biostar/a68n_5200/Kconfig D src/mainboard/biostar/a68n_5200/mptable.c M src/mainboard/biostar/am1ml/Kconfig D src/mainboard/biostar/am1ml/mptable.c M src/mainboard/elmex/pcm205400/Kconfig D src/mainboard/elmex/pcm205400/mptable.c M src/mainboard/gizmosphere/gizmo/Kconfig D src/mainboard/gizmosphere/gizmo/mptable.c M src/mainboard/gizmosphere/gizmo2/Kconfig D src/mainboard/gizmosphere/gizmo2/mptable.c D src/mainboard/google/kahlee/mptable.c M src/mainboard/hp/abm/Kconfig D src/mainboard/hp/abm/mptable.c M src/mainboard/hp/pavilion_m6_1035dx/Kconfig D src/mainboard/hp/pavilion_m6_1035dx/mptable.c M src/mainboard/jetway/nf81-t56n-lf/Kconfig D src/mainboard/jetway/nf81-t56n-lf/mptable.c M src/mainboard/lenovo/g505s/Kconfig D src/mainboard/lenovo/g505s/mptable.c M src/mainboard/lippert/frontrunner-af/Kconfig D src/mainboard/lippert/frontrunner-af/mptable.c M src/mainboard/lippert/toucan-af/Kconfig D src/mainboard/lippert/toucan-af/mptable.c M src/mainboard/msi/ms7721/Kconfig D src/mainboard/msi/ms7721/mptable.c M src/mainboard/pcengines/apu1/Kconfig D src/mainboard/pcengines/apu1/mptable.c M src/mainboard/pcengines/apu2/Kconfig D src/mainboard/pcengines/apu2/mptable.c 65 files changed, 0 insertions(+), 4,840 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/38313/1 diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig index 4617360..50140f7 100644 --- a/src/mainboard/amd/bettong/Kconfig +++ b/src/mainboard/amd/bettong/Kconfig @@ -28,7 +28,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select GFXUMA diff --git a/src/mainboard/amd/bettong/mptable.c b/src/mainboard/amd/bettong/mptable.c deleted file mode 100644 index d9632d5..0000000 --- a/src/mainboard/amd/bettong/mptable.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/pi/hudson/hudson.h> -#include <southbridge/amd/common/amd_pci_util.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig index f17d2d3..7f24015 100644 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig +++ b/src/mainboard/amd/db-ft3b-lc/Kconfig @@ -29,7 +29,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select GFXUMA diff --git a/src/mainboard/amd/db-ft3b-lc/mptable.c b/src/mainboard/amd/db-ft3b-lc/mptable.c deleted file mode 100644 index 40a75ad..0000000 --- a/src/mainboard/amd/db-ft3b-lc/mptable.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/gardenia/Kconfig b/src/mainboard/amd/gardenia/Kconfig index e97a3ba..424a47d 100644 --- a/src/mainboard/amd/gardenia/Kconfig +++ b/src/mainboard/amd/gardenia/Kconfig @@ -21,7 +21,6 @@ select AMD_APU_STONEYRIDGE select AMD_APU_PKG_FP4 select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select GFXUMA diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c deleted file mode 100644 index 5bb70e9..0000000 --- a/src/mainboard/amd/gardenia/mptable.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <soc/southbridge.h> -#include <amdblocks/amd_pci_util.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), \ - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \ - (intr), (apicid), (pin)) - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, \ - MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \ - (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index a5ba07e..77f6b8a 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -27,7 +27,6 @@ select SUPERIO_SMSC_KBC1100 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 select GFXUMA diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c deleted file mode 100644 index b8bd0b3..0000000 --- a/src/mainboard/amd/inagua/mptable.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig index c856534..2e19c3d 100644 --- a/src/mainboard/amd/lamar/Kconfig +++ b/src/mainboard/amd/lamar/Kconfig @@ -29,7 +29,6 @@ select SUPERIO_FINTEK_F81216H select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select GFXUMA diff --git a/src/mainboard/amd/lamar/mptable.c b/src/mainboard/amd/lamar/mptable.c deleted file mode 100644 index 1f2093d..0000000 --- a/src/mainboard/amd/lamar/mptable.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> -#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h> -#include <northbridge/amd/pi/00630F01/pci_devs.h> - -#define NB_APIC_ADDR ((u8 *)0xFEC20000) - -#define PCI_INT(bus, dev, fn, apic, pin) \ - if (((pin) != 0x00) && ((pin) != 0x1F)) \ - { \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apic, (pin)); \ - } - -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - - u8 apicid_nb = (io_apic_read(NB_APIC_ADDR, 0x00) >> 24); /* Get the GNB IOAPIC ID */ - u8 apicver_nb = (io_apic_read(NB_APIC_ADDR, 0x01) & 0xFF); /* Get the GNB IOAPIC version */ - - smp_write_ioapic(mc, apicid_nb, apicver_nb, NB_APIC_ADDR); - - u8 apicid_sb = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); /* Get the southbridge IOAPIC ID */ - u8 apicver_sb = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); /* Get the southbridge IOAPIC version */ - - smp_write_ioapic(mc, apicid_sb, apicver_sb, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, apicid_nb, 0); - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, apicid_nb, intr_data_ptr[PIRQ_GFX]); - PCI_INT(0x0, 0x01, 0x1, apicid_nb, intr_data_ptr[PIRQ_ACTL]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, apicid_sb, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, apicid_sb, intr_data_ptr[PIRQ_HDA]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x5, apicid_sb, intr_data_ptr[PIRQ_OHCI4]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, apicid_sb, intr_data_ptr[PIRQ_SATA]); - - /* IDE */ - PCI_INT(0x0, 0x14, 0x1, apicid_sb, intr_data_ptr[PIRQ_IDE]); - - /* PCI slots */ - /* NB Gfx PCIe Bridges */ - PCI_INT(0, 0x2, 0x1, apicid_nb, intr_data_ptr[PIRQ_A]); - PCI_INT(0, 0x2, 0x2, apicid_nb, intr_data_ptr[PIRQ_A]); - - /* NB GPP PCIe Bridges */ - PCI_INT(0, 0x3, 0x1, apicid_nb, intr_data_ptr[PIRQ_A]); - PCI_INT(0, 0x3, 0x2, apicid_nb, intr_data_ptr[PIRQ_A]); - PCI_INT(0, 0x3, 0x3, apicid_nb, intr_data_ptr[PIRQ_A]); - PCI_INT(0, 0x3, 0x4, apicid_nb, intr_data_ptr[PIRQ_A]); - PCI_INT(0, 0x3, 0x5, apicid_nb, intr_data_ptr[PIRQ_A]); - - /* PCI slots */ - PCI_INT(0, 0x14, 0x4, apicid_sb, intr_data_ptr[PIRQ_A]); - - /* FCH GPP PCIe Bridges */ - PCI_INT(0x0, 0x15, 0x0, apicid_sb, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, apicid_sb, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, apicid_sb, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, apicid_sb, intr_data_ptr[PIRQ_A]); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 78f768f..8810c1d 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -27,7 +27,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c deleted file mode 100644 index 7082013..0000000 --- a/src/mainboard/amd/olivehill/mptable.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig index 907de3b..1745969 100644 --- a/src/mainboard/amd/olivehillplus/Kconfig +++ b/src/mainboard/amd/olivehillplus/Kconfig @@ -28,7 +28,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select GFXUMA diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c deleted file mode 100644 index 0f6ca81..0000000 --- a/src/mainboard/amd/olivehillplus/mptable.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/pi/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index ae024dd..94f55ce 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -27,7 +27,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c deleted file mode 100644 index 3a5540c..0000000 --- a/src/mainboard/amd/parmer/mptable.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index f243f0f..248e4d4 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -27,7 +27,6 @@ select SUPERIO_FINTEK_F81865F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c deleted file mode 100644 index bc7a3ac..0000000 --- a/src/mainboard/amd/persimmon/mptable.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> -#include <arch/ioapic.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); - - /* IDE */ - PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index 42841cb..0d76d50 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -27,7 +27,6 @@ select SUPERIO_FINTEK_F81865F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c deleted file mode 100644 index b8bd0b3..0000000 --- a/src/mainboard/amd/south_station/mptable.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index e556592..b79511f 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -27,7 +27,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select SUPERIO_SMSC_LPC47N217 diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c deleted file mode 100644 index 05d222a..0000000 --- a/src/mainboard/amd/thatcher/mptable.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - u8 byte; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index 1532d34..2dc82c9 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -26,7 +26,6 @@ select SOUTHBRIDGE_AMD_CIMX_SB800 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 select GFXUMA diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c deleted file mode 100644 index b8bd0b3..0000000 --- a/src/mainboard/amd/union_station/mptable.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 3bbc2a5..18058c9 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -24,7 +24,6 @@ select SB_SUPERIO_HWM select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c deleted file mode 100644 index ce8cfa0..0000000 --- a/src/mainboard/asrock/e350m1/mptable.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <stdint.h> -#include <string.h> - -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "ASROCK ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig index 8fca61c..7110c89 100644 --- a/src/mainboard/asrock/imb-a180/Kconfig +++ b/src/mainboard/asrock/imb-a180/Kconfig @@ -24,7 +24,6 @@ select SUPERIO_WINBOND_W83627UHG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c deleted file mode 100644 index 7082013..0000000 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index a0dae9f..8a7e7e9 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -10,7 +10,6 @@ select USE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB diff --git a/src/mainboard/asus/am1i-a/mptable.c b/src/mainboard/asus/am1i-a/mptable.c deleted file mode 100644 index 9efcab3..0000000 --- a/src/mainboard/asus/am1i-a/mptable.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2018 Gergely Kiss <mail.gery(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_A]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_B]); - - /* GPP Ports */ - PCI_INT(0x0, 0x02, 0x0, intr_data_ptr[PIRQ_A]); - PCI_INT(0x0, 0x02, 0x1, intr_data_ptr[PIRQ_B]); - PCI_INT(0x0, 0x02, 0x2, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x02, 0x3, intr_data_ptr[PIRQ_D]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* USB */ - PCI_INT(0x0, 0x10, 0x0, intr_data_ptr[PIRQ_C]); /* XHCI */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_HDA]); - - /* PCIe slot & Onboard NIC */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_A]); - PCI_INT(0x1, 0x0, 0x1, intr_data_ptr[PIRQ_B]); - PCI_INT(0x1, 0x0, 0x2, intr_data_ptr[PIRQ_C]); - PCI_INT(0x1, 0x0, 0x3, intr_data_ptr[PIRQ_D]); - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_B]); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index c1dd063..5d5adb4 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -23,7 +23,6 @@ select SOUTHBRIDGE_AMD_AGESA_HUDSON select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select SUPERIO_ITE_IT8728F if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_LE diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c deleted file mode 100644 index b5b0433..0000000 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <cpu/x86/lapic.h> -#include <stdint.h> -#include <string.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - u8 byte; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* IOMMU */ - PCI_INT(0x0, 0x0, 0x0, 0x10); - PCI_INT(0x0, 0x0, 0x1, 0x11); - PCI_INT(0x0, 0x0, 0x2, 0x12); - PCI_INT(0x0, 0x0, 0x3, 0x13); - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index 2a72deb..6d417ed 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -28,7 +28,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA diff --git a/src/mainboard/bap/ode_e20XX/mptable.c b/src/mainboard/bap/ode_e20XX/mptable.c deleted file mode 100644 index e4edc5f..0000000 --- a/src/mainboard/bap/ode_e20XX/mptable.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); - - /* PCI_SLOT 1 */ - PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]); - - /* PCI_SLOT 2 */ - PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]); - - PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]); - PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index ff71d5b..c1b78c8 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -28,7 +28,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select GFXUMA diff --git a/src/mainboard/bap/ode_e21XX/mptable.c b/src/mainboard/bap/ode_e21XX/mptable.c deleted file mode 100644 index 0f6ca81..0000000 --- a/src/mainboard/bap/ode_e21XX/mptable.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/pi/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/biostar/a68n_5200/Kconfig b/src/mainboard/biostar/a68n_5200/Kconfig index f608513..c8d8884 100644 --- a/src/mainboard/biostar/a68n_5200/Kconfig +++ b/src/mainboard/biostar/a68n_5200/Kconfig @@ -29,7 +29,6 @@ select SUPERIO_ITE_IT8728F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA diff --git a/src/mainboard/biostar/a68n_5200/mptable.c b/src/mainboard/biostar/a68n_5200/mptable.c deleted file mode 100644 index 7082013..0000000 --- a/src/mainboard/biostar/a68n_5200/mptable.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig index 9eaa6fb..c9960e3 100644 --- a/src/mainboard/biostar/am1ml/Kconfig +++ b/src/mainboard/biostar/am1ml/Kconfig @@ -24,7 +24,6 @@ select GFXUMA select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB diff --git a/src/mainboard/biostar/am1ml/mptable.c b/src/mainboard/biostar/am1ml/mptable.c deleted file mode 100644 index 659a141..0000000 --- a/src/mainboard/biostar/am1ml/mptable.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); - - /* PCI_SLOT 1 */ - PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]); - - /* PCI_SLOT 2 */ - PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]); - - PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]); - PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]); - } - - /* PCIe Lan*/ - //PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig index e94a6d8..5892992 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig +++ b/src/mainboard/elmex/pcm205400/Kconfig @@ -39,7 +39,6 @@ select SUPERIO_FINTEK_F81865F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/elmex/pcm205400/mptable.c b/src/mainboard/elmex/pcm205400/mptable.c deleted file mode 100644 index bc7a3ac..0000000 --- a/src/mainboard/elmex/pcm205400/mptable.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> -#include <arch/ioapic.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); - - /* IDE */ - PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index e195e8f..30c88c1 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -23,7 +23,6 @@ select SOUTHBRIDGE_AMD_CIMX_SB800 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c deleted file mode 100644 index a47336c..0000000 --- a/src/mainboard/gizmosphere/gizmo/mptable.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 685e271..6a8095d 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -28,7 +28,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/gizmosphere/gizmo2/mptable.c b/src/mainboard/gizmosphere/gizmo2/mptable.c deleted file mode 100644 index e4edc5f..0000000 --- a/src/mainboard/gizmosphere/gizmo2/mptable.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); - - /* PCI_SLOT 1 */ - PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]); - - /* PCI_SLOT 2 */ - PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]); - - PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]); - PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/google/kahlee/mptable.c b/src/mainboard/google/kahlee/mptable.c deleted file mode 100644 index 5bb70e9..0000000 --- a/src/mainboard/google/kahlee/mptable.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <soc/southbridge.h> -#include <amdblocks/amd_pci_util.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), \ - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \ - (intr), (apicid), (pin)) - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, \ - MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \ - (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig index 907c025..6239086 100644 --- a/src/mainboard/hp/abm/Kconfig +++ b/src/mainboard/hp/abm/Kconfig @@ -29,7 +29,6 @@ select SUPERIO_NUVOTON_NCT5104D select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c deleted file mode 100644 index 7082013..0000000 --- a/src/mainboard/hp/abm/mptable.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index c6c35df..1f17a15 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -25,7 +25,6 @@ select EC_COMPAL_ENE932 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select HAVE_ACPI_TABLES diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c deleted file mode 100644 index ecc57b0..0000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <cpu/x86/lapic.h> -#include <stdint.h> -#include <string.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* IOMMU */ - PCI_INT(0x0, 0x00, 0x0, 0x10); - PCI_INT(0x0, 0x00, 0x1, 0x11); - PCI_INT(0x0, 0x00, 0x2, 0x12); - PCI_INT(0x0, 0x00, 0x3, 0x13); - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index dfa01b9..dddca36 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -28,7 +28,6 @@ select SUPERIO_FINTEK_F71869AD select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c deleted file mode 100644 index 9a983b4..0000000 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <drivers/generic/ioapic/chip.h> -#include <stdint.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); - - /* IDE */ - PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* On-board NIC & Slot PCIE. */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - } - - /* On-board Realtek NIC 2. (PCIe PortA) */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 6ffe508..7f0d7bf 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -24,7 +24,6 @@ select DEFAULT_POST_ON_LPC select EC_COMPAL_ENE932 select HAVE_OPTION_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c deleted file mode 100644 index ecc57b0..0000000 --- a/src/mainboard/lenovo/g505s/mptable.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <cpu/x86/lapic.h> -#include <stdint.h> -#include <string.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* IOMMU */ - PCI_INT(0x0, 0x00, 0x0, 0x10); - PCI_INT(0x0, 0x00, 0x1, 0x11); - PCI_INT(0x0, 0x00, 0x2, 0x12); - PCI_INT(0x0, 0x00, 0x3, 0x13); - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index 4a007bf..64a8f14 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -27,7 +27,6 @@ select SUPERIO_SMSC_SMSCSUPERIO select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE # This erases 28 KB and writes 10 KB register dumps to SPI flash on every # boot, wasting 3 s and causing wear! Therefore disable S3 for now. #select HAVE_ACPI_RESUME diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c deleted file mode 100644 index 78b8ec2..0000000 --- a/src/mainboard/lippert/frontrunner-af/mptable.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index b62da2e..e97099b 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -29,7 +29,6 @@ select SUPERIO_WINBOND_W83627DHG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE # This erases 28 KB and writes 10 KB register dumps to SPI flash on every # boot, wasting 3 s and causing wear! Therefore disable S3 for now. #select HAVE_ACPI_RESUME diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c deleted file mode 100644 index 78b8ec2..0000000 --- a/src/mainboard/lippert/toucan-af/mptable.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/msi/ms7721/Kconfig b/src/mainboard/msi/ms7721/Kconfig index 1fee747..b57bc48 100644 --- a/src/mainboard/msi/ms7721/Kconfig +++ b/src/mainboard/msi/ms7721/Kconfig @@ -25,7 +25,6 @@ select SOUTHBRIDGE_AMD_AGESA_HUDSON select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select SUPERIO_FINTEK_F71869AD select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/msi/ms7721/mptable.c b/src/mainboard/msi/ms7721/mptable.c deleted file mode 100644 index fd55eda..0000000 --- a/src/mainboard/msi/ms7721/mptable.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <cpu/x86/lapic.h> -#include <stdint.h> -#include <string.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* IOMMU */ - PCI_INT(0x0, 0x0, 0x0, 0x10); - PCI_INT(0x0, 0x0, 0x1, 0x11); - PCI_INT(0x0, 0x0, 0x2, 0x12); - PCI_INT(0x0, 0x0, 0x3, 0x13); - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 3396845..9871051 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -23,7 +23,6 @@ select SOUTHBRIDGE_AMD_CIMX_SB800 select SUPERIO_NUVOTON_NCT5104D select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/pcengines/apu1/mptable.c b/src/mainboard/pcengines/apu1/mptable.c deleted file mode 100644 index 89e5dfc..0000000 --- a/src/mainboard/pcengines/apu1/mptable.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> -#include <arch/ioapic.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); - - /* IDE */ - PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - PCI_INT(0x3, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - PCI_INT(0x4, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 8c713e5..604d490 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -26,7 +26,6 @@ select DEFAULT_POST_ON_LPC select SUPERIO_NUVOTON_NCT5104D select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select USE_BLOBS diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c deleted file mode 100644 index 772ee31..0000000 --- a/src/mainboard/pcengines/apu2/mptable.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <southbridge/amd/common/amd_pci_util.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* SD card */ - PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_SD]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); - - - /* GPP0 */ - PCI_INT(0x0, 0x2, 0x0, 0x10); // Network 3 - /* GPP1 */ - PCI_INT(0x0, 0x2, 0x1, 0x11); // Network 2 - /* GPP2 */ - PCI_INT(0x0, 0x2, 0x2, 0x12); // Network 1 - /* GPP3 */ - PCI_INT(0x0, 0x2, 0x3, 0x13); // mPCI - /* GPP4 */ - PCI_INT(0x0, 0x2, 0x4, 0x14); // mPCI - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/38313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b Gerrit-Change-Number: 38313 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 38

Change in coreboot[master]: [WIP] AGESA,binaryPI boards: Move IRQ table programming
by Kyösti Mälkki (Code Review) 17 Mar '21

17 Mar '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38564 ) Change subject: [WIP] AGESA,binaryPI boards: Move IRQ table programming ...................................................................... [WIP] AGESA,binaryPI boards: Move IRQ table programming IRQ programming should be done outside (obsolete) MP table generation. Change-Id: Ibce2af4de91549c4c9743cd997f625164672a713 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/inagua/mainboard.c M src/mainboard/amd/inagua/mptable.c M src/mainboard/amd/olivehill/mainboard.c M src/mainboard/amd/olivehill/mptable.c M src/mainboard/amd/olivehillplus/mainboard.c M src/mainboard/amd/olivehillplus/mptable.c M src/mainboard/amd/parmer/mainboard.c M src/mainboard/amd/parmer/mptable.c M src/mainboard/amd/south_station/mainboard.c M src/mainboard/amd/south_station/mptable.c M src/mainboard/amd/thatcher/mainboard.c M src/mainboard/amd/thatcher/mptable.c M src/mainboard/amd/union_station/mainboard.c M src/mainboard/amd/union_station/mptable.c M src/mainboard/asrock/e350m1/mainboard.c M src/mainboard/asrock/e350m1/mptable.c M src/mainboard/asrock/imb-a180/mainboard.c M src/mainboard/asrock/imb-a180/mptable.c M src/mainboard/asus/f2a85-m/mainboard.c M src/mainboard/asus/f2a85-m/mptable.c M src/mainboard/bap/ode_e21XX/mainboard.c M src/mainboard/bap/ode_e21XX/mptable.c M src/mainboard/biostar/a68n_5200/mainboard.c M src/mainboard/biostar/a68n_5200/mptable.c M src/mainboard/gizmosphere/gizmo/mainboard.c M src/mainboard/gizmosphere/gizmo/mptable.c M src/mainboard/hp/abm/mainboard.c M src/mainboard/hp/abm/mptable.c M src/mainboard/hp/pavilion_m6_1035dx/mainboard.c M src/mainboard/hp/pavilion_m6_1035dx/mptable.c M src/mainboard/lenovo/g505s/mainboard.c M src/mainboard/lenovo/g505s/mptable.c M src/mainboard/lippert/frontrunner-af/mainboard.c M src/mainboard/lippert/frontrunner-af/mptable.c M src/mainboard/lippert/toucan-af/mainboard.c M src/mainboard/lippert/toucan-af/mptable.c M src/mainboard/msi/ms7721/mainboard.c M src/mainboard/msi/ms7721/mptable.c 38 files changed, 661 insertions(+), 715 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/38564/1 diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index 47a267b..06faa6d 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -17,6 +17,20 @@ #include <console/console.h> #include <device/device.h> +static const u8 mainboard_intr_data[] = { + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */ + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */ + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, + [0x18] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, + [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, + [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x50] = 0x10, 0x11, 0x12, 0x13 +}; + static void init_gpios(void) { /** diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index 1b4e64a..b8bd0b3 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -14,26 +14,11 @@ */ #include <arch/smp/mpspec.h> -#include <arch/io.h> #include <arch/ioapic.h> #include <string.h> #include <stdint.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -u8 intr_data[] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00, - [0x18] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, - [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00, - [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - [0x40] = 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00, - [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - [0x50] = 0x10,0x11,0x12,0x13 -}; - static void *smp_write_config_table(void *v) { struct mp_config_table *mc; @@ -59,13 +44,6 @@ /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - u8 byte; - - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); @@ -79,23 +57,23 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ diff --git a/src/mainboard/amd/olivehill/mainboard.c b/src/mainboard/amd/olivehill/mainboard.c index 65e838b..514b9c3 100644 --- a/src/mainboard/amd/olivehill/mainboard.c +++ b/src/mainboard/amd/olivehill/mainboard.c @@ -15,6 +15,31 @@ #include <console/console.h> #include <device/device.h> +#include <southbridge/amd/common/amd_pci_util.h> + +static const u8 mainboard_picr_data[0x54] = { + 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0x04, 0x05, 0x07 +}; +static const u8 mainboard_intr_data[0x54] = { + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} /********************************************** * enable the dedicated function in mainboard. @@ -22,6 +47,7 @@ static void mainboard_enable(struct device *dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + pirq_setup(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index 52374f1..7082013 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -14,30 +14,13 @@ */ #include <arch/smp/mpspec.h> -#include <arch/io.h> #include <arch/ioapic.h> #include <string.h> #include <stdint.h> #include <cpu/x86/lapic.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/hudson.h> -u8 picr_data[0x54] = { - 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x03,0x04,0x05,0x07 -}; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; @@ -60,7 +43,6 @@ { struct mp_config_table *mc; int bus_isa; - u8 byte; /* * By the time this function gets called, the IOAPIC registers @@ -87,17 +69,6 @@ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ @@ -111,27 +82,27 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ diff --git a/src/mainboard/amd/olivehillplus/mainboard.c b/src/mainboard/amd/olivehillplus/mainboard.c index 1367b03..9fb3a30 100644 --- a/src/mainboard/amd/olivehillplus/mainboard.c +++ b/src/mainboard/amd/olivehillplus/mainboard.c @@ -15,16 +15,44 @@ #include <console/console.h> #include <device/device.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <device/pci_def.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> + +static const u8 mainboard_picr_data[0x54] = { + 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0x04, 0x05, 0x07 +}; + +static const u8 mainboard_intr_data[0x54] = { + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + /********************************************** * enable the dedicated function in mainboard. **********************************************/ static void mainboard_enable(struct device *dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + pirq_setup(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c index 6c81d06..0f6ca81 100644 --- a/src/mainboard/amd/olivehillplus/mptable.c +++ b/src/mainboard/amd/olivehillplus/mptable.c @@ -14,30 +14,12 @@ */ #include <arch/smp/mpspec.h> -#include <arch/io.h> #include <arch/ioapic.h> #include <string.h> #include <stdint.h> #include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> -u8 picr_data[0x54] = { - 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x03,0x04,0x05,0x07 -}; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; @@ -60,7 +42,6 @@ { struct mp_config_table *mc; int bus_isa; - u8 byte; /* * By the time this function gets called, the IOAPIC registers @@ -87,17 +68,7 @@ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); @@ -110,27 +81,27 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index 0051d74..668a648 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -15,6 +15,31 @@ #include <console/console.h> #include <device/device.h> +#include <southbridge/amd/common/amd_pci_util.h> + +static const u8 mainboard_picr_data[0x54] = { + 0x1F, 0x1f, 0x1f, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x0B, 0x1F, 0x0B, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F +}; +static const u8 mainboard_intr_data[0x54] = { + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} /************************************************* * enable the dedicated function in parmer board. @@ -22,6 +47,7 @@ static void mainboard_enable(struct device *dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + pirq_setup(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index c2b9f98..3a5540c 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -14,30 +14,13 @@ */ #include <arch/smp/mpspec.h> -#include <arch/io.h> #include <arch/ioapic.h> #include <string.h> #include <stdint.h> #include <cpu/x86/lapic.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/hudson.h> -u8 picr_data[0x54] = { - 0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F -}; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; @@ -60,7 +43,6 @@ { struct mp_config_table *mc; int bus_isa; - u8 byte; /* * By the time this function gets called, the IOAPIC registers @@ -86,18 +68,6 @@ /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); @@ -110,27 +80,27 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index d9e4c5f..59b4b17 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -17,6 +17,23 @@ #include <console/console.h> #include <delay.h> #include <device/device.h> +#include <southbridge/amd/common/amd_pci_util.h> + +static const u8 mainboard_intr_data[] = { + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */ + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */ + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; +} /** * Southstation using SB GPIO 17/18 to control the Red/Green LED @@ -45,6 +62,8 @@ static void mainboard_enable(struct device *dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + pirq_setup(); + southstation_led_init(); /* diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index c38708e..b8bd0b3 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -14,22 +14,11 @@ */ #include <arch/smp/mpspec.h> -#include <arch/io.h> #include <arch/ioapic.h> #include <string.h> #include <stdint.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -u8 intr_data[] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - static void *smp_write_config_table(void *v) { struct mp_config_table *mc; @@ -55,13 +44,6 @@ /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - u8 byte; - - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); @@ -75,23 +57,23 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c index ef8f9c1..4bd608e 100644 --- a/src/mainboard/amd/thatcher/mainboard.c +++ b/src/mainboard/amd/thatcher/mainboard.c @@ -15,9 +15,34 @@ #include <console/console.h> #include <device/device.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <cpu/x86/msr.h> #include <cpu/amd/msr.h> +static const u8 mainboard_picr_data[] = { + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F +}; +static const u8 mainboard_intr_data[0x54] = { + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + /************************************************* * enable the dedicated function in thatcher board. *************************************************/ @@ -26,6 +51,7 @@ msr_t msr; printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + pirq_setup(); msr = rdmsr(LS_CFG_MSR); msr.lo &= ~(1 << 28); diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index b23d036..05d222a 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -14,30 +14,13 @@ */ #include <arch/smp/mpspec.h> -#include <arch/io.h> #include <arch/ioapic.h> #include <string.h> #include <stdint.h> #include <cpu/x86/lapic.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/hudson.h> -u8 picr_data[] = { - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F -}; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; @@ -86,18 +69,6 @@ /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); @@ -110,27 +81,27 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index d680520..d677c4e 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -16,14 +16,32 @@ #include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /* Platform Specific Definitions */ +static const u8 mainboard_intr_data[] = { + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */ + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */ + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; +} + /********************************************** * Enable the dedicated functions of the board. **********************************************/ static void mainboard_enable(struct device *dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + pirq_setup(); /* * Initialize ASF registers to an arbitrary address because someone diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index c38708e..b8bd0b3 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -14,22 +14,11 @@ */ #include <arch/smp/mpspec.h> -#include <arch/io.h> #include <arch/ioapic.h> #include <string.h> #include <stdint.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -u8 intr_data[] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - static void *smp_write_config_table(void *v) { struct mp_config_table *mc; @@ -55,13 +44,6 @@ /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - u8 byte; - - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); @@ -75,23 +57,23 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index 96744a3..d8764bc 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -16,15 +16,33 @@ #include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <device/mmio.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> +static const u8 mainboard_intr_data[] = { + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */ + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */ + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; +} + /********************************************** * Enable the dedicated functions of the board. **********************************************/ static void mainboard_enable(struct device *dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + pirq_setup(); /* Power off unused clock pins of GPP PCIe devices * GPP CLK0 connected to unpopulated mini PCIe slot diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index 6093e8f..0eeaa0b 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -14,25 +14,13 @@ */ -#include <arch/io.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <stdint.h> #include <string.h> - +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -u8 intr_data[] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - static void *smp_write_config_table(void *v) { struct mp_config_table *mc; @@ -58,13 +46,6 @@ /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - u8 byte; - - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); @@ -78,23 +59,23 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ diff --git a/src/mainboard/asrock/imb-a180/mainboard.c b/src/mainboard/asrock/imb-a180/mainboard.c index 65e838b..e463589 100644 --- a/src/mainboard/asrock/imb-a180/mainboard.c +++ b/src/mainboard/asrock/imb-a180/mainboard.c @@ -15,6 +15,32 @@ #include <console/console.h> #include <device/device.h> +#include <southbridge/amd/common/amd_pci_util.h> + +static const u8 mainboard_picr_data[0x54] = { + 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0x04, 0x05, 0x07 +}; + +static const u8 mainboard_intr_data[0x54] = { + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} /********************************************** * enable the dedicated function in mainboard. @@ -22,6 +48,7 @@ static void mainboard_enable(struct device *dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + pirq_setup(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c index 37080ea..7082013 100644 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ b/src/mainboard/asrock/imb-a180/mptable.c @@ -14,31 +14,13 @@ */ #include <arch/smp/mpspec.h> -#include <arch/io.h> #include <arch/ioapic.h> #include <string.h> #include <stdint.h> #include <cpu/x86/lapic.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/hudson.h> - -u8 picr_data[0x54] = { - 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x03,0x04,0x05,0x07 -}; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; @@ -61,7 +43,6 @@ { struct mp_config_table *mc; int bus_isa; - u8 byte; /* * By the time this function gets called, the IOAPIC registers @@ -88,17 +69,6 @@ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ @@ -112,27 +82,27 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c index 2a0e618..719039f 100644 --- a/src/mainboard/asus/f2a85-m/mainboard.c +++ b/src/mainboard/asus/f2a85-m/mainboard.c @@ -17,6 +17,31 @@ #include <cpu/x86/msr.h> #include <cpu/amd/msr.h> #include <device/device.h> +#include <southbridge/amd/common/amd_pci_util.h> + +static const u8 mainboard_picr_data[] = { + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F +}; +static const u8 mainboard_intr_data[0x54] = { + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} /************************************************* * enable the dedicated function in thatcher board. @@ -26,6 +51,7 @@ msr_t msr; printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + pirq_setup(); msr = rdmsr(LS_CFG_MSR); msr.lo &= ~(1 << 28); diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index 303f3bf..fd55eda 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -13,31 +13,14 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <cpu/x86/lapic.h> #include <stdint.h> #include <string.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/hudson.h> -u8 picr_data[] = { - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F -}; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; @@ -60,7 +43,6 @@ { struct mp_config_table *mc; int bus_isa; - u8 byte; /* * By the time this function gets called, the IOAPIC registers @@ -86,18 +68,6 @@ /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); @@ -116,27 +86,27 @@ PCI_INT(0x0, 0x0, 0x3, 0x13); /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ diff --git a/src/mainboard/bap/ode_e21XX/mainboard.c b/src/mainboard/bap/ode_e21XX/mainboard.c index 1367b03..f659d3a 100644 --- a/src/mainboard/bap/ode_e21XX/mainboard.c +++ b/src/mainboard/bap/ode_e21XX/mainboard.c @@ -15,16 +15,42 @@ #include <console/console.h> #include <device/device.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <device/pci_def.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> +static const u8 mainboard_picr_data[0x54] = { + 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0x04, 0x05, 0x07 +}; +static const u8 mainboard_intr_data[0x54] = { + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + /********************************************** * enable the dedicated function in mainboard. **********************************************/ static void mainboard_enable(struct device *dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + pirq_setup(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/bap/ode_e21XX/mptable.c b/src/mainboard/bap/ode_e21XX/mptable.c index 6c81d06..0f6ca81 100644 --- a/src/mainboard/bap/ode_e21XX/mptable.c +++ b/src/mainboard/bap/ode_e21XX/mptable.c @@ -14,30 +14,12 @@ */ #include <arch/smp/mpspec.h> -#include <arch/io.h> #include <arch/ioapic.h> #include <string.h> #include <stdint.h> #include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> -u8 picr_data[0x54] = { - 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x03,0x04,0x05,0x07 -}; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; @@ -60,7 +42,6 @@ { struct mp_config_table *mc; int bus_isa; - u8 byte; /* * By the time this function gets called, the IOAPIC registers @@ -87,17 +68,7 @@ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); @@ -110,27 +81,27 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ diff --git a/src/mainboard/biostar/a68n_5200/mainboard.c b/src/mainboard/biostar/a68n_5200/mainboard.c index 65e838b..514b9c3 100644 --- a/src/mainboard/biostar/a68n_5200/mainboard.c +++ b/src/mainboard/biostar/a68n_5200/mainboard.c @@ -15,6 +15,31 @@ #include <console/console.h> #include <device/device.h> +#include <southbridge/amd/common/amd_pci_util.h> + +static const u8 mainboard_picr_data[0x54] = { + 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0x04, 0x05, 0x07 +}; +static const u8 mainboard_intr_data[0x54] = { + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} /********************************************** * enable the dedicated function in mainboard. @@ -22,6 +47,7 @@ static void mainboard_enable(struct device *dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + pirq_setup(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/biostar/a68n_5200/mptable.c b/src/mainboard/biostar/a68n_5200/mptable.c index 52374f1..7082013 100644 --- a/src/mainboard/biostar/a68n_5200/mptable.c +++ b/src/mainboard/biostar/a68n_5200/mptable.c @@ -14,30 +14,13 @@ */ #include <arch/smp/mpspec.h> -#include <arch/io.h> #include <arch/ioapic.h> #include <string.h> #include <stdint.h> #include <cpu/x86/lapic.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/hudson.h> -u8 picr_data[0x54] = { - 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x03,0x04,0x05,0x07 -}; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; @@ -60,7 +43,6 @@ { struct mp_config_table *mc; int bus_isa; - u8 byte; /* * By the time this function gets called, the IOAPIC registers @@ -87,17 +69,6 @@ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ @@ -111,27 +82,27 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index 63d9453..caa4530 100644 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -19,14 +19,32 @@ #include <console/console.h> #include <delay.h> #include <device/device.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <device/pci_ops.h> +static const u8 mainboard_intr_data[] = { + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */ + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */ + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; +} + /********************************************** * Enable the dedicated functions of the board. **********************************************/ static void mainboard_enable(struct device *dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + pirq_setup(); /* enable GPP CLK0 thru CLK1 */ /* disable GPP CLK2 thru SLT_GFX_CLK */ diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c index dca5f3c..94a5d0c 100644 --- a/src/mainboard/gizmosphere/gizmo/mptable.c +++ b/src/mainboard/gizmosphere/gizmo/mptable.c @@ -15,22 +15,12 @@ */ #include <arch/smp/mpspec.h> -#include <arch/io.h> #include <arch/ioapic.h> #include <string.h> #include <stdint.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -u8 intr_data[] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - static void *smp_write_config_table(void *v) { struct mp_config_table *mc; @@ -56,13 +46,6 @@ /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - u8 byte; - - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); @@ -76,23 +59,23 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ diff --git a/src/mainboard/hp/abm/mainboard.c b/src/mainboard/hp/abm/mainboard.c index aaa899b..b5156cc 100644 --- a/src/mainboard/hp/abm/mainboard.c +++ b/src/mainboard/hp/abm/mainboard.c @@ -21,6 +21,25 @@ #include <southbridge/amd/agesa/hudson/pci_devs.h> #include <northbridge/amd/agesa/family16kb/pci_devs.h> +#if 0 +static const u8 mainboard_picr_data[0x54] = { + 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0x04, 0x05, 0x07 +}; +static const u8 mainboard_intr_data[0x54] = { + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 +}; +#endif + /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. * This table is responsible for physically routing the PIC and @@ -33,21 +52,21 @@ * MP Tables. TODO: Make ACPI use these values too. */ static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { - [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, /* INTA# - INTH# */ - [0x08] = 0x00,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F,0x0A, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon, SD */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* IMC INT0 - 5 */ - [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, /* USB Devs 18/19/20/22 INTA-C */ - [0x40] = 0x0B,0x0B, /* IDE, SATA */ + [0x00] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, /* INTA# - INTH# */ + [0x08] = 0x00, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */ + [0x10] = 0x1F, 0x1F, 0x1F, 0x0A, 0x1F, 0x1F, 0x1F, 0x0A, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon, SD */ + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, /* IMC INT0 - 5 */ + [0x30] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, /* USB Devs 18/19/20/22 INTA-C */ + [0x40] = 0x0B, 0x0B, /* IDE, SATA */ }; static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x10, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* IMC INT0 - 5 */ - [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, /* USB Devs 18/19/22/20 INTA-C */ - [0x40] = 0x11,0x13, /* IDE, SATA */ + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */ + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */ + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x10, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, /* IMC INT0 - 5 */ + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, /* USB Devs 18/19/22/20 INTA-C */ + [0x40] = 0x11, 0x13, /* IDE, SATA */ }; /* diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c index 52374f1..7082013 100644 --- a/src/mainboard/hp/abm/mptable.c +++ b/src/mainboard/hp/abm/mptable.c @@ -14,30 +14,13 @@ */ #include <arch/smp/mpspec.h> -#include <arch/io.h> #include <arch/ioapic.h> #include <string.h> #include <stdint.h> #include <cpu/x86/lapic.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/hudson.h> -u8 picr_data[0x54] = { - 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x03,0x04,0x05,0x07 -}; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; @@ -60,7 +43,6 @@ { struct mp_config_table *mc; int bus_isa; - u8 byte; /* * By the time this function gets called, the IOAPIC registers @@ -87,17 +69,6 @@ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ @@ -111,27 +82,27 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index da450c6..d874bc2f 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -18,9 +18,27 @@ #include <arch/acpi.h> #include <console/console.h> #include <device/device.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/smi.h> +static const u8 mainboard_picr_data[0x54] = { + 0x1F, 0x1f, 0x1f, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x0B, 0x1F, 0x0B, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F +}; +static const u8 mainboard_intr_data[0x54] = { + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 +}; + static void pavilion_cold_boot_init(void) { /* Lid SMI is only used in non-ACPI mode; leave it off in S3 resume */ @@ -29,9 +47,17 @@ pavilion_m6_1035dx_ec_init(); } +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + static void mainboard_enable(struct device *dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + pirq_setup(); hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH); hudson_enable_smi_generation(); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c index f3c2f0a..ecc57b0 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c @@ -13,31 +13,14 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <cpu/x86/lapic.h> #include <stdint.h> #include <string.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/hudson.h> -u8 picr_data[0x54] = { - 0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F -}; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; @@ -60,7 +43,6 @@ { struct mp_config_table *mc; int bus_isa; - u8 byte; /* * By the time this function gets called, the IOAPIC registers @@ -86,18 +68,6 @@ /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); @@ -116,27 +86,27 @@ PCI_INT(0x0, 0x00, 0x3, 0x13); /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c index c9e00b6..ff9db03 100644 --- a/src/mainboard/lenovo/g505s/mainboard.c +++ b/src/mainboard/lenovo/g505s/mainboard.c @@ -18,9 +18,28 @@ #include <arch/acpi.h> #include <console/console.h> #include <device/device.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/smi.h> +static const u8 mainboard_picr_data[0x54] = { + 0x1F, 0x1f, 0x1f, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x0B, 0x1F, 0x0B, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F +}; +static const u8 mainboard_intr_data[0x54] = { + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 +}; + + static void pavilion_cold_boot_init(void) { /* Lid SMI is only used in non-ACPI mode; leave it off in S3 resume */ @@ -29,9 +48,17 @@ lenovo_g505s_ec_init(); } +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + static void mainboard_enable(struct device *dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + pirq_setup(); hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH); hudson_enable_smi_generation(); diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c index f3c2f0a..ecc57b0 100644 --- a/src/mainboard/lenovo/g505s/mptable.c +++ b/src/mainboard/lenovo/g505s/mptable.c @@ -13,31 +13,14 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <cpu/x86/lapic.h> #include <stdint.h> #include <string.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/hudson.h> -u8 picr_data[0x54] = { - 0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F -}; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; @@ -60,7 +43,6 @@ { struct mp_config_table *mc; int bus_isa; - u8 byte; /* * By the time this function gets called, the IOAPIC registers @@ -86,18 +68,6 @@ /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); @@ -116,27 +86,27 @@ PCI_INT(0x0, 0x00, 0x3, 0x13); /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index 9e3eab7..56972d4 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -17,6 +17,7 @@ #include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> @@ -26,6 +27,16 @@ #include <southbridge/amd/cimx/sb800/gpio_oem.h> #include "sema.h" +static const u8 mainboard_intr_data[] = { + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */ + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */ + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 +}; + /* Init SIO GPIOs. */ #define SIO_RUNTIME_BASE 0x0E00 static const u16 sio_init_table[] = { // hi = offset, lo = value @@ -57,6 +68,12 @@ 0x5780, // GP65: USB power 4/5 = open drain output }; +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; +} + static void init(struct device *dev) { volatile u8 *spi_base; /* base addr of Hudson's SPI host controller */ diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c index 347b781..78b8ec2 100644 --- a/src/mainboard/lippert/frontrunner-af/mptable.c +++ b/src/mainboard/lippert/frontrunner-af/mptable.c @@ -14,22 +14,11 @@ */ #include <arch/smp/mpspec.h> -#include <arch/io.h> #include <arch/ioapic.h> #include <string.h> #include <stdint.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -u8 intr_data[] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - static void *smp_write_config_table(void *v) { struct mp_config_table *mc; @@ -55,13 +44,6 @@ /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - u8 byte; - - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); @@ -75,23 +57,23 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index 158613f..e8fc09a 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -17,6 +17,7 @@ #include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -25,6 +26,16 @@ #include <southbridge/amd/cimx/sb800/gpio_oem.h> #include "mainboard/lippert/frontrunner-af/sema.h" +static const u8 mainboard_intr_data[] = { + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */ + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */ + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 +}; + static void init(struct device *dev) { volatile u8 *spi_base; /* base addr of Hudson's SPI host controller */ @@ -95,6 +106,12 @@ printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " EXIT %s\n", __func__); } +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; +} + /********************************************** * Enable the dedicated functions of the board. **********************************************/ diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c index 347b781..78b8ec2 100644 --- a/src/mainboard/lippert/toucan-af/mptable.c +++ b/src/mainboard/lippert/toucan-af/mptable.c @@ -14,22 +14,11 @@ */ #include <arch/smp/mpspec.h> -#include <arch/io.h> #include <arch/ioapic.h> #include <string.h> #include <stdint.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -u8 intr_data[] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - static void *smp_write_config_table(void *v) { struct mp_config_table *mc; @@ -55,13 +44,6 @@ /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - u8 byte; - - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); @@ -75,23 +57,23 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ diff --git a/src/mainboard/msi/ms7721/mainboard.c b/src/mainboard/msi/ms7721/mainboard.c index 2a0e618..719039f 100644 --- a/src/mainboard/msi/ms7721/mainboard.c +++ b/src/mainboard/msi/ms7721/mainboard.c @@ -17,6 +17,31 @@ #include <cpu/x86/msr.h> #include <cpu/amd/msr.h> #include <device/device.h> +#include <southbridge/amd/common/amd_pci_util.h> + +static const u8 mainboard_picr_data[] = { + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F +}; +static const u8 mainboard_intr_data[0x54] = { + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} /************************************************* * enable the dedicated function in thatcher board. @@ -26,6 +51,7 @@ msr_t msr; printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + pirq_setup(); msr = rdmsr(LS_CFG_MSR); msr.lo &= ~(1 << 28); diff --git a/src/mainboard/msi/ms7721/mptable.c b/src/mainboard/msi/ms7721/mptable.c index 303f3bf..fd55eda 100644 --- a/src/mainboard/msi/ms7721/mptable.c +++ b/src/mainboard/msi/ms7721/mptable.c @@ -13,31 +13,14 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <cpu/x86/lapic.h> #include <stdint.h> #include <string.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/hudson.h> -u8 picr_data[] = { - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F -}; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; @@ -60,7 +43,6 @@ { struct mp_config_table *mc; int bus_isa; - u8 byte; /* * By the time this function gets called, the IOAPIC registers @@ -86,18 +68,6 @@ /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); @@ -116,27 +86,27 @@ PCI_INT(0x0, 0x0, 0x3, 0x13); /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibce2af4de91549c4c9743cd997f625164672a713 Gerrit-Change-Number: 38564 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

6 28

Change in coreboot[master]: [RFC] AMD APM_CNT and SMI enablement
by Kyösti Mälkki (Code Review) 16 Mar '21

16 Mar '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42563 ) Change subject: [RFC] AMD APM_CNT and SMI enablement ...................................................................... [RFC] AMD APM_CNT and SMI enablement Some suspicious callsite caught my eye. Change-Id: I8d1287566061bc5d6f05e687f2b30c6bcb66c999 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/picasso/southbridge.c M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/42563/1 diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 0ff5606..89b49f6 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -233,6 +233,7 @@ u32 reg; msr_t cst_addr; + /* We use some of these ports in SMM regardless of whether or not * ACPI tables are generated. Enable these ports indiscriminately. */ diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index e90fe1b..8a45fda 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -470,6 +470,7 @@ { u32 reg; + /* We use some of these ports in SMM regardless of whether or not * ACPI tables are generated. Enable these ports indiscriminately. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d1287566061bc5d6f05e687f2b30c6bcb66c999 Gerrit-Change-Number: 42563 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: mb/lenovo/t440p: update VBT
by DaLao (Code Review) 15 Mar '21

15 Mar '21

DaLao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40723 ) Change subject: mb/lenovo/t440p: update VBT ...................................................................... mb/lenovo/t440p: update VBT Update T440p's VBT from to version 2179. Extracted from the latest bios update file: T440p's bios image https://download.lenovo.com/pccbbs/mobiles/gluj42us.iso Test: boot t440p with both SeaBIOS and Tianocore payloads, verify dp output and backlight control all works under both Linux and Windows. Signed-off-by: dalao <dalao(a)tutanota.com> Change-Id: If8669b8de6fa0801e261138651b8b2cf50432a70 --- M src/mainboard/lenovo/t440p/data.vbt 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/40723/1 diff --git a/src/mainboard/lenovo/t440p/data.vbt b/src/mainboard/lenovo/t440p/data.vbt index 1b2cd87..79077cc 100644 --- a/src/mainboard/lenovo/t440p/data.vbt +++ b/src/mainboard/lenovo/t440p/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/40723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8669b8de6fa0801e261138651b8b2cf50432a70 Gerrit-Change-Number: 40723 Gerrit-PatchSet: 1 Gerrit-Owner: DaLao <dalao(a)tutanota.com> Gerrit-MessageType: newchange

5 19

Change in coreboot[master]: mb/ocp/deltalake: Override uart base address via VPD variable
by Bryant Ou (Code Review) 15 Mar '21

15 Mar '21

Bryant Ou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45408 ) Change subject: mb/ocp/deltalake: Override uart base address via VPD variable ...................................................................... mb/ocp/deltalake: Override uart base address via VPD variable Use VPD of "uart_ioport" to override base address at run time, the data will be used during FSP/coreboot if UART_OVERRIDE_BASE_ADDR is selected. Tested=On OCP Delta Lake, console messages correctly output to uart port which is defined in VPD. Signed-off-by: Bryant Ou <Bryant.Ou.Q(a)gmail.com> Change-Id: I55a85d6f137ef1aba95466e7b094740b685bf9bd --- M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/deltalake/Makefile.inc M src/mainboard/ocp/deltalake/romstage.c A src/mainboard/ocp/deltalake/uart.c M src/mainboard/ocp/deltalake/vpd.h 5 files changed, 66 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/45408/1 diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index adce988..5671664 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -16,6 +16,7 @@ select IPMI_OCP select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM2 + select UART_OVERRIDE_BASE_ADDR config POWER_STATE_DEFAULT_ON_AFTER_FAILURE default n diff --git a/src/mainboard/ocp/deltalake/Makefile.inc b/src/mainboard/ocp/deltalake/Makefile.inc index be6af24..ecef891 100644 --- a/src/mainboard/ocp/deltalake/Makefile.inc +++ b/src/mainboard/ocp/deltalake/Makefile.inc @@ -8,5 +8,14 @@ ramstage-y += ramstage.c ipmi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c +ifeq ($(CONFIG_UART_OVERRIDE_BASE_ADDR),y) +bootblock-y += uart.c +verstage-y += uart.c +romstage-y += uart.c +postcar-y += uart.c +ramstage-y += uart.c +smm-$(CONFIG_DEBUG_SMI) += uart.c +endif + CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH) diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index 71a26c8..bf7491c 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -20,6 +20,8 @@ { uint8_t val; char val_str[VPD_LEN]; + uint16_t base; + char port[VPD_LEN]; /* Send FSP log message to SOL */ if (vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) @@ -29,7 +31,12 @@ "SerialIoUartDebugEnable to %d\n", FSP_LOG, FSP_LOG_DEFAULT); mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; } - mupd->FspmConfig.SerialIoUartDebugIoBase = 0x2f8; + + if (vpd_gets(UART_IOPORT, port, VPD_LEN, VPD_RW_THEN_RO)) + base = hex2int(port); + else + base = hex2int(UART_IOPORT_DEFAULT); + mupd->FspmConfig.SerialIoUartDebugIoBase = base; if (mupd->FspmConfig.SerialIoUartDebugEnable) { /* FSP debug log level */ diff --git a/src/mainboard/ocp/deltalake/uart.c b/src/mainboard/ocp/deltalake/uart.c new file mode 100644 index 0000000..28801c8 --- /dev/null +++ b/src/mainboard/ocp/deltalake/uart.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/uart.h> +#include <drivers/vpd/vpd.h> +#include <string.h> +#include "vpd.h" + +int hex2int(const char *hexstr) +{ + int val = 0; + + if (hexstr[0] == '0' && hexstr[1] == 'x') + hexstr = hexstr + 2; + + while (*hexstr) { + char c = *hexstr++; + if (c >= '0' && c <= '9') + c = c - '0'; + else if (c >= 'a' && c <='f') + c = c - 'a' + 10; + else if (c >= 'A' && c <='F') + c = c - 'A' + 10; + val = (val << 4) | (c & 0xF); + } + + return val; +} + +#if (CONFIG(UART_OVERRIDE_BASE_ADDR)) +uintptr_t uart_platform_base(unsigned int idx) +{ + char port[VPD_LEN]; + uintptr_t base; + + if (vpd_gets(UART_IOPORT, port, VPD_LEN, VPD_RW_THEN_RO)) + base = hex2int(port); + else + base = hex2int(UART_IOPORT_DEFAULT); + + return base; +} +#endif \ No newline at end of file diff --git a/src/mainboard/ocp/deltalake/vpd.h b/src/mainboard/ocp/deltalake/vpd.h index ae2099d..4285e68 100644 --- a/src/mainboard/ocp/deltalake/vpd.h +++ b/src/mainboard/ocp/deltalake/vpd.h @@ -32,4 +32,10 @@ #define FSP_DCI "fsp_dci_enable" /* 1 or 0: enable or disable DCI */ #define FSP_DCI_DEFAULT 0 /* Default value when the VPD variable is not found */ +/* Define uart io port for FSP/coreboot/payload */ +#define UART_IOPORT "uart_ioport" +#define UART_IOPORT_DEFAULT "0x2f8" + +int hex2int(const char *hexstr); + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55a85d6f137ef1aba95466e7b094740b685bf9bd Gerrit-Change-Number: 45408 Gerrit-PatchSet: 1 Gerrit-Owner: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-MessageType: newchange

8 30

Change in coreboot[master]: cbfstool: Add support for platform "fixups" when modifying bootblock
by Julius Werner (Code Review) 13 Mar '21

13 Mar '21

Hello Patrick Georgi, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41122 to review the following change. Change subject: cbfstool: Add support for platform "fixups" when modifying bootblock ...................................................................... cbfstool: Add support for platform "fixups" when modifying bootblock To support the new CONFIG_CBFS_VERIFICATION feature, cbfstool needs to update the master hash embedded in the bootblock code every time it adds or removes a CBFS file. This can lead to problems on certain platforms where the bootblock needs to be specially wrapped in some platform-specific data structure so that the platform's masked ROM can recognize it. If that data structure contains any form of hash or signature of the bootblock code that is checked on every boot, it will no longer match if cbfstool modifies it after the fact. In general, we should always try to disable these kinds of features where possible (they're not super useful anyway). But for platforms where the hardware simply doesn't allow that, this patch introduces the concept of "platform fixups" to cbfstool. Whenever cbfstool finds a master hash anchor in a CBFS image, it will run all built-in "fixup probe" functions on that bootblock to check if it can recognize it as the wrapper format for a platform known to have such an issue. If so, it will register a corresponding fixup function that will run whenever it tries to write back modified data to that bootblock. The function can then modify any platform-specific headers as necessary. As first supported platform, this patch adds a fixup for Qualcomm platforms (specifically the header format used by sc7180), which recalculates the bootblock body hash originally added by util/qualcomm/createxbl.py. (Note that this feature is not intended to support platform-specific signature schemes like BootGuard directly in cbfstool. For anything that requires an actual secret key, it should be okay if the user needs to run a platform-specific signing tool on the final CBFS image before flashing. This feature is intended for the normal unsigned case (which on some platforms may be implemented as signing with a well-known key) so that on a board that is not "locked down" in any way the normal use case of manipulating an image with cbfstool and then directly flashing the output file stays working with CONFIG_CBFS_VERIFICATION.) Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I02a83a40f1d0009e6f9561ae5d2d9f37a510549a --- M util/cbfstool/Makefile.inc M util/cbfstool/cbfs.h M util/cbfstool/cbfstool.c M util/cbfstool/elf.h A util/cbfstool/platform_fixups.c 5 files changed, 131 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/41122/1 diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index e98b52e..1a5882f 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -22,6 +22,7 @@ cbfsobj += rmodule.o cbfsobj += xdr.o cbfsobj += partitioned_file.o +cbfsobj += platform_fixups.o # COMMONLIB cbfsobj += cbfs_private.o cbfsobj += fsp_relocate.o diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index 10b478c..0199d9c 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -78,4 +78,9 @@ void xdr_get_seg(struct cbfs_payload_segment *out, struct cbfs_payload_segment *in); +/* platform_fixups.c */ +typedef int (*platform_fixup_func)(struct buffer *buffer, size_t offset); +platform_fixup_func platform_fixups_probe(struct buffer *buffer, size_t offset, + const char *region_name); + #endif diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index bc07b6f..0b0fea7 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -108,6 +108,7 @@ const char *region; size_t offset; struct vb2_hash cbfs_hash; + platform_fixup_func fixup; }; static struct mh_cache *get_mh_cache(void) @@ -157,6 +158,8 @@ } mhc.cbfs_hash = anchor->cbfs_hash; mhc.offset = (void *)anchor - buffer_get(&buffer); + mhc.fixup = platform_fixups_probe(&buffer, mhc.offset, + mhc.region); return &mhc; } @@ -198,6 +201,8 @@ master_hash_anchor_fmap_hash(anchor), fmap_hash, vb2_digest_size(anchor->cbfs_hash.algo)); } + if (mhc->fixup && mhc->fixup(&buffer, mhc->offset) != 0) + return -1; if (!partitioned_file_write_region(param.image_file, &buffer)) return -1; return 0; diff --git a/util/cbfstool/elf.h b/util/cbfstool/elf.h index 11cee4f..9ba55a6 100644 --- a/util/cbfstool/elf.h +++ b/util/cbfstool/elf.h @@ -574,6 +574,8 @@ #define PF_W (1 << 1) /* Segment is writable */ #define PF_R (1 << 2) /* Segment is readable */ #define PF_MASKOS 0x0ff00000 /* OS-specific */ +#define PF_QC_SG_MASK 0x07000000 /* Qualcomm "segment" types */ +#define PF_QC_SG_HASH 0x02000000 /* Qualcomm hash segment */ #define PF_MASKPROC 0xf0000000 /* Processor-specific */ /* Legal values for note segment descriptor types for core files. */ diff --git a/util/cbfstool/platform_fixups.c b/util/cbfstool/platform_fixups.c new file mode 100644 index 0000000..f893a4d --- /dev/null +++ b/util/cbfstool/platform_fixups.c @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "cbfs.h" +#include "cbfs_sections.h" +#include "elfparsing.h" + +/* + * NOTE: This currently only implements support for MBN version 6 (as used by sc7180). Support + * for other MBN versions could probably be added but may require more parsing to tell them + * apart, and minor modifications (e.g. different hash algorithm). Add later as needed. + */ +static void *qualcomm_find_hash(struct buffer *in, size_t bb_offset, struct vb2_hash *real_hash) +{ + size_t search_end_size = MIN(0, buffer_size(in) - 32 * KiB); + struct buffer elf; + buffer_clone(&elf, in); + + /* To identify a Qualcomm image, first we find the GPT header... */ + while (buffer_size(&elf) > search_end_size && + !buffer_check_magic(&elf, "EFI PART", 8)) + buffer_seek(&elf, 512); + + /* ...then shortly afterwards there's an ELF header... */ + while (buffer_size(&elf) > search_end_size && + !buffer_check_magic(&elf, ELFMAG, 4)) + buffer_seek(&elf, 512); + + if (buffer_size(&elf) <= search_end_size) + return NULL; /* Doesn't seem to be a Qualcomm image. */ + + struct parsed_elf pelf; + if (parse_elf(&elf, &pelf, ELF_PARSE_PHDR)) + return NULL; /* Not an ELF -- guess not a Qualcomm MBN after all? */ + + /* Qualcomm stores an array of SHA-384 hashes in a special ELF segment. One special one + to start with, and then one for each segment in order. */ + void *bb_hash = NULL; + void *hashtable = NULL; + int i; + int bb_segment = -1; + for (i = 0; i < pelf.ehdr.e_phnum; i++) { + Elf64_Phdr *ph = &pelf.phdr[i]; + if ((ph->p_flags & PF_QC_SG_MASK) == PF_QC_SG_HASH) { + if ((int)ph->p_filesz != + (pelf.ehdr.e_phnum + 1) * VB2_SHA384_DIGEST_SIZE) { + ERROR("fixups: Qualcomm hash segment has wrong size!\n"); + goto destroy_elf; + } /* Found the table with the hashes -- store its address. */ + hashtable = buffer_get(&elf) + ph->p_offset; + } else if (bb_segment < 0 && ph->p_offset + ph->p_filesz < buffer_size(&elf) && + buffer_offset(&elf) + ph->p_offset <= bb_offset && + buffer_offset(&elf) + ph->p_offset + ph->p_filesz > bb_offset) { + bb_segment = i; /* Found the bootblock segment -- store its index. */ + } + } + if (!hashtable) /* ELF but no special QC hash segment -- guess not QC after all? */ + goto destroy_elf; + if (bb_segment < 0) { /* Can assume it's QC if we found the special segment. */ + ERROR("fixups: Cannot find bootblock code in Qualcomm MBN!\n"); + goto destroy_elf; + } + + /* Pass out the actual hash of the current bootblock segment in |real_hash|. */ + if (vb2_hash_calculate(buffer_get(&elf) + pelf.phdr[bb_segment].p_offset, + pelf.phdr[bb_segment].p_filesz, VB2_HASH_SHA384, real_hash)) { + ERROR("fixups: vboot digest error\n"); + goto destroy_elf; + } /* Return pointer to where the bootblock hash needs to go in Qualcomm's table. */ + bb_hash = hashtable + (bb_segment + 1) * VB2_SHA384_DIGEST_SIZE; + +destroy_elf: + parsed_elf_destroy(&pelf); + return bb_hash; +} + +static bool qualcomm_probe(struct buffer *buffer, size_t offset) +{ + struct vb2_hash real_hash; + void *table_hash = qualcomm_find_hash(buffer, offset, &real_hash); + if (!table_hash) + return false; + + if (memcmp(real_hash.raw, table_hash, VB2_SHA384_DIGEST_SIZE)) { + ERROR("fixups: Identified Qualcomm MBN, but existing hash doesn't match!\n"); + return false; + } + + return true; +} + +static int qualcomm_fixup(struct buffer *buffer, size_t offset) +{ + struct vb2_hash real_hash; + void *table_hash = qualcomm_find_hash(buffer, offset, &real_hash); + if (!table_hash) { + ERROR("fixups: Cannot find Qualcomm MBN headers anymore!\n"); + return -1; + } + + memcpy(table_hash, real_hash.raw, VB2_SHA384_DIGEST_SIZE); + INFO("fixups: Updated Qualcomm MBN header bootblock hash.\n"); + return 0; +} + +platform_fixup_func platform_fixups_probe(struct buffer *buffer, size_t offset, + const char *region_name) +{ + if (!strcmp(region_name, SECTION_NAME_BOOTBLOCK)) { + if (qualcomm_probe(buffer, offset)) + return qualcomm_fixup; + } else if (!strcmp(region_name, SECTION_NAME_PRIMARY_CBFS)) { + /* TODO: add fixups for primary CBFS bootblock platforms, if needed */ + } else { + ERROR("%s called for unexpected FMAP region %s!\n", __func__, region_name); + } + + return NULL; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02a83a40f1d0009e6f9561ae5d2d9f37a510549a Gerrit-Change-Number: 41122 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: cbfstool: Support CONFIG_CBFS_VERIFICATION and master hash anchor
by Julius Werner (Code Review) 13 Mar '21

13 Mar '21

Hello Patrick Georgi, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41121 to review the following change. Change subject: cbfstool: Support CONFIG_CBFS_VERIFICATION and master hash anchor ...................................................................... cbfstool: Support CONFIG_CBFS_VERIFICATION and master hash anchor This patch adds support for the new CONFIG_CBFS_VERIFICATION feature to cbfstool. When CBFS verification is enabled, cbfstool must automatically add a hash attribute to every CBFS file it adds (with a handful of exceptions like bootblock and "header" pseudofiles that are never read by coreboot code itself). It must also automatically update the master hash that is embedded in the bootblock code. It will automatically find the master hash by scanning the bootblock for its magic number and use its presence to auto-detect whether CBFS verification is enabled for an image (and which hash algorithm to use). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I61a84add8654f60c683ef213b844a11b145a5cb7 --- M util/cbfstool/Makefile.inc A util/cbfstool/cbfs_glue.h M util/cbfstool/cbfs_sections.h M util/cbfstool/cbfstool.c 4 files changed, 243 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/41121/1 diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 000ceb2..e98b52e 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -23,10 +23,8 @@ cbfsobj += xdr.o cbfsobj += partitioned_file.o # COMMONLIB -cbfsobj += cbfs.o +cbfsobj += cbfs_private.o cbfsobj += fsp_relocate.o -cbfsobj += mem_pool.o -cbfsobj += region.o # FMAP cbfsobj += fmap.o cbfsobj += kv_pair.o @@ -72,10 +70,6 @@ ifitobj += cbfs-mkstage.o ifitobj += cbfs-mkpayload.o ifitobj += rmodule.o -# COMMONLIB -ifitobj += cbfs.o -ifitobj += mem_pool.o -ifitobj += region.o # FMAP ifitobj += fmap.o ifitobj += kv_pair.o @@ -101,6 +95,7 @@ TOOLCPPFLAGS ?= -D_DEFAULT_SOURCE # memccpy() from string.h TOOLCPPFLAGS += -D_BSD_SOURCE -D_SVID_SOURCE # _DEFAULT_SOURCE for older glibc TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h +TOOLCPPFLAGS += -D_GNU_SOURCE # memmem() from string.h TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap TOOLCPPFLAGS += -I$(top)/util/cbfstool TOOLCPPFLAGS += -I$(objutil)/cbfstool @@ -207,9 +202,7 @@ # Tolerate lzma sdk warnings $(objutil)/cbfstool/LzmaEnc.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual # Tolerate commonlib warnings -$(objutil)/cbfstool/region.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual -$(objutil)/cbfstool/cbfs.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual -$(objutil)/cbfstool/mem_pool.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual +$(objutil)/cbfstool/cbfs_private.o: TOOLCFLAGS += -Wno-sign-compare # Tolerate lz4 warnings $(objutil)/cbfstool/lz4.o: TOOLCFLAGS += -Wno-missing-prototypes $(objutil)/cbfstool/lz4_wrapper.o: TOOLCFLAGS += -Wno-attributes diff --git a/util/cbfstool/cbfs_glue.h b/util/cbfstool/cbfs_glue.h new file mode 100644 index 0000000..11786be --- /dev/null +++ b/util/cbfstool/cbfs_glue.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _CBFS_GLUE_H_ +#define _CBFS_GLUE_H_ + +#include "cbfs_image.h" + +#define CBFS_ENABLE_HASHING 1 + +typedef const struct cbfs_image *cbfs_dev_t; + +static inline ssize_t cbfs_dev_read(cbfs_dev_t dev, void *buffer, size_t offset, size_t size) +{ + if (buffer_size(&dev->buffer) < offset || + buffer_size(&dev->buffer) - offset < size) + return -1; + + memcpy(buffer, buffer_get(&dev->buffer) + offset, size); + return size; +} + +static inline size_t cbfs_dev_size(cbfs_dev_t dev) +{ + return buffer_size(&dev->buffer); +} + +#endif /* _CBFS_GLUE_H_ */ diff --git a/util/cbfstool/cbfs_sections.h b/util/cbfstool/cbfs_sections.h index 3526f8d..d444cce 100644 --- a/util/cbfstool/cbfs_sections.h +++ b/util/cbfstool/cbfs_sections.h @@ -22,6 +22,7 @@ #define SECTION_NAME_FMAP "FMAP" #define SECTION_NAME_PRIMARY_CBFS "COREBOOT" +#define SECTION_NAME_BOOTBLOCK "BOOTBLOCK" #define SECTION_ANNOTATION_CBFS "CBFS" diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 6015603..bc07b6f 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -31,13 +31,13 @@ #include "cbfs_sections.h" #include "elfparsing.h" #include "partitioned_file.h" +#include <commonlib/bsd/cbfs_private.h> +#include <commonlib/bsd/master_hash.h> #include <commonlib/fsp.h> #include <commonlib/endian.h> #include <commonlib/helpers.h> #include <vboot_host.h> -#define SECTION_WITH_FIT_TABLE "BOOTBLOCK" - struct command { const char *name; const char *optstring; @@ -104,6 +104,144 @@ .u64val = -1, }; +struct mh_cache { + const char *region; + size_t offset; + struct vb2_hash cbfs_hash; +}; + +static struct mh_cache *get_mh_cache(void) +{ + static struct mh_cache mhc; + + if (mhc.region) + return &mhc; + + const struct fmap *fmap = partitioned_file_get_fmap(param.image_file); + if (!fmap) + goto no_master_hash; + + size_t offset, size; + struct buffer buffer; + if (fmap_find_area(fmap, SECTION_NAME_BOOTBLOCK)) { + if (!partitioned_file_read_region(&buffer, param.image_file, + SECTION_NAME_BOOTBLOCK)) + goto no_master_hash; + mhc.region = SECTION_NAME_BOOTBLOCK; + offset = 0; + size = buffer.size; + } else { + struct cbfs_image cbfs; + struct cbfs_file *bootblock; + if (!partitioned_file_read_region(&buffer, param.image_file, + SECTION_NAME_PRIMARY_CBFS)) + goto no_master_hash; + mhc.region = SECTION_NAME_PRIMARY_CBFS; + if (cbfs_image_from_buffer(&cbfs, &buffer, param.headeroffset)) + goto no_master_hash; + bootblock = cbfs_get_entry(&cbfs, "bootblock"); + if (!bootblock || ntohl(bootblock->type) != CBFS_TYPE_BOOTBLOCK) + goto no_master_hash; + offset = (void *)bootblock + ntohl(bootblock->offset) - + buffer_get(&cbfs.buffer); + size = ntohl(bootblock->len); + } + + struct master_hash_anchor *anchor = memmem(buffer_get(&buffer) + offset, + size, MASTER_HASH_ANCHOR_MAGIC, sizeof(anchor->magic)); + if (anchor) { + if (!vb2_digest_size(anchor->cbfs_hash.algo)) { + ERROR("Unknown CBFS master hash type: %d\n", + anchor->cbfs_hash.algo); + goto no_master_hash; + } + mhc.cbfs_hash = anchor->cbfs_hash; + mhc.offset = (void *)anchor - buffer_get(&buffer); + return &mhc; + } + +no_master_hash: + mhc.cbfs_hash.algo = VB2_HASH_INVALID; + mhc.region = (void *)-1; + return &mhc; +} + +static void update_and_info(const char *name, void *dst, void *src, size_t size) +{ + if (!memcmp(dst, src, size)) + return; + char *src_str = bintohex(src, size); + char *dst_str = bintohex(dst, size); + INFO("Updating %s from %s to %s\n", name, dst_str, src_str); + memcpy(dst, src, size); + free(src_str); + free(dst_str); +} + +static int update_anchor(struct mh_cache *mhc, uint8_t *fmap_hash) +{ + struct buffer buffer; + if (!partitioned_file_read_region(&buffer, param.image_file, + mhc->region)) + return -1; + struct master_hash_anchor *anchor = buffer_get(&buffer) + mhc->offset; + if (memcmp(anchor->magic, MASTER_HASH_ANCHOR_MAGIC, + sizeof(anchor->magic)) || + anchor->cbfs_hash.algo != mhc->cbfs_hash.algo) { + ERROR("Master hash anchor no longer where it used to be!\n"); + return -1; + } + update_and_info("CBFS master hash", anchor->cbfs_hash.raw, + mhc->cbfs_hash.raw, vb2_digest_size(anchor->cbfs_hash.algo)); + if (fmap_hash) { + update_and_info("FMAP hash", + master_hash_anchor_fmap_hash(anchor), fmap_hash, + vb2_digest_size(anchor->cbfs_hash.algo)); + } + if (!partitioned_file_write_region(param.image_file, &buffer)) + return -1; + return 0; + +} + +static int maybe_update_master_hash(struct cbfs_image *cbfs) +{ + if (strcmp(param.region_name, SECTION_NAME_PRIMARY_CBFS)) + return 0; /* Master hash only embedded in primary CBFS. */ + + struct mh_cache *mhc = get_mh_cache(); + if (mhc->cbfs_hash.algo == VB2_HASH_INVALID) + return 0; + + cb_err_t err = cbfs_walk(cbfs, NULL, NULL, &mhc->cbfs_hash, + CBFS_WALK_WRITEBACK_HASH); + if (err != CB_CBFS_NOT_FOUND) { + ERROR("Unexpected cbfs_walk() error %d\n", err); + return -1; + } + + return update_anchor(mhc, NULL); +} + +static int maybe_update_fmap_hash(void) +{ + if (strcmp(param.region_name, SECTION_NAME_BOOTBLOCK) && + strcmp(param.region_name, SECTION_NAME_FMAP) && + param.type != CBFS_TYPE_BOOTBLOCK) + return 0; /* FMAP and bootblock didn't change. */ + + struct mh_cache *mhc = get_mh_cache(); + if (mhc->cbfs_hash.algo == VB2_HASH_INVALID) + return 0; + + uint8_t fmap_hash[VB2_MAX_DIGEST_SIZE]; + const struct fmap *fmap = partitioned_file_get_fmap(param.image_file); + if (!fmap || vb2_digest_buffer((const void *)fmap, fmap_size(fmap), + mhc->cbfs_hash.algo, fmap_hash, sizeof(fmap_hash))) + return -1; + return update_anchor(mhc, fmap_hash); +} + static bool region_is_flashmap(const char *region) { return partitioned_file_region_check_magic(param.image_file, region, @@ -253,13 +391,21 @@ header = cbfs_create_file_header(CBFS_TYPE_RAW, buffer.size, name); + + enum vb2_hash_algorithm algo = get_mh_cache()->cbfs_hash.algo; + if (algo != VB2_HASH_INVALID) + if (cbfs_add_file_hash(header, &buffer, algo)) { + ERROR("couldn't add hash for '%s'\n", name); + goto done; + } + if (cbfs_add_entry(&image, &buffer, offset, header, 0) != 0) { ERROR("Failed to add %llu into ROM image as '%s'.\n", (long long unsigned)u64val, name); goto done; } - ret = 0; + ret = maybe_update_master_hash(&image); done: free(header); @@ -366,6 +512,7 @@ h->offset = htonl(offset); h->architecture = htonl(CBFS_ARCHITECTURE_UNKNOWN); + /* Never add a hash attribute to the master header. */ header = cbfs_create_file_header(CBFS_TYPE_CBFSHEADER, buffer_size(&buffer), name); if (cbfs_add_entry(&image, &buffer, 0, header, 0) != 0) { @@ -396,7 +543,7 @@ return 1; } - ret = 0; + ret = maybe_update_master_hash(&image); done: free(header); @@ -497,18 +644,32 @@ if (convert && convert(&buffer, &offset, header) != 0) { ERROR("Failed to parse file '%s'.\n", filename); - buffer_delete(&buffer); - return 1; + goto error; } - if (param.hash != VB2_HASH_INVALID) - if (cbfs_add_file_hash(header, &buffer, param.hash) == -1) { - ERROR("couldn't add hash for '%s'\n", name); - free(header); - buffer_delete(&buffer); - return 1; + /* Bootblock and CBFS header should never have file hashes. When adding + the bootblock it is important that we *don't* look up the master hash + yet (before it is added) or we'll cache an outdated result. */ + if (type != CBFS_TYPE_BOOTBLOCK && type != CBFS_TYPE_CBFSHEADER) { + enum vb2_hash_algorithm mh_algo = get_mh_cache()->cbfs_hash.algo; + if (mh_algo != VB2_HASH_INVALID && param.hash != mh_algo) { + if (param.hash == VB2_HASH_INVALID) { + param.hash = mh_algo; + } else { + ERROR("Cannot specify hash %s that's different from master hash algorithm %s\n", + vb2_get_hash_algorithm_name(param.hash), + vb2_get_hash_algorithm_name(mh_algo)); + goto error; + } } + if (param.hash != VB2_HASH_INVALID && + cbfs_add_file_hash(header, &buffer, param.hash) == -1) { + ERROR("couldn't add hash for '%s'\n", name); + goto error; + } + } + if (param.autogen_attr) { /* Add position attribute if assigned */ if (param.baseaddress_assigned || param.stage_xip) { @@ -573,14 +734,18 @@ -offset); if (cbfs_add_entry(&image, &buffer, offset, header, len_align) != 0) { ERROR("Failed to add '%s' into ROM image.\n", filename); - free(header); - buffer_delete(&buffer); - return 1; + goto error; } free(header); buffer_delete(&buffer); - return 0; + + return maybe_update_master_hash(&image) || maybe_update_fmap_hash(); + +error: + free(header); + buffer_delete(&buffer); + return 1; } static int cbfstool_convert_raw(struct buffer *buffer, @@ -925,7 +1090,7 @@ return 1; } - return 0; + return maybe_update_master_hash(&image); } static int cbfs_create(void) @@ -1096,6 +1261,33 @@ cbfs_print_directory(&image); } + if (verbose) { + struct mh_cache *mhc = get_mh_cache(); + if (mhc->cbfs_hash.algo == VB2_HASH_INVALID) + return 0; + + struct vb2_hash real_hash = { .algo = mhc->cbfs_hash.algo }; + cb_err_t err = cbfs_walk(&image, NULL, NULL, &real_hash, + CBFS_WALK_WRITEBACK_HASH); + if (err != CB_CBFS_NOT_FOUND) { + ERROR("Unexpected cbfs_walk() error %d\n", err); + return 1; + } + char *hash_str = bintohex(real_hash.raw, + vb2_digest_size(real_hash.algo)); + printf("[MASTER HASH]\t%s:%s", + vb2_get_hash_algorithm_name(real_hash.algo), hash_str); + if (!strcmp(param.region_name, SECTION_NAME_PRIMARY_CBFS)) { + if (!memcmp(mhc->cbfs_hash.raw, real_hash.raw, + vb2_digest_size(real_hash.algo))) + printf(":valid"); + else + printf(":invalid"); + } + printf("\n"); + free(hash_str); + } + return 0; } @@ -1194,7 +1386,8 @@ memcpy(param.image_region->data + offset, new_content.data, new_content.size); buffer_delete(&new_content); - return 0; + + return maybe_update_fmap_hash(); } static int cbfs_read(void) @@ -1454,7 +1647,7 @@ "Find a place for a file of that size\n" " layout [-w] " "List mutable (or, with -w, readable) image regions\n" - " print [-r image,regions] " + " print [-r image,regions] [-k] " "Show the contents of the ROM\n" " extract [-r image,regions] [-m ARCH] -n NAME -f FILE [-U] " "Extracts a file from ROM\n" -- To view, visit https://review.coreboot.org/c/coreboot/+/41121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61a84add8654f60c683ef213b844a11b145a5cb7 Gerrit-Change-Number: 41121 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 40

Change in coreboot[master]: [WIP] common sb/intel fadt
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43470 ) Change subject: [WIP] common sb/intel fadt ...................................................................... [WIP] common sb/intel fadt Change-Id: I6b995d526d6781d1f53c017068ed83ea46a93f32 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc A src/southbridge/intel/common/fadt.c A src/southbridge/intel/common/fadt.h 4 files changed, 81 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/43470/1 diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 9356a2b..a3095bc 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -52,6 +52,9 @@ select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select SOUTHBRIDGE_INTEL_COMMON_PMBASE +config SOUTHBRIDGE_INTEL_COMMON_ACPI_FADT + bool + config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT bool diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index b3c48fa..77f0795 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -35,6 +35,7 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smi.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smihandler.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_FADT) += fadt.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT) += madt.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c diff --git a/src/southbridge/intel/common/fadt.c b/src/southbridge/intel/common/fadt.c new file mode 100644 index 0000000..31feff6 --- /dev/null +++ b/src/southbridge/intel/common/fadt.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/common/fadt.h> +#include <southbridge/intel/common/pmbase.h> + +/* FIXME: pmutil.h definitions are a mess */ +#define PM1_STS 0x00 +#define PM1_CNT 0x04 +#define PM1_TMR 0x08 +#define GPE0_STS 0x20 +#define PM2_CNT 0x50 + +#define PM1A_EVT_BYTES 4 +#define PM1A_CNT_BYTES 2 +#define PM2_CNT_BYTES 1 +#define PM_TMR_BYTES 4 +#define GPE0_BYTES 16 + +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + const u16 pmbase = lpc_get_pmbase(); + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm2_cnt_blk = pmbase + PM2_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; +} diff --git a/src/southbridge/intel/common/fadt.h b/src/southbridge/intel/common/fadt.h new file mode 100644 index 0000000..48fe1cd --- /dev/null +++ b/src/southbridge/intel/common/fadt.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_FADT_H +#define SOUTHBRIDGE_INTEL_COMMON_FADT_H + +#endif /* SOUTHBRIDGE_INTEL_COMMON_FADT_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/43470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b995d526d6781d1f53c017068ed83ea46a93f32 Gerrit-Change-Number: 43470 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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