Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38313 )
Change subject: [WIP] AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
[WIP] AGESA,binaryPI boards: Drop invalid MP table files
If we spot any error in the file, treat it as untested and broken copy-paste.
Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/amd/bettong/Kconfig D src/mainboard/amd/bettong/mptable.c M src/mainboard/amd/db-ft3b-lc/Kconfig D src/mainboard/amd/db-ft3b-lc/mptable.c M src/mainboard/amd/gardenia/Kconfig D src/mainboard/amd/gardenia/mptable.c M src/mainboard/amd/inagua/Kconfig D src/mainboard/amd/inagua/mptable.c M src/mainboard/amd/lamar/Kconfig D src/mainboard/amd/lamar/mptable.c M src/mainboard/amd/olivehill/Kconfig D src/mainboard/amd/olivehill/mptable.c M src/mainboard/amd/olivehillplus/Kconfig D src/mainboard/amd/olivehillplus/mptable.c M src/mainboard/amd/parmer/Kconfig D src/mainboard/amd/parmer/mptable.c M src/mainboard/amd/persimmon/Kconfig D src/mainboard/amd/persimmon/mptable.c M src/mainboard/amd/south_station/Kconfig D src/mainboard/amd/south_station/mptable.c M src/mainboard/amd/thatcher/Kconfig D src/mainboard/amd/thatcher/mptable.c M src/mainboard/amd/union_station/Kconfig D src/mainboard/amd/union_station/mptable.c M src/mainboard/asrock/e350m1/Kconfig D src/mainboard/asrock/e350m1/mptable.c M src/mainboard/asrock/imb-a180/Kconfig D src/mainboard/asrock/imb-a180/mptable.c M src/mainboard/asus/am1i-a/Kconfig D src/mainboard/asus/am1i-a/mptable.c M src/mainboard/asus/f2a85-m/Kconfig D src/mainboard/asus/f2a85-m/mptable.c M src/mainboard/bap/ode_e20XX/Kconfig D src/mainboard/bap/ode_e20XX/mptable.c M src/mainboard/bap/ode_e21XX/Kconfig D src/mainboard/bap/ode_e21XX/mptable.c M src/mainboard/biostar/a68n_5200/Kconfig D src/mainboard/biostar/a68n_5200/mptable.c M src/mainboard/biostar/am1ml/Kconfig D src/mainboard/biostar/am1ml/mptable.c M src/mainboard/elmex/pcm205400/Kconfig D src/mainboard/elmex/pcm205400/mptable.c M src/mainboard/gizmosphere/gizmo/Kconfig D src/mainboard/gizmosphere/gizmo/mptable.c M src/mainboard/gizmosphere/gizmo2/Kconfig D src/mainboard/gizmosphere/gizmo2/mptable.c D src/mainboard/google/kahlee/mptable.c M src/mainboard/hp/abm/Kconfig D src/mainboard/hp/abm/mptable.c M src/mainboard/hp/pavilion_m6_1035dx/Kconfig D src/mainboard/hp/pavilion_m6_1035dx/mptable.c M src/mainboard/jetway/nf81-t56n-lf/Kconfig D src/mainboard/jetway/nf81-t56n-lf/mptable.c M src/mainboard/lenovo/g505s/Kconfig D src/mainboard/lenovo/g505s/mptable.c M src/mainboard/lippert/frontrunner-af/Kconfig D src/mainboard/lippert/frontrunner-af/mptable.c M src/mainboard/lippert/toucan-af/Kconfig D src/mainboard/lippert/toucan-af/mptable.c M src/mainboard/msi/ms7721/Kconfig D src/mainboard/msi/ms7721/mptable.c M src/mainboard/pcengines/apu1/Kconfig D src/mainboard/pcengines/apu1/mptable.c M src/mainboard/pcengines/apu2/Kconfig D src/mainboard/pcengines/apu2/mptable.c 65 files changed, 0 insertions(+), 4,840 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/38313/1
diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig index 4617360..50140f7 100644 --- a/src/mainboard/amd/bettong/Kconfig +++ b/src/mainboard/amd/bettong/Kconfig @@ -28,7 +28,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select GFXUMA diff --git a/src/mainboard/amd/bettong/mptable.c b/src/mainboard/amd/bettong/mptable.c deleted file mode 100644 index d9632d5..0000000 --- a/src/mainboard/amd/bettong/mptable.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/pi/hudson/hudson.h> -#include <southbridge/amd/common/amd_pci_util.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig index f17d2d3..7f24015 100644 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig +++ b/src/mainboard/amd/db-ft3b-lc/Kconfig @@ -29,7 +29,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select GFXUMA diff --git a/src/mainboard/amd/db-ft3b-lc/mptable.c b/src/mainboard/amd/db-ft3b-lc/mptable.c deleted file mode 100644 index 40a75ad..0000000 --- a/src/mainboard/amd/db-ft3b-lc/mptable.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/gardenia/Kconfig b/src/mainboard/amd/gardenia/Kconfig index e97a3ba..424a47d 100644 --- a/src/mainboard/amd/gardenia/Kconfig +++ b/src/mainboard/amd/gardenia/Kconfig @@ -21,7 +21,6 @@ select AMD_APU_STONEYRIDGE select AMD_APU_PKG_FP4 select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select GFXUMA diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c deleted file mode 100644 index 5bb70e9..0000000 --- a/src/mainboard/amd/gardenia/mptable.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <soc/southbridge.h> -#include <amdblocks/amd_pci_util.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), \ - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \ - (intr), (apicid), (pin)) - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, \ - MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \ - (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index a5ba07e..77f6b8a 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -27,7 +27,6 @@ select SUPERIO_SMSC_KBC1100 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 select GFXUMA diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c deleted file mode 100644 index b8bd0b3..0000000 --- a/src/mainboard/amd/inagua/mptable.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig index c856534..2e19c3d 100644 --- a/src/mainboard/amd/lamar/Kconfig +++ b/src/mainboard/amd/lamar/Kconfig @@ -29,7 +29,6 @@ select SUPERIO_FINTEK_F81216H select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select GFXUMA diff --git a/src/mainboard/amd/lamar/mptable.c b/src/mainboard/amd/lamar/mptable.c deleted file mode 100644 index 1f2093d..0000000 --- a/src/mainboard/amd/lamar/mptable.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> -#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h> -#include <northbridge/amd/pi/00630F01/pci_devs.h> - -#define NB_APIC_ADDR ((u8 *)0xFEC20000) - -#define PCI_INT(bus, dev, fn, apic, pin) \ - if (((pin) != 0x00) && ((pin) != 0x1F)) \ - { \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apic, (pin)); \ - } - -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - - u8 apicid_nb = (io_apic_read(NB_APIC_ADDR, 0x00) >> 24); /* Get the GNB IOAPIC ID */ - u8 apicver_nb = (io_apic_read(NB_APIC_ADDR, 0x01) & 0xFF); /* Get the GNB IOAPIC version */ - - smp_write_ioapic(mc, apicid_nb, apicver_nb, NB_APIC_ADDR); - - u8 apicid_sb = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); /* Get the southbridge IOAPIC ID */ - u8 apicver_sb = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); /* Get the southbridge IOAPIC version */ - - smp_write_ioapic(mc, apicid_sb, apicver_sb, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, apicid_nb, 0); - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, apicid_nb, intr_data_ptr[PIRQ_GFX]); - PCI_INT(0x0, 0x01, 0x1, apicid_nb, intr_data_ptr[PIRQ_ACTL]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, apicid_sb, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, apicid_sb, intr_data_ptr[PIRQ_HDA]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x5, apicid_sb, intr_data_ptr[PIRQ_OHCI4]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, apicid_sb, intr_data_ptr[PIRQ_SATA]); - - /* IDE */ - PCI_INT(0x0, 0x14, 0x1, apicid_sb, intr_data_ptr[PIRQ_IDE]); - - /* PCI slots */ - /* NB Gfx PCIe Bridges */ - PCI_INT(0, 0x2, 0x1, apicid_nb, intr_data_ptr[PIRQ_A]); - PCI_INT(0, 0x2, 0x2, apicid_nb, intr_data_ptr[PIRQ_A]); - - /* NB GPP PCIe Bridges */ - PCI_INT(0, 0x3, 0x1, apicid_nb, intr_data_ptr[PIRQ_A]); - PCI_INT(0, 0x3, 0x2, apicid_nb, intr_data_ptr[PIRQ_A]); - PCI_INT(0, 0x3, 0x3, apicid_nb, intr_data_ptr[PIRQ_A]); - PCI_INT(0, 0x3, 0x4, apicid_nb, intr_data_ptr[PIRQ_A]); - PCI_INT(0, 0x3, 0x5, apicid_nb, intr_data_ptr[PIRQ_A]); - - /* PCI slots */ - PCI_INT(0, 0x14, 0x4, apicid_sb, intr_data_ptr[PIRQ_A]); - - /* FCH GPP PCIe Bridges */ - PCI_INT(0x0, 0x15, 0x0, apicid_sb, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, apicid_sb, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, apicid_sb, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, apicid_sb, intr_data_ptr[PIRQ_A]); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 78f768f..8810c1d 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -27,7 +27,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c deleted file mode 100644 index 7082013..0000000 --- a/src/mainboard/amd/olivehill/mptable.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig index 907de3b..1745969 100644 --- a/src/mainboard/amd/olivehillplus/Kconfig +++ b/src/mainboard/amd/olivehillplus/Kconfig @@ -28,7 +28,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select GFXUMA diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c deleted file mode 100644 index 0f6ca81..0000000 --- a/src/mainboard/amd/olivehillplus/mptable.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/pi/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index ae024dd..94f55ce 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -27,7 +27,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c deleted file mode 100644 index 3a5540c..0000000 --- a/src/mainboard/amd/parmer/mptable.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index f243f0f..248e4d4 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -27,7 +27,6 @@ select SUPERIO_FINTEK_F81865F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c deleted file mode 100644 index bc7a3ac..0000000 --- a/src/mainboard/amd/persimmon/mptable.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> -#include <arch/ioapic.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); - - /* IDE */ - PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index 42841cb..0d76d50 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -27,7 +27,6 @@ select SUPERIO_FINTEK_F81865F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c deleted file mode 100644 index b8bd0b3..0000000 --- a/src/mainboard/amd/south_station/mptable.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index e556592..b79511f 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -27,7 +27,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select SUPERIO_SMSC_LPC47N217 diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c deleted file mode 100644 index 05d222a..0000000 --- a/src/mainboard/amd/thatcher/mptable.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - u8 byte; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index 1532d34..2dc82c9 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -26,7 +26,6 @@ select SOUTHBRIDGE_AMD_CIMX_SB800 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 select GFXUMA diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c deleted file mode 100644 index b8bd0b3..0000000 --- a/src/mainboard/amd/union_station/mptable.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 3bbc2a5..18058c9 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -24,7 +24,6 @@ select SB_SUPERIO_HWM select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c deleted file mode 100644 index ce8cfa0..0000000 --- a/src/mainboard/asrock/e350m1/mptable.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <stdint.h> -#include <string.h> - -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "ASROCK ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig index 8fca61c..7110c89 100644 --- a/src/mainboard/asrock/imb-a180/Kconfig +++ b/src/mainboard/asrock/imb-a180/Kconfig @@ -24,7 +24,6 @@ select SUPERIO_WINBOND_W83627UHG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c deleted file mode 100644 index 7082013..0000000 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index a0dae9f..8a7e7e9 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -10,7 +10,6 @@ select USE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB diff --git a/src/mainboard/asus/am1i-a/mptable.c b/src/mainboard/asus/am1i-a/mptable.c deleted file mode 100644 index 9efcab3..0000000 --- a/src/mainboard/asus/am1i-a/mptable.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2018 Gergely Kiss mail.gery@gmail.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_A]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_B]); - - /* GPP Ports */ - PCI_INT(0x0, 0x02, 0x0, intr_data_ptr[PIRQ_A]); - PCI_INT(0x0, 0x02, 0x1, intr_data_ptr[PIRQ_B]); - PCI_INT(0x0, 0x02, 0x2, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x02, 0x3, intr_data_ptr[PIRQ_D]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* USB */ - PCI_INT(0x0, 0x10, 0x0, intr_data_ptr[PIRQ_C]); /* XHCI */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_HDA]); - - /* PCIe slot & Onboard NIC */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_A]); - PCI_INT(0x1, 0x0, 0x1, intr_data_ptr[PIRQ_B]); - PCI_INT(0x1, 0x0, 0x2, intr_data_ptr[PIRQ_C]); - PCI_INT(0x1, 0x0, 0x3, intr_data_ptr[PIRQ_D]); - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_B]); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index c1dd063..5d5adb4 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -23,7 +23,6 @@ select SOUTHBRIDGE_AMD_AGESA_HUDSON select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select SUPERIO_ITE_IT8728F if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_LE diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c deleted file mode 100644 index b5b0433..0000000 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <cpu/x86/lapic.h> -#include <stdint.h> -#include <string.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - u8 byte; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* IOMMU */ - PCI_INT(0x0, 0x0, 0x0, 0x10); - PCI_INT(0x0, 0x0, 0x1, 0x11); - PCI_INT(0x0, 0x0, 0x2, 0x12); - PCI_INT(0x0, 0x0, 0x3, 0x13); - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index 2a72deb..6d417ed 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -28,7 +28,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA diff --git a/src/mainboard/bap/ode_e20XX/mptable.c b/src/mainboard/bap/ode_e20XX/mptable.c deleted file mode 100644 index e4edc5f..0000000 --- a/src/mainboard/bap/ode_e20XX/mptable.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); - - /* PCI_SLOT 1 */ - PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]); - - /* PCI_SLOT 2 */ - PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]); - - PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]); - PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index ff71d5b..c1b78c8 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -28,7 +28,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select GFXUMA diff --git a/src/mainboard/bap/ode_e21XX/mptable.c b/src/mainboard/bap/ode_e21XX/mptable.c deleted file mode 100644 index 0f6ca81..0000000 --- a/src/mainboard/bap/ode_e21XX/mptable.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/pi/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/biostar/a68n_5200/Kconfig b/src/mainboard/biostar/a68n_5200/Kconfig index f608513..c8d8884 100644 --- a/src/mainboard/biostar/a68n_5200/Kconfig +++ b/src/mainboard/biostar/a68n_5200/Kconfig @@ -29,7 +29,6 @@ select SUPERIO_ITE_IT8728F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA diff --git a/src/mainboard/biostar/a68n_5200/mptable.c b/src/mainboard/biostar/a68n_5200/mptable.c deleted file mode 100644 index 7082013..0000000 --- a/src/mainboard/biostar/a68n_5200/mptable.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig index 9eaa6fb..c9960e3 100644 --- a/src/mainboard/biostar/am1ml/Kconfig +++ b/src/mainboard/biostar/am1ml/Kconfig @@ -24,7 +24,6 @@ select GFXUMA select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB diff --git a/src/mainboard/biostar/am1ml/mptable.c b/src/mainboard/biostar/am1ml/mptable.c deleted file mode 100644 index 659a141..0000000 --- a/src/mainboard/biostar/am1ml/mptable.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); - - /* PCI_SLOT 1 */ - PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]); - - /* PCI_SLOT 2 */ - PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]); - - PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]); - PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]); - } - - /* PCIe Lan*/ - //PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig index e94a6d8..5892992 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig +++ b/src/mainboard/elmex/pcm205400/Kconfig @@ -39,7 +39,6 @@ select SUPERIO_FINTEK_F81865F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/elmex/pcm205400/mptable.c b/src/mainboard/elmex/pcm205400/mptable.c deleted file mode 100644 index bc7a3ac..0000000 --- a/src/mainboard/elmex/pcm205400/mptable.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> -#include <arch/ioapic.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); - - /* IDE */ - PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index e195e8f..30c88c1 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -23,7 +23,6 @@ select SOUTHBRIDGE_AMD_CIMX_SB800 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c deleted file mode 100644 index a47336c..0000000 --- a/src/mainboard/gizmosphere/gizmo/mptable.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 685e271..6a8095d 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -28,7 +28,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/gizmosphere/gizmo2/mptable.c b/src/mainboard/gizmosphere/gizmo2/mptable.c deleted file mode 100644 index e4edc5f..0000000 --- a/src/mainboard/gizmosphere/gizmo2/mptable.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); - - /* PCI_SLOT 1 */ - PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]); - - /* PCI_SLOT 2 */ - PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]); - - PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]); - PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/google/kahlee/mptable.c b/src/mainboard/google/kahlee/mptable.c deleted file mode 100644 index 5bb70e9..0000000 --- a/src/mainboard/google/kahlee/mptable.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <soc/southbridge.h> -#include <amdblocks/amd_pci_util.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), \ - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \ - (intr), (apicid), (pin)) - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, \ - MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \ - (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig index 907c025..6239086 100644 --- a/src/mainboard/hp/abm/Kconfig +++ b/src/mainboard/hp/abm/Kconfig @@ -29,7 +29,6 @@ select SUPERIO_NUVOTON_NCT5104D select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192
diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c deleted file mode 100644 index 7082013..0000000 --- a/src/mainboard/hp/abm/mptable.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index c6c35df..1f17a15 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -25,7 +25,6 @@ select EC_COMPAL_ENE932 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select HAVE_ACPI_TABLES diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c deleted file mode 100644 index ecc57b0..0000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <cpu/x86/lapic.h> -#include <stdint.h> -#include <string.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* IOMMU */ - PCI_INT(0x0, 0x00, 0x0, 0x10); - PCI_INT(0x0, 0x00, 0x1, 0x11); - PCI_INT(0x0, 0x00, 0x2, 0x12); - PCI_INT(0x0, 0x00, 0x3, 0x13); - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index dfa01b9..dddca36 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -28,7 +28,6 @@ select SUPERIO_FINTEK_F71869AD select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c deleted file mode 100644 index 9a983b4..0000000 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2014 Edward O'Callaghan eocallaghan@alterapraxis.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <drivers/generic/ioapic/chip.h> -#include <stdint.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); - - /* IDE */ - PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* On-board NIC & Slot PCIE. */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - } - - /* On-board Realtek NIC 2. (PCIe PortA) */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 6ffe508..7f0d7bf 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -24,7 +24,6 @@ select DEFAULT_POST_ON_LPC select EC_COMPAL_ENE932 select HAVE_OPTION_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c deleted file mode 100644 index ecc57b0..0000000 --- a/src/mainboard/lenovo/g505s/mptable.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <cpu/x86/lapic.h> -#include <stdint.h> -#include <string.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* IOMMU */ - PCI_INT(0x0, 0x00, 0x0, 0x10); - PCI_INT(0x0, 0x00, 0x1, 0x11); - PCI_INT(0x0, 0x00, 0x2, 0x12); - PCI_INT(0x0, 0x00, 0x3, 0x13); - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index 4a007bf..64a8f14 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -27,7 +27,6 @@ select SUPERIO_SMSC_SMSCSUPERIO select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE # This erases 28 KB and writes 10 KB register dumps to SPI flash on every # boot, wasting 3 s and causing wear! Therefore disable S3 for now. #select HAVE_ACPI_RESUME diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c deleted file mode 100644 index 78b8ec2..0000000 --- a/src/mainboard/lippert/frontrunner-af/mptable.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index b62da2e..e97099b 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -29,7 +29,6 @@ select SUPERIO_WINBOND_W83627DHG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE # This erases 28 KB and writes 10 KB register dumps to SPI flash on every # boot, wasting 3 s and causing wear! Therefore disable S3 for now. #select HAVE_ACPI_RESUME diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c deleted file mode 100644 index 78b8ec2..0000000 --- a/src/mainboard/lippert/toucan-af/mptable.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/msi/ms7721/Kconfig b/src/mainboard/msi/ms7721/Kconfig index 1fee747..b57bc48 100644 --- a/src/mainboard/msi/ms7721/Kconfig +++ b/src/mainboard/msi/ms7721/Kconfig @@ -25,7 +25,6 @@ select SOUTHBRIDGE_AMD_AGESA_HUDSON select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select SUPERIO_FINTEK_F71869AD select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/msi/ms7721/mptable.c b/src/mainboard/msi/ms7721/mptable.c deleted file mode 100644 index fd55eda..0000000 --- a/src/mainboard/msi/ms7721/mptable.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <cpu/x86/lapic.h> -#include <stdint.h> -#include <string.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* IOMMU */ - PCI_INT(0x0, 0x0, 0x0, 0x10); - PCI_INT(0x0, 0x0, 0x1, 0x11); - PCI_INT(0x0, 0x0, 0x2, 0x12); - PCI_INT(0x0, 0x0, 0x3, 0x13); - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 3396845..9871051 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -23,7 +23,6 @@ select SOUTHBRIDGE_AMD_CIMX_SB800 select SUPERIO_NUVOTON_NCT5104D select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/pcengines/apu1/mptable.c b/src/mainboard/pcengines/apu1/mptable.c deleted file mode 100644 index 89e5dfc..0000000 --- a/src/mainboard/pcengines/apu1/mptable.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> -#include <arch/ioapic.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); - - /* IDE */ - PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - PCI_INT(0x3, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - PCI_INT(0x4, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 8c713e5..604d490 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -26,7 +26,6 @@ select DEFAULT_POST_ON_LPC select SUPERIO_NUVOTON_NCT5104D select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select USE_BLOBS diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c deleted file mode 100644 index 772ee31..0000000 --- a/src/mainboard/pcengines/apu2/mptable.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <southbridge/amd/common/amd_pci_util.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* SD card */ - PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_SD]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); - - - /* GPP0 */ - PCI_INT(0x0, 0x2, 0x0, 0x10); // Network 3 - /* GPP1 */ - PCI_INT(0x0, 0x2, 0x1, 0x11); // Network 2 - /* GPP2 */ - PCI_INT(0x0, 0x2, 0x2, 0x12); // Network 1 - /* GPP3 */ - PCI_INT(0x0, 0x2, 0x3, 0x13); // mPCI - /* GPP4 */ - PCI_INT(0x0, 0x2, 0x4, 0x14); // mPCI - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -}
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38313 )
Change subject: [WIP] AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 1: Code-Review-2
Let's flag the errors or invalid PCI device references.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38313 )
Change subject: [WIP] AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 1: Code-Review+1
Hmm, I like the idea
Hello Alexander Couzens, Patrick Rudolph, Piotr Król, Angel Pons, build bot (Jenkins), Michał Żygowski,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38313
to look at the new patch set (#2).
Change subject: [WIP] AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
[WIP] AGESA,binaryPI boards: Drop invalid MP table files
If we spot any error in the file, treat it as untested and broken copy-paste.
Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/amd/bettong/Kconfig D src/mainboard/amd/bettong/mptable.c M src/mainboard/amd/db-ft3b-lc/Kconfig D src/mainboard/amd/db-ft3b-lc/mptable.c M src/mainboard/amd/gardenia/Kconfig D src/mainboard/amd/gardenia/mptable.c M src/mainboard/amd/inagua/Kconfig D src/mainboard/amd/inagua/mptable.c M src/mainboard/amd/lamar/Kconfig D src/mainboard/amd/lamar/mptable.c M src/mainboard/amd/olivehill/Kconfig D src/mainboard/amd/olivehill/mptable.c M src/mainboard/amd/olivehillplus/Kconfig D src/mainboard/amd/olivehillplus/mptable.c M src/mainboard/amd/parmer/Kconfig D src/mainboard/amd/parmer/mptable.c M src/mainboard/amd/persimmon/Kconfig D src/mainboard/amd/persimmon/mptable.c M src/mainboard/amd/south_station/Kconfig D src/mainboard/amd/south_station/mptable.c M src/mainboard/amd/thatcher/Kconfig D src/mainboard/amd/thatcher/mptable.c M src/mainboard/amd/union_station/Kconfig D src/mainboard/amd/union_station/mptable.c M src/mainboard/asrock/e350m1/Kconfig D src/mainboard/asrock/e350m1/mptable.c M src/mainboard/asrock/imb-a180/Kconfig D src/mainboard/asrock/imb-a180/mptable.c M src/mainboard/asus/am1i-a/Kconfig D src/mainboard/asus/am1i-a/mptable.c M src/mainboard/asus/f2a85-m/Kconfig D src/mainboard/asus/f2a85-m/mptable.c M src/mainboard/bap/ode_e20XX/Kconfig D src/mainboard/bap/ode_e20XX/mptable.c M src/mainboard/bap/ode_e21XX/Kconfig D src/mainboard/bap/ode_e21XX/mptable.c M src/mainboard/biostar/a68n_5200/Kconfig D src/mainboard/biostar/a68n_5200/mptable.c M src/mainboard/biostar/am1ml/Kconfig D src/mainboard/biostar/am1ml/mptable.c M src/mainboard/elmex/pcm205400/Kconfig D src/mainboard/elmex/pcm205400/mptable.c M src/mainboard/gizmosphere/gizmo/Kconfig D src/mainboard/gizmosphere/gizmo/mptable.c M src/mainboard/gizmosphere/gizmo2/Kconfig D src/mainboard/gizmosphere/gizmo2/mptable.c D src/mainboard/google/kahlee/mptable.c M src/mainboard/hp/abm/Kconfig D src/mainboard/hp/abm/mptable.c M src/mainboard/hp/pavilion_m6_1035dx/Kconfig D src/mainboard/hp/pavilion_m6_1035dx/mptable.c M src/mainboard/jetway/nf81-t56n-lf/Kconfig D src/mainboard/jetway/nf81-t56n-lf/mptable.c M src/mainboard/lenovo/g505s/Kconfig D src/mainboard/lenovo/g505s/mptable.c M src/mainboard/lippert/frontrunner-af/Kconfig D src/mainboard/lippert/frontrunner-af/mptable.c M src/mainboard/lippert/toucan-af/Kconfig D src/mainboard/lippert/toucan-af/mptable.c M src/mainboard/msi/ms7721/Kconfig D src/mainboard/msi/ms7721/mptable.c M src/mainboard/pcengines/apu1/Kconfig D src/mainboard/pcengines/apu1/mptable.c M src/mainboard/pcengines/apu2/Kconfig D src/mainboard/pcengines/apu2/mptable.c 65 files changed, 0 insertions(+), 4,840 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/38313/2
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38313 )
Change subject: [WIP] AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 3:
Seems to be a merge conflict
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38313 )
Change subject: [WIP] AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 3:
Patch Set 3:
Seems to be a merge conflict
so what?
Hello Alexander Couzens, Patrick Rudolph, Piotr Król, Angel Pons, build bot (Jenkins), Michał Żygowski,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38313
to look at the new patch set (#4).
Change subject: [WIP] AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
[WIP] AGESA,binaryPI boards: Drop invalid MP table files
If we spot any error in the file, treat it as untested and broken copy-paste.
Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/amd/bettong/Kconfig D src/mainboard/amd/bettong/mptable.c M src/mainboard/amd/db-ft3b-lc/Kconfig D src/mainboard/amd/db-ft3b-lc/mptable.c M src/mainboard/amd/gardenia/Kconfig D src/mainboard/amd/gardenia/mptable.c M src/mainboard/amd/inagua/Kconfig D src/mainboard/amd/inagua/mptable.c M src/mainboard/amd/lamar/Kconfig D src/mainboard/amd/lamar/mptable.c M src/mainboard/amd/olivehill/Kconfig D src/mainboard/amd/olivehill/mptable.c M src/mainboard/amd/olivehillplus/Kconfig D src/mainboard/amd/olivehillplus/mptable.c M src/mainboard/amd/parmer/Kconfig D src/mainboard/amd/parmer/mptable.c M src/mainboard/amd/persimmon/Kconfig D src/mainboard/amd/persimmon/mptable.c M src/mainboard/amd/south_station/Kconfig D src/mainboard/amd/south_station/mptable.c M src/mainboard/amd/thatcher/Kconfig D src/mainboard/amd/thatcher/mptable.c M src/mainboard/amd/union_station/Kconfig D src/mainboard/amd/union_station/mptable.c M src/mainboard/asrock/e350m1/Kconfig D src/mainboard/asrock/e350m1/mptable.c M src/mainboard/asrock/imb-a180/Kconfig D src/mainboard/asrock/imb-a180/mptable.c M src/mainboard/asus/am1i-a/Kconfig D src/mainboard/asus/am1i-a/mptable.c M src/mainboard/asus/f2a85-m/Kconfig D src/mainboard/asus/f2a85-m/mptable.c M src/mainboard/bap/ode_e20XX/Kconfig D src/mainboard/bap/ode_e20XX/mptable.c M src/mainboard/bap/ode_e21XX/Kconfig D src/mainboard/bap/ode_e21XX/mptable.c M src/mainboard/biostar/a68n_5200/Kconfig D src/mainboard/biostar/a68n_5200/mptable.c M src/mainboard/biostar/am1ml/Kconfig D src/mainboard/biostar/am1ml/mptable.c M src/mainboard/elmex/pcm205400/Kconfig D src/mainboard/elmex/pcm205400/mptable.c M src/mainboard/gizmosphere/gizmo/Kconfig D src/mainboard/gizmosphere/gizmo/mptable.c M src/mainboard/gizmosphere/gizmo2/Kconfig D src/mainboard/gizmosphere/gizmo2/mptable.c D src/mainboard/google/kahlee/mptable.c M src/mainboard/hp/abm/Kconfig D src/mainboard/hp/abm/mptable.c M src/mainboard/hp/pavilion_m6_1035dx/Kconfig D src/mainboard/hp/pavilion_m6_1035dx/mptable.c M src/mainboard/jetway/nf81-t56n-lf/Kconfig D src/mainboard/jetway/nf81-t56n-lf/mptable.c M src/mainboard/lenovo/g505s/Kconfig D src/mainboard/lenovo/g505s/mptable.c M src/mainboard/lippert/frontrunner-af/Kconfig D src/mainboard/lippert/frontrunner-af/mptable.c M src/mainboard/lippert/toucan-af/Kconfig D src/mainboard/lippert/toucan-af/mptable.c M src/mainboard/msi/ms7721/Kconfig D src/mainboard/msi/ms7721/mptable.c M src/mainboard/pcengines/apu1/Kconfig D src/mainboard/pcengines/apu1/mptable.c M src/mainboard/pcengines/apu2/Kconfig D src/mainboard/pcengines/apu2/mptable.c 65 files changed, 0 insertions(+), 4,842 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/38313/4
Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/38313 )
Change subject: [WIP] AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Abandoned
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38313 )
Change subject: [WIP] AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 4:
I'm going to pick it up a bit later...
Attention is currently required from: Mike Banon. Kyösti Mälkki has restored this change. ( https://review.coreboot.org/c/coreboot/+/38313 )
Change subject: [WIP] AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Restored
Attention is currently required from: Mike Banon. Hello build bot (Jenkins), Michał Żygowski, Angel Pons, Alexander Couzens, Patrick Rudolph, Piotr Król,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38313
to look at the new patch set (#5).
Change subject: [WIP] AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
[WIP] AGESA,binaryPI boards: Drop invalid MP table files
If we spot any error in the file, treat it as untested and broken copy-paste.
Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/amd/gardenia/Kconfig D src/mainboard/amd/gardenia/mptable.c M src/mainboard/amd/inagua/Kconfig D src/mainboard/amd/inagua/mptable.c M src/mainboard/amd/olivehill/Kconfig D src/mainboard/amd/olivehill/mptable.c M src/mainboard/amd/parmer/Kconfig D src/mainboard/amd/parmer/mptable.c M src/mainboard/amd/persimmon/Kconfig D src/mainboard/amd/persimmon/mptable.c M src/mainboard/amd/south_station/Kconfig D src/mainboard/amd/south_station/mptable.c M src/mainboard/amd/thatcher/Kconfig D src/mainboard/amd/thatcher/mptable.c M src/mainboard/amd/union_station/Kconfig D src/mainboard/amd/union_station/mptable.c M src/mainboard/asrock/e350m1/Kconfig D src/mainboard/asrock/e350m1/mptable.c M src/mainboard/asrock/imb-a180/Kconfig D src/mainboard/asrock/imb-a180/mptable.c M src/mainboard/asus/am1i-a/Kconfig D src/mainboard/asus/am1i-a/mptable.c M src/mainboard/asus/f2a85-m/Kconfig D src/mainboard/asus/f2a85-m/mptable.c M src/mainboard/bap/ode_e20XX/Kconfig D src/mainboard/bap/ode_e20XX/mptable.c M src/mainboard/biostar/a68n_5200/Kconfig D src/mainboard/biostar/a68n_5200/mptable.c M src/mainboard/biostar/am1ml/Kconfig D src/mainboard/biostar/am1ml/mptable.c M src/mainboard/elmex/pcm205400/Kconfig D src/mainboard/elmex/pcm205400/mptable.c M src/mainboard/gizmosphere/gizmo/Kconfig D src/mainboard/gizmosphere/gizmo/mptable.c M src/mainboard/gizmosphere/gizmo2/Kconfig D src/mainboard/gizmosphere/gizmo2/mptable.c D src/mainboard/google/kahlee/mptable.c M src/mainboard/hp/abm/Kconfig D src/mainboard/hp/abm/mptable.c M src/mainboard/hp/pavilion_m6_1035dx/Kconfig D src/mainboard/hp/pavilion_m6_1035dx/mptable.c M src/mainboard/jetway/nf81-t56n-lf/Kconfig D src/mainboard/jetway/nf81-t56n-lf/mptable.c M src/mainboard/lenovo/g505s/Kconfig D src/mainboard/lenovo/g505s/mptable.c M src/mainboard/lippert/frontrunner-af/Kconfig D src/mainboard/lippert/frontrunner-af/mptable.c M src/mainboard/msi/ms7721/Kconfig D src/mainboard/msi/ms7721/mptable.c M src/mainboard/pcengines/apu1/Kconfig D src/mainboard/pcengines/apu1/mptable.c M src/mainboard/pcengines/apu2/Kconfig D src/mainboard/pcengines/apu2/mptable.c 53 files changed, 0 insertions(+), 3,586 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/38313/5
Attention is currently required from: Mike Banon, Kyösti Mälkki. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38313 )
Change subject: [WIP] AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 5: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/38313/comment/88cfff31_42a03012 PS5, Line 9: error Could you please provide examples of errors in the dropped tables?
Attention is currently required from: Mike Banon, Angel Pons. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38313 )
Change subject: [WIP] AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 5:
(58 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/38313/comment/f263fab1_c710e274 PS5, Line 9: error
Could you please provide examples of errors in the dropped tables?
Done
File src/mainboard/amd/gardenia/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/a78c9042_e97536bd PS5, Line 99: /* PCI slots */ legacy pci?
https://review.coreboot.org/c/coreboot/+/38313/comment/4a149dd1_8d12f055 PS5, Line 122: /* PCIe Lan*/ Not even with sb800 / fam14 generation?
https://review.coreboot.org/c/coreboot/+/38313/comment/bbc3f12a_e1a26613 PS5, Line 125: /* FCH PCIe PortA */ No docs, but I suspect not at 0:15.0 listed below.
File src/mainboard/amd/olivehill/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/99c6467a_4c6ff35c PS5, Line 95: /* PCI slots */ ?
https://review.coreboot.org/c/coreboot/+/38313/comment/83ea2538_be80ee65 PS5, Line 118: /* PCIe Lan*/ ?
File src/mainboard/amd/parmer/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/fc979e02_6c9bd037 PS5, Line 116: /* PCIe Lan*/ ?
File src/mainboard/amd/persimmon/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/6ce5c512_9e3854b1 PS5, Line 81: /* IDE */ ?
https://review.coreboot.org/c/coreboot/+/38313/comment/e619d132_add8a9f0 PS5, Line 89: PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ Should not use static number for PCI buses.
File src/mainboard/amd/thatcher/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/74a31ff4_5b487f29 PS5, Line 117: /* PCIe Lan*/ ?
File src/mainboard/asrock/e350m1/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/e0c1b974_9ff09e4f PS5, Line 68: /* PCI slots */ AFAIR, none
File src/mainboard/asrock/imb-a180/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/e986a92e_65b65bee PS5, Line 95: /* PCI slots */ none
https://review.coreboot.org/c/coreboot/+/38313/comment/5ca88202_96ef8dad PS5, Line 118: /* PCIe Lan*/ Bus 0, so would be internal LAN, not existing.
File src/mainboard/asus/am1i-a/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/7e8d2d61_1d463bf9 PS5, Line 90: PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_B]); Using static numbers for PCI buses.
File src/mainboard/asus/f2a85-m/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/956b11ec_b3ff0122 PS5, Line 99: /* PCI slots */ From what I remember, there were 1-3 slots depending of board variant.
https://review.coreboot.org/c/coreboot/+/38313/comment/8026e971_6fa98b07 PS5, Line 110: /* PCIe Lan*/ Bus 0, internal non-existing
File src/mainboard/bap/ode_e20XX/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/cab7c4b5_a19b5ac6 PS5, Line 87: PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); Uses static number for PCI bus
https://review.coreboot.org/c/coreboot/+/38313/comment/0bd284d0_a16a1a98 PS5, Line 89: /* PCI slots */ I doubt it
https://review.coreboot.org/c/coreboot/+/38313/comment/290c71e5_afd45fd7 PS5, Line 116: /* PCIe Lan*/ Hmm... no?
File src/mainboard/biostar/a68n_5200/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/8f089a14_855835ed PS5, Line 95: /* PCI slots */ I doubt it
https://review.coreboot.org/c/coreboot/+/38313/comment/69a91872_7b8b1566 PS5, Line 118: /* PCIe Lan*/ No ?
File src/mainboard/biostar/am1ml/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/a6449b98_206f38db PS5, Line 68: PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); Duplicate 0:14.2 with OHCI4 ?
https://review.coreboot.org/c/coreboot/+/38313/comment/6c1269ef_e3fe4538 PS5, Line 80: PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); Duplicate 0:14.2 with HDA ?
https://review.coreboot.org/c/coreboot/+/38313/comment/86d6f5be_0e41057f PS5, Line 87: PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); Uses static PCI bus number
https://review.coreboot.org/c/coreboot/+/38313/comment/f73cfc80_a75f9f03 PS5, Line 89: /* PCI slots */ I doubt it
File src/mainboard/elmex/pcm205400/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/46ee5efa_32aeda21 PS5, Line 81: /* IDE */ I doubt it
https://review.coreboot.org/c/coreboot/+/38313/comment/051972d6_924db3bc PS5, Line 89: PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ Use static PCI bus number
File src/mainboard/gizmosphere/gizmo/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/ad159d78_7905fb95 PS5, Line 68: /* PCI slots */ none
File src/mainboard/gizmosphere/gizmo2/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/e53cb2c0_3eda3fd6 PS5, Line 87: PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); static PCI bus number
https://review.coreboot.org/c/coreboot/+/38313/comment/a1e0a30b_6d2ff7dd PS5, Line 89: /* PCI slots */ none
https://review.coreboot.org/c/coreboot/+/38313/comment/585ea099_aaa29dcb PS5, Line 116: /* PCIe Lan*/ no internal
File src/mainboard/google/kahlee/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/86326b09_8e184ff9 PS5, Line 82: PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); Duplicate 0:14.0.
https://review.coreboot.org/c/coreboot/+/38313/comment/2dc49074_a7ece99f PS5, Line 95: PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); Duplicate 0:11.0?
https://review.coreboot.org/c/coreboot/+/38313/comment/8308fab7_66ddde30 PS5, Line 99: /* PCI slots */ none most likely
https://review.coreboot.org/c/coreboot/+/38313/comment/4f1f414c_917e6f78 PS5, Line 122: /* PCIe Lan*/ Internal, not since 2012?
File src/mainboard/hp/abm/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/b8751d5f_08527867 PS5, Line 78: PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); Duplicate 0:14.0
https://review.coreboot.org/c/coreboot/+/38313/comment/d3180838_ae685670 PS5, Line 91: PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); Duplicate 0:11.0
https://review.coreboot.org/c/coreboot/+/38313/comment/70dc013d_77357604 PS5, Line 95: /* PCI slots */ I doubt it
https://review.coreboot.org/c/coreboot/+/38313/comment/68d0b138_8b5b91ca PS5, Line 118: /* PCIe Lan*/ None
File src/mainboard/hp/pavilion_m6_1035dx/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/881e3230_4b5f44eb PS5, Line 82: PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); Duplicate 0:14.0
https://review.coreboot.org/c/coreboot/+/38313/comment/beed24c1_928c40b7 PS5, Line 95: PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); Duplicate 0:11.0
https://review.coreboot.org/c/coreboot/+/38313/comment/97261c86_8162cd98 PS5, Line 99: /* PCI slots */ Wow, laptop and 3 PCI legacy slots?
https://review.coreboot.org/c/coreboot/+/38313/comment/e3b926ef_bb0c1589 PS5, Line 122: /* PCIe Lan*/ no
File src/mainboard/jetway/nf81-t56n-lf/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/2e7f1fd5_e62982cd PS5, Line 81: /* IDE */ I doubt it
https://review.coreboot.org/c/coreboot/+/38313/comment/de761444_484b2cb2 PS5, Line 89: PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ Static PCI numbers.
File src/mainboard/lenovo/g505s/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/b4522015_3ebe19b0 PS5, Line 82: PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); Duplicate 0:14.0
https://review.coreboot.org/c/coreboot/+/38313/comment/06f57d05_cc073f3b PS5, Line 95: PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); Duplicate 0:11.0
https://review.coreboot.org/c/coreboot/+/38313/comment/8f7dfff3_2824c501 PS5, Line 99: /* PCI slots */ none
https://review.coreboot.org/c/coreboot/+/38313/comment/ec3051ee_b9bba419 PS5, Line 122: /* PCIe Lan*/ Internal, none.
File src/mainboard/lippert/frontrunner-af/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/dd4abd54_06f716f2 PS5, Line 67: /* PCI slots */ Some of this might even be correct. It's PC104+ form factor so bit hard to tell or test.
File src/mainboard/msi/ms7721/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/1e43c114_67e09537 PS5, Line 82: PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); Duplicate 0:14.0
https://review.coreboot.org/c/coreboot/+/38313/comment/ec341c24_4cac4ac6 PS5, Line 95: PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); Duplicate 0:11.0
https://review.coreboot.org/c/coreboot/+/38313/comment/da3b6289_e504b4b9 PS5, Line 110: /* PCIe Lan*/ no
File src/mainboard/pcengines/apu1/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/47b523e5_3da8a7c9 PS5, Line 61: /* APU Internal Graphic Device */ No graphics
https://review.coreboot.org/c/coreboot/+/38313/comment/938a4c60_04fc7cf6 PS5, Line 68: /* Southbridge HD Audio */ Could be disabled, audio pins are not routed?
https://review.coreboot.org/c/coreboot/+/38313/comment/25c9e53d_f85f896a PS5, Line 81: /* IDE */ No
https://review.coreboot.org/c/coreboot/+/38313/comment/1a320e52_ee3fe298 PS5, Line 91: PCI_INT(0x4, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ Static PCI bus numbers.
File src/mainboard/pcengines/apu2/mptable.c:
https://review.coreboot.org/c/coreboot/+/38313/comment/eb12c1fe_cad597e5 PS5, Line 80: PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); Static PCI bus numbers.
Attention is currently required from: Mike Banon, Kyösti Mälkki. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38313 )
Change subject: [WIP] AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/38313/comment/6375a32d_609af2ec PS5, Line 9: error
Done
Thanks!
Attention is currently required from: Mike Banon. Hello build bot (Jenkins), Michał Żygowski, Angel Pons, Alexander Couzens, Patrick Rudolph, Piotr Król,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38313
to look at the new patch set (#6).
Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
AGESA,binaryPI boards: Drop invalid MP table files
If we spot any error in the file, treat it as untested and broken copy-paste.
Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/amd/gardenia/Kconfig D src/mainboard/amd/gardenia/mptable.c M src/mainboard/amd/inagua/Kconfig D src/mainboard/amd/inagua/mptable.c M src/mainboard/amd/olivehill/Kconfig D src/mainboard/amd/olivehill/mptable.c M src/mainboard/amd/parmer/Kconfig D src/mainboard/amd/parmer/mptable.c M src/mainboard/amd/persimmon/Kconfig D src/mainboard/amd/persimmon/mptable.c M src/mainboard/amd/south_station/Kconfig D src/mainboard/amd/south_station/mptable.c M src/mainboard/amd/thatcher/Kconfig D src/mainboard/amd/thatcher/mptable.c M src/mainboard/amd/union_station/Kconfig D src/mainboard/amd/union_station/mptable.c M src/mainboard/asrock/e350m1/Kconfig D src/mainboard/asrock/e350m1/mptable.c M src/mainboard/asrock/imb-a180/Kconfig D src/mainboard/asrock/imb-a180/mptable.c M src/mainboard/asus/am1i-a/Kconfig D src/mainboard/asus/am1i-a/mptable.c M src/mainboard/asus/f2a85-m/Kconfig D src/mainboard/asus/f2a85-m/mptable.c M src/mainboard/bap/ode_e20XX/Kconfig D src/mainboard/bap/ode_e20XX/mptable.c M src/mainboard/biostar/a68n_5200/Kconfig D src/mainboard/biostar/a68n_5200/mptable.c M src/mainboard/biostar/am1ml/Kconfig D src/mainboard/biostar/am1ml/mptable.c M src/mainboard/elmex/pcm205400/Kconfig D src/mainboard/elmex/pcm205400/mptable.c M src/mainboard/gizmosphere/gizmo/Kconfig D src/mainboard/gizmosphere/gizmo/mptable.c M src/mainboard/gizmosphere/gizmo2/Kconfig D src/mainboard/gizmosphere/gizmo2/mptable.c D src/mainboard/google/kahlee/mptable.c M src/mainboard/hp/abm/Kconfig D src/mainboard/hp/abm/mptable.c M src/mainboard/hp/pavilion_m6_1035dx/Kconfig D src/mainboard/hp/pavilion_m6_1035dx/mptable.c M src/mainboard/jetway/nf81-t56n-lf/Kconfig D src/mainboard/jetway/nf81-t56n-lf/mptable.c M src/mainboard/lenovo/g505s/Kconfig D src/mainboard/lenovo/g505s/mptable.c M src/mainboard/lippert/frontrunner-af/Kconfig D src/mainboard/lippert/frontrunner-af/mptable.c M src/mainboard/msi/ms7721/Kconfig D src/mainboard/msi/ms7721/mptable.c M src/mainboard/pcengines/apu1/Kconfig D src/mainboard/pcengines/apu1/mptable.c M src/mainboard/pcengines/apu2/Kconfig D src/mainboard/pcengines/apu2/mptable.c 53 files changed, 0 insertions(+), 3,593 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/38313/6
Attention is currently required from: Mike Banon. Kyösti Mälkki has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/38313 )
Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Removed Code-Review-2 by Kyösti Mälkki kyosti.malkki@gmail.com
Attention is currently required from: Mike Banon, Marshall Dawson, Kyösti Mälkki, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38313 )
Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 6: Code-Review+1
Attention is currently required from: Mike Banon, Marshall Dawson, Kyösti Mälkki, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38313 )
Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6: The Linux kernel, for example Debian’s 5.10.13, and self-built Linux 5.12-rc0, are unable to initialize the SSD connected over S-ATA.
``` [ 0.004860] __common_interrupt: 1.55 No irq handler for vector [ 0.244118] PCI: After pci_direct_probe [ 0.244534] PCI: After pci_probe [ 0.245533] PCI: After 2nd if [ 0.246657] PCI: After pci_pcbios_init [ 0.247541] PCI: After dmi_check [ 0.248526] PCI: After isa_align [ 0.356947] ata_host_alloc: ENTER [ 0.360341] ata_port_alloc: ENTER [ 0.363739] ata_port_alloc: ENTER [ 0.367193] ata_port_alloc: ENTER [ 0.370562] ata_port_alloc: ENTER [ 0.373932] ata_port_alloc: ENTER [ 0.377303] ata_port_alloc: ENTER [ 0.380911] __ata_port_freeze: ata4294967295 port frozen [ 0.386406] __ata_port_freeze: ata4294967295 port frozen [ 0.391905] __ata_port_freeze: ata4294967295 port frozen [ 0.397395] __ata_port_freeze: ata4294967295 port frozen [ 0.402889] __ata_port_freeze: ata4294967295 port frozen [ 0.408386] __ata_port_freeze: ata4294967295 port frozen [ 0.417856] ata_std_sched_eh: port EH scheduled [ 0.422550] ata_scsi_error: ENTER [ 0.425924] ata_eh_link_autopsy: ENTER [ 0.429732] ata_eh_recover: ENTER [ 0.433110] __ata_port_freeze: ata1 port frozen [ 0.437696] ahci_do_hardreset: ENTER [ 0.441328] sata_link_hardreset: ENTER [ 0.445133] ata_dev_classify: found ATA device by sig [ 0.445137] ahci_do_hardreset: EXIT, rc=0, class=1 [ 0.445143] ahci_pmp_retry_softreset: ENTER [ 0.455095] ahci_do_softreset: ENTER [ 0.455155] ata_std_sched_eh: port EH scheduled [ 0.462967] ata_scsi_error: ENTER [ 0.470968] ata_eh_link_autopsy: ENTER [ 0.474838] ata_eh_recover: ENTER [ 0.478208] __ata_port_freeze: ata2 port frozen [ 0.482791] ahci_do_hardreset: ENTER [ 0.486417] sata_link_hardreset: ENTER [ 0.486458] ata_std_sched_eh: port EH scheduled [ 0.490225] ata_dev_classify: unknown device [ 0.494806] ata_scsi_error: ENTER [ 0.499119] ahci_do_hardreset: EXIT, rc=0, class=0 [ 0.507330] ata_eh_thaw_port: ata2 port thawed [ 0.507581] ata_std_sched_eh: port EH scheduled [ 0.511825] ata_std_postreset: ENTER [ 0.516403] ata_scsi_error: ENTER [ 0.523394] ata_std_postreset: EXIT [ 0.526579] ata_std_sched_eh: port EH scheduled [ 0.531516] ata_scsi_error: ENTER [ 0.531518] ata_eh_revalidate_and_attach: ENTER [ 0.535608] ata_std_sched_eh: port EH scheduled [ 0.539459] ata_eh_recover: EXIT, rc=0 [ 0.547843] ata_scsi_error: EXIT [ 0.551130] ata_scsi_error: ENTER [ 0.551135] ata_eh_link_autopsy: ENTER [ 0.558306] ata_eh_recover: ENTER [ 0.561673] __ata_port_freeze: ata6 port frozen [ 0.566264] ahci_do_hardreset: ENTER [ 0.569896] sata_link_hardreset: ENTER [ 0.573717] ata_dev_classify: unknown device [ 0.578049] ahci_do_hardreset: EXIT, rc=0, class=0 [ 0.582906] ata_eh_thaw_port: ata6 port thawed [ 0.587415] ata_std_postreset: ENTER [ 0.591065] ata_std_postreset: EXIT [ 0.594621] ata_eh_revalidate_and_attach: ENTER [ 0.594625] ata_eh_recover: EXIT, rc=0 [ 0.603022] ata_scsi_error: EXIT [ 0.606306] ata_eh_link_autopsy: ENTER [ 0.610114] ata_eh_recover: ENTER [ 0.613485] __ata_port_freeze: ata5 port frozen [ 0.618079] ahci_do_hardreset: ENTER [ 0.621710] sata_link_hardreset: ENTER [ 0.625523] ata_dev_classify: unknown device [ 0.629845] ahci_do_hardreset: EXIT, rc=0, class=0 [ 0.634693] ata_eh_thaw_port: ata5 port thawed [ 0.634696] ata_std_postreset: ENTER [ 0.634706] ata_std_postreset: EXIT [ 0.634711] ata_eh_revalidate_and_attach: ENTER [ 0.634713] ata_eh_recover: EXIT, rc=0 [ 0.634728] ata_scsi_error: EXIT [ 0.639221] ata_eh_link_autopsy: ENTER [ 0.661841] ata_eh_recover: ENTER [ 0.665217] __ata_port_freeze: ata4 port frozen [ 0.669803] ahci_do_hardreset: ENTER [ 0.673435] sata_link_hardreset: ENTER [ 0.677243] ata_dev_classify: unknown device [ 0.681560] ahci_do_hardreset: EXIT, rc=0, class=0 [ 0.686412] ata_eh_thaw_port: ata4 port thawed [ 0.690906] ata_std_postreset: ENTER [ 0.694549] ata_std_postreset: EXIT [ 0.698094] ata_eh_revalidate_and_attach: ENTER [ 0.702675] ata_eh_recover: EXIT, rc=0 [ 0.706491] ata_scsi_error: EXIT [ 0.706584] ata_eh_link_autopsy: ENTER [ 0.713583] ata_eh_recover: ENTER [ 0.716955] __ata_port_freeze: ata3 port frozen [ 0.721548] ahci_do_hardreset: ENTER [ 0.725180] sata_link_hardreset: ENTER [ 0.728986] ata_dev_classify: unknown device [ 0.733305] ahci_do_hardreset: EXIT, rc=0, class=0 [ 0.738155] ata_eh_thaw_port: ata3 port thawed [ 0.742648] ata_std_postreset: ENTER [ 0.746280] ata_std_postreset: EXIT [ 0.749825] ata_eh_revalidate_and_attach: ENTER [ 0.754407] ata_eh_recover: EXIT, rc=0 [ 0.758216] ata_scsi_error: EXIT [ 0.765638] ata_dev_classify: found ATA device by sig [ 0.770801] ahci_do_softreset: EXIT, class=1 [ 0.775150] ata_eh_thaw_port: ata1 port thawed [ 0.779652] ata_std_postreset: ENTER [ 0.783297] ata_std_postreset: EXIT [ 0.786842] ata_eh_revalidate_and_attach: ENTER [ 5.723709] __ata_port_freeze: ata1 port frozen [ 5.728404] ata_eh_revalidate_and_attach: EXIT rc=-5 [ 5.733430] __ata_port_freeze: ata1 port frozen [ 5.738010] ahci_do_hardreset: ENTER [ 5.741644] sata_link_hardreset: ENTER [ 5.745449] ata_dev_classify: found ATA device by sig [ 5.750550] ahci_do_hardreset: EXIT, rc=0, class=1 [ 5.755399] ahci_pmp_retry_softreset: ENTER [ 5.759633] ahci_do_softreset: ENTER [ 5.767693] ata_dev_classify: found ATA device by sig [ 5.772824] ahci_do_softreset: EXIT, class=1 [ 5.777156] ata_eh_thaw_port: ata1 port thawed [ 5.781658] ata_std_postreset: ENTER [ 5.785298] ata_std_postreset: EXIT [ 5.788850] ata_eh_revalidate_and_attach: ENTER ```
Attention is currently required from: Mike Banon, Marshall Dawson, Kyösti Mälkki, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38313 )
Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 6: Code-Review+1
(1 comment)
Patchset:
PS6: Sorry, wrong alarm. This seems to be something else on my system.
Attention is currently required from: Mike Banon, Marshall Dawson, Kyösti Mälkki, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38313 )
Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/asrock/e350m1/mptable.c:
PS5: Good old times:
1. [[coreboot] PIC instead of APIC mode for KolibriOS - mouse fix](https://mail.coreboot.org/pipermail/coreboot/2014-May/077913.html) 2. [[coreboot] PIC instead of APIC mode for KolibriOS - mouse fix](https://mail.coreboot.org/pipermail/coreboot/2014-May/077942.html)
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Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 6: Code-Review+1
(1 comment)
Patchset:
PS6: i'd also assume that the mptables aren't valid for most of the boards. on the picasso/cezanne boards i already removed the mptables, since they were both stale and basically unused. don't have a too strong opinion on the boards in this patch though
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Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6: If the MPTABLEs for ASUS AM1I-A, A88XM-E and Lenovo G505S are to be removed (and no auto-generation for them introduced), they could be replaced with much better MPTABLEs from my "good IRQs" not-merged-yet patches. Maybe I could also help Paul to fix the MPTABLE for his Asrock E350M1 board, since the MPTABLEs are important for the "old-style OS" like KolibriOS and there's a good patch for his board.
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Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
If the MPTABLEs for ASUS AM1I-A, A88XM-E and Lenovo G505S are to be removed (and no auto-generation […]
It would be great if you could document how to create a correct MP table for a given mainboard, and how to test it.
Another idea: AFAIUI, the interrupt mapping in the MP tables is the same as that in DSDT. Describe the mapping once, and derive the MP tables and DSDT ACPI code from that mapping. You would need to use acpigen. Ideally, mainboards would only define the interrupt mapping, and chipset or more generic code would generate both tables.
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Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 7: Code-Review-1
(1 comment)
Patchset:
PS7: The broken mptables are a problem only for the hobby OSes like Kolibri: since the more sophisticated OSes like Linux are working perfectly. Meanwhile, removing the broken mptables completely - is reducing a likehood of someone fixing them, since (in terms of a workflow) it is much easier to remove stuff than to research and find a suitable place to inject it. So let the broken tables be - and those who care enough (i.e. about the hobby OSes) will fix them for their boards.
Kyosti, I highly value your work at the other directions, but sorry for the reasons above I can't support this particular patch.
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Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
The broken mptables are a problem only for the hobby OSes like Kolibri: since the more sophisticated […]
Discussion in progress...
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Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS6:
It would be great if you could document how to create a correct MP table for a given mainboard, and how to test it.
A good starting point is these messages (search a coreboot mailing list archive by "banon irq") https://mail.coreboot.org/hyperkitty/search?q=banon+irq&page=1&mlist... . After looking through them, temporarily flash a proprietary UEFI BIOS to your board and use a getpir utility mentioned at "https://mail.coreboot.org/hyperkitty/search?mlist=coreboot%40coreboot.org&am..." to produce the initial version of PIRQ tables, then do the lspci commands - and compare this initial PIRQ and lspci's properties of your board against the successful "a88xm-e / am1i-a / g505s".
There's a relation between the PIRQ tables, ACPI IRQ routing and MPTABLEs, so after you'll produce the initial version of PIRQ irq_tables.c - by looking at the successful examples above and the differences between the boards - it's just a matter of time to update all this stuff accordingly for it to match each other and to be suitable for your board.
Verification could be done by a hobby OS like Kolibri: if you see that the IRQs got successfully assigned to the devices and they are working, it's safe to assume you did everything correctly for them - otherwise, if some device is problematic (doesn't work in Kolibri and maybe makes a Linux kernel to print some angry messages at dmesg kernel log), change its' PIRQ / ACPI IRQ routing / MPTABLE of this device and test again.
Doing it right for g505s took me 1 month only because there weren't any good examples except am1i-a which was also far from being perfect. But after that, a88xm-e took just a couple of days and one more day to go back to fix am1i-a using this experience.
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Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS6:
It would be great if you could document how to create a correct MP table for a given mainboard, an […]
Mike, also note CB:47081. All AGESA and binaryPI are to be depreated with May 2021 release unless someone adressed "Resource allocator v3" as identified with 4.13 release notes. Apparently, it should be less work than ROMCC bootblock deprecations were.
This commit describes some of the obvious semantical issues that should be solved for boards whose MPTABLE are to be maintained_ If I am not mistaken, for Kolibri OS you add both PIRQ table and MP table -- you should not need both, do you know exactly whice one you test for?
There is also the chance KolibriOS does not utilise either of those, but picks up IRQ assignments from PCI configuration space only.
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Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS6:
also note CB:47081
Are you sure this is a correct ID? Sorry if I misunderstood but it tells "Abandoned - Done differently". Regarding the upgrade from resource allocator v3 to v4 and newer:
I tried getting v4 work with CB:41431 shortly after the v4 has been suddenly merged into master for all the boards (forcing the AMD ones to fail booting). This successfully fixed the boot problems of fam15tn A88XM-E with v4 but failed to fix a fam16kb AM1I-A. So maybe it was a correct approach, but it's needed that someone with a deeper understanding than mine takes a look and fixes.
KolibriOS definitely uses some tables, considering by that - when they were very wrong before - a half of the stuff didn't work and fixing the tables helped to get it working. Although it's not just about Kolibri: if some legacy OS may need an MPTABLE, I'd like to let the MPTABLEs stay.
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Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS6:
also note CB:47081 […]
Should have been CB:47801
These two IRQ patches were offered to you to continue with in January 2020. You returned to the topic several months later and changed the approach from fixing the implementation to working around it, likely adding even more undesirable redundancy across the tables.
So you have a niche/obsolete feature and bugfixes for couple boards you have. When such bugfixes jeopardize the proper fix across those older AMD platforms, your chances to get your work merged are slim, I would say. In short; I don't plan to rebase my work on yours, and there is no indication of you willing to rebase your work on mine either. What do you want to do?
Nobody is saying MP tables could not be supported. That's why most of the were already reviewed for existing and obvious flaws. You're not telling with certainty that MP tables are even the ones you test for.
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Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 7: Code-Review+2
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Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS6:
When such bugfixes jeopardize the proper fix across those older AMD platforms
Sorry I just don't understand, how the existence of MP tables is preventing the required (by May 2021 release) progress for v4 allocator? While trying CB:41431 I didn't have to touch them at all?
You're not telling with certainty that MP tables are even the ones you test for.
Since I've been fixing all this stuff (MP tables, PIRQ tables and ACPI routing) simultaneously & in accordance to each other, I don't know what of them are important for Kolibri. Guess I can try applying CB:48427 but with MPTables removed - and see what happens to Kolibri without them
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Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS6:
When such bugfixes jeopardize the proper fix across those older AMD platforms
Sorry I just don't understand, how the existence of MP tables is preventing the required (by May 2021 release) progress for v4 allocator? While trying CB:41431 I didn't have to touch them at all?
My reference to "such bugfixes" did not cover any allocator related work you may have as open patches, just the recently rebased IRQ patches. And CB:41431 is indeed the topic with some urgency, currently you should be driving that to completion instead of trying to push niche Legacy OS support things.
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Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 8:
(2 comments)
Patchset:
PS6:
When such bugfixes jeopardize the proper fix across those older AMD platforms […]
I am done with discussion, raise a new unresolved comment if you feel so.
Patchset:
PS7:
Discussion in progress...
I am done with discussion, raise a new unresolved comment if you feel so.
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Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS6:
I am done with discussion, raise a new unresolved comment if you feel so.
I will re-test Kolibri with MPTables dropped and report the results here, to fully resolve this issue. Will be done ASAP
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Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/38313/comment/43ce024c_85d90e7b PS8, Line 10: broken copy-paste. Is there any AGESA board with a valid MP table file? Maybe add that summary to the commit message.
There is currently no board with a valid MP table.
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Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/38313/comment/4013f99f_44c87ef5 PS8, Line 10: broken copy-paste.
Is there any AGESA board with a valid MP table file? Maybe add that summary to the commit message. […]
I believe that my not-merged-yet CB:48161, CB:48424 and CB:48605 have the valid MP tables for g505s, a88xm-e and am1i-a respectively - but at the current coreboot master, there are no AGESA boards with a valid MP tables judging by my prior research (otherwise it would have been easier).
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Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/38313/comment/3af23c90_40a5931e PS8, Line 10: broken copy-paste.
I believe that my not-merged-yet CB:48161, CB:48424 and CB:48605 have the valid MP tables for g505s, […]
Sooo, if no AGESA board has a valid MP table... I'd drop all broken MP tables, and then you can re-add correct and tested MP tables for individual boards. Would this work for you?
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Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
Patch Set 8: Code-Review+2
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/38313/comment/283a2c49_ad4fa92d PS8, Line 10: broken copy-paste.
Sooo, if no AGESA board has a valid MP table... […]
Great idea, thank you a lot, this is a right approach. And the patches mentioned by Paul:
1. [[coreboot] PIC instead of APIC mode for KolibriOS - mouse fix](https://mail.coreboot.org/pipermail/coreboot/2014-May/077913.html) 2. [[coreboot] PIC instead of APIC mode for KolibriOS - mouse fix](https://mail.coreboot.org/pipermail/coreboot/2014-May/077942.html)
- these pci_write_config32 could be moved from a patch's mptable.c to another file like mainboard.c
Patchset:
PS6:
I will re-test Kolibri with MPTables dropped and report the results here, to fully resolve this issu […]
Kolibri and other floppy OS from my CB:33509 collection - are still working fine even without MP tables, i.e. Kolibri still sees the interrupts and USB is working good.
Patchset:
PS8: Considering the new findings (see comments below), it's safe to +2
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38313 )
Change subject: AGESA,binaryPI boards: Drop invalid MP table files ......................................................................
AGESA,binaryPI boards: Drop invalid MP table files
If we spot any error in the file, treat it as untested and broken copy-paste.
Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38313 Reviewed-by: Mike Banon mikebdp2@gmail.com Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Felix Held felix-coreboot@felixheld.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/amd/gardenia/Kconfig D src/mainboard/amd/gardenia/mptable.c M src/mainboard/amd/inagua/Kconfig D src/mainboard/amd/inagua/mptable.c M src/mainboard/amd/olivehill/Kconfig D src/mainboard/amd/olivehill/mptable.c M src/mainboard/amd/parmer/Kconfig D src/mainboard/amd/parmer/mptable.c M src/mainboard/amd/persimmon/Kconfig D src/mainboard/amd/persimmon/mptable.c M src/mainboard/amd/south_station/Kconfig D src/mainboard/amd/south_station/mptable.c M src/mainboard/amd/thatcher/Kconfig D src/mainboard/amd/thatcher/mptable.c M src/mainboard/amd/union_station/Kconfig D src/mainboard/amd/union_station/mptable.c M src/mainboard/asrock/e350m1/Kconfig D src/mainboard/asrock/e350m1/mptable.c M src/mainboard/asrock/imb-a180/Kconfig D src/mainboard/asrock/imb-a180/mptable.c M src/mainboard/asus/am1i-a/Kconfig D src/mainboard/asus/am1i-a/mptable.c M src/mainboard/asus/f2a85-m/Kconfig D src/mainboard/asus/f2a85-m/mptable.c M src/mainboard/bap/ode_e20XX/Kconfig D src/mainboard/bap/ode_e20XX/mptable.c M src/mainboard/biostar/a68n_5200/Kconfig D src/mainboard/biostar/a68n_5200/mptable.c M src/mainboard/biostar/am1ml/Kconfig D src/mainboard/biostar/am1ml/mptable.c M src/mainboard/elmex/pcm205400/Kconfig D src/mainboard/elmex/pcm205400/mptable.c M src/mainboard/gizmosphere/gizmo/Kconfig D src/mainboard/gizmosphere/gizmo/mptable.c M src/mainboard/gizmosphere/gizmo2/Kconfig D src/mainboard/gizmosphere/gizmo2/mptable.c D src/mainboard/google/kahlee/mptable.c M src/mainboard/hp/abm/Kconfig D src/mainboard/hp/abm/mptable.c M src/mainboard/hp/pavilion_m6_1035dx/Kconfig D src/mainboard/hp/pavilion_m6_1035dx/mptable.c M src/mainboard/jetway/nf81-t56n-lf/Kconfig D src/mainboard/jetway/nf81-t56n-lf/mptable.c M src/mainboard/lenovo/g505s/Kconfig D src/mainboard/lenovo/g505s/mptable.c M src/mainboard/lippert/frontrunner-af/Kconfig D src/mainboard/lippert/frontrunner-af/mptable.c M src/mainboard/msi/ms7721/Kconfig D src/mainboard/msi/ms7721/mptable.c M src/mainboard/pcengines/apu1/Kconfig D src/mainboard/pcengines/apu1/mptable.c M src/mainboard/pcengines/apu2/Kconfig D src/mainboard/pcengines/apu2/mptable.c 53 files changed, 0 insertions(+), 3,593 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Felix Held: Looks good to me, but someone else must approve Mike Banon: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/amd/gardenia/Kconfig b/src/mainboard/amd/gardenia/Kconfig index a77aa69..94c098b 100644 --- a/src/mainboard/amd/gardenia/Kconfig +++ b/src/mainboard/amd/gardenia/Kconfig @@ -8,7 +8,6 @@ select AMD_APU_STONEYRIDGE select AMD_APU_PKG_FP4 select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select GFXUMA diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c deleted file mode 100644 index 6460fed..0000000 --- a/src/mainboard/amd/gardenia/mptable.c +++ /dev/null @@ -1,148 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <soc/southbridge.h> -#include <amdblocks/amd_pci_util.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), \ - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \ - (intr), (apicid), (pin)) - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, \ - MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \ - (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index 6dcc9f1..5cca387 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -10,7 +10,6 @@ select SUPERIO_SMSC_KBC1100 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 select GFXUMA diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c deleted file mode 100644 index df3452a..0000000 --- a/src/mainboard/amd/inagua/mptable.c +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include <southbridge/amd/common/amd_pci_util.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 3a0c98e..e56200b 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -10,7 +10,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c deleted file mode 100644 index 5555a33..0000000 --- a/src/mainboard/amd/olivehill/mptable.c +++ /dev/null @@ -1,144 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index 204e497..ce2f95d 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -10,7 +10,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c deleted file mode 100644 index 5e8f9f1..0000000 --- a/src/mainboard/amd/parmer/mptable.c +++ /dev/null @@ -1,142 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 4e92313..ae68fce 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -10,7 +10,6 @@ select SUPERIO_FINTEK_F81865F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c deleted file mode 100644 index 2784c3e..0000000 --- a/src/mainboard/amd/persimmon/mptable.c +++ /dev/null @@ -1,128 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/smp/mpspec.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> -#include <arch/ioapic.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); - - /* IDE */ - PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index d2dd0fb..5a0ac8b 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -10,7 +10,6 @@ select SUPERIO_FINTEK_F81865F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c deleted file mode 100644 index df3452a..0000000 --- a/src/mainboard/amd/south_station/mptable.c +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include <southbridge/amd/common/amd_pci_util.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index c0cc712..95dc8f0 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -10,7 +10,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select SUPERIO_SMSC_LPC47N217 diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c deleted file mode 100644 index 5e8f9f1..0000000 --- a/src/mainboard/amd/thatcher/mptable.c +++ /dev/null @@ -1,142 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index d4f1495..a92b47b 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -9,7 +9,6 @@ select SOUTHBRIDGE_AMD_CIMX_SB800 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 select GFXUMA diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c deleted file mode 100644 index df3452a..0000000 --- a/src/mainboard/amd/union_station/mptable.c +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include <southbridge/amd/common/amd_pci_util.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 091d57a..3616d2d 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -11,7 +11,6 @@ select SB_SUPERIO_HWM select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c deleted file mode 100644 index 53e2817..0000000 --- a/src/mainboard/asrock/e350m1/mptable.c +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <stdint.h> -#include <string.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "ASROCK ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig index 4d9b1e8..9879b81 100644 --- a/src/mainboard/asrock/imb-a180/Kconfig +++ b/src/mainboard/asrock/imb-a180/Kconfig @@ -11,7 +11,6 @@ select SUPERIO_WINBOND_W83627UHG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c deleted file mode 100644 index 5555a33..0000000 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ /dev/null @@ -1,144 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index 172d808..78948b2 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -10,7 +10,6 @@ select USE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB diff --git a/src/mainboard/asus/am1i-a/mptable.c b/src/mainboard/asus/am1i-a/mptable.c deleted file mode 100644 index cd72ca3..0000000 --- a/src/mainboard/asus/am1i-a/mptable.c +++ /dev/null @@ -1,109 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_A]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_B]); - - /* GPP Ports */ - PCI_INT(0x0, 0x02, 0x0, intr_data_ptr[PIRQ_A]); - PCI_INT(0x0, 0x02, 0x1, intr_data_ptr[PIRQ_B]); - PCI_INT(0x0, 0x02, 0x2, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x02, 0x3, intr_data_ptr[PIRQ_D]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* USB */ - PCI_INT(0x0, 0x10, 0x0, intr_data_ptr[PIRQ_C]); /* XHCI */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_HDA]); - - /* PCIe slot & Onboard NIC */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_A]); - PCI_INT(0x1, 0x0, 0x1, intr_data_ptr[PIRQ_B]); - PCI_INT(0x1, 0x0, 0x2, intr_data_ptr[PIRQ_C]); - PCI_INT(0x1, 0x0, 0x3, intr_data_ptr[PIRQ_D]); - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_B]); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index 326fedd9..6a57263 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -9,7 +9,6 @@ select SOUTHBRIDGE_AMD_AGESA_HUDSON select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select SUPERIO_ITE_IT8728F if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_LE diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c deleted file mode 100644 index 8f7fa5d..0000000 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ /dev/null @@ -1,136 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <stdint.h> -#include <string.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* IOMMU */ - PCI_INT(0x0, 0x0, 0x0, 0x10); - PCI_INT(0x0, 0x0, 0x1, 0x11); - PCI_INT(0x0, 0x0, 0x2, 0x12); - PCI_INT(0x0, 0x0, 0x3, 0x13); - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index bea756a..7e9e583 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -10,7 +10,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA diff --git a/src/mainboard/bap/ode_e20XX/mptable.c b/src/mainboard/bap/ode_e20XX/mptable.c deleted file mode 100644 index c0ad4ed..0000000 --- a/src/mainboard/bap/ode_e20XX/mptable.c +++ /dev/null @@ -1,145 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); - - /* PCI_SLOT 1 */ - PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]); - - /* PCI_SLOT 2 */ - PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]); - - PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]); - PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/biostar/a68n_5200/Kconfig b/src/mainboard/biostar/a68n_5200/Kconfig index 506d6ba..14c7e6d 100644 --- a/src/mainboard/biostar/a68n_5200/Kconfig +++ b/src/mainboard/biostar/a68n_5200/Kconfig @@ -10,7 +10,6 @@ select SUPERIO_ITE_IT8728F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA diff --git a/src/mainboard/biostar/a68n_5200/mptable.c b/src/mainboard/biostar/a68n_5200/mptable.c deleted file mode 100644 index 5555a33..0000000 --- a/src/mainboard/biostar/a68n_5200/mptable.c +++ /dev/null @@ -1,144 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig index de2b85d..e550bfc 100644 --- a/src/mainboard/biostar/am1ml/Kconfig +++ b/src/mainboard/biostar/am1ml/Kconfig @@ -10,7 +10,6 @@ select GFXUMA select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB diff --git a/src/mainboard/biostar/am1ml/mptable.c b/src/mainboard/biostar/am1ml/mptable.c deleted file mode 100644 index 41e70b9..0000000 --- a/src/mainboard/biostar/am1ml/mptable.c +++ /dev/null @@ -1,145 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); - - /* PCI_SLOT 1 */ - PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]); - - /* PCI_SLOT 2 */ - PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]); - - PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]); - PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]); - } - - /* PCIe Lan*/ - //PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig index 6eed3d7..e9c2ac4 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig +++ b/src/mainboard/elmex/pcm205400/Kconfig @@ -22,7 +22,6 @@ select SUPERIO_FINTEK_F81865F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/elmex/pcm205400/mptable.c b/src/mainboard/elmex/pcm205400/mptable.c deleted file mode 100644 index 2784c3e..0000000 --- a/src/mainboard/elmex/pcm205400/mptable.c +++ /dev/null @@ -1,128 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/smp/mpspec.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> -#include <arch/ioapic.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); - - /* IDE */ - PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index 19d9190..5bf296e 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -9,7 +9,6 @@ select SOUTHBRIDGE_AMD_CIMX_SB800 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c deleted file mode 100644 index a155c84..0000000 --- a/src/mainboard/gizmosphere/gizmo/mptable.c +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 6375bc4..9337290 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -10,7 +10,6 @@ select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/gizmosphere/gizmo2/mptable.c b/src/mainboard/gizmosphere/gizmo2/mptable.c deleted file mode 100644 index c0ad4ed..0000000 --- a/src/mainboard/gizmosphere/gizmo2/mptable.c +++ /dev/null @@ -1,145 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); - - /* PCI_SLOT 1 */ - PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]); - PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]); - - /* PCI_SLOT 2 */ - PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]); - PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]); - PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]); - PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]); - - PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]); - PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/google/kahlee/mptable.c b/src/mainboard/google/kahlee/mptable.c deleted file mode 100644 index 6460fed..0000000 --- a/src/mainboard/google/kahlee/mptable.c +++ /dev/null @@ -1,148 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <soc/southbridge.h> -#include <amdblocks/amd_pci_util.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), \ - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \ - (intr), (apicid), (pin)) - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, \ - MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \ - (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig index ce8ecee..495254b 100644 --- a/src/mainboard/hp/abm/Kconfig +++ b/src/mainboard/hp/abm/Kconfig @@ -11,7 +11,6 @@ select SUPERIO_NUVOTON_NCT5104D select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192
diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c deleted file mode 100644 index 5555a33..0000000 --- a/src/mainboard/hp/abm/mptable.c +++ /dev/null @@ -1,144 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index 77c929f..0262362 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -12,7 +12,6 @@ select EC_COMPAL_ENE932 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select HAVE_ACPI_TABLES diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c deleted file mode 100644 index 3ff707d..0000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c +++ /dev/null @@ -1,148 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <stdint.h> -#include <string.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* IOMMU */ - PCI_INT(0x0, 0x00, 0x0, 0x10); - PCI_INT(0x0, 0x00, 0x1, 0x11); - PCI_INT(0x0, 0x00, 0x2, 0x12); - PCI_INT(0x0, 0x00, 0x3, 0x13); - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index eebf7af..2e28784 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -10,7 +10,6 @@ select SUPERIO_FINTEK_F71869AD select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c deleted file mode 100644 index dd055ec..0000000 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ /dev/null @@ -1,128 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <drivers/generic/ioapic/chip.h> -#include <stdint.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); - - /* IDE */ - PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* On-board NIC & Slot PCIE. */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - } - - /* On-board Realtek NIC 2. (PCIe PortA) */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 322d3a7..e6278af 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -11,7 +11,6 @@ select DEFAULT_POST_ON_LPC select EC_COMPAL_ENE932 select HAVE_OPTION_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c deleted file mode 100644 index 3ff707d..0000000 --- a/src/mainboard/lenovo/g505s/mptable.c +++ /dev/null @@ -1,148 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <stdint.h> -#include <string.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* IOMMU */ - PCI_INT(0x0, 0x00, 0x0, 0x10); - PCI_INT(0x0, 0x00, 0x1, 0x11); - PCI_INT(0x0, 0x00, 0x2, 0x12); - PCI_INT(0x0, 0x00, 0x3, 0x13); - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index 3c38e27..0bf8ccf 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -13,7 +13,6 @@ select SUPERIO_WINBOND_W83627DHG if BOARD_LIPPERT_TOUCAN_AF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE # This erases 28 KB and writes 10 KB register dumps to SPI flash on every # boot, wasting 3 s and causing wear! Therefore disable S3 for now. #select HAVE_ACPI_RESUME diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c deleted file mode 100644 index d948cd0..0000000 --- a/src/mainboard/lippert/frontrunner-af/mptable.c +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include <southbridge/amd/common/amd_pci_util.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/msi/ms7721/Kconfig b/src/mainboard/msi/ms7721/Kconfig index fe7c9ed..a4834ee 100644 --- a/src/mainboard/msi/ms7721/Kconfig +++ b/src/mainboard/msi/ms7721/Kconfig @@ -9,7 +9,6 @@ select SOUTHBRIDGE_AMD_AGESA_HUDSON select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select SUPERIO_FINTEK_F71869AD select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/msi/ms7721/mptable.c b/src/mainboard/msi/ms7721/mptable.c deleted file mode 100644 index 8f7fa5d..0000000 --- a/src/mainboard/msi/ms7721/mptable.c +++ /dev/null @@ -1,136 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <stdint.h> -#include <string.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* IOMMU */ - PCI_INT(0x0, 0x0, 0x0, 0x10); - PCI_INT(0x0, 0x0, 0x1, 0x11); - PCI_INT(0x0, 0x0, 0x2, 0x12); - PCI_INT(0x0, 0x0, 0x3, 0x13); - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 04019d2..2c6e657 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -9,7 +9,6 @@ select SOUTHBRIDGE_AMD_CIMX_SB800 select SUPERIO_NUVOTON_NCT5104D select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/pcengines/apu1/mptable.c b/src/mainboard/pcengines/apu1/mptable.c deleted file mode 100644 index 52aca2e..0000000 --- a/src/mainboard/pcengines/apu1/mptable.c +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/smp/mpspec.h> -#include <stdint.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <drivers/generic/ioapic/chip.h> -#include <arch/ioapic.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* Southbridge HD Audio */ - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - - /* LPC */ - PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); - - /* IDE */ - PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - PCI_INT(0x3, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - PCI_INT(0x4, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index fde7340..875c01c 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -11,7 +11,6 @@ select DEFAULT_POST_ON_LPC select SUPERIO_NUVOTON_NCT5104D select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select HAVE_SPD_IN_CBFS diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c deleted file mode 100644 index a24863f..0000000 --- a/src/mainboard/pcengines/apu2/mptable.c +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> -#include <northbridge/amd/nb_common.h> -#include <southbridge/amd/common/amd_pci_util.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* Initialize the MP_Table */ - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - /* - * Type 0: Processor Entries: - * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, - * CPU Signature (Stepping, Model, Family), - * Feature Flags - */ - smp_write_processors(mc); - - /* - * Type 1: Bus Entries: - * Bus ID, Bus Type - */ - mptable_write_buses(mc, NULL, &bus_isa); - - /* - * Type 2: I/O APICs: - * APIC ID, Version, APIC Flags:EN, Address - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - ioapic_id = (io_apic_read((void *)IO_APIC2_ADDR, 0x00) >> 24); - ioapic_ver = (io_apic_read((void *)IO_APIC2_ADDR, 0x01) & 0xFF); - - smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC2_ADDR); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - /* - * Type 3: I/O Interrupt Table Entries: - * Int Type, Int Polarity, Int Level, Source Bus ID, - * Source Bus IRQ, Dest APIC ID, Dest PIN# - */ - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* SMBUS / ACPI */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); - - /* SD card */ - PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_SD]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); - - /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); - - /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); - - /* GPP0 */ - PCI_INT(0x0, 0x2, 0x0, 0x10); // Network 3 - /* GPP1 */ - PCI_INT(0x0, 0x2, 0x1, 0x11); // Network 2 - /* GPP2 */ - PCI_INT(0x0, 0x2, 0x2, 0x12); // Network 1 - /* GPP3 */ - PCI_INT(0x0, 0x2, 0x3, 0x13); // mPCI - /* GPP4 */ - PCI_INT(0x0, 0x2, 0x4, 0x14); // mPCI - - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ - return (unsigned long)smp_write_config_table(v); -}
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