coreboot-gerrit September 2020

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Change in coreboot[master]: lib/Makefile.inc: Enable UBSAN on SMM, too
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43976 ) Change subject: lib/Makefile.inc: Enable UBSAN on SMM, too ...................................................................... lib/Makefile.inc: Enable UBSAN on SMM, too We don't want undefined behavior on such privileged code, do we? Change-Id: I24f4c074ff90365cf96abf1f5bad3e2cde68547d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/lib/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/43976/1 diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 72d4f24..c96aa90 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -4,7 +4,9 @@ ifeq ($(CONFIG_UBSAN),y) ramstage-y += ubsan.c +smm-y += ubsan.c CFLAGS_ramstage += -fsanitize=undefined +CFLAGS_smm += -fsanitize=undefined endif decompressor-y += decompressor.c -- To view, visit https://review.coreboot.org/c/coreboot/+/43976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24f4c074ff90365cf96abf1f5bad3e2cde68547d Gerrit-Change-Number: 43976 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sandybridge boards: Drop gpio.c from bootblock
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45671 ) Change subject: sandybridge boards: Drop gpio.c from bootblock ...................................................................... sandybridge boards: Drop gpio.c from bootblock It is only used in romstage. Also update autoport. Change-Id: If6508997ce5b266d1fbf2aac56b22a8b542ae7b1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/apple/macbookair4_2/Makefile.inc M src/mainboard/asrock/b75pro3-m/Makefile.inc M src/mainboard/asus/h61m-cs/Makefile.inc M src/mainboard/asus/maximus_iv_gene-z/Makefile.inc M src/mainboard/asus/p8h61-m_lx/Makefile.inc M src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc M src/mainboard/asus/p8h61-m_pro/Makefile.inc M src/mainboard/asus/p8z77-m_pro/Makefile.inc M src/mainboard/asus/p8z77-v_lx2/Makefile.inc M src/mainboard/biostar/th61-itx/Makefile.inc M src/mainboard/compulab/intense_pc/Makefile.inc M src/mainboard/dell/optiplex_9010/Makefile.inc M src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc M src/mainboard/gigabyte/ga-h61m-series/Makefile.inc M src/mainboard/google/butterfly/Makefile.inc M src/mainboard/google/link/Makefile.inc M src/mainboard/google/parrot/Makefile.inc M src/mainboard/google/stout/Makefile.inc M src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc M src/mainboard/hp/snb_ivb_laptops/Makefile.inc M src/mainboard/hp/z220_sff_workstation/Makefile.inc M src/mainboard/intel/dcp847ske/Makefile.inc M src/mainboard/intel/emeraldlake2/Makefile.inc M src/mainboard/kontron/ktqm77/Makefile.inc M src/mainboard/lenovo/l520/Makefile.inc M src/mainboard/lenovo/s230u/Makefile.inc M src/mainboard/lenovo/t420/Makefile.inc M src/mainboard/lenovo/t420s/Makefile.inc M src/mainboard/lenovo/t430/Makefile.inc M src/mainboard/lenovo/t430s/Makefile.inc M src/mainboard/lenovo/t520/Makefile.inc M src/mainboard/lenovo/t530/Makefile.inc M src/mainboard/lenovo/x131e/Makefile.inc M src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc M src/mainboard/lenovo/x220/Makefile.inc M src/mainboard/lenovo/x230/Makefile.inc M src/mainboard/msi/ms7707/Makefile.inc M src/mainboard/roda/rv11/Makefile.inc M src/mainboard/samsung/lumpy/Makefile.inc M src/mainboard/samsung/stumpy/Makefile.inc M src/mainboard/sapphire/pureplatinumh61/Makefile.inc M src/mainboard/supermicro/x9scl/Makefile.inc M util/autoport/bd82x6x.go 43 files changed, 0 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/45671/1 diff --git a/src/mainboard/apple/macbookair4_2/Makefile.inc b/src/mainboard/apple/macbookair4_2/Makefile.inc index 665a95f..ab64c56 100644 --- a/src/mainboard/apple/macbookair4_2/Makefile.inc +++ b/src/mainboard/apple/macbookair4_2/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += gnvs.c diff --git a/src/mainboard/asrock/b75pro3-m/Makefile.inc b/src/mainboard/asrock/b75pro3-m/Makefile.inc index e4b6fbf..a6025c2 100644 --- a/src/mainboard/asrock/b75pro3-m/Makefile.inc +++ b/src/mainboard/asrock/b75pro3-m/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/h61m-cs/Makefile.inc b/src/mainboard/asus/h61m-cs/Makefile.inc index f0b34f9..3e0a0fa 100644 --- a/src/mainboard/asus/h61m-cs/Makefile.inc +++ b/src/mainboard/asus/h61m-cs/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c diff --git a/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc b/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc index e09d538..db6dc1d 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc +++ b/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c diff --git a/src/mainboard/asus/p8h61-m_lx/Makefile.inc b/src/mainboard/asus/p8h61-m_lx/Makefile.inc index e09d538..db6dc1d 100644 --- a/src/mainboard/asus/p8h61-m_lx/Makefile.inc +++ b/src/mainboard/asus/p8h61-m_lx/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc b/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc index 7167e10..45d063e 100644 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc @@ -1,5 +1,4 @@ bootblock-y += early_init.c -bootblock-y += gpio.c romstage-y += early_init.c romstage-y += gpio.c diff --git a/src/mainboard/asus/p8h61-m_pro/Makefile.inc b/src/mainboard/asus/p8h61-m_pro/Makefile.inc index e402ffa..ec8df11 100644 --- a/src/mainboard/asus/p8h61-m_pro/Makefile.inc +++ b/src/mainboard/asus/p8h61-m_pro/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p8z77-m_pro/Makefile.inc b/src/mainboard/asus/p8z77-m_pro/Makefile.inc index 26b20d7..b04939b 100644 --- a/src/mainboard/asus/p8z77-m_pro/Makefile.inc +++ b/src/mainboard/asus/p8z77-m_pro/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p8z77-v_lx2/Makefile.inc b/src/mainboard/asus/p8z77-v_lx2/Makefile.inc index 7167e10..45d063e 100644 --- a/src/mainboard/asus/p8z77-v_lx2/Makefile.inc +++ b/src/mainboard/asus/p8z77-v_lx2/Makefile.inc @@ -1,5 +1,4 @@ bootblock-y += early_init.c -bootblock-y += gpio.c romstage-y += early_init.c romstage-y += gpio.c diff --git a/src/mainboard/biostar/th61-itx/Makefile.inc b/src/mainboard/biostar/th61-itx/Makefile.inc index 549a84f..5d34b89 100644 --- a/src/mainboard/biostar/th61-itx/Makefile.inc +++ b/src/mainboard/biostar/th61-itx/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += hda_verb.c diff --git a/src/mainboard/compulab/intense_pc/Makefile.inc b/src/mainboard/compulab/intense_pc/Makefile.inc index e402ffa..ec8df11 100644 --- a/src/mainboard/compulab/intense_pc/Makefile.inc +++ b/src/mainboard/compulab/intense_pc/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/optiplex_9010/Makefile.inc b/src/mainboard/dell/optiplex_9010/Makefile.inc index 7a8a684..9c21731 100644 --- a/src/mainboard/dell/optiplex_9010/Makefile.inc +++ b/src/mainboard/dell/optiplex_9010/Makefile.inc @@ -2,7 +2,6 @@ smm-y += smihandler.c -bootblock-y += gpio.c romstage-y += gpio.c bootblock-y += early_init.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc index 5dcf9e2..f1265f4 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads diff --git a/src/mainboard/gigabyte/ga-h61m-series/Makefile.inc b/src/mainboard/gigabyte/ga-h61m-series/Makefile.inc index 9916927..0f0fd22 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/Makefile.inc +++ b/src/mainboard/gigabyte/ga-h61m-series/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc index 342c9f7..1ca07da 100644 --- a/src/mainboard/google/butterfly/Makefile.inc +++ b/src/mainboard/google/butterfly/Makefile.inc @@ -4,7 +4,6 @@ romstage-y += chromeos.c ramstage-y += chromeos.c -bootblock-y += gpio.c romstage-y += gpio.c smm-y += mainboard_smi.c diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index ee411c2..eec3fcc 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -13,7 +13,6 @@ SPD_SOURCES += samsung_4Gb_1600_1.35v_x16 SPD_SOURCES += micron_4Gb_1600_1.35v_x16 -bootblock-y += gpio.c romstage-y += gpio.c bootblock-y += early_init.c romstage-y += early_init.c diff --git a/src/mainboard/google/parrot/Makefile.inc b/src/mainboard/google/parrot/Makefile.inc index f2166e1..70c3922 100644 --- a/src/mainboard/google/parrot/Makefile.inc +++ b/src/mainboard/google/parrot/Makefile.inc @@ -4,7 +4,6 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc index 5c196f0..3f7ef94 100644 --- a/src/mainboard/google/stout/Makefile.inc +++ b/src/mainboard/google/stout/Makefile.inc @@ -9,7 +9,6 @@ smm-y += ec.c SRC_ROOT = $(src)/mainboard/google/stout -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc b/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc index f0b34f9..3e0a0fa 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc +++ b/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c diff --git a/src/mainboard/hp/snb_ivb_laptops/Makefile.inc b/src/mainboard/hp/snb_ivb_laptops/Makefile.inc index c007bb6..c743a26 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Makefile.inc +++ b/src/mainboard/hp/snb_ivb_laptops/Makefile.inc @@ -2,7 +2,6 @@ bootblock-y += variants/$(VARIANT_DIR)/early_init.c romstage-y += variants/$(VARIANT_DIR)/early_init.c -bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads diff --git a/src/mainboard/hp/z220_sff_workstation/Makefile.inc b/src/mainboard/hp/z220_sff_workstation/Makefile.inc index f0b34f9..3e0a0fa 100644 --- a/src/mainboard/hp/z220_sff_workstation/Makefile.inc +++ b/src/mainboard/hp/z220_sff_workstation/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c diff --git a/src/mainboard/intel/dcp847ske/Makefile.inc b/src/mainboard/intel/dcp847ske/Makefile.inc index 28bc7c7..217f9d2 100644 --- a/src/mainboard/intel/dcp847ske/Makefile.inc +++ b/src/mainboard/intel/dcp847ske/Makefile.inc @@ -1,6 +1,5 @@ bootblock-y += early_southbridge.c romstage-y += early_southbridge.c -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads smm-y += smihandler.c diff --git a/src/mainboard/intel/emeraldlake2/Makefile.inc b/src/mainboard/intel/emeraldlake2/Makefile.inc index 151a3c3..43224bd 100644 --- a/src/mainboard/intel/emeraldlake2/Makefile.inc +++ b/src/mainboard/intel/emeraldlake2/Makefile.inc @@ -2,7 +2,6 @@ romstage-y += chromeos.c ramstage-y += chromeos.c -bootblock-y += gpio.c romstage-y += gpio.c bootblock-y += early_init.c romstage-y += early_init.c diff --git a/src/mainboard/kontron/ktqm77/Makefile.inc b/src/mainboard/kontron/ktqm77/Makefile.inc index e402ffa..ec8df11 100644 --- a/src/mainboard/kontron/ktqm77/Makefile.inc +++ b/src/mainboard/kontron/ktqm77/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/l520/Makefile.inc b/src/mainboard/lenovo/l520/Makefile.inc index 0126a75..3a538f2 100644 --- a/src/mainboard/lenovo/l520/Makefile.inc +++ b/src/mainboard/lenovo/l520/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-y += gpio.c romstage-y += gpio.c smm-y += smihandler.c diff --git a/src/mainboard/lenovo/s230u/Makefile.inc b/src/mainboard/lenovo/s230u/Makefile.inc index 12e7709..b6d9a57 100644 --- a/src/mainboard/lenovo/s230u/Makefile.inc +++ b/src/mainboard/lenovo/s230u/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += ec.c smm-y += smihandler.c diff --git a/src/mainboard/lenovo/t420/Makefile.inc b/src/mainboard/lenovo/t420/Makefile.inc index 991eadb..7405a36 100644 --- a/src/mainboard/lenovo/t420/Makefile.inc +++ b/src/mainboard/lenovo/t420/Makefile.inc @@ -1,7 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only smm-y += smihandler.c -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/t420s/Makefile.inc b/src/mainboard/lenovo/t420s/Makefile.inc index 991eadb..7405a36 100644 --- a/src/mainboard/lenovo/t420s/Makefile.inc +++ b/src/mainboard/lenovo/t420s/Makefile.inc @@ -1,7 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only smm-y += smihandler.c -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/t430/Makefile.inc b/src/mainboard/lenovo/t430/Makefile.inc index 0f49600..2cf65ae 100644 --- a/src/mainboard/lenovo/t430/Makefile.inc +++ b/src/mainboard/lenovo/t430/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c smm-y += smihandler.c diff --git a/src/mainboard/lenovo/t430s/Makefile.inc b/src/mainboard/lenovo/t430s/Makefile.inc index 196a098..244cb6b 100644 --- a/src/mainboard/lenovo/t430s/Makefile.inc +++ b/src/mainboard/lenovo/t430s/Makefile.inc @@ -1,7 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only smm-y += smihandler.c -bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/lenovo/t520/Makefile.inc b/src/mainboard/lenovo/t520/Makefile.inc index ab5aa4d..3c28088 100644 --- a/src/mainboard/lenovo/t520/Makefile.inc +++ b/src/mainboard/lenovo/t520/Makefile.inc @@ -1,7 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only smm-y += smihandler.c -bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/t530/Makefile.inc b/src/mainboard/lenovo/t530/Makefile.inc index ab5aa4d..3c28088 100644 --- a/src/mainboard/lenovo/t530/Makefile.inc +++ b/src/mainboard/lenovo/t530/Makefile.inc @@ -1,7 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only smm-y += smihandler.c -bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x131e/Makefile.inc b/src/mainboard/lenovo/x131e/Makefile.inc index e4b6fbf..a6025c2 100644 --- a/src/mainboard/lenovo/x131e/Makefile.inc +++ b/src/mainboard/lenovo/x131e/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc index e9e74dd..5a1764b 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += spd smm-y += smihandler.c -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc index d870c4d..c316ad1 100644 --- a/src/mainboard/lenovo/x220/Makefile.inc +++ b/src/mainboard/lenovo/x220/Makefile.inc @@ -1,7 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only smm-y += smihandler.c -bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc index 5316d24..6cd7764 100644 --- a/src/mainboard/lenovo/x230/Makefile.inc +++ b/src/mainboard/lenovo/x230/Makefile.inc @@ -2,7 +2,6 @@ smm-y += smihandler.c bootblock-y += variants/$(VARIANT_DIR)/early_init.c -bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/early_init.c romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/msi/ms7707/Makefile.inc b/src/mainboard/msi/ms7707/Makefile.inc index 2fa05da..b4f8b65 100644 --- a/src/mainboard/msi/ms7707/Makefile.inc +++ b/src/mainboard/msi/ms7707/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c bootblock-y += early_init.c romstage-y += early_init.c diff --git a/src/mainboard/roda/rv11/Makefile.inc b/src/mainboard/roda/rv11/Makefile.inc index cb9c725..edafd79 100644 --- a/src/mainboard/roda/rv11/Makefile.inc +++ b/src/mainboard/roda/rv11/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-y += gpio.c romstage-y += gpio.c bootblock-y += variants/$(VARIANT_DIR)/early_init.c diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc index 1fd9498..18b38d8 100644 --- a/src/mainboard/samsung/lumpy/Makefile.inc +++ b/src/mainboard/samsung/lumpy/Makefile.inc @@ -5,7 +5,6 @@ romstage-y += chromeos.c ramstage-y += chromeos.c -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/samsung/stumpy/Makefile.inc b/src/mainboard/samsung/stumpy/Makefile.inc index 57ec1c5..63a1216 100644 --- a/src/mainboard/samsung/stumpy/Makefile.inc +++ b/src/mainboard/samsung/stumpy/Makefile.inc @@ -2,7 +2,6 @@ romstage-y += chromeos.c ramstage-y += chromeos.c -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/sapphire/pureplatinumh61/Makefile.inc b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc index 1abca53..04b3798 100644 --- a/src/mainboard/sapphire/pureplatinumh61/Makefile.inc +++ b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc @@ -1,6 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-or-later -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/supermicro/x9scl/Makefile.inc b/src/mainboard/supermicro/x9scl/Makefile.inc index 3465dfe..38cf7f1 100644 --- a/src/mainboard/supermicro/x9scl/Makefile.inc +++ b/src/mainboard/supermicro/x9scl/Makefile.inc @@ -1,4 +1,3 @@ bootblock-y += early_init.c -bootblock-y += gpio.c romstage-y += early_init.c romstage-y += gpio.c diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 5d943e4..55f22b9 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -288,7 +288,6 @@ File: "southbridge/intel/bd82x6x/acpi/pch.asl", }) - AddBootBlockFile("early_init.c", "") AddROMStageFile("early_init.c", "") sb := Create(ctx, "early_init.c") -- To view, visit https://review.coreboot.org/c/coreboot/+/45671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6508997ce5b266d1fbf2aac56b22a8b542ae7b1 Gerrit-Change-Number: 45671 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/intel: Factor out `select CPU_INTEL_COMMON`
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45042 ) Change subject: soc/intel: Factor out `select CPU_INTEL_COMMON` ...................................................................... soc/intel: Factor out `select CPU_INTEL_COMMON` All affected platforms select `SOC_INTEL_COMMON_BLOCK_CPU` already. Change-Id: Iedcd3073b8e0287908eab1d886d2d5efff09088b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig 10 files changed, 1 insertion(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/45042/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 96808cf..964e7d4 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -28,7 +28,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES # CPU specific options - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select IOAPIC select PCR_COMMON_IOSF_1_0 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 156d58a..66030b1 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -15,7 +15,6 @@ select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index d36e214..52896b9 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -65,7 +65,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_COMPRESS_FSP_S_LZMA select FSP_M_XIP diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 3c29b24..094cf05 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -1,6 +1,7 @@ config SOC_INTEL_COMMON_BLOCK_CPU bool default n + select CPU_INTEL_COMMON help This option selects Intel Common CPU Model support code which provides various CPU related APIs which are common diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index e6d3237..3fce223 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -16,7 +16,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select DEBUG_GPIO - select CPU_INTEL_COMMON select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET select PLATFORM_USES_FSP2_0 diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 2aeb6d6..8a98304 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -15,7 +15,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index fd5648f..d172322 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -15,7 +15,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 9f9cb18..adb43ad 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -26,7 +26,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_COMMON_HYPERTHREADING select FSP_M_XIP diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 8718f97..de92090 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -15,7 +15,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 31d12fc..a4274df 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -31,7 +31,6 @@ select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES - select CPU_INTEL_COMMON select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS -- To view, visit https://review.coreboot.org/c/coreboot/+/45042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedcd3073b8e0287908eab1d886d2d5efff09088b Gerrit-Change-Number: 45042 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: [DO NOT MERGE] {soc,mb}/intel/dehydratedlake: Add empty SoC/mainboard
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45670 ) Change subject: [DO NOT MERGE] {soc,mb}/intel/dehydratedlake: Add empty SoC/mainboard ...................................................................... [DO NOT MERGE] {soc,mb}/intel/dehydratedlake: Add empty SoC/mainboard This lake got dried up. It contains a fraction of the code in other SoCs and is meant to be used as a base when adding support for new SoCs. It could be slimmed down even further, but this should be good enough. Change-Id: I5b1387b2826a7cad98c40d67cdc476c5d77ce0fd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/intel/dehydratedlake_rvp/Kconfig A src/mainboard/intel/dehydratedlake_rvp/Kconfig.name A src/mainboard/intel/dehydratedlake_rvp/board_info.txt A src/mainboard/intel/dehydratedlake_rvp/devicetree.cb A src/mainboard/intel/dehydratedlake_rvp/dsdt.asl A src/soc/intel/dehydratedlake/Kconfig A src/soc/intel/dehydratedlake/Makefile.inc A src/soc/intel/dehydratedlake/acpi.c A src/soc/intel/dehydratedlake/bootblock/bootblock.c A src/soc/intel/dehydratedlake/chip.c A src/soc/intel/dehydratedlake/chip.h A src/soc/intel/dehydratedlake/espi.c A src/soc/intel/dehydratedlake/fsp_params.c A src/soc/intel/dehydratedlake/gpio.c A src/soc/intel/dehydratedlake/i2c.c A src/soc/intel/dehydratedlake/include/soc/cpu.h A src/soc/intel/dehydratedlake/include/soc/gpe.h A src/soc/intel/dehydratedlake/include/soc/gpio.h A src/soc/intel/dehydratedlake/include/soc/gpio_defs.h A src/soc/intel/dehydratedlake/include/soc/gpio_soc_defs.h A src/soc/intel/dehydratedlake/include/soc/iomap.h A src/soc/intel/dehydratedlake/include/soc/irq.h A src/soc/intel/dehydratedlake/include/soc/itss.h A src/soc/intel/dehydratedlake/include/soc/me.h A src/soc/intel/dehydratedlake/include/soc/nvs.h A src/soc/intel/dehydratedlake/include/soc/p2sb.h A src/soc/intel/dehydratedlake/include/soc/pci_devs.h A src/soc/intel/dehydratedlake/include/soc/pcr_ids.h A src/soc/intel/dehydratedlake/include/soc/pm.h A src/soc/intel/dehydratedlake/include/soc/pmc.h A src/soc/intel/dehydratedlake/include/soc/ramstage.h A src/soc/intel/dehydratedlake/include/soc/smbus.h A src/soc/intel/dehydratedlake/include/soc/soc_chip.h A src/soc/intel/dehydratedlake/include/soc/systemagent.h A src/soc/intel/dehydratedlake/lockdown.c A src/soc/intel/dehydratedlake/p2sb.c A src/soc/intel/dehydratedlake/pmc.c A src/soc/intel/dehydratedlake/pmutil.c A src/soc/intel/dehydratedlake/reset.c A src/soc/intel/dehydratedlake/romstage/Makefile.inc A src/soc/intel/dehydratedlake/romstage/romstage.c A src/soc/intel/dehydratedlake/smihandler.c A src/soc/intel/dehydratedlake/smmrelocate.c A src/soc/intel/dehydratedlake/spi.c 44 files changed, 874 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/45670/1 diff --git a/src/mainboard/intel/dehydratedlake_rvp/Kconfig b/src/mainboard/intel/dehydratedlake_rvp/Kconfig new file mode 100644 index 0000000..bab01c9 --- /dev/null +++ b/src/mainboard/intel/dehydratedlake_rvp/Kconfig @@ -0,0 +1,29 @@ +if BOARD_INTEL_DEHYDRATEDLAKE_RVP + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SOC_INTEL_DEHYDRATEDLAKE + +config MAINBOARD_DIR + string + default "intel/dehydratedlake_rvp" + +config MAINBOARD_PART_NUMBER + string + default "Dehydrated Lake RVP" + +config MAINBOARD_FAMILY + string + default "Intel_dehydratedlake_rvp" + +config MAX_CPUS + int + default 8 + +config DIMM_SPD_SIZE + int + default 512 +endif diff --git a/src/mainboard/intel/dehydratedlake_rvp/Kconfig.name b/src/mainboard/intel/dehydratedlake_rvp/Kconfig.name new file mode 100644 index 0000000..b2ece12 --- /dev/null +++ b/src/mainboard/intel/dehydratedlake_rvp/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_DEHYDRATEDLAKE_RVP + bool "Dehydrated Lake RVP" diff --git a/src/mainboard/intel/dehydratedlake_rvp/board_info.txt b/src/mainboard/intel/dehydratedlake_rvp/board_info.txt new file mode 100644 index 0000000..3be4e3e --- /dev/null +++ b/src/mainboard/intel/dehydratedlake_rvp/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Dehydrated Lake RVP +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/intel/dehydratedlake_rvp/devicetree.cb b/src/mainboard/intel/dehydratedlake_rvp/devicetree.cb new file mode 100644 index 0000000..44c02ff --- /dev/null +++ b/src/mainboard/intel/dehydratedlake_rvp/devicetree.cb @@ -0,0 +1,10 @@ +chip soc/intel/dehydratedlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + end +end diff --git a/src/mainboard/intel/dehydratedlake_rvp/dsdt.asl b/src/mainboard/intel/dehydratedlake_rvp/dsdt.asl new file mode 100644 index 0000000..8bb2332 --- /dev/null +++ b/src/mainboard/intel/dehydratedlake_rvp/dsdt.asl @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // global NVS and variables + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/soc/intel/dehydratedlake/Kconfig b/src/soc/intel/dehydratedlake/Kconfig new file mode 100644 index 0000000..cad5286 --- /dev/null +++ b/src/soc/intel/dehydratedlake/Kconfig @@ -0,0 +1,119 @@ +config SOC_INTEL_DEHYDRATEDLAKE + bool + help + Intel Dehydrated Lake support + +if SOC_INTEL_DEHYDRATEDLAKE + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ARCH_BOOTBLOCK_X86_32 + select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select BOOT_DEVICE_SUPPORTS_WRITES + select CACHE_MRC_SETTINGS + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select FSP_M_XIP + select GENERIC_GPIO_LIB + select HAVE_FSP_GOP + select HAVE_INTEL_FSP_REPO + select INTEL_DESCRIPTOR_MODE_CAPABLE + select HAVE_SMI_HANDLER + select IDT_IN_EVERY_STAGE + select INTEL_GMA_ACPI + select INTEL_GMA_ADD_VBT if RUN_FSP_GOP + select IOAPIC + select MRC_SETTINGS_PROTECT + select PARALLEL_MP + select PARALLEL_MP_AP_WORK + select MICROCODE_BLOB_UNDISCLOSED + select PLATFORM_USES_FSP2_1 + select FSP_PEIM_TO_PEIM_INTERFACE + select REG_SCRIPT + select PMC_GLOBAL_RESET_ENABLE_LOCK + select CPU_INTEL_COMMON_SMM + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG + select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SMM + select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_BLOCK_THERMAL + select SOC_INTEL_COMMON_PCH_BASE + select SOC_INTEL_COMMON_RESET + select SOC_INTEL_COMMON_BLOCK_CAR + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS + select TSC_MONOTONIC_TIMER + select UDELAY_TSC + select UDK_2017_BINDING + select DISPLAY_FSP_VERSION_INFO + select HECI_DISABLE_USING_SMM + select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + select USE_CAR_NEM_ENHANCED_V1 + +config DCACHE_RAM_BASE + default 0xdead0000 + +config DCACHE_RAM_SIZE + default 0x8000 + +config DCACHE_BSP_STACK_SIZE + hex + default 0x4000 + +config MAX_ROOT_PORTS + int + default 1 + +config SMM_TSEG_SIZE + hex + default 0x800000 + +config PCR_BASE_ADDRESS + hex + default 0xdeadbeef + help + This option allows you to select MMIO Base Address of sideband bus. + +config MMCONF_BASE_ADDRESS + hex + default 0xdeadbeef + +config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 133 + +config FSP_HEADER_PATH + default "3rdparty/fsp/IceLakeFspBinPkg/Include" + +config FSP_FD_PATH + default "3rdparty/fsp/IceLakeFspBinPkg/Fsp.fd" + +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xfe032000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + +# Clock divider parameters for 115200 baud rate +config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL + hex + default 0x30 + +config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL + hex + default 0xc35 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x4000 + +endif diff --git a/src/soc/intel/dehydratedlake/Makefile.inc b/src/soc/intel/dehydratedlake/Makefile.inc new file mode 100644 index 0000000..be8b70e --- /dev/null +++ b/src/soc/intel/dehydratedlake/Makefile.inc @@ -0,0 +1,44 @@ +ifeq ($(CONFIG_SOC_INTEL_DEHYDRATEDLAKE),y) + +subdirs-y += romstage +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/smm +subdirs-y += ../../../cpu/x86/tsc + +# all (bootblock, verstage, romstage, postcar, ramstage) +all-y += i2c.c +all-y += pmutil.c + +bootblock-y += bootblock/bootblock.c +bootblock-y += espi.c +bootblock-y += gpio.c +bootblock-y += p2sb.c + +romstage-y += espi.c +romstage-y += gpio.c +romstage-y += reset.c + +ramstage-y += acpi.c +ramstage-y += chip.c +ramstage-y += espi.c +ramstage-y += fsp_params.c +ramstage-y += gpio.c +ramstage-y += lockdown.c +ramstage-y += p2sb.c +ramstage-y += pmc.c +ramstage-y += reset.c +ramstage-y += smmrelocate.c +ramstage-y += spi.c + +smm-y += gpio.c +smm-y += p2sb.c +smm-y += pmc.c +smm-y += pmutil.c +smm-y += smihandler.c + +CPPFLAGS_common += -I$(src)/soc/intel/dehydratedlake/include + +endif diff --git a/src/soc/intel/dehydratedlake/acpi.c b/src/soc/intel/dehydratedlake/acpi.c new file mode 100644 index 0000000..6e0ec29 --- /dev/null +++ b/src/soc/intel/dehydratedlake/acpi.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> +#include <intelblocks/acpi.h> + +acpi_cstate_t *soc_get_cstate_map(size_t *entries) +{ + entries = 0; + return NULL; +} + +void soc_power_states_generation(int core_id, int cores_per_package) +{ +} + +void soc_fill_fadt(acpi_fadt_t *fadt) +{ +} + +uint32_t soc_read_sci_irq_select(void) +{ + return 0; +} + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ +} + +uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, const struct chipset_power_state *ps) +{ + return 0; +} + +int soc_madt_sci_irq_polarity(int sci) +{ + return 0; +} diff --git a/src/soc/intel/dehydratedlake/bootblock/bootblock.c b/src/soc/intel/dehydratedlake/bootblock/bootblock.c new file mode 100644 index 0000000..9780e3b --- /dev/null +++ b/src/soc/intel/dehydratedlake/bootblock/bootblock.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + /* Call lib/bootblock.c main */ + bootblock_main_with_basetime(base_timestamp); +} + +void bootblock_soc_early_init(void) +{ +} + +void bootblock_soc_init(void) +{ +} diff --git a/src/soc/intel/dehydratedlake/chip.c b/src/soc/intel/dehydratedlake/chip.c new file mode 100644 index 0000000..b93498d --- /dev/null +++ b/src/soc/intel/dehydratedlake/chip.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <intelblocks/acpi.h> + +#if CONFIG(HAVE_ACPI_TABLES) +const char *soc_acpi_name(const struct device *dev) +{ + return NULL; +} +#endif + +struct chip_operations soc_intel_dehydratedlake_ops = { + CHIP_NAME("Intel Dehydrated Lake") +}; diff --git a/src/soc/intel/dehydratedlake/chip.h b/src/soc/intel/dehydratedlake/chip.h new file mode 100644 index 0000000..09f5249 --- /dev/null +++ b/src/soc/intel/dehydratedlake/chip.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_CHIP_H_ +#define _SOC_CHIP_H_ + +#include <intelblocks/cfg.h> +#include <stdint.h> + +struct soc_intel_dehydratedlake_config { + + /* Common struct containing soc config data required by common code */ + struct soc_intel_common_config common_soc_config; + + /* TCC activation offset */ + uint32_t tcc_offset; +}; + +typedef struct soc_intel_dehydratedlake_config config_t; + +#endif diff --git a/src/soc/intel/dehydratedlake/espi.c b/src/soc/intel/dehydratedlake/espi.c new file mode 100644 index 0000000..969d314 --- /dev/null +++ b/src/soc/intel/dehydratedlake/espi.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <intelblocks/lpc_lib.h> + +const struct lpc_mmio_range *soc_get_fixed_mmio_ranges() +{ + return NULL; +} + +void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +{ +} + +void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) +{ +} diff --git a/src/soc/intel/dehydratedlake/fsp_params.c b/src/soc/intel/dehydratedlake/fsp_params.c new file mode 100644 index 0000000..d12cf8f --- /dev/null +++ b/src/soc/intel/dehydratedlake/fsp_params.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <device/pci.h> +#include <fsp/api.h> +#include <intelblocks/lpss.h> + +/* UPD parameters to be initialized before SiliconInit */ +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) +{ +} + +/* Return list of SOC LPSS controllers */ +const pci_devfn_t *soc_lpss_controllers_list(size_t *size) +{ + *size = 0; + return NULL; +} diff --git a/src/soc/intel/dehydratedlake/gpio.c b/src/soc/intel/dehydratedlake/gpio.c new file mode 100644 index 0000000..e375d9f --- /dev/null +++ b/src/soc/intel/dehydratedlake/gpio.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <intelblocks/gpio.h> +#include <stddef.h> + +const struct pad_community *soc_gpio_get_community(size_t *num_communities) +{ + *num_communities = 0; + return NULL; +} + +const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) +{ + *num = 0; + return NULL; +} diff --git a/src/soc/intel/dehydratedlake/i2c.c b/src/soc/intel/dehydratedlake/i2c.c new file mode 100644 index 0000000..54ec270 --- /dev/null +++ b/src/soc/intel/dehydratedlake/i2c.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/i2c/designware/dw_i2c.h> + +int dw_i2c_soc_devfn_to_bus(unsigned int devfn) +{ + return -1; +} + +int dw_i2c_soc_bus_to_devfn(unsigned int bus) +{ + return -1; +} diff --git a/src/soc/intel/dehydratedlake/include/soc/cpu.h b/src/soc/intel/dehydratedlake/include/soc/cpu.h new file mode 100644 index 0000000..5826e55 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/cpu.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DEHYDRATEDLAKE_CPU_H_ +#define _SOC_DEHYDRATEDLAKE_CPU_H_ + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/gpe.h b/src/soc/intel/dehydratedlake/include/soc/gpe.h new file mode 100644 index 0000000..925af18 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/gpe.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_GPE_H_ +#define _SOC_GPE_H_ + +#define GPE_MAX 0 + +#endif /* _SOC_GPE_H_ */ diff --git a/src/soc/intel/dehydratedlake/include/soc/gpio.h b/src/soc/intel/dehydratedlake/include/soc/gpio.h new file mode 100644 index 0000000..cffe631 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DEHYDRATEDLAKE_GPIO_H_ +#define _SOC_DEHYDRATEDLAKE_GPIO_H_ + +#include <soc/gpio_defs.h> +#include <intelblocks/gpio.h> + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/gpio_defs.h b/src/soc/intel/dehydratedlake/include/soc/gpio_defs.h new file mode 100644 index 0000000..a542edf --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/gpio_defs.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DEHYDRATEDLAKE_GPIO_DEFS_H_ +#define _SOC_DEHYDRATEDLAKE_GPIO_DEFS_H_ + +#ifndef __ACPI__ +#include <stddef.h> +#endif +#include <soc/gpio_soc_defs.h> + +#define GPIO_NUM_PAD_CFG_REGS 2 + +#define NUM_GPI_STATUS_REGS 1 + +#define GPIO_MISCCFG 0 + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/gpio_soc_defs.h b/src/soc/intel/dehydratedlake/include/soc/gpio_soc_defs.h new file mode 100644 index 0000000..2233cc6 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/gpio_soc_defs.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DEHYDRATEDLAKE_GPIO_SOC_DEFS_H_ +#define _SOC_DEHYDRATEDLAKE_GPIO_SOC_DEFS_H_ + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/iomap.h b/src/soc/intel/dehydratedlake/include/soc/iomap.h new file mode 100644 index 0000000..dd97f42 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/iomap.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DEHYDRATEDLAKE_IOMAP_H_ +#define _SOC_DEHYDRATEDLAKE_IOMAP_H_ + +#define EARLY_I2C_BASE(x) 0 + +#define MCH_BASE_ADDRESS 0 + +#define HECI1_BASE_ADDRESS 0 + +#define ACPI_BASE_ADDRESS 0 + +#define TCO_BASE_ADDRESS 0 + +#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS +#define P2SB_SIZE (-4 * MiB) + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/irq.h b/src/soc/intel/dehydratedlake/include/soc/irq.h new file mode 100644 index 0000000..7dfb121 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/irq.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_IRQ_H_ +#define _SOC_IRQ_H_ + +#define LPSS_UART0_IRQ -2 +#define LPSS_UART1_IRQ -4 +#define LPSS_UART2_IRQ -6 + +#endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/dehydratedlake/include/soc/itss.h b/src/soc/intel/dehydratedlake/include/soc/itss.h new file mode 100644 index 0000000..f29e1c3 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/itss.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ITSS_H_ +#define _SOC_ITSS_H_ + +#define ITSS_MAX_IRQ 0 +#define IRQS_PER_IPC 1 +#define NUM_IPC_REGS 0 + +#endif /* _SOC_ITSS_H_ */ diff --git a/src/soc/intel/dehydratedlake/include/soc/me.h b/src/soc/intel/dehydratedlake/include/soc/me.h new file mode 100644 index 0000000..9be7b67 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/me.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _DEHYDRATEDLAKE_ME_H_ +#define _DEHYDRATEDLAKE_ME_H_ + +/* ME Host Firmware Status register 1 */ +union me_hfsts1 { + u32 data; + struct { + u32 working_state: 4; + u32 mfg_mode: 1; + u32 fpt_bad: 1; + u32 operation_state: 3; + u32 fw_init_complete: 1; + u32 ft_bup_ld_flr: 1; + u32 update_in_progress: 1; + u32 error_code: 4; + u32 operation_mode: 4; + u32 reset_count: 4; + u32 boot_options_present: 1; + u32 reserved1: 1; + u32 bist_test_state: 1; + u32 bist_reset_request: 1; + u32 current_power_source: 2; + u32 reserved: 1; + u32 d0i3_support_valid: 1; + } __packed fields; +}; + +/* ME Host Firmware Status Register 3 */ +union me_hfsts3 { + u32 data; + struct { + u32 reserved_0: 4; + u32 fw_sku: 3; + u32 reserved_7: 2; + u32 reserved_9: 2; + u32 resered_11: 3; + u32 resered_14: 16; + u32 reserved_30: 2; + } __packed fields; +}; + +#endif /* _DEHYDRATEDLAKE_ME_H_ */ diff --git a/src/soc/intel/dehydratedlake/include/soc/nvs.h b/src/soc/intel/dehydratedlake/include/soc/nvs.h new file mode 100644 index 0000000..5129458 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/nvs.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NVS_H_ +#define _SOC_NVS_H_ + +#include <intelblocks/nvs.h> + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/p2sb.h b/src/soc/intel/dehydratedlake/include/soc/p2sb.h new file mode 100644 index 0000000..0114693 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/p2sb.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DEHYDRATEDLAKE_P2SB_H_ +#define _SOC_DEHYDRATEDLAKE_P2SB_H_ + +#define HPTC_OFFSET 0 +#define HPTC_ADDR_ENABLE_BIT 0 + +#define PCH_P2SB_EPMASK0 0 + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/pci_devs.h b/src/soc/intel/dehydratedlake/include/soc/pci_devs.h new file mode 100644 index 0000000..5c929b6 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/pci_devs.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DEHYDRATEDLAKE_PCI_DEVS_H_ +#define _SOC_DEHYDRATEDLAKE_PCI_DEVS_H_ + +#include <device/pci_def.h> + +#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) + +#if !defined(__SIMPLE_DEVICE__) +#include <device/device.h> +#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#else +#define _PCH_DEV(slot, func) PCI_DEV(-98, PCH_DEV_SLOT_ ## slot, func) +#endif + +/* System Agent Devices */ +#define SA_DEV_SLOT_ROOT 0x54 +#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, -45) +#if defined(__SIMPLE_DEVICE__) +#define SA_DEV_ROOT PCI_DEV(-117, SA_DEV_SLOT_ROOT, -103) +#endif + +#define SA_DEV_SLOT_IGD -2 +#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, -39) +#define SA_DEV_IGD PCI_DEV(42, SA_DEV_SLOT_IGD, 67) + +/* PCH Devices */ +#define PCH_DEV_SLOT_THERMAL 93 +#define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 121) +#define PCH_DEV_THERMAL _PCH_DEV(THERMAL, -78) + +#define PCH_DEV_SLOT_XHCI 0xf3 +#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 88) +#define PCH_DEV_XHCI _PCH_DEV(XHCI, 97) + +#define PCH_DEV_SLOT_CSE 0xe2 +#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, -3) +#define PCH_DEV_CSE _PCH_DEV(CSE, -5) + +#define PCH_DEV_SLOT_SIO2 0x66 +#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO2, -62) +#define PCH_DEV_UART2 _PCH_DEV(SIO2, -32) + +#define PCH_DEV_SLOT_SIO3 0x99 +#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 50) +#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO3, -1) +#define PCH_DEV_UART0 _PCH_DEV(SIO3, 45) +#define PCH_DEV_UART1 _PCH_DEV(SIO3, -37) + +#define PCH_DEV_SLOT_ESPI 0xaa +#define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI +#define PCH_DEVFN_ESPI _PCH_DEVFN(ESPI, -1) +#define PCH_DEVFN_P2SB _PCH_DEVFN(ESPI, -4) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(ESPI, -9) +#define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, -2) +#define PCH_DEV_ESPI _PCH_DEV(ESPI, -6) +#define PCH_DEV_LPC PCH_DEV_ESPI +#define PCH_DEV_P2SB _PCH_DEV(ESPI, -7) +#define PCH_DEV_SMBUS _PCH_DEV(ESPI, -3) +#define PCH_DEV_SPI _PCH_DEV(ESPI, -8) + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/pcr_ids.h b/src/soc/intel/dehydratedlake/include/soc/pcr_ids.h new file mode 100644 index 0000000..ae4f939 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/pcr_ids.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_DEHYDRATEDLAKE_PCR_H +#define SOC_DEHYDRATEDLAKE_PCR_H + +#define PID_DMI 0 +#define PID_PSTH 0 +#define PID_CSME0 0 +#define PID_RTC 0 +#define PID_ITSS 0 + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/pm.h b/src/soc/intel/dehydratedlake/include/soc/pm.h new file mode 100644 index 0000000..c5685c4 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/pm.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PM_H_ +#define _SOC_PM_H_ + +#define PM1_STS 0 +#define WAK_STS 0 +#define PWRBTN_STS 0 +#define PM1_EN 0 +#define PWRBTN_EN 0 +#define GBL_EN 0 +#define PM1_CNT 0 +#define SCI_EN 0 +#define SMI_EN 0 +#define ESPI_SMI_EN 0 +#define PERIODIC_EN 0 +#define TCO_SMI_EN 0 +#define MCSMI_EN 0 +#define APMC_EN 0 +#define SLP_SMI_EN 0 +#define EOS 0 +#define SMI_STS 0 +#define APM_STS_BIT 0 +#define SMI_ON_SLP_EN_STS_BIT 0 + +#define GPE0_REG_MAX 0 +#define GPE0_STS(x) 0 +#define GPE_STD 0 +#define GPE0_EN(x) 0 +#define PME_B0_EN 0 + +#define EN_BLOCK 0 + +#define ENABLE_SMI_PARAMS 0 + +#define PSS_RATIO_STEP 0 +#define PSS_MAX_ENTRIES 0 +#define PSS_LATENCY_TRANSITION 0 +#define PSS_LATENCY_BUSMASTER 0 + +#if !defined(__ACPI__) + +#include <acpi/acpi.h> +#include <soc/gpe.h> +#include <soc/iomap.h> +#include <soc/pmc.h> + +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint16_t tco1_sts; + uint16_t tco2_sts; + uint32_t gpe0_sts[4]; + uint32_t gpe0_en[4]; + uint32_t gen_pmcon_a; + uint32_t gen_pmcon_b; + uint32_t gblrst_cause[2]; + uint32_t prev_sleep_state; +} __packed; + +/* Get base address PMC memory mapped registers. */ +uint8_t *pmc_mmio_regs(void); + +#endif /* !defined(__ACPI__) */ +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/pmc.h b/src/soc/intel/dehydratedlake/include/soc/pmc.h new file mode 100644 index 0000000..f6d203e --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/pmc.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DEHYDRATEDLAKE_PMC_H_ +#define _SOC_DEHYDRATEDLAKE_PMC_H_ + +#define ETR 0 +#define CF9_LOCK 0 +#define CF9_GLB_RST 0 + +#define PRSTS 0 + +#define GPIO_GPE_CFG 0 +#define GPE0_DWX_MASK 0 +#define GPE0_DW_SHIFT(x) 0 + +#define SCI_IRQ_ADJUST 0 +#define SCI_IRQ_SEL 0 + +#define SCIS_IRQ9 -8 +#define SCIS_IRQ10 -1 +#define SCIS_IRQ11 -2 +#define SCIS_IRQ20 -4 +#define SCIS_IRQ21 -5 +#define SCIS_IRQ22 -6 +#define SCIS_IRQ23 -7 + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/ramstage.h b/src/soc/intel/dehydratedlake/include/soc/ramstage.h new file mode 100644 index 0000000..258a672 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/ramstage.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_RAMSTAGE_H_ +#define _SOC_RAMSTAGE_H_ + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/smbus.h b/src/soc/intel/dehydratedlake/include/soc/smbus.h new file mode 100644 index 0000000..41f0d0a --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/smbus.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DEHYDRATEDLAKE_SMBUS_H_ +#define _SOC_DEHYDRATEDLAKE_SMBUS_H_ + +#define TCO1_STS 0 +#define TCO_TIMEOUT 0 +#define TCO2_STS 0 +#define TCO_STS_SECOND_TO 0 +#define TCO_INTRD_DET 0 +#define TCO1_CNT 0 +#define TCO_LOCK 0 +#define TCO_TMR_HLT 0 +#define TCO2_CNT 0 +#define TCO_INTRD_SEL_MASK 0 +#define TCO_INTRD_SEL_SMI 0 +#define TCO_INTRD_SEL_INT 0 + +#define SMBUS_SLAVE_ADDR 0 + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/soc_chip.h b/src/soc/intel/dehydratedlake/include/soc/soc_chip.h new file mode 100644 index 0000000..9676c46 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/soc_chip.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DEHYDRATEDLAKE_SOC_CHIP_H_ +#define _SOC_DEHYDRATEDLAKE_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif /* _SOC_DEHYDRATEDLAKE_SOC_CHIP_H_ */ diff --git a/src/soc/intel/dehydratedlake/include/soc/systemagent.h b/src/soc/intel/dehydratedlake/include/soc/systemagent.h new file mode 100644 index 0000000..a6e6402 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/systemagent.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_DEHYDRATEDLAKE_SYSTEMAGENT_H +#define SOC_DEHYDRATEDLAKE_SYSTEMAGENT_H + +#define CAPID0_A 0 + +#define BIOS_RESET_CPL 0 + +#endif diff --git a/src/soc/intel/dehydratedlake/lockdown.c b/src/soc/intel/dehydratedlake/lockdown.c new file mode 100644 index 0000000..f5012f5 --- /dev/null +++ b/src/soc/intel/dehydratedlake/lockdown.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelpch/lockdown.h> + +void soc_lockdown_config(int chipset_lockdown) +{ +} diff --git a/src/soc/intel/dehydratedlake/p2sb.c b/src/soc/intel/dehydratedlake/p2sb.c new file mode 100644 index 0000000..5ce4990 --- /dev/null +++ b/src/soc/intel/dehydratedlake/p2sb.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/p2sb.h> + +void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count) +{ +} diff --git a/src/soc/intel/dehydratedlake/pmc.c b/src/soc/intel/dehydratedlake/pmc.c new file mode 100644 index 0000000..4cebc30 --- /dev/null +++ b/src/soc/intel/dehydratedlake/pmc.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/pmclib.h> +#include <stdbool.h> + +void pmc_soc_set_afterg3_en(const bool on) +{ +} diff --git a/src/soc/intel/dehydratedlake/pmutil.c b/src/soc/intel/dehydratedlake/pmutil.c new file mode 100644 index 0000000..bec6841 --- /dev/null +++ b/src/soc/intel/dehydratedlake/pmutil.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ + +#include <device/device.h> +#include <intelblocks/pmclib.h> +#include <soc/pm.h> + +const char *const *soc_smi_sts_array(size_t *a) +{ + *a = 0; + return NULL; +} + +const char *const *soc_tco_sts_array(size_t *a) +{ + *a = 0; + return NULL; +} + +const char *const *soc_std_gpe_sts_array(size_t *a) +{ + *a = 0; + return NULL; +} + +uint8_t *pmc_mmio_regs(void) +{ + return NULL; +} + +uintptr_t soc_read_pmc_base(void) +{ + return 0; +} + +uint32_t *soc_pmc_etr_addr(void) +{ + return NULL; +} + +void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) +{ +} + +int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state) +{ + return ACPI_S5; +} + +void soc_fill_power_state(struct chipset_power_state *ps) +{ +} diff --git a/src/soc/intel/dehydratedlake/reset.c b/src/soc/intel/dehydratedlake/reset.c new file mode 100644 index 0000000..ed8a30e --- /dev/null +++ b/src/soc/intel/dehydratedlake/reset.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fsp/util.h> +#include <soc/intel/common/reset.h> + +void do_global_reset(void) +{ +} + +void chipset_handle_reset(uint32_t status) +{ +} diff --git a/src/soc/intel/dehydratedlake/romstage/Makefile.inc b/src/soc/intel/dehydratedlake/romstage/Makefile.inc new file mode 100644 index 0000000..da933d5 --- /dev/null +++ b/src/soc/intel/dehydratedlake/romstage/Makefile.inc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += ../../../../cpu/intel/car/romstage.c +romstage-y += romstage.c diff --git a/src/soc/intel/dehydratedlake/romstage/romstage.c b/src/soc/intel/dehydratedlake/romstage/romstage.c new file mode 100644 index 0000000..056da92 --- /dev/null +++ b/src/soc/intel/dehydratedlake/romstage/romstage.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/romstage.h> + +void mainboard_romstage_entry(void) +{ +} diff --git a/src/soc/intel/dehydratedlake/smihandler.c b/src/soc/intel/dehydratedlake/smihandler.c new file mode 100644 index 0000000..c0e91f9 --- /dev/null +++ b/src/soc/intel/dehydratedlake/smihandler.c @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/smihandler.h> + +const smi_handler_t southbridge_smi[32] = {}; diff --git a/src/soc/intel/dehydratedlake/smmrelocate.c b/src/soc/intel/dehydratedlake/smmrelocate.c new file mode 100644 index 0000000..e15e70f --- /dev/null +++ b/src/soc/intel/dehydratedlake/smmrelocate.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/intel/smm_reloc.h> +#include <types.h> + +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) +{ +} + +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) +{ +} + +void smm_initialize(void) +{ +} + +void smm_relocate(void) +{ +} diff --git a/src/soc/intel/dehydratedlake/spi.c b/src/soc/intel/dehydratedlake/spi.c new file mode 100644 index 0000000..a95be42 --- /dev/null +++ b/src/soc/intel/dehydratedlake/spi.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <intelblocks/spi.h> + +int spi_soc_devfn_to_bus(unsigned int devfn) +{ + return -1; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b1387b2826a7cad98c40d67cdc476c5d77ce0fd Gerrit-Change-Number: 45670 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: nb/intel/x4x: Put DMIBAR/EPBAR/MCHBAR registers into separate files
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45425 ) Change subject: nb/intel/x4x: Put DMIBAR/EPBAR/MCHBAR registers into separate files ...................................................................... nb/intel/x4x: Put DMIBAR/EPBAR/MCHBAR registers into separate files Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I457fd753079fb9658d0b89a26003a0e83a32ade0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/northbridge/intel/x4x/registers/dmibar.h A src/northbridge/intel/x4x/registers/epbar.h A src/northbridge/intel/x4x/registers/mchbar.h M src/northbridge/intel/x4x/x4x.h 4 files changed, 113 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/45425/1 diff --git a/src/northbridge/intel/x4x/registers/dmibar.h b/src/northbridge/intel/x4x/registers/dmibar.h new file mode 100644 index 0000000..6fef8d3 --- /dev/null +++ b/src/northbridge/intel/x4x/registers/dmibar.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __X4X_REGISTERS_DMIBAR_H__ +#define __X4X_REGISTERS_DMIBAR_H__ + +#define DMIVCECH 0x000 /* 32bit */ +#define DMIPVCCAP1 0x004 /* 32bit */ + +#define DMIVC0RCAP 0x010 /* 32bit */ +#define DMIVC0RCTL 0x014 /* 32bit */ +#define DMIVC0RSTS 0x01a /* 16bit */ +#define VC0NP (1 << 1) + +#define DMIVC1RCAP 0x01c /* 32bit */ +#define DMIVC1RCTL 0x020 /* 32bit */ +#define DMIVC1RSTS 0x026 /* 16bit */ +#define VC1NP (1 << 1) + +#define DMIVCPRCAP 0x028 /* 32bit */ +#define DMIVCPRCTL 0x02c /* 32bit */ +#define DMIVCPRSTS 0x032 /* 16bit */ +#define VCPNP (1 << 1) + +#define DMIVCMRCAP 0x034 /* 32bit */ +#define DMIVCMRCTL 0x038 /* 32bit */ +#define DMIVCMRSTS 0x03e /* 16bit */ +#define VCMNP (1 << 1) + +#define DMIESD 0x044 /* 32bit */ + +#define DMILE1D 0x050 /* 32bit */ +#define DMILE1A 0x058 /* 64bit */ +#define DMILE2D 0x060 /* 32bit */ +#define DMILE2A 0x068 /* 64bit */ + +#define DMILCAP 0x084 /* 32bit */ +#define DMILCTL 0x088 /* 16bit */ +#define DMILSTS 0x08a /* 16bit */ + +#define DMIUESTS 0x1c4 /* 32bit */ +#define DMICESTS 0x1d0 /* 32bit */ + +#endif /* __X4X_REGISTERS_DMIBAR_H__ */ diff --git a/src/northbridge/intel/x4x/registers/epbar.h b/src/northbridge/intel/x4x/registers/epbar.h new file mode 100644 index 0000000..14ba313 --- /dev/null +++ b/src/northbridge/intel/x4x/registers/epbar.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __X4X_REGISTERS_EPBAR_H__ +#define __X4X_REGISTERS_EPBAR_H__ + +#define EPPVCCAP1 0x004 /* 32bit */ +#define EPPVCCTL 0x00c /* 32bit */ + +#define EPVC0RCAP 0x010 /* 32bit */ +#define EPVC0RCTL 0x014 /* 32bit */ +#define EPVC0RSTS 0x01a /* 16bit */ + +#define EPVC1RCAP 0x01c /* 32bit */ +#define EPVC1RCTL 0x020 /* 32bit */ +#define EPVC1RSTS 0x026 /* 16bit */ + +#define EPVC1MTS 0x028 /* 32bit */ +#define EPVC1ITC 0x02c /* 32bit */ + +#define EPESD 0x044 /* 32bit */ + +#define EPLE1D 0x050 /* 32bit */ +#define EPLE1A 0x058 /* 64bit */ +#define EPLE2D 0x060 /* 32bit */ +#define EPLE2A 0x068 /* 64bit */ + +#define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */ + +#endif /* __X4X_REGISTERS_EPBAR_H__ */ diff --git a/src/northbridge/intel/x4x/registers/mchbar.h b/src/northbridge/intel/x4x/registers/mchbar.h new file mode 100644 index 0000000..e44078c --- /dev/null +++ b/src/northbridge/intel/x4x/registers/mchbar.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __X4X_REGISTERS_MCHBAR_H__ +#define __X4X_REGISTERS_MCHBAR_H__ + +#define CHDECMISC 0x111 +#define STACKED_MEM (1 << 1) + +#define C0DRB0 0x200 +#define C0DRB1 0x202 +#define C0DRB2 0x204 +#define C0DRB3 0x206 +#define C0DRA01 0x208 +#define C0DRA23 0x20a +#define C0CKECTRL 0x260 + +#define C1DRB0 0x600 +#define C1DRB1 0x602 +#define C1DRB2 0x604 +#define C1DRB3 0x606 +#define C1DRA01 0x608 +#define C1DRA23 0x60a +#define C1CKECTRL 0x660 + +#define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */ +#define PMSTS_WARM_RESET (1 << 8) +#define PMSTS_BOTH_SELFREFRESH (3 << 0) + +#define CLKCFG_MCHBAR 0x0c00 +#define CLKCFG_FSBCLK_SHIFT 0 +#define CLKCFG_FSBCLK_MASK (7 << CLKCFG_FSBCLK_SHIFT) +#define CLKCFG_MEMCLK_SHIFT 4 +#define CLKCFG_MEMCLK_MASK (7 << CLKCFG_MEMCLK_SHIFT) +#define CLKCFG_UPDATE (1 << 12) + +#define SSKPD_MCHBAR 0x0c20 /* 64 bit */ + +#endif /* __X4X_REGISTERS_MCHBAR_H__ */ diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index ea34fe0..948f5f8 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -57,37 +57,7 @@ #define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) -#define CHDECMISC 0x111 -#define STACKED_MEM (1 << 1) - -#define C0DRB0 0x200 -#define C0DRB1 0x202 -#define C0DRB2 0x204 -#define C0DRB3 0x206 -#define C0DRA01 0x208 -#define C0DRA23 0x20a -#define C0CKECTRL 0x260 - -#define C1DRB0 0x600 -#define C1DRB1 0x602 -#define C1DRB2 0x604 -#define C1DRB3 0x606 -#define C1DRA01 0x608 -#define C1DRA23 0x60a -#define C1CKECTRL 0x660 - -#define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */ -#define PMSTS_WARM_RESET (1 << 8) -#define PMSTS_BOTH_SELFREFRESH (3 << 0) - -#define CLKCFG_MCHBAR 0x0c00 -#define CLKCFG_FSBCLK_SHIFT 0 -#define CLKCFG_FSBCLK_MASK (7 << CLKCFG_FSBCLK_SHIFT) -#define CLKCFG_MEMCLK_SHIFT 4 -#define CLKCFG_MEMCLK_MASK (7 << CLKCFG_MEMCLK_SHIFT) -#define CLKCFG_UPDATE (1 << 12) - -#define SSKPD_MCHBAR 0x0c20 /* 64 bit */ +#include "registers/mchbar.h" /* * DMIBAR @@ -97,42 +67,7 @@ #define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) #define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) -#define DMIVCECH 0x000 /* 32bit */ -#define DMIPVCCAP1 0x004 /* 32bit */ - -#define DMIVC0RCAP 0x010 /* 32bit */ -#define DMIVC0RCTL 0x014 /* 32bit */ -#define DMIVC0RSTS 0x01a /* 16bit */ -#define VC0NP (1 << 1) - -#define DMIVC1RCAP 0x01c /* 32bit */ -#define DMIVC1RCTL 0x020 /* 32bit */ -#define DMIVC1RSTS 0x026 /* 16bit */ -#define VC1NP (1 << 1) - -#define DMIVCPRCAP 0x028 /* 32bit */ -#define DMIVCPRCTL 0x02c /* 32bit */ -#define DMIVCPRSTS 0x032 /* 16bit */ -#define VCPNP (1 << 1) - -#define DMIVCMRCAP 0x034 /* 32bit */ -#define DMIVCMRCTL 0x038 /* 32bit */ -#define DMIVCMRSTS 0x03e /* 16bit */ -#define VCMNP (1 << 1) - -#define DMIESD 0x044 /* 32bit */ - -#define DMILE1D 0x050 /* 32bit */ -#define DMILE1A 0x058 /* 64bit */ -#define DMILE2D 0x060 /* 32bit */ -#define DMILE2A 0x068 /* 64bit */ - -#define DMILCAP 0x084 /* 32bit */ -#define DMILCTL 0x088 /* 16bit */ -#define DMILSTS 0x08a /* 16bit */ - -#define DMIUESTS 0x1c4 /* 32bit */ -#define DMICESTS 0x1d0 /* 32bit */ +#include "registers/dmibar.h" /* * EPBAR @@ -142,28 +77,7 @@ #define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) #define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) -#define EPPVCCAP1 0x004 /* 32bit */ -#define EPPVCCTL 0x00c /* 32bit */ - -#define EPVC0RCAP 0x010 /* 32bit */ -#define EPVC0RCTL 0x014 /* 32bit */ -#define EPVC0RSTS 0x01a /* 16bit */ - -#define EPVC1RCAP 0x01c /* 32bit */ -#define EPVC1RCTL 0x020 /* 32bit */ -#define EPVC1RSTS 0x026 /* 16bit */ - -#define EPVC1MTS 0x028 /* 32bit */ -#define EPVC1ITC 0x02c /* 32bit */ - -#define EPESD 0x044 /* 32bit */ - -#define EPLE1D 0x050 /* 32bit */ -#define EPLE1A 0x058 /* 64bit */ -#define EPLE2D 0x060 /* 32bit */ -#define EPLE2A 0x068 /* 64bit */ - -#define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */ +#include "registers/epbar.h" void x4x_early_init(void); void x4x_late_init(int s3resume); -- To view, visit https://review.coreboot.org/c/coreboot/+/45425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I457fd753079fb9658d0b89a26003a0e83a32ade0 Gerrit-Change-Number: 45425 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: nb/intel/gm45: Put register definitions into separate files
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45450 ) Change subject: nb/intel/gm45: Put register definitions into separate files ...................................................................... nb/intel/gm45: Put register definitions into separate files MCHBAR registers are scattered throughout raminit, and located next to the code using them. Therefore, they have not been moved in this patch. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: I9bb3c907565ef2a278b748b1b7771dbd11d42df9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/gm45/gm45.h A src/northbridge/intel/gm45/registers/dmibar.h A src/northbridge/intel/gm45/registers/epbar.h A src/northbridge/intel/gm45/registers/host_bridge.h 4 files changed, 93 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/45450/1 diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 4c16abf..061bf2d 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -184,27 +184,8 @@ /* * D0:F0 */ -#define D0F0_EPBAR_LO 0x40 -#define D0F0_EPBAR_HI 0x44 -#define D0F0_MCHBAR_LO 0x48 -#define D0F0_MCHBAR_HI 0x4c -#define D0F0_GGC 0x52 -#define D0F0_DEVEN 0x54 -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 -#define D0F0_DMIBAR_LO 0x68 -#define D0F0_DMIBAR_HI 0x6c -#define D0F0_PMBASE 0x78 -#define D0F0_PAM(x) (0x90 + (x)) /* 0-6 */ -#define D0F0_REMAPBASE 0x98 -#define D0F0_REMAPLIMIT 0x9a -#define D0F0_SMRAM 0x9d -#define D0F0_ESMRAMC 0x9e -#define D0F0_TOM 0xa0 -#define D0F0_TOUUD 0xa2 -#define D0F0_TOLUD 0xb0 -#define D0F0_SKPD 0xdc /* Scratchpad Data */ -#define D0F0_CAPID0 0xe0 + +#include "registers/host_bridge.h" /* * D1:F0 PEG @@ -361,29 +342,7 @@ #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + (x))) #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + (x))) -#define DMIVCECH 0x000 /* 32bit */ -#define DMIPVCCAP1 0x004 /* 32bit */ - -#define DMIVC0RCAP 0x010 /* 32bit */ -#define DMIVC0RCTL 0x014 /* 32bit */ -#define DMIVC0RSTS 0x01a /* 16bit */ -#define VC0NP (1 << 1) - -#define DMIVC1RCAP 0x01c /* 32bit */ -#define DMIVC1RCTL 0x020 /* 32bit */ -#define DMIVC1RSTS 0x026 /* 16bit */ -#define VC1NP (1 << 1) - -#define DMIESD 0x044 /* 32bit */ - -#define DMILE1D 0x050 /* 32bit */ -#define DMILE1A 0x058 /* 64bit */ -#define DMILE2D 0x060 /* 32bit */ -#define DMILE2A 0x068 /* 64bit */ - -#define DMILCAP 0x084 /* 32bit */ -#define DMILCTL 0x088 /* 16bit */ -#define DMILSTS 0x08a /* 16bit */ +#include "registers/dmibar.h" /* * EPBAR @@ -393,30 +352,7 @@ #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + (x))) #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + (x))) -#define EPPVCCAP1 0x004 /* 32bit */ -#define EPPVCCTL 0x00c /* 32bit */ - -#define EPVC0RCAP 0x010 /* 32bit */ -#define EPVC0RCTL 0x014 /* 32bit */ -#define EPVC0RSTS 0x01a /* 16bit */ - -#define EPVC1RCAP 0x01c /* 32bit */ -#define EPVC1RCTL 0x020 /* 32bit */ -#define EPVC1RSTS 0x026 /* 16bit */ - -#define EPVC1MTS 0x028 /* 32bit */ -#define EPVC1ITC 0x02c /* 32bit */ - -#define EPVC1IST 0x038 /* 64bit */ - -#define EPESD 0x044 /* 32bit */ - -#define EPLE1D 0x050 /* 32bit */ -#define EPLE1A 0x058 /* 64bit */ -#define EPLE2D 0x060 /* 32bit */ -#define EPLE2A 0x068 /* 64bit */ - -#define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */ +#include "registers/epbar.h" #ifndef __ACPI__ diff --git a/src/northbridge/intel/gm45/registers/dmibar.h b/src/northbridge/intel/gm45/registers/dmibar.h new file mode 100644 index 0000000..2ece871 --- /dev/null +++ b/src/northbridge/intel/gm45/registers/dmibar.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __GM45_REGISTERS_DMIBAR_H__ +#define __GM45_REGISTERS_DMIBAR_H__ + +#define DMIVCECH 0x000 /* 32bit */ +#define DMIPVCCAP1 0x004 /* 32bit */ + +#define DMIVC0RCAP 0x010 /* 32bit */ +#define DMIVC0RCTL 0x014 /* 32bit */ +#define DMIVC0RSTS 0x01a /* 16bit */ +#define VC0NP (1 << 1) + +#define DMIVC1RCAP 0x01c /* 32bit */ +#define DMIVC1RCTL 0x020 /* 32bit */ +#define DMIVC1RSTS 0x026 /* 16bit */ +#define VC1NP (1 << 1) + +#define DMIESD 0x044 /* 32bit */ + +#define DMILE1D 0x050 /* 32bit */ +#define DMILE1A 0x058 /* 64bit */ +#define DMILE2D 0x060 /* 32bit */ +#define DMILE2A 0x068 /* 64bit */ + +#define DMILCAP 0x084 /* 32bit */ +#define DMILCTL 0x088 /* 16bit */ +#define DMILSTS 0x08a /* 16bit */ + +#endif /* __GM45_REGISTERS_DMIBAR_H__ */ diff --git a/src/northbridge/intel/gm45/registers/epbar.h b/src/northbridge/intel/gm45/registers/epbar.h new file mode 100644 index 0000000..6342844 --- /dev/null +++ b/src/northbridge/intel/gm45/registers/epbar.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __GM45_REGISTERS_EPBAR_H__ +#define __GM45_REGISTERS_EPBAR_H__ + +#define EPPVCCAP1 0x004 /* 32bit */ +#define EPPVCCTL 0x00c /* 32bit */ + +#define EPVC0RCAP 0x010 /* 32bit */ +#define EPVC0RCTL 0x014 /* 32bit */ +#define EPVC0RSTS 0x01a /* 16bit */ + +#define EPVC1RCAP 0x01c /* 32bit */ +#define EPVC1RCTL 0x020 /* 32bit */ +#define EPVC1RSTS 0x026 /* 16bit */ + +#define EPVC1MTS 0x028 /* 32bit */ +#define EPVC1ITC 0x02c /* 32bit */ + +#define EPVC1IST 0x038 /* 64bit */ + +#define EPESD 0x044 /* 32bit */ + +#define EPLE1D 0x050 /* 32bit */ +#define EPLE1A 0x058 /* 64bit */ +#define EPLE2D 0x060 /* 32bit */ +#define EPLE2A 0x068 /* 64bit */ + +#define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */ + +#endif /* __GM45_REGISTERS_EPBAR_H__ */ diff --git a/src/northbridge/intel/gm45/registers/host_bridge.h b/src/northbridge/intel/gm45/registers/host_bridge.h new file mode 100644 index 0000000..4d50d39 --- /dev/null +++ b/src/northbridge/intel/gm45/registers/host_bridge.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __GM45_REGISTERS_HOST_BRIDGE_H__ +#define __GM45_REGISTERS_HOST_BRIDGE_H__ + +#define D0F0_EPBAR_LO 0x40 +#define D0F0_EPBAR_HI 0x44 +#define D0F0_MCHBAR_LO 0x48 +#define D0F0_MCHBAR_HI 0x4c +#define D0F0_GGC 0x52 +#define D0F0_DEVEN 0x54 +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 +#define D0F0_DMIBAR_LO 0x68 +#define D0F0_DMIBAR_HI 0x6c +#define D0F0_PMBASE 0x78 +#define D0F0_PAM(x) (0x90 + (x)) /* 0-6 */ +#define D0F0_REMAPBASE 0x98 +#define D0F0_REMAPLIMIT 0x9a +#define D0F0_SMRAM 0x9d +#define D0F0_ESMRAMC 0x9e +#define D0F0_TOM 0xa0 +#define D0F0_TOUUD 0xa2 +#define D0F0_TOLUD 0xb0 +#define D0F0_SKPD 0xdc /* Scratchpad Data */ +#define D0F0_CAPID0 0xe0 + +#endif /* __GM45_REGISTERS_HOST_BRIDGE_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bb3c907565ef2a278b748b1b7771dbd11d42df9 Gerrit-Change-Number: 45450 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: Do rx dqs gating training
by CK HU (Code Review) 09 Mar '21

09 Mar '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44718 to review the following change. Change subject: soc/mediatek/mt8192: Do rx dqs gating training ...................................................................... soc/mediatek/mt8192: Do rx dqs gating training Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I141abc1fdd283f4898d0772736bc777e87017561 --- M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 323 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/44718/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c index e531de0..8d65a67 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -18,6 +18,15 @@ }, }; +struct rxdqs_gating_best_win { + u8 dqsien_dly_mck[DQS_NUMBER]; + u8 dqsien_dly_ui[DQS_NUMBER]; + u8 dqsien_dly_pi[DQS_NUMBER]; + u8 dqsien_dly_mck_p1[DQS_NUMBER]; + u8 dqsien_dly_ui_p1[DQS_NUMBER]; + u8 dqsien_dly_pi_p1[DQS_NUMBER]; +}; + static const u8 imp_vref_sel[ODT_MAX][IMP_DRV_MAX] = { /* DRVP DRVN ODTP ODTN */ [ODT_OFF] = {0x37, 0x33, 0x00, 0x37}, @@ -1378,3 +1387,311 @@ dramc_set_broadcast(bc_bak); } + +static u8 rxdqs_gating_get_tx_dly_min(dram_freq_grp freq_group, + struct rxdqs_gating_best_win *rxdqs_best_win) +{ + u8 tx_dly_dqs_gated = 0, tx_dly_min = 0xff; + + for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) { + dramc_dbg("best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs, + rxdqs_best_win->dqsien_dly_mck[dqs], + rxdqs_best_win->dqsien_dly_ui[dqs], + rxdqs_best_win->dqsien_dly_pi[dqs]); + + tx_dly_dqs_gated = (rxdqs_best_win->dqsien_dly_mck[dqs] << 4) + + rxdqs_best_win->dqsien_dly_ui[dqs]; + + if (freq_group != DDRFREQ_400) + tx_dly_dqs_gated >>= 3; + else + tx_dly_dqs_gated >>= 2; + + if (tx_dly_dqs_gated < tx_dly_min) + tx_dly_min = tx_dly_dqs_gated; + } + return tx_dly_min; +} + +static u8 rxdqs_gating_get_tx_dly_max(dram_freq_grp freq_group, + struct rxdqs_gating_best_win *rxdqs_best_win) +{ + u8 tx_dly_dqs_gated = 0, tx_dly_max = 0; + + for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) { + dramc_dbg("best DQS%d P1 dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs, + rxdqs_best_win->dqsien_dly_mck_p1[dqs], + rxdqs_best_win->dqsien_dly_ui_p1[dqs], + rxdqs_best_win->dqsien_dly_pi_p1[dqs]); + + tx_dly_dqs_gated = (rxdqs_best_win->dqsien_dly_mck_p1[dqs] << 4) + + rxdqs_best_win->dqsien_dly_ui_p1[dqs]; + + if (freq_group != DDRFREQ_400) + tx_dly_dqs_gated >>= 3; + else + tx_dly_dqs_gated >>= 2; + + if (tx_dly_dqs_gated > tx_dly_max) + tx_dly_max = tx_dly_dqs_gated; + } + return tx_dly_max; +} + +void dramc_rx_dqs_gating_cal(const struct ddr_cali* cali, + u8 *tx_dly_min, u8 *tx_dly_max) +{ + u8 chn, rank; + u8 pi_per_ui, ui_per_mck, freq_div; + dram_freq_grp freq_group; + struct rxdqs_gating_best_win best_win = {0}; + const struct sdram_params *params = cali->params; + + chn = cali->chn; + rank = cali->rank; + freq_group = get_freq_group(cali); + + struct reg_bak regs_bak[] = { + {&ch[chn].ao.refctrl0}, + {&ch[chn].phy_ao.dvs_b[0].b0_dq6}, + {&ch[chn].phy_ao.dvs_b[1].b0_dq6}, + {&ch[chn].phy_ao.misc_stbcal1}, + {&ch[chn].phy_ao.misc_stbcal2}, + }; + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + pi_per_ui = 32; + ui_per_mck = 16; + if (get_div_mode(cali) == DIV4_MODE) + freq_div = 2; + else + freq_div = 4; + + for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) { + best_win.dqsien_dly_mck[dqs] = params->gating_MCK[chn][rank][dqs]; + best_win.dqsien_dly_ui[dqs] = params->gating_UI[chn][rank][dqs]; + best_win.dqsien_dly_pi[dqs] = params->gating_PI[chn][rank][dqs]; + + /* Calculate P1 */ + best_win.dqsien_dly_ui_p1[dqs] = + best_win.dqsien_dly_mck[dqs] * ui_per_mck + + best_win.dqsien_dly_ui[dqs] + freq_div; + best_win.dqsien_dly_mck_p1[dqs] = + best_win.dqsien_dly_ui_p1[dqs] / ui_per_mck; + best_win.dqsien_dly_ui_p1[dqs] = + best_win.dqsien_dly_ui_p1[dqs] % ui_per_mck; + dramc_dbg("[FAST_K] CH%d RK%d best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", + chn, rank, dqs, best_win.dqsien_dly_mck[dqs], + best_win.dqsien_dly_ui[dqs], + best_win.dqsien_dly_pi[dqs]); + dramc_dbg("[FAST_K] CH%d RK%d best DQS%d P1 dly(MCK, UI, PI) = (%d, %d, %d)\n", + chn, rank, dqs, best_win.dqsien_dly_mck_p1[dqs], + best_win.dqsien_dly_ui_p1[dqs], + best_win.dqsien_dly_pi_p1[dqs]); + } + + *tx_dly_min = rxdqs_gating_get_tx_dly_min(freq_group, &best_win); + *tx_dly_max = rxdqs_gating_get_tx_dly_max(freq_group, &best_win); + + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rank].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, best_win.dqsien_dly_mck[0], + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, best_win.dqsien_dly_ui[0], + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, best_win.dqsien_dly_mck_p1[0], + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, best_win.dqsien_dly_ui_p1[0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rank].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, best_win.dqsien_dly_mck[1], + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, best_win.dqsien_dly_ui[1], + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, best_win.dqsien_dly_mck_p1[1], + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, best_win.dqsien_dly_ui_p1[1]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rank].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, best_win.dqsien_dly_pi[0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rank].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, best_win.dqsien_dly_pi[1]); + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); + + dramc_phy_reset(chn); +} + +static void dramc_rx_dqs_gating_post_process_find_best_coarse( + const struct ddr_cali* cali, s8 change_dqs_inctl, u8 mck2ui_shift) +{ + u8 chn, rk; + u8 best_coarse_mck[RANK_MAX][DQS_NUMBER]; + u8 best_coarse_ui[RANK_MAX][DQS_NUMBER]; + u8 best_coarse_mck_P1[RANK_MAX][DQS_NUMBER]; + u8 best_coarse_ui_P1[RANK_MAX][DQS_NUMBER]; + u32 rank_sel_mck_p0[2], rank_sel_mck_p1[2]; + + chn = cali->chn; + for (rk = 0; rk < cali->support_ranks; rk++) { + best_coarse_mck[rk][0] = + READ32_BITFIELD(&ch[chn].phy_ao.byte[0].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0); + best_coarse_ui[rk][0] = + READ32_BITFIELD(&ch[chn].phy_ao.byte[0].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0); + best_coarse_mck_P1[rk][0] = + READ32_BITFIELD(&ch[chn].phy_ao.byte[0].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0); + best_coarse_ui_P1[rk][0] = + READ32_BITFIELD(&ch[chn].phy_ao.byte[0].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0); + + best_coarse_mck[rk][1] = + READ32_BITFIELD(&ch[chn].phy_ao.byte[1].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0); + best_coarse_ui[rk][1] = + READ32_BITFIELD(&ch[chn].phy_ao.byte[1].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0); + best_coarse_mck_P1[rk][1] = + READ32_BITFIELD(&ch[chn].phy_ao.byte[1].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0); + best_coarse_ui_P1[rk][1] = + READ32_BITFIELD(&ch[chn].phy_ao.byte[1].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0); + } + + if (change_dqs_inctl != 0) { + for (rk = 0; rk < cali->support_ranks; rk++) { + for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) { + u8 total_ui, total_ui_P1; + total_ui = (best_coarse_mck[rk][dqs] << 4) + + best_coarse_ui[rk][dqs]; + total_ui_P1 = (best_coarse_mck_P1[rk][dqs] << 4) + + best_coarse_ui_P1[rk][dqs]; + + total_ui += (change_dqs_inctl << mck2ui_shift); + total_ui_P1 += (change_dqs_inctl << mck2ui_shift); + + best_coarse_mck[rk][dqs] = (total_ui >> 4); + best_coarse_ui[rk][dqs] = total_ui & 0xf; + + best_coarse_mck_P1[rk][dqs] = (total_ui_P1 >> 4); + best_coarse_ui_P1[rk][dqs] = total_ui_P1 & 0xf; + dramc_dbg("best DQS%d dly(2T, 0.5T) = (%d, %d)\n", + dqs, best_coarse_mck[rk][dqs], + best_coarse_ui[rk][dqs]); + } + for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) + dramc_dbg("best DQS%d P1 dly(2T, 0.5T) = (%d, %d)\n", + dqs, best_coarse_mck_P1[rk][dqs], + best_coarse_ui_P1[rk][dqs]); + } + + for (rk = 0; rk < cali->support_ranks; rk++) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, + best_coarse_mck[rk][0], + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, + best_coarse_ui[rk][0], + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, + best_coarse_mck_P1[rk][0], + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, + best_coarse_ui_P1[rk][0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, + best_coarse_mck[rk][1], + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, + best_coarse_ui[rk][1], + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, + best_coarse_mck_P1[rk][1], + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, + best_coarse_ui_P1[rk][1]); + } + } + + for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) { + if (best_coarse_mck[RANK_0][dqs] > best_coarse_mck[RANK_1][dqs]) { + rank_sel_mck_p0[dqs] = (best_coarse_mck[RANK_0][dqs] > 0) ? + (best_coarse_mck[RANK_0][dqs] - 1) : 0; + rank_sel_mck_p1[dqs] = (best_coarse_mck_P1[RANK_0][dqs] > 0) ? + (best_coarse_mck_P1[RANK_0][dqs] - 1) : 0; + } else { + rank_sel_mck_p0[dqs] = (best_coarse_mck[RANK_1][dqs] > 0) ? + (best_coarse_mck[RANK_1][dqs] - 1) : 0; + rank_sel_mck_p1[dqs] = (best_coarse_mck_P1[RANK_1][dqs] > 0) ? + (best_coarse_mck_P1[RANK_1][dqs] - 1) : 0; + } + } + + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_rank_selph_ui_dly, + SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B0, rank_sel_mck_p0[0], + SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B0, rank_sel_mck_p1[0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_rank_selph_ui_dly, + SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B1, rank_sel_mck_p0[1], + SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B1, rank_sel_mck_p1[1]); +} + +void dramc_rx_dqs_gating_post_process(const struct ddr_cali* cali, + u8 tx_dly_min, u8 tx_dly_max) +{ + u8 chn, rank; + dram_freq_grp freq_group; + + u8 mck2ui_shift; + s8 change_dqs_inctl; + u16 phs_inctl = 0; + u32 read_dqs_inctl, rank_inctl_root, xrtr2r, tx_dly_dqs_gate_min = 0; + u32 rank_inctl_stb; + + chn = cali->chn; + rank = cali->rank; + freq_group = get_freq_group(cali); + + if (get_div_mode(cali) == DIV8_MODE) { + if (freq_group > DDRFREQ_1200) + tx_dly_dqs_gate_min = 2; + else + tx_dly_dqs_gate_min = 1; + mck2ui_shift = 3; + } else { + tx_dly_dqs_gate_min = 2; + mck2ui_shift = 2; + } + + change_dqs_inctl = tx_dly_dqs_gate_min - tx_dly_min; + dramc_dbg("[RxdqsGatingPostProcess] freq %d\n" + "ChangeDQSINCTL %d, tx_dly_dqs_gate_min %d, tx_dly_min %d\n", + get_frequency(cali), + change_dqs_inctl, tx_dly_dqs_gate_min, tx_dly_min); + + dramc_rx_dqs_gating_post_process_find_best_coarse(cali, change_dqs_inctl, mck2ui_shift); + + read_dqs_inctl = READ32_BITFIELD(&ch[chn].phy_ao.misc_rk[rank].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL); + read_dqs_inctl -= change_dqs_inctl; + rank_inctl_stb = (read_dqs_inctl > 2) ? (read_dqs_inctl - 2) : 0; + phs_inctl = (read_dqs_inctl == 0) ? 0 : (read_dqs_inctl - 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_STB, rank_inctl_stb); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_rank_sel_stb, + SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, phs_inctl); + + if (read_dqs_inctl >= 2) + rank_inctl_root = read_dqs_inctl - 2; + else + rank_inctl_root = 0; + + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rk[0].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, read_dqs_inctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rk[1].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, read_dqs_inctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_PHY, read_dqs_inctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL, rank_inctl_root); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_ROOT1, rank_inctl_root); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_RXDLY, rank_inctl_root); + xrtr2r = READ32_BITFIELD(&ch[chn].ao.shu_actim_xrt, + SHU_ACTIM_XRT_XRTR2R); + dramc_dbg("TX_dly_DQSgated check: min %d max %d, ChangeDQSINCTL=%d\n", + tx_dly_min, tx_dly_max, change_dqs_inctl); + dramc_dbg("DQSINCTL=%d, RANKINCTL=%d, xrtr2r=%d\n", + read_dqs_inctl, rank_inctl_root, xrtr2r); +} + diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 2be3962..4b77c85 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -220,6 +220,7 @@ static void dramc_calibration_single_channel(struct ddr_cali *cali, u8 chn) { + u8 txdly_min, txdly_max; u8 dqs_final_delay[RANK_MAX][DQS_NUMBER]; cali->chn = chn; @@ -243,7 +244,12 @@ /* should disable the auto refresh before do write leveling */ dramc_auto_refresh_switch(chn, false); dramc_write_leveling(cali, dqs_final_delay); + + /* should enable the auto refresh before do RX and TX calibration */ + dramc_auto_refresh_switch(chn, true); + dramc_rx_dqs_gating_cal(cali, &txdly_min, &txdly_max); } + dramc_rx_dqs_gating_post_process(cali, txdly_min, txdly_max); } static void dramc_calibration_all_channels(struct ddr_cali *cali) -- To view, visit https://review.coreboot.org/c/coreboot/+/44718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I141abc1fdd283f4898d0772736bc777e87017561 Gerrit-Change-Number: 44718 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: soc/mediatek/mt8192: Do dramc rx window training
by CK HU (Code Review) 09 Mar '21

09 Mar '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44719 to review the following change. Change subject: soc/mediatek/mt8192: Do dramc rx window training ...................................................................... soc/mediatek/mt8192: Do dramc rx window training Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I584db990a9777551bcf3d4d59cdd3fd64d6e52cc --- M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 264 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/44719/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c index 8d65a67..363a3bd 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -27,6 +27,15 @@ u8 dqsien_dly_pi_p1[DQS_NUMBER]; }; +typedef struct { + s16 first_pass; + s16 last_pass; + s16 win_center; + u16 win_size; + u16 best_dqdly; +} pass_win_data_t; + + static const u8 imp_vref_sel[ODT_MAX][IMP_DRV_MAX] = { /* DRVP DRVN ODTP ODTN */ [ODT_OFF] = {0x37, 0x33, 0x00, 0x37}, @@ -1695,3 +1704,255 @@ read_dqs_inctl, rank_inctl_root, xrtr2r); } + +static void dramc_set_rank_engin2(u8 chn, u8 rank) +{ + SET32_BITFIELDS(&ch[chn].ao.test2_a3, TEST2_A3_ADRDECEN_TARKMODE, 1); + SET32_BITFIELDS(&ch[chn].ao.test2_a4, TEST2_A4_TESTAGENTRKSEL, 0); + SET32_BITFIELDS(&ch[chn].ao.test2_a4, TEST2_A4_TESTAGENTRK, rank); +} + +static void dramc_engin2_set_ui_shift(u8 chn) +{ + SET32_BITFIELDS(&ch[chn].ao.test2_a0, + TEST2_A0_TA2_LOOP_EN, 1, + TEST2_A0_LOOP_CNT_INDEX, 3); + SET32_BITFIELDS(&ch[chn].ao.test2_a3, + TEST2_A3_TEST2_PAT_SHIFT, 1, + TEST2_A3_PAT_SHIFT_SW_EN, 0); +} + +static void dramc_engin2_set_pat(u8 chn, u8 rank, u8 loop_cnt) +{ + SET32_BITFIELDS(&ch[chn].ao.test2_a4, + TEST2_A4_TEST_REQ_LEN1, 1, + TEST2_A4_TESTAUDINIT, 0, + TEST2_A4_TESTAUDINC, 0, + TEST2_A4_TESTXTALKPAT, 0, + TEST2_A4_TESTSSOPAT, 0); + SET32_BITFIELDS(&ch[chn].ao.test2_a3, + TEST2_A3_TESTAUDPAT, 0, + TEST2_A3_AUTO_GEN_PAT, 1, + TEST2_A3_HFIDPAT, 1, + TEST2_A3_TEST_AID_EN, 1, + TEST2_A3_TESTCNT, loop_cnt); + SET32_BITFIELDS(&ch[chn].ao.test2_a2, TEST2_A2_TEST2_OFF, 0x56); + dramc_engin2_set_ui_shift(chn); +} + +static void dramc_engine2_init(u8 chn, u8 rank) +{ + u32 test2_1 = 0x55000000; + u32 test2_2 = 0xaa000100; + + dramc_set_rank_engin2(chn, rank); + SET32_BITFIELDS(&ch[chn].ao.dummy_rd, + DUMMY_RD_DQSG_DMYRD_EN, 0, + DUMMY_RD_DQSG_DMYWR_EN, 0, + DUMMY_RD_DUMMY_RD_EN, 0, + DUMMY_RD_SREF_DMYRD_EN, 0, + DUMMY_RD_DMY_RD_DBG, 0, + DUMMY_RD_DMY_WR_DBG, 0); + SET32_BITFIELDS(&ch[chn].ao.test2_a3, + TEST2_A3_TEST2W, 0, + TEST2_A3_TEST2R, 0, + TEST2_A3_TEST1, 0); + SET32_BITFIELDS(&ch[chn].ao.test2_a0, + TEST2_A0_TEST2_PAT0, test2_1 >> 24, + TEST2_A0_TEST2_PAT1, test2_2 >> 24); + SET32_BITFIELDS(&ch[chn].ao.rk[rank].rk_test2_a1, + RK_TEST2_A1_TEST2_BASE, (test2_1 + 0x10000) & 0x00ffffff); + SET32_BITFIELDS(&ch[chn].ao.test2_a2, TEST2_A2_TEST2_OFF, test2_2 & 0x00ffffff); + + dramc_engin2_set_pat(chn, rank, 0); +} + +static const u8 uiLPDDR4_RDDQC_Mapping_POP[PINMUX_MAX][CHANNEL_MAX][DQ_DATA_WIDTH] = +{ + [PINMUX_DSC] = { + [CHANNEL_A] = { 0, 1, 6, 7, 4, 5, 3, 2, 9, 8, 11, 10, 15, 14, 12, 13}, + [CHANNEL_B] = { 1, 0, 5, 4, 7, 2, 3, 6, 8, 9, 11, 10, 12, 14, 13, 15}, + }, + [PINMUX_LPBK] = { + }, + [PINMUX_EMCP] = { + [CHANNEL_A] = {1, 0, 3, 2, 4, 7, 6, 5, 8, 9, 10, 12, 15, 14, 11, 13}, + [CHANNEL_B] = {0, 1, 7, 4, 2, 5, 6, 3, 9, 8, 10, 12, 11, 14, 13, 15}, + } +}; + +static void rddqc_pinmux_set(const struct ddr_cali* cali) +{ + u8 chn = cali->chn; + u8 pinmux = get_pinmux_type(cali); + + const u8 *pinmux_map = uiLPDDR4_RDDQC_Mapping_POP[pinmux][chn]; + + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux1, + MRR_BIT_MUX1_MRR_BIT0_SEL, pinmux_map[0], + MRR_BIT_MUX1_MRR_BIT1_SEL, pinmux_map[1], + MRR_BIT_MUX1_MRR_BIT2_SEL, pinmux_map[2], + MRR_BIT_MUX1_MRR_BIT3_SEL, pinmux_map[3]); + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux2, + MRR_BIT_MUX2_MRR_BIT4_SEL, pinmux_map[4], + MRR_BIT_MUX2_MRR_BIT5_SEL, pinmux_map[5], + MRR_BIT_MUX2_MRR_BIT6_SEL, pinmux_map[6], + MRR_BIT_MUX2_MRR_BIT7_SEL, pinmux_map[7]); + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux3, + MRR_BIT_MUX3_MRR_BIT8_SEL, pinmux_map[8], + MRR_BIT_MUX3_MRR_BIT9_SEL, pinmux_map[9], + MRR_BIT_MUX3_MRR_BIT10_SEL, pinmux_map[10], + MRR_BIT_MUX3_MRR_BIT11_SEL, pinmux_map[11]); + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux4, + MRR_BIT_MUX4_MRR_BIT12_SEL, pinmux_map[12], + MRR_BIT_MUX4_MRR_BIT13_SEL, pinmux_map[13], + MRR_BIT_MUX4_MRR_BIT14_SEL, pinmux_map[14], + MRR_BIT_MUX4_MRR_BIT15_SEL, pinmux_map[15]); +} + +static void dramc_rx_rddqc_init(const struct ddr_cali* cali) +{ + u8 rddqc_bit_ctrl_lower = 0x55; + u8 rddqc_bit_ctrl_upper = 0x55; + u8 rddqc_patternA = 0x5A; + u8 rddqc_patternB = 0x3C; + + u8 chn = cali->chn; + u8 rank = cali->rank; + + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 0); + + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank); + rddqc_pinmux_set(cali); + dramc_mode_reg_write_by_rank(cali, chn, rank, 15, rddqc_bit_ctrl_lower); + dramc_mode_reg_write_by_rank(cali, chn, rank, 20, rddqc_bit_ctrl_upper); + dramc_mode_reg_write_by_rank(cali, chn, rank, 32, rddqc_patternA); + dramc_mode_reg_write_by_rank(cali, chn, rank, 40, rddqc_patternB); + + SET32_BITFIELDS(&ch[chn].ao.rddqcgolden, + RDDQCGOLDEN_MR15_GOLDEN, rddqc_bit_ctrl_lower, + RDDQCGOLDEN_MR20_GOLDEN, rddqc_bit_ctrl_upper, + RDDQCGOLDEN_MR32_GOLDEN, rddqc_patternA, + RDDQCGOLDEN_MR40_GOLDEN, rddqc_patternB); + + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq8, + SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq8, + SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 1); +} +void dramc_rx_window_perbit_cal(const struct ddr_cali* cali, rx_cali_type cali_type) +{ + u8 chn, rank, fsp; + dram_odt_state odt; + dram_freq_grp freq_group = cali->freq_group; + const struct sdram_params *params = cali->params; + + u8 bit, byte; + bool enable_vref_scan = false; + u16 final_vref[DQS_NUMBER] = {0xe, 0xe}; + pass_win_data_t final_win_perbit[DQ_DATA_WIDTH]; + s32 dqs_dly_perbyte[DQS_NUMBER] = {0x0}, dqm_dly_perbyte[DQS_NUMBER] = {0x0}; + + chn = cali->chn; + rank = cali->rank; + fsp = get_fsp(cali); + odt = get_odt_state(cali); + dramc_dbg("RX window ch:%d, rank:%d, freq_group:%d, type:%d\n", + chn, rank, freq_group, cali_type); + + struct reg_bak regs_bak[] = { + {&ch[chn].ao.mrr_bit_mux1}, + {&ch[chn].ao.mrr_bit_mux2}, + {&ch[chn].ao.mrr_bit_mux3}, + {&ch[chn].ao.mrr_bit_mux4}, + }; + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + dramc_auto_refresh_switch(chn, false); + + if (cali_type == RX_WIN_TEST_ENG) { + dramc_engine2_init(chn, rank); + + if ((rank == RANK_0) || (freq_group == DDRFREQ_2133)) + enable_vref_scan = true; + } else { + dramc_rx_rddqc_init(cali); + } + + if (enable_vref_scan) { + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq5, + B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq5, + B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 1); + } + + for (byte = 0; byte < BYTE_NUM; byte++) { + if (enable_vref_scan) + final_vref[byte] = params->rx_best_vref[chn][rank][byte]; + + dqs_dly_perbyte[byte] = params->rx_perbit_dqs[chn][rank][byte]; + dqm_dly_perbyte[byte] = params->rx_perbit_dqm[chn][rank][byte]; + } + + for (bit = 0; bit < DQ_DATA_WIDTH; bit++) + final_win_perbit[bit].best_dqdly = params->rx_perbit_dq[chn][rank][bit]; + + if (enable_vref_scan) { + for (u8 rk = rank; rk < cali->support_ranks; rk++) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rk].shu_b0_phy_vref_sel, + RG_RX_ARDQ_VREF_SEL_LB_B0, final_vref[0], + RG_RX_ARDQ_VREF_SEL_UB_B0, final_vref[0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rk].shu_b0_phy_vref_sel, + RG_RX_ARDQ_VREF_SEL_LB_B1, final_vref[1], + RG_RX_ARDQ_VREF_SEL_UB_B1, final_vref[1]); + + for (byte = 0; byte < BYTE_NUM; byte++) { + dramc_dbg("Final RX Vref Byte %d = %d to rank%d\n", + byte, final_vref[byte], rk); + } + } + } + + /* set dqs delay, (dqm delay) */ + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rank].shu_r0_b0_rxdly5, + SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, dqs_dly_perbyte[0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rank].shu_r0_b0_rxdly4, + SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, dqm_dly_perbyte[0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rank].shu_r0_b0_rxdly5, + SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, dqs_dly_perbyte[1]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rank].shu_r0_b0_rxdly4, + SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, dqm_dly_perbyte[1]); + + /* set dq delay */ + for (bit = 0; bit < DQS_BIT_NUMBER; bit += 2) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rank].shu_r0_b0_rxdly0 + bit / 2, + SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, final_win_perbit[bit].best_dqdly, + SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, final_win_perbit[bit + 1].best_dqdly); + + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rank].shu_r0_b0_rxdly0 + bit / 2, + SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, final_win_perbit[bit + 8].best_dqdly, + SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, final_win_perbit[bit + 9].best_dqdly); + } + + dramc_phy_reset(chn); + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); + + dramc_dbg("DQS Delay:\nDQS0 = %d, DQS1 = %d\n" + "DQM Delay:\nDQM0 = %d, DQM1 = %d\n", + dqs_dly_perbyte[0], dqs_dly_perbyte[1], + dqm_dly_perbyte[0], dqm_dly_perbyte[1]); + + dramc_dbg("DQ Delay:\n"); + for (bit = 0; bit < DQ_DATA_WIDTH; bit = bit + 4) + dramc_dbg("DQ%d =%d, DQ%d =%d, DQ%d =%d, DQ%d =%d\n", + bit, final_win_perbit[bit].best_dqdly, + bit + 1, final_win_perbit[bit + 1].best_dqdly, + bit + 2, final_win_perbit[bit + 2].best_dqdly, + bit + 3, final_win_perbit[bit + 3].best_dqdly); +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 4b77c85..41d85a2 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -248,6 +248,9 @@ /* should enable the auto refresh before do RX and TX calibration */ dramc_auto_refresh_switch(chn, true); dramc_rx_dqs_gating_cal(cali, &txdly_min, &txdly_max); + + dramc_rx_window_perbit_cal(cali, RX_WIN_RD_DQC); + dramc_rx_window_perbit_cal(cali, RX_WIN_TEST_ENG); } dramc_rx_dqs_gating_post_process(cali, txdly_min, txdly_max); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I584db990a9777551bcf3d4d59cdd3fd64d6e52cc Gerrit-Change-Number: 44719 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/mediatek/mt8192: Do dramc command bus training
by CK HU (Code Review) 09 Mar '21

09 Mar '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44716 to review the following change. Change subject: soc/mediatek/mt8192: Do dramc command bus training ...................................................................... soc/mediatek/mt8192: Do dramc command bus training Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I06ee26e3b82811bffa09ab5e3e535b3174c3e3a6 --- M src/soc/mediatek/mt8192/dramc_dvfs.c M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 4 files changed, 761 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/44716/1 diff --git a/src/soc/mediatek/mt8192/dramc_dvfs.c b/src/soc/mediatek/mt8192/dramc_dvfs.c index 67e2340..c51c261 100644 --- a/src/soc/mediatek/mt8192/dramc_dvfs.c +++ b/src/soc/mediatek/mt8192/dramc_dvfs.c @@ -193,3 +193,19 @@ MISC_SRAM_DMA0_SW_MODE, 0); } } + +void shuffle_dfs_to_fsp1(const struct ddr_cali* cali) +{ + u8 operating_fsp = cali->fsp; + struct mr_values *mr_value = cali->mr_value; + + /* Double confirm PLL switched from CLRPLL to PHYPLL */ + if (operating_fsp == FSP_1) { + for (u8 rk = 0; rk < cali->support_ranks; rk++) { + u8 mr13 = mr_value->mr13[rk]; + mr13 |= (BIT(6) | BIT(7)); + mr_value->mr13[rk] = mr13; + } + cbt_switch_freq(cali, CBT_HIGH_FREQ); + } +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 8362c05..84acb3e 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -111,6 +111,26 @@ set_dqO1_pinmux_mapping(cali); } +u8 get_cbt_vref_pinmux_value(const struct ddr_cali* cali, u8 range, u8 vref_lev) +{ + u8 chn = cali->chn; + u8 vref_bit, vref_org; + u8 vref_new = 0; + const u8 *map = mrr_o1_pinmux_mapping[get_pinmux_type(cali)][chn]; + + if (get_cbt_mode(cali) == CBT_BYTE_MODE1) + return ((range & 0x1) << 6) | (vref_lev & 0x3f); + + vref_org = ((range & 0x1) << 6) | (vref_lev & 0x3f); + + for (vref_bit = 0; vref_bit < 8; vref_bit++) + if (vref_org & (1 << vref_bit)) + vref_new |= (1 << map[vref_bit]); + + dramc_dbg("=== vref_new: 0x%x --> 0x%x\n", vref_org, vref_new); + return vref_new; +} + static void dramc_init_default_mr_value(const struct ddr_cali *cali) { struct mr_values *mr_value = cali->mr_value; diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c index e1f3d67..e531de0 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -5,6 +5,19 @@ #include <soc/dramc_register.h> #include <timer.h> +static const u8 ca_pinmux_mapping[PINMUX_MAX][CHANNEL_MAX][CA_NUM_LP4] = { + [PINMUX_DSC] = { + [CHANNEL_A] = {1, 4, 5, 3, 2, 0}, + [CHANNEL_B] = {3, 5, 0, 2, 4, 1}, + }, + [PINMUX_LPBK] = { + }, + [PINMUX_EMCP] = { + [CHANNEL_A] = {2, 4, 3, 5, 1, 0}, + [CHANNEL_B] = {4, 5, 2, 0, 3, 1} + }, +}; + static const u8 imp_vref_sel[ODT_MAX][IMP_DRV_MAX] = { /* DRVP DRVN ODTP ODTN */ [ODT_OFF] = {0x37, 0x33, 0x00, 0x37}, @@ -580,6 +593,710 @@ write32(regs_bak[i].addr, regs_bak[i].value); } +static void ca_training_set_perbit_delay_cell(const struct ddr_cali* cali, + u8 chn, u8 rank, u8 *ca_center) +{ + u8 ca_prebit_delay[DQS_BIT_NUMBER] = {0}; + const u8 *ca_mapping = ca_pinmux_mapping[get_pinmux_type(cali)][chn]; + + for (u8 u1CA = 0;u1CA < CA_NUM_LP4;u1CA++) { + ca_prebit_delay[ca_mapping[u1CA]] = ca_center[u1CA]; + dramc_dbg("CA_PerBit_DelayLine[%d]= %d\n", + ca_mapping[u1CA], ca_prebit_delay[ca_mapping[u1CA]]); + } + + SET32_BITFIELDS(&ch[chn].phy_ao.ca_rk[rank].shu_r0_ca_txdly0, + SHU_R0_CA_TXDLY0_TX_ARCA0_DLY, ca_prebit_delay[0], + SHU_R0_CA_TXDLY0_TX_ARCA1_DLY, ca_prebit_delay[1], + SHU_R0_CA_TXDLY0_TX_ARCA2_DLY, ca_prebit_delay[2], + SHU_R0_CA_TXDLY0_TX_ARCA3_DLY, ca_prebit_delay[3]); + SET32_BITFIELDS(&ch[chn].phy_ao.ca_rk[rank].shu_r0_ca_txdly1, + SHU_R0_CA_TXDLY1_TX_ARCA4_DLY, ca_prebit_delay[4], + SHU_R0_CA_TXDLY1_TX_ARCA5_DLY, ca_prebit_delay[5], + SHU_R0_CA_TXDLY1_TX_ARCA6_DLY, ca_prebit_delay[6], + SHU_R0_CA_TXDLY1_TX_ARCA7_DLY, ca_prebit_delay[7]); +} + +static u32 get_ca_ui(u8 chn) +{ + u32 dly = read32(&ch[chn].ao.shu_selph_ca7); + return dly & 0x0FFFFFFFU; +} + +static void put_ca_ui(u8 chn, u32 ca_ui) +{ + u32 dly; + + dly = read32(&ch[chn].ao.shu_selph_ca7); + dly &= 0xF0000000U; + ca_ui &= 0x0FFFFFFFU; + dly |= ca_ui; + + write32(&ch[chn].ao.shu_selph_ca7, dly); + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca5, SHU_SELPH_CA5_DLY_CKE, ca_ui & 0xF); + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca6, SHU_SELPH_CA6_DLY_CKE1, ca_ui & 0xF); +} + +static void put_ca_mck(u8 chn, u32 ca_mck) +{ + u32 dly; + + dly = read32(&ch[chn].ao.shu_selph_ca3); + dly &= 0xF0000000U; + ca_mck &= 0x0FFFFFFFU; + dly |= ca_mck; + + write32(&ch[chn].ao.shu_selph_ca3, dly); +} + +static u32 get_cs_ui(u8 chn, u8 rank) +{ + if (rank == RANK_1) + return READ32_BITFIELD(&ch[chn].ao.shu_selph_ca5, SHU_SELPH_CA5_DLY_CS1); + else + return READ32_BITFIELD(&ch[chn].ao.shu_selph_ca5, SHU_SELPH_CA5_DLY_CS); +} + +static u32 get_cs_mck(u8 chn, u8 rank) +{ + if (rank == RANK_1) + return READ32_BITFIELD(&ch[chn].ao.shu_selph_ca1, SHU_SELPH_CA1_TXDLY_CS1); + else + return READ32_BITFIELD(&ch[chn].ao.shu_selph_ca1, SHU_SELPH_CA1_TXDLY_CS); +} + +static int get_capi_max(dram_freq_grp freq_group) +{ + if (freq_group == DDRFREQ_400) + return 32; + + return 64; +} + +static u8 get_ca_pi_per_ui(void) +{ + return 32; +} + +static u8 get_mck_ck_ratio(u8 chn) +{ + u32 ratio = READ32_BITFIELD(&ch[chn].ao.shu_lp5_cmd, SHU_LP5_CMD_LP5_CMD1TO2EN); + + dramc_dbg("MCK:CK=%s\n", ratio == 1 ? "1:1" : "1:2"); + return ratio; +} + +static u8 get_cbtui_adjustable_maxvalue(u8 chn) +{ + u8 ratio = get_mck_ck_ratio(chn); + return ratio == 1 ? 1 : 3; +} + +static void put_cs_ui(u8 chn, u8 rank, u32 cs_ui) +{ + if (rank == RANK_1) + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca5, SHU_SELPH_CA5_DLY_CS1, cs_ui); + else + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca5, SHU_SELPH_CA5_DLY_CS, cs_ui); +} + +static void put_cs_mck(u8 chn, u8 rank, u32 cs_ui) +{ + if (rank == RANK_1) + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca1, SHU_SELPH_CA1_TXDLY_CS1, cs_ui); + else + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca1, SHU_SELPH_CA1_TXDLY_CS, cs_ui); +} + +static u32 get_ca_mck(u8 chn) +{ + u32 dly = read32(&ch[chn].ao.shu_selph_ca3); + return dly & 0x0FFFFFFFU; +} + +static void xlate_ca_mck_ui(u8 chn, u32 ui_delta, + u32 mck_old, u32 ui_old, u32 *mck_new, u32 *ui_new) +{ + u8 i; + u32 mask, max; + u32 bit_ui, bit_mck; + u32 ui_tmp = 0, mck_tmp = 0; + + max = get_cbtui_adjustable_maxvalue(chn); + mask = max; + + for (i = 0; i < 7; i++) { + bit_mck = 0; + bit_ui = ((ui_old >> (i * 4)) & mask) + ui_delta; + if (bit_ui > max) { + bit_mck = bit_ui / (max + 1); + bit_ui = bit_ui % (max + 1); + } + + mck_tmp += (bit_mck << (i * 4)); + ui_tmp += (bit_ui << (i * 4)); + } + + if (ui_new) + *ui_new = ui_tmp; + + if (mck_new) + *mck_new = mck_old + mck_tmp; +} + +static s16 adjust_cs_ui(const struct ddr_cali* cali, u32 cs_mck, u32 cs_ui, s16 pi_dly) +{ + u8 ratio; + s16 p2u,ui = 0, pi = 0; + u32 ui_max, cs_bit_mask, cs_ui_tmp, cs_mck_tmp; + dram_freq_grp freq_group = get_freq_group(cali); + + u8 chn = cali->chn; + u8 rank = cali->rank; + dramc_dbg("pi_dly:%d, get_capi_max:%d\n", pi_dly, get_capi_max(freq_group)); + + if (pi_dly < get_capi_max(freq_group)) + return pi_dly; + + p2u = get_ca_pi_per_ui(); + + ui = pi_dly / p2u; + pi = pi_dly % p2u; + + ratio = get_mck_ck_ratio(chn); + if (ratio) + /* 1:1 */ + cs_bit_mask = 1; + else + /* 1:2 */ + cs_bit_mask = 3; + + ui_max = get_cbtui_adjustable_maxvalue(chn); + cs_ui_tmp = (cs_ui & cs_bit_mask) + ui; + cs_mck_tmp = 0; + if (cs_ui_tmp > ui_max) { + cs_mck_tmp = cs_ui_tmp / (ui_max + 1); + cs_ui_tmp = cs_ui_tmp % (ui_max + 1); + } + + cs_mck_tmp += cs_mck; + put_cs_ui(chn, rank, cs_ui_tmp); + put_cs_mck(chn, rank, cs_mck_tmp); + + return pi; +} + +static s8 adjust_ca_ui(const struct ddr_cali* cali, u32 ca_mck, u32 ca_ui, s16 pi_dly) +{ + s16 p2u; + s16 ui, pi; + u32 ui_new = 0, mck_new = 0; + dram_freq_grp freq_group = get_freq_group(cali); + + u8 chn = cali->chn; + if (pi_dly < get_capi_max(freq_group)) + return pi_dly; + + p2u = get_ca_pi_per_ui(); + ui = pi_dly / p2u; + pi = pi_dly % p2u; + xlate_ca_mck_ui(chn, ui, ca_mck, ca_ui, &mck_new, &ui_new); + + put_ca_ui(chn, ui_new); + put_ca_mck(chn, mck_new); + dramc_dbg("mck_new: %#x, ui_new: %#x, pi:%d\n", mck_new, ui_new, pi); + + return pi; +} + +static void cbt_set_ca_clk_result(const struct ddr_cali* cali, u32 mck, u32 ui) +{ + s8 final_ca_clk; + u8 chn, rank; + u8 ca_center[DQS_BIT_NUMBER] = {0}; + + chn = cali->chn; + rank = cali->rank; + const struct sdram_params *params = cali->params; + s8 cmd_dly = params->cbt_cmd_dly[chn][rank]; + + for (u8 ca = 0; ca < CA_NUM_LP4; ca++) { + ca_center[ca] = params->cbt_ca_prebit_dly[chn][rank][ca]; + dramc_dbg("ca_center[%d]= %d\n", ca, ca_center[ca]); + } + + final_ca_clk = cmd_dly; + dramc_dbg("CA Dly = %d\n", final_ca_clk); + + final_ca_clk = adjust_ca_ui(cali, mck, ui, final_ca_clk); + dramc_dbg("after adjust, CA Dly = %d\n", final_ca_clk); + for (u8 rk = RANK_0; rk <= rank; rk++) { + cbt_delay_ca_clk(chn, rk, final_ca_clk); + ca_training_set_perbit_delay_cell(cali, chn, rk, ca_center); + } +} + +static void cbt_adjust_cs(const struct ddr_cali* cali) +{ + u8 chn, rank, cs_dly[RANK_MAX]; + u8 cs_final_delay; + u32 pi_dly; + u32 cs_ui, cs_mck; + + const struct sdram_params *params = cali->params; + chn = cali->chn; + rank = cali->rank; + cs_dly[RANK_0] = params->cbt_cs_dly[chn][RANK_0]; + cs_dly[RANK_1] = params->cbt_cs_dly[chn][RANK_1]; + + cs_ui = get_cs_ui(chn, rank); + cs_mck = get_cs_mck(chn, rank); + + if (rank == RANK_0) + cs_final_delay = cs_dly[RANK_0]; + else + cs_final_delay = (cs_dly[RANK_0] + cs_dly[RANK_1]) >> 1; + + for (u8 rk = RANK_0; rk <= rank; rk++) { + pi_dly = adjust_cs_ui(cali, cs_mck, cs_ui, cs_final_delay); + SET32_BITFIELDS(&ch[chn].phy_ao.ca_rk[rk].shu_r0_ca_cmd0, + SHU_R0_CA_CMD0_RG_ARPI_CS, pi_dly); + } + + dramc_dbg("CS Dly: %d\n", cs_final_delay); +} + +static void set_dram_mr_cbt_on_off(const struct ddr_cali* cali, o1_state o1) +{ + u8 chn, rank, fsp; + struct mr_values *mr_value = cali->mr_value; + + chn = cali->chn; + rank = cali->rank; + fsp = get_fsp(cali); + u8 mr13 = mr_value->mr13[rank] & (~ BIT(0)) & (~ BIT(6)) & (~ BIT(7)) ; + + if (o1 == O1_ON) { + if (fsp == FSP_1) + mr13 |= BIT(0) | BIT(6); + else + mr13 |= BIT(0) | BIT(7); + + if (get_cbt_mode(cali) == CBT_BYTE_MODE1) + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, + CBT_WLEV_CTRL0_BYTEMODECBTEN, 1, + CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE, 1); + } else { + if (fsp == FSP_1) + mr13 |= BIT(6); + } + + dramc_mode_reg_write_by_rank(cali, chn, rank, 13, mr13); + mr_value->mr13[rank] = mr13; +} + +void o1_path_on_off(const struct ddr_cali* cali, o1_state o1) +{ + u8 chn = cali->chn; + u8 rank = cali->rank; + u8 vref_sel = 0x37; + + if (o1 == O1_ON) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_vref, + SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_vref, + SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rank].shu_b0_phy_vref_sel, + RG_RX_ARDQ_VREF_SEL_LB_B0, vref_sel, + RG_RX_ARDQ_VREF_SEL_UB_B0, vref_sel); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rank].shu_b0_phy_vref_sel, + RG_RX_ARDQ_VREF_SEL_LB_B1, vref_sel, + RG_RX_ARDQ_VREF_SEL_UB_B1, vref_sel); + } + + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq6, + B0_DQ6_RG_RX_ARDQ_O1_SEL_B0, o1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq6, + B1_DQ6_RG_RX_ARDQ_O1_SEL_B1, o1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq3, + B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0, o1, + B0_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B0, o1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq3, + B1_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B1, o1, + B1_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B1, o1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_phy3, + B0_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B0, o1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_phy3, + B1_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B1, o1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rx_in_gate_en_ctrl, + MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN, (o1 << 1) | o1); + + udelay(1); +} + +static void dramc_mode_reg_ca_term(const struct ddr_cali* cali, u8 do_term) +{ + + u8 chn = cali->chn; + u8 fsp = get_fsp(cali); + u8 mr11, mr13, mr22; + struct mr_values *mr_value = cali->mr_value; + static u8 state_do_term[CHANNEL_MAX] = {0}; + + if (state_do_term[chn] == do_term) + return; + + state_do_term[chn] = do_term; + u32 bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + + mr11 = 0x3; + if (get_cbt_mode(cali) == CBT_NORMAL_MODE) + mr11 |= 0x40; + else + mr11 |= 0x20; + + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) { + mr13 = mr_value->mr13[rk] & (~ BIT(6)) & (~ BIT(7)); + mr13 |= BIT(6); + dramc_mode_reg_write_by_rank(cali, chn, rk, 13, mr13); + mr_value->mr13[rk] = mr13; + + dramc_mode_reg_write_by_rank(cali, chn, rk, 11, mr11); + mr_value->mr11[fsp] = mr11; + + if (do_term) { + mr22 = 0x4; + } else { + if (rk == RANK_0) + mr22 = 0x4; + else + mr22 = 0x2c; + } + + dramc_mode_reg_write_by_rank(cali, chn, rk, 22, mr22); + mr_value->mr22[fsp] = mr22; + } + + dramc_set_broadcast(bc_bak); +} + +static void cbt_entry(const struct ddr_cali* cali) +{ + u8 chn, rank, fsp; + u8 mr13, dram_dq_b0 = 0; + struct mr_values *mr_value = cali->mr_value; + + chn = cali->chn; + rank = cali->rank; + fsp = get_fsp(cali); + mr13 = mr_value->mr13[rank]; + + if (fsp == FSP_1) + dramc_mode_reg_ca_term(cali, 1); + + SET32_BITFIELDS(&ch[chn].phy_ao.misc_stbcal, MISC_STBCAL_DQSIENCG_NORMAL_EN, 0); + + cke_fix_onoff(cali, chn, rank, CKE_FIXON); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank); + + set_dram_mr_cbt_on_off(cali, true); + + if (get_cbt_mode(cali) == CBT_NORMAL_MODE) { + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, + CBT_WLEV_CTRL0_WRITE_LEVEL_EN, 1); + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, + CBT_WLEV_CTRL0_DQSOEAOEN, 0x1); + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, + CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN, 1 << dram_dq_b0); + } + + udelay(1); + cke_fix_onoff(cali, chn, rank, CKE_FIXOFF); + + if (fsp == FSP_1) + mr13 |= BIT(7); + else + mr13 &= (~ BIT(7)); + mr_value->mr13[rank] = mr13; + + o1_path_on_off(cali, O1_ON); + + udelay(1); +} + +static void cbt_exit(const struct ddr_cali* cali) +{ + u8 chn = cali->chn; + u8 rank = cali->rank; + u8 cbt_mode = get_cbt_mode(cali); + + if (cbt_mode == CBT_NORMAL_MODE || cbt_mode == CBT_BYTE_MODE1) { + cke_fix_onoff(cali, chn, rank, CKE_FIXON); + udelay(1); + set_dram_mr_cbt_on_off(cali, false); + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, CBT_WLEV_CTRL0_WRITE_LEVEL_EN, 0); + } + + o1_path_on_off(cali, O1_OFF); + if (cbt_mode == CBT_BYTE_MODE1) + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, + CBT_WLEV_CTRL0_BYTEMODECBTEN, 0, + CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE, 0); + + udelay(1); +} + +static void cbt_entry_top(const struct ddr_cali* cali) +{ + u8 chn, fsp; + + chn = cali->chn; + fsp = get_fsp(cali); + + if(fsp == FSP_1) { + SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + cbt_switch_freq(cali, CBT_LOW_FREQ); + SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + } + cbt_entry(cali); + + if(fsp == FSP_1) + cbt_switch_freq(cali, CBT_HIGH_FREQ); +} + +static void cbt_exit_top(const struct ddr_cali* cali, cbt_state state) +{ + if (state == OUT_CBT || get_cbt_mode(cali) == CBT_BYTE_MODE1){ + if (get_fsp(cali) == FSP_1) + cbt_switch_freq(cali, CBT_LOW_FREQ); + cbt_exit(cali); + } +} + +static void cbt_set_vref(const struct ddr_cali* cali, cbt_state state) +{ + u8 chn, rank, fsp, range; + u8 dram_dq_b0 = 0; + u8 vref_value_pinmux; + u8 ca_vref, mr12, mr13; + struct mr_values *mr_value = cali->mr_value; + const struct sdram_params *params = cali->params; + + chn = cali->chn; + rank = cali->rank; + fsp = get_fsp(cali); + ca_vref = params->cbt_final_vref[chn][rank]; + mr12 = mr_value->mr12[chn][rank][fsp]; + range = mr12 >> 6; + + if (state == IN_CBT && get_cbt_mode(cali) == CBT_NORMAL_MODE) { + vref_value_pinmux = get_cbt_vref_pinmux_value(cali, range, ca_vref); + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl4, + CBT_WLEV_CTRL4_CBT_TXDQ_B0, vref_value_pinmux); + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, + CBT_WLEV_CTRL0_CBT_WLEV_DQS_SEL, 0x1 << dram_dq_b0); + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl3, + CBT_WLEV_CTRL3_DQSBX_G, 0xa); + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, + CBT_WLEV_CTRL0_CBT_WLEV_DQS_TRIG, 1); + udelay(1); + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, + CBT_WLEV_CTRL0_CBT_WLEV_DQS_TRIG, 0); + } else { + if (fsp == FSP_1) { + mr13 = mr_value->mr13[rank] | (0x1 << 6); + dramc_mode_reg_write_by_rank(cali, chn, rank, 13, mr13); + mr_value->mr13[rank] = mr13; + } + + dramc_dbg("CmdBusTraining Vref(ca) range %d: %d\n", range, ca_vref); + + ca_vref = ((range & 0x1) << 6) | (ca_vref & 0x3f); + dramc_mode_reg_write_by_rank(cali, chn, rank, 12, ca_vref); + mr_value->mr12[chn][rank][fsp] = ca_vref; + } + udelay(1); +} + +static void cbt_set_best_vref(const struct ddr_cali* cali, cbt_state state) +{ + u8 fsp = get_fsp(cali); + + if (state == IN_CBT && get_cbt_mode(cali) == CBT_BYTE_MODE1) { + if (fsp == FSP_1) + cbt_switch_freq(cali, CBT_LOW_FREQ); + + cbt_exit(cali); + cbt_set_vref(cali, state); + cbt_entry(cali); + if (fsp == FSP_1) + cbt_switch_freq(cali, CBT_HIGH_FREQ); + } else { + cbt_set_vref(cali, state); + } +} + +static void set_cbt_wlev_intv(u8 chn, dram_freq_grp freq_group) +{ + u8 tcmdo1lat; + u8 catrain_intv; + u8 new_cbt_pat_intv; + u8 wlev_dqspat_lat; + + switch (freq_group) { + case DDRFREQ_400: + tcmdo1lat = 12; + catrain_intv = 13; + new_cbt_pat_intv = 12; + wlev_dqspat_lat = 12; + break; + case DDRFREQ_600: + tcmdo1lat = 9; + catrain_intv = 8; + new_cbt_pat_intv = 11; + wlev_dqspat_lat = 11; + break; + case DDRFREQ_800: + tcmdo1lat = 10; + catrain_intv = 8; + new_cbt_pat_intv = 12; + wlev_dqspat_lat = 12; + break; + case DDRFREQ_933: + tcmdo1lat = 11; + catrain_intv = 9; + new_cbt_pat_intv = 13; + wlev_dqspat_lat = 13; + break; + case DDRFREQ_1200: + tcmdo1lat = 12; + catrain_intv = 9; + new_cbt_pat_intv = 14; + wlev_dqspat_lat = 14; + break; + case DDRFREQ_1600: + tcmdo1lat = 14; + catrain_intv = 11; + new_cbt_pat_intv = 16; + wlev_dqspat_lat = 16; + break; + case DDRFREQ_2133: + tcmdo1lat = 17; + catrain_intv = 14; + new_cbt_pat_intv = 19; + wlev_dqspat_lat = 19; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl1, + CBT_WLEV_CTRL1_TCMDO1LAT, tcmdo1lat, + CBT_WLEV_CTRL1_CATRAIN_INTV, catrain_intv); + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl5, + CBT_WLEV_CTRL5_NEW_CBT_PAT_INTV, new_cbt_pat_intv); + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, + CBT_WLEV_CTRL0_WLEV_DQSPAT_LAT, wlev_dqspat_lat); +} + +static void dramc_cmd_ui_delay_setting(u8 chn, u8 value) +{ + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca7, + SHU_SELPH_CA7_DLY_RA0, value, + SHU_SELPH_CA7_DLY_RA1, value, + SHU_SELPH_CA7_DLY_RA2, value, + SHU_SELPH_CA7_DLY_RA3, value, + SHU_SELPH_CA7_DLY_RA4, value, + SHU_SELPH_CA7_DLY_RA5, value, + SHU_SELPH_CA7_DLY_RA6, value); + + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca5, + SHU_SELPH_CA5_DLY_CKE, value); + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca6, + SHU_SELPH_CA6_DLY_CKE1, value); +} + +void dramc_cmd_bus_training(const struct ddr_cali* cali) +{ + u8 chn, rank, fsp; + u32 ca_ui, ca_mck; + u8 ca_final_center[CA_NUM_LP4] = {0}; + + chn = cali->chn; + rank = cali->rank; + fsp = get_fsp(cali); + + struct reg_bak regs_bak[] = { + {&ch[chn].ao.dramc_pd_ctrl}, + {&ch[chn].phy_ao.misc_stbcal}, + {&ch[chn].ao.ckectrl}, + {&ch[chn].phy_ao.dvs_b[0].b0_dq2}, + {&ch[chn].phy_ao.dvs_b[1].b0_dq2}, + {&ch[chn].ao.cbt_wlev_ctrl0}, + {&ch[chn].ao.cbt_wlev_ctrl1}, + {&ch[chn].ao.cbt_wlev_ctrl2}, + {&ch[chn].ao.cbt_wlev_ctrl3}, + {&ch[chn].ao.cbt_wlev_ctrl4}, + {&ch[chn].ao.swcmd_ctrl0}, + {&ch[chn].ao.refctrl0}, + {&ch[chn].phy_ao.byte[0].shu_b0_vref}, + {&ch[chn].phy_ao.byte[1].shu_b0_vref}, + {&ch[chn].phy_ao.byte[0].rk[rank].shu_b0_phy_vref_sel}, + {&ch[chn].phy_ao.byte[1].rk[rank].shu_b0_phy_vref_sel}, + }; + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + ca_training_set_perbit_delay_cell(cali, chn, rank, ca_final_center); + dramc_cmd_ui_delay_setting(chn, 1); + cbt_delay_ca_clk(chn, rank, 0); + + ca_mck = get_ca_mck(chn); + dramc_auto_refresh_switch(chn, false); + + set_cbt_wlev_intv(chn, get_freq_group(cali)); + SET32_BITFIELDS(&ch[chn].ao.tx_set0, TX_SET0_TXRANK, rank); + SET32_BITFIELDS(&ch[chn].ao.tx_set0, TX_SET0_TXRANKFIX, 1); + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, + DRAMC_PD_CTRL_DCMEN2, 0, + DRAMC_PD_CTRL_MIOCKCTRLOFF, 1, + DRAMC_PD_CTRL_PHYCLKDYNGEN, 0, + DRAMC_PD_CTRL_COMBCLKCTRL, 0, + DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 1, + DRAMC_PD_CTRL_TCKFIXON, 1); + + cbt_entry_top(cali); + cbt_set_best_vref(cali, IN_CBT); + dramc_cmd_UI_delay_setting(chn, 0); + ca_ui = get_ca_ui(chn); + + put_ca_ui(chn, ca_ui); + cbt_set_ca_clk_result(cali, ca_mck, ca_ui); + udelay(1); + + cbt_adjust_cs(cali); + cbt_exit_top(cali, OUT_CBT); + cbt_set_best_vref(cali, OUT_CBT); + + if (fsp == FSP_1) + dramc_mode_reg_ca_term(cali, 0); + + SET32_BITFIELDS(&ch[chn].ao.tx_set0, TX_SET0_TXRANK, 0); + SET32_BITFIELDS(&ch[chn].ao.tx_set0, TX_SET0_TXRANKFIX, 0); + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); + +} + static void duty_delay_reg_convert(s8 duty_delay, u8 *delay) { u8 delay_tmp; @@ -615,7 +1332,6 @@ } } - static void dramc_duty_set_wck_delay_cell(u8 chn, const s8* duty_delay) { u8 dqs; diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 11ec636..214bf55 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -225,6 +225,14 @@ CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 1, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + + for (u8 rank = RANK_0; rank < cali->support_ranks; rank++) { + cali->rank = rank; + dramc_auto_refresh_switch(chn, false); + dramc_cmd_bus_training(cali); + } + + shuffle_dfs_to_fsp1(cali); } static void dramc_calibration_all_channels(struct ddr_cali *cali) -- To view, visit https://review.coreboot.org/c/coreboot/+/44716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06ee26e3b82811bffa09ab5e3e535b3174c3e3a6 Gerrit-Change-Number: 44716 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

7 17

Change in coreboot[master]: soc/mediatek/mt8192: Do dramc rx datlat training
by CK HU (Code Review) 09 Mar '21

09 Mar '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44721 to review the following change. Change subject: soc/mediatek/mt8192: Do dramc rx datlat training ...................................................................... soc/mediatek/mt8192: Do dramc rx datlat training Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I9a426e1273dceae3a739bbbfc36db44d3ba9140d --- M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/44721/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c index 602e61d..9ccedf1 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -1408,6 +1408,36 @@ dramc_set_broadcast(bc_bak); } +static void dramc_dle_factor_handler(u8 chn, u8 value) +{ + u8 datlat_dsel = 0, dlecg_ext1 = 0, dlecg_ext2 = 0, dlecg_ext3 = 0; + + if (READ32_BITFIELD(&ch[chn].phy_ao.shu_misc_rx_pipe_ctrl, + SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN)) + datlat_dsel = value; + else + datlat_dsel = (value < 1) ? value : value - 1; + + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rdat, + MISC_SHU_RDAT_DATLAT, value, + MISC_SHU_RDAT_DATLAT_DSEL, datlat_dsel, + MISC_SHU_RDAT_DATLAT_DSEL_PHY, datlat_dsel); + + dlecg_ext1 = (value >= 8) ? 1 : 0; + dlecg_ext2 = (value >= 14) ? 1 : 0; + dlecg_ext3 = (value >= 19) ? 1 : 0; + + SET32_BITFIELDS(&ch[chn].ao.shu_rx_cg_set0, + SHU_RX_CG_SET0_READ_START_EXTEND1, dlecg_ext1, + SHU_RX_CG_SET0_DLE_LAST_EXTEND1, dlecg_ext1, + SHU_RX_CG_SET0_READ_START_EXTEND2, dlecg_ext2, + SHU_RX_CG_SET0_DLE_LAST_EXTEND2, dlecg_ext2, + SHU_RX_CG_SET0_READ_START_EXTEND3, dlecg_ext3, + SHU_RX_CG_SET0_DLE_LAST_EXTEND3, dlecg_ext3); + + dramc_phy_reset(chn); +} + static u8 rxdqs_gating_get_tx_dly_min(dram_freq_grp freq_group, struct rxdqs_gating_best_win *rxdqs_best_win) { @@ -2713,3 +2743,25 @@ update_tx_tracking(chn, rk, cali_type, dq_pi, dqm_pi); } } + +void dramc_rx_datlat_cal(const struct ddr_cali* cali) +{ + u8 chn = cali->chn; + u8 rank = cali->rank; + u8 datlat = cali->params->rx_datlat[chn][rank]; + dramc_dbg("best_step = %d\n", datlat); + + dramc_engine2_init(chn, rank); + dramc_dle_factor_handler(chn, datlat); +} + +void dramc_dual_rank_rx_datlat_cal(const struct ddr_cali* cali) +{ + u8 chn = cali->chn; + u8 datlat_1 = cali->params->rx_datlat[chn][0]; + u8 datlat_2 = cali->params->rx_datlat[chn][1]; + u8 final_datlat = MAX(datlat_1, datlat_2); + + dramc_dle_factor_handler(chn, final_datlat); +} + diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index f724e54..9df4285 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -287,9 +287,11 @@ switch_write_dbi_settings(cali, DBI_OFF); } + dramc_rx_datlat_cal(cali); dramc_rx_window_perbit_cal(cali, RX_WIN_TEST_ENG); } dramc_rx_dqs_gating_post_process(cali, txdly_min, txdly_max); + dramc_dual_rank_rx_datlat_cal(cali); } static void dramc_calibration_all_channels(struct ddr_cali *cali) -- To view, visit https://review.coreboot.org/c/coreboot/+/44721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a426e1273dceae3a739bbbfc36db44d3ba9140d Gerrit-Change-Number: 44721 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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