coreboot-gerrit September 2020

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Change in coreboot[master]: nb/i945: Rewrite peg_bits for MCHBAR16(UPMC1)
by HAOUAS Elyes (Code Review) 18 Feb '21

18 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40370 ) Change subject: nb/i945: Rewrite peg_bits for MCHBAR16(UPMC1) ...................................................................... nb/i945: Rewrite peg_bits for MCHBAR16(UPMC1) Change-Id: I3c9e848077cdd13158dbfd19326b95b42fc1c1fb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 5 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/40370/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 4353a9c..bb886d4 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2171,18 +2171,14 @@ MCHBAR32(C1DRC1) = reg32; if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { - if (i945_silicon_revision() > 1) { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); - + /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ + u16 peg_bits = MCHBAR16(UPMC1); + peg_bits &= ((1 << 5) | (1 << 0)); + if (i945_silicon_revision() > 1) MCHBAR16(UPMC1) = 0x1010 | peg_bits; - } else { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); - + else /* Rev 0 and 1 */ MCHBAR16(UPMC1) = 0x0010 | peg_bits; - } } reg16 = MCHBAR16(UPMC2); -- To view, visit https://review.coreboot.org/c/coreboot/+/40370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c9e848077cdd13158dbfd19326b95b42fc1c1fb Gerrit-Change-Number: 40370 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: nb/intel/i945/acpi: COnvert igd.asl to ASL+ Syntax
by HAOUAS Elyes (Code Review) 18 Feb '21

18 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45273 ) Change subject: nb/intel/i945/acpi: COnvert igd.asl to ASL+ Syntax ...................................................................... nb/intel/i945/acpi: COnvert igd.asl to ASL+ Syntax Change-Id: Id0c3063b5a448fee4bcf283e56e7dc2008edcf7c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/acpi/igd.asl 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/45273/1 diff --git a/src/northbridge/intel/i945/acpi/igd.asl b/src/northbridge/intel/i945/acpi/igd.asl index 5258c52..43662d1 100644 --- a/src/northbridge/intel/i945/acpi/igd.asl +++ b/src/northbridge/intel/i945/acpi/igd.asl @@ -28,7 +28,7 @@ Method (XBCM, 1, NotSerialized) { - Store (Or(ShiftLeft (Arg0, 4), 0xf), ^^DSPC.BRTC) + ^^DSPC.BRTC = ((Arg0 << 0x04) | 0x0F) #ifdef SMI_SAVE_CMOS Trap(SMI_SAVE_CMOS) #endif @@ -36,8 +36,8 @@ Method (XBQC, 0, NotSerialized) { - Store (^^DSPC.BRTC, Local0) - ShiftRight (Local0, 4, Local0) + Local0 = ^^DSPC.BRTC + Local0 >>= 4 Return (Local0) } #include <drivers/intel/gma/acpi/common.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/45273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0c3063b5a448fee4bcf283e56e7dc2008edcf7c Gerrit-Change-Number: 45273 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 20

Change in coreboot[master]: nb/intel/pineview: Use new mchbar{8,16,32}_and_or()
by HAOUAS Elyes (Code Review) 18 Feb '21

18 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45517 ) Change subject: nb/intel/pineview: Use new mchbar{8,16,32}_and_or() ...................................................................... nb/intel/pineview: Use new mchbar{8,16,32}_and_or() Change-Id: I5fa844a8a13a75d6d802ca48f72c513bfa16d0a5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- A src/northbridge/intel/common/mchbar_ops.c A src/northbridge/intel/common/mchbar_ops.h M src/northbridge/intel/pineview/Makefile.inc M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/pineview/raminit.c 6 files changed, 417 insertions(+), 344 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45517/1 diff --git a/src/northbridge/intel/common/mchbar_ops.c b/src/northbridge/intel/common/mchbar_ops.c new file mode 100644 index 0000000..c3fccad --- /dev/null +++ b/src/northbridge/intel/common/mchbar_ops.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <stdint.h> +#include "mchbar_ops.h" + +void mchbar8_and_or(int offset, u8 mask, u8 or) +{ + u8 reg8 = MCHBAR8(offset); + + reg8 &= mask; + reg8 |= or; + MCHBAR8(offset) = reg8; +} + +void mchbar16_and_or(int offset, u16 mask, u16 or) +{ + u16 reg16 = MCHBAR32(offset); + + reg16 &= mask; + reg16 |= or; + MCHBAR16(offset) = reg16; +} + +void mchbar32_and_or(int offset, u32 mask, u32 or) +{ + u32 reg32 = MCHBAR32(offset); + + reg32 &= mask; + reg32 |= or; + MCHBAR32(offset) = reg32; +} + +void mchbar8_and(int offset, u8 and) +{ + mchbar8_and_or(offset, and, 0); +} + +void mchbar16_and(int offset, u16 and) +{ + mchbar16_and_or(offset, and, 0); +} + +void mchbar32_and(int offset, u32 and) +{ + mchbar32_and_or(offset, and, 0); +} + +void mchbar8_or(int offset, u8 or) +{ + mchbar8_and_or(offset, 0xff, or); +} + +void mchbar16_or(int offset, u16 or) +{ + mchbar16_and_or(offset, 0xffff, or); +} + +void mchbar32_or(int offset, u32 or) +{ + mchbar32_and_or(offset, 0xffffffff, or); +} diff --git a/src/northbridge/intel/common/mchbar_ops.h b/src/northbridge/intel/common/mchbar_ops.h new file mode 100644 index 0000000..cf39c2b --- /dev/null +++ b/src/northbridge/intel/common/mchbar_ops.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MCHBAR_OPS_H +#define MCHBAR_OPS_H + +#include <stdint.h> +#include <northbridge/intel/pineview/memmap.h> + +#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + x))) +#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + x))) +#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) + +void mchbar8_and_or(int offset, u8 mask, u8 or); +void mchbar16_and_or(int offset, u16 mask, u16 or); +void mchbar32_and_or(int offset, u32 mask, u32 or); +void mchbar8_and(int offset, u8 and); +void mchbar16_and(int offset, u16 and); +void mchbar32_and(int offset, u32 and); +void mchbar8_or(int offset, u8 or); +void mchbar16_or(int offset, u16 or); +void mchbar32_or(int offset, u32 or); + +#endif diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index 08e04f2..4ba902e 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -14,6 +14,7 @@ romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c +romstage-y += ../common/mchbar_ops.c postcar-y += memmap.c diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 42a68d8..ec7c575 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -3,6 +3,7 @@ #include <console/console.h> #include <device/pci_ops.h> #include <device/pci_def.h> +#include <northbridge/intel/common/mchbar_ops.h> #include <northbridge/intel/pineview/pineview.h> #include <northbridge/intel/pineview/chip.h> #include <option.h> @@ -67,10 +68,10 @@ if (config->use_crt) { /* Enable VGA */ - MCHBAR32_OR(DACGIOCTRL1, 1 << 15); + mchbar32_or(DACGIOCTRL1, 1 << 15); } else { /* Disable VGA */ - MCHBAR32_AND(DACGIOCTRL1, ~(1 << 15)); + mchbar32_and(DACGIOCTRL1, ~(1 << 15)); } if (config->use_lvds) { @@ -79,17 +80,17 @@ reg32 &= ~0xf1000000; reg32 |= 0x90000000; MCHBAR32(LVDSICR2) = reg32; - MCHBAR32_OR(IOCKTRR1, 1 << 9); + mchbar32_or(IOCKTRR1, 1 << 9); } else { /* Disable LVDS */ - MCHBAR32_OR(DACGIOCTRL1, 3 << 25); + mchbar32_or(DACGIOCTRL1, 3 << 25); } MCHBAR32(CICTRL) = 0xc6db8b5f; MCHBAR16(CISDCTRL) = 0x024f; - MCHBAR32_AND(DACGIOCTRL1, 0xffffff00); - MCHBAR32_OR(DACGIOCTRL1, 1 << 5); + mchbar32_and(DACGIOCTRL1, 0xffffff00); + mchbar32_or(DACGIOCTRL1, 1 << 5); /* Legacy backlight control */ pci_write_config8(GMCH_IGD, 0xf4, 0x4c); diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 03fa318..121c65b 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -5,6 +5,7 @@ #include <northbridge/intel/pineview/memmap.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <northbridge/intel/common/mchbar_ops.h> #define BOOT_PATH_NORMAL 0 #define BOOT_PATH_RESET 1 @@ -36,23 +37,8 @@ /* * MCHBAR + *As there are many registers, define them on a separate file */ - -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) /* FIXME: causes changes */ -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) - -/* As there are many registers, define them on a separate file */ - #include "mchbar_regs.h" /* diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 43149be..b190781 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -8,6 +8,7 @@ #include <console/console.h> #include <delay.h> #include <lib.h> +#include <northbridge/intel/common/mchbar_ops.h> #include "pineview.h" #include "raminit.h" #include <spd.h> @@ -501,7 +502,7 @@ if (s->boot_path == BOOT_PATH_RESET) return; - MCHBAR32_OR(PMSTS, 1); + mchbar32_or(PMSTS, 1); reg32 = (MCHBAR32(CLKCFG) & ~0x70) | (1 << 10); if (s->selected_timings.mem_clock == MEM_CLOCK_800MHz) { @@ -566,7 +567,7 @@ MCHBAR32(HMCCPEXT) = 0; MCHBAR32(HMDCPEXT) = clkcross[fsb_freq][ddr_freq][3]; - MCHBAR32_OR(HMCCMC, 1 << 7); + mchbar32_or(HMCCMC, 1 << 7); if ((fsb_freq == 0) && (ddr_freq == 1)) { MCHBAR8(CLKXSSH2MCBYPPHAS) = 0; @@ -616,8 +617,8 @@ u8 ddr_freq; u16 mpll_ctl; - MCHBAR16_AND(CSHRMISCCTL1, ~(1 << 8)); - MCHBAR8_AND(CSHRMISCCTL1, ~0x3f); + mchbar16_and(CSHRMISCCTL1, (u16)~(1 << 8)); + mchbar8_and(CSHRMISCCTL1, (u8)~0x3f); if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { ddr_freq = 0; @@ -627,10 +628,10 @@ mpll_ctl = (1 << 8) | (1 << 5); } if (s->boot_path != BOOT_PATH_RESET) - MCHBAR16_AND_OR(MPLLCTL, ~(0x033f), mpll_ctl); + mchbar16_and_or(MPLLCTL, (u16)~(0x033f), mpll_ctl); MCHBAR32(C0GNT2LNCH1) = 0x58001117; - MCHBAR32_OR(C0STATRDCTRL, 1 << 23); + mchbar32_or(C0STATRDCTRL, 1 << 23); const u32 cas_to_reg[2][4] = { {0x00000000, 0x00030100, 0x0C240201, 0x00000000}, /* DDR = 667 */ @@ -682,7 +683,7 @@ flag = 1; } - MCHBAR8_OR(C0PVCFG, 0x03); + mchbar8_or(C0PVCFG, 0x03); MCHBAR16(C0CYCTRKPCHG) = ((wl + 4 + s->selected_timings.tWR) << 6) | ((2 + MAX(s->selected_timings.tRTP, 2)) << 2) | 1; @@ -699,7 +700,7 @@ /* FIXME: Only applies to DDR2 */ reg16 = (MCHBAR16(C0CYCTRKACT + 2) & 0x0fc0) >> 6; - MCHBAR16_AND_OR(SHCYCTRKCKEL, ~0x1f80, (reg16 << 7)); + mchbar16_and_or(SHCYCTRKCKEL, (u16)~0x1f80, (reg16 << 7)); reg16 = (s->selected_timings.tRCD << 12) | (4 << 8) | (ta2 << 4) | ta4; MCHBAR16(C0CYCTRKWR) = reg16; @@ -714,10 +715,10 @@ MCHBAR8(C0CYCTRKREFR) = (u8) (reg16); MCHBAR8(C0CYCTRKREFR + 1) = (u8) (reg16 >> 8); - MCHBAR16_AND_OR(C0CKECTRL, ~0x03fe, 100 << 1); - MCHBAR8_AND_OR(C0CYCTRKPCHG2, ~0x3f, s->selected_timings.tRAS); + mchbar16_and_or(C0CKECTRL, (u16)~0x03fe, 100 << 1); + mchbar8_and_or(C0CYCTRKPCHG2, (u8)~0x3f, s->selected_timings.tRAS); MCHBAR16(C0ARBCTRL) = 0x2310; - MCHBAR8_AND_OR(C0ADDCSCTRL, ~0x1f, 1); + mchbar8_and_or(C0ADDCSCTRL, (u8)~0x1f, 1); if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { reg32 = 3000; @@ -730,7 +731,7 @@ reg2 = 5000; } reg16 = (u16)((((s->selected_timings.CAS + 7) * (reg32)) / reg2) << 8); - MCHBAR16_AND_OR(C0STATRDCTRL, ~0x1f00, reg16); + mchbar16_and_or(C0STATRDCTRL, (u16)~0x1f00, reg16); flag = 0; if (wl > 2) { @@ -739,13 +740,13 @@ reg16 = (u8) (wl - 1 - flag); reg16 |= reg16 << 4; reg16 |= flag << 8; - MCHBAR16_AND_OR(C0WRDATACTRL, ~0x01ff, reg16); + mchbar16_and_or(C0WRDATACTRL, (u16)~0x01ff, reg16); MCHBAR16(C0RDQCTRL) = 0x1585; - MCHBAR8_AND(C0PWLRCTRL, ~0x1f); + mchbar8_and(C0PWLRCTRL, (u8)~0x1f); /* rdmodwr_window[5..0] = CL+4+5 265[13..8] (264[21..16]) */ - MCHBAR16_AND_OR(C0PWLRCTRL, ~0x3f00, (s->selected_timings.CAS + 9) << 8); + mchbar16_and_or(C0PWLRCTRL, (u16)~0x3f00, (s->selected_timings.CAS + 9) << 8); if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { reg16 = 0x0514; @@ -754,115 +755,115 @@ reg16 = 0x0618; reg32 = 0x0c30; } - MCHBAR32_AND_OR(C0REFRCTRL2, ~0x0fffff00, (0x3f << 22) | (reg32 << 8)); + mchbar32_and_or(C0REFRCTRL2, (u32)~0x0fffff00, (0x3f << 22) | (reg32 << 8)); /* FIXME: Is this weird access necessary? Reference code does it */ MCHBAR8(C0REFRCTRL + 3) = 0; - MCHBAR16_AND_OR(C0REFCTRL, 0xc000, reg16); + mchbar16_and_or(C0REFCTRL, 0xc000, reg16); /* NPUT Static Mode */ - MCHBAR8_OR(C0DYNRDCTRL, 1); + mchbar8_or(C0DYNRDCTRL, 1); - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x7f000000, 0xb << 25); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x7f000000, 0xb << 25); i = s->selected_timings.mem_clock; j = s->selected_timings.fsb_clock; if (i > j) { - MCHBAR32_OR(C0STATRDCTRL, 1 << 24); + mchbar32_or(C0STATRDCTRL, 1 << 24); } - MCHBAR8_AND(C0RDFIFOCTRL, ~0x3); - MCHBAR16_AND_OR(C0WRDATACTRL, ~0x7c00, (wl + 10) << 10); - MCHBAR32_AND_OR(C0CKECTRL, ~0x070e0000, (3 << 24) | (3 << 17)); + mchbar8_and(C0RDFIFOCTRL, (u8)~0x3); + mchbar16_and_or(C0WRDATACTRL, (u16)~0x7c00, (wl + 10) << 10); + mchbar32_and_or(C0CKECTRL, (u32)~0x070e0000, (3 << 24) | (3 << 17)); reg16 = 0x15 << 6; reg16 |= 0x1f; reg16 |= (0x6 << 12); - MCHBAR16_AND_OR(C0REFRCTRL + 4, ~0x7fff, reg16); + mchbar16_and_or(C0REFRCTRL + 4, (u16)~0x7fff, reg16); reg32 = (0x6 << 27) | (1 << 25); /* FIXME: For DDR3, set BIT26 as well */ - MCHBAR32_AND_OR(C0REFRCTRL2, ~0x30000000, reg32 << 8); - MCHBAR8_AND_OR(C0REFRCTRL + 3, ~0xfa, reg32 >> 24); - MCHBAR8_AND(C0JEDEC, ~(1 << 7)); - MCHBAR8_AND(C0DYNRDCTRL, ~0x6); + mchbar32_and_or(C0REFRCTRL2, (u32)~0x30000000, reg32 << 8); + mchbar8_and_or(C0REFRCTRL + 3, (u8)~0xfa, reg32 >> 24); + mchbar8_and(C0JEDEC, (u8)~(1 << 7)); + mchbar8_and(C0DYNRDCTRL, (u8)~0x6); /* Note: This is a 64-bit register, [34..30] = 0b00110 is split across two writes */ reg32 = ((6 & 3) << 30) | (4 << 25) | (1 << 20) | (8 << 15) | (6 << 10) | (4 << 5) | 1; MCHBAR32(C0WRWMFLSH) = reg32; - MCHBAR16_AND_OR(C0WRWMFLSH + 4, ~0x1ff, (8 << 3) | (6 >> 2)); - MCHBAR16_OR(SHPENDREG, 0x1c00 | (0x1f << 5)); + mchbar16_and_or(C0WRWMFLSH + 4, (u16)~0x1ff, (8 << 3) | (6 >> 2)); + mchbar16_or(SHPENDREG, 0x1c00 | (0x1f << 5)); /* FIXME: Why not do a single word write? */ - MCHBAR8_AND_OR(SHPAGECTRL, ~0xff, 0x40); - MCHBAR8_AND_OR(SHPAGECTRL + 1, ~0x07, 0x05); - MCHBAR8_OR(SHCMPLWRCMD, 0x1f); + mchbar8_and_or(SHPAGECTRL, (u8)~0xff, 0x40); + mchbar8_and_or(SHPAGECTRL + 1, (u8)~0x07, 0x05); + mchbar8_or(SHCMPLWRCMD, 0x1f); reg8 = (3 << 6); reg8 |= (s->dt0mode << 4); reg8 |= 0x0c; - MCHBAR8_AND_OR(SHBONUSREG, ~0xdf, reg8); - MCHBAR8_AND(CSHRWRIOMLNS, ~0x02); - MCHBAR8_AND_OR(C0MISCTM, ~0x07, 0x02); - MCHBAR16_AND_OR(C0BYPCTRL, ~0x3fc, 4 << 2); + mchbar8_and_or(SHBONUSREG, (u8)~0xdf, reg8); + mchbar8_and(CSHRWRIOMLNS, (u8)~0x02); + mchbar8_and_or(C0MISCTM, (u8)~0x07, 0x02); + mchbar16_and_or(C0BYPCTRL, (u16)~0x3fc, 4 << 2); /* [31..29] = 0b010 for kN = 2 (2N) */ reg32 = (2 << 29) | (1 << 28) | (1 << 23); - MCHBAR32_AND_OR(WRWMCONFIG, ~0xffb00000, reg32); + mchbar32_and_or(WRWMCONFIG, (u32)~0xffb00000, reg32); reg8 = (u8) ((MCHBAR16(C0CYCTRKACT) & 0xe000) >> 13); reg8 |= (u8) ((MCHBAR16(C0CYCTRKACT + 2) & 1) << 3); - MCHBAR8_AND_OR(BYPACTSF, ~0xf0, reg8 << 4); + mchbar8_and_or(BYPACTSF, (u8)~0xf0, reg8 << 4); reg8 = (u8) ((MCHBAR32(C0CYCTRKRD) & 0x000f0000) >> 17); - MCHBAR8_AND_OR(BYPACTSF, ~0x0f, reg8); + mchbar8_and_or(BYPACTSF, (u8)~0x0f, reg8); /* FIXME: Why not clear everything at once? */ - MCHBAR8_AND(BYPKNRULE, ~0xfc); - MCHBAR8_AND(BYPKNRULE, ~0x03); - MCHBAR8_AND(SHBONUSREG, ~0x03); - MCHBAR8_OR(C0BYPCTRL, 1); - MCHBAR16_OR(CSHRMISCCTL1, 1 << 9); + mchbar8_and(BYPKNRULE, (u8)~0xfc); + mchbar8_and(BYPKNRULE, (u8)~0x03); + mchbar8_and(SHBONUSREG, (u8)~0x03); + mchbar8_or(C0BYPCTRL, 1); + mchbar16_or(CSHRMISCCTL1, 1 << 9); for (i = 0; i < 8; i++) { /* FIXME: Hardcoded for DDR2 SO-DIMMs */ - MCHBAR32_AND_OR(C0DLLRCVCTLy(i), ~0x3f3f3f3f, 0x0c0c0c0c); + mchbar32_and_or(C0DLLRCVCTLy(i), (u32)~0x3f3f3f3f, 0x0c0c0c0c); } /* RDCS to RCVEN delay: Program coarse common to all bytelanes to default tCL + 1 */ - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, (s->selected_timings.CAS + 1) << 16); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, (s->selected_timings.CAS + 1) << 16); /* Program RCVEN delay with DLL-safe settings */ for (i = 0; i < 8; i++) { - MCHBAR8_AND(C0RXRCVyDLL(i), ~0x3f); - MCHBAR16_AND(C0RCVMISCCTL2, (u16) ~(3 << (i * 2))); - MCHBAR16_AND(C0RCVMISCCTL1, (u16) ~(3 << (i * 2))); - MCHBAR16_AND(C0COARSEDLY0, (u16) ~(3 << (i * 2))); + mchbar8_and(C0RXRCVyDLL(i), (u8)~0x3f); + mchbar16_and(C0RCVMISCCTL2, (u16)~(3 << (i * 2))); + mchbar16_and(C0RCVMISCCTL1, (u16)~(3 << (i * 2))); + mchbar16_and(C0COARSEDLY0, (u16)~(3 << (i * 2))); } - MCHBAR8_AND(C0DLLPIEN, ~1); /* Power up receiver */ - MCHBAR8_OR(C0DLLPIEN, 2); /* Enable RCVEN DLL */ - MCHBAR8_OR(C0DLLPIEN, 4); /* Enable receiver DQS DLL */ - MCHBAR32_OR(C0COREBONUS, 0x000c0400); - MCHBAR32_OR(C0CMDTX1, 1 << 31); + mchbar8_and(C0DLLPIEN, (u8)~1); /* Power up receiver */ + mchbar8_or(C0DLLPIEN, 2); /* Enable RCVEN DLL */ + mchbar8_or(C0DLLPIEN, 4); /* Enable receiver DQS DLL */ + mchbar32_or(C0COREBONUS, 0x000c0400); + mchbar32_or(C0CMDTX1, 1 << 31); } /* Program clkset0's register for Kcoarse, Tap, PI, DBEn and DBSel */ static void sdram_p_clkset0(const struct pllparam *pll, u8 f, u8 i) { - MCHBAR16_AND_OR(C0CKTX, ~0xc440, + mchbar16_and_or(C0CKTX, (u16)~0xc440, (pll->clkdelay[f][i] << 14) | (pll->dben[f][i] << 10) | (pll->dbsel[f][i] << 6)); - MCHBAR8_AND_OR(C0TXCK0DLL, ~0x3f, pll->pi[f][i]); + mchbar8_and_or(C0TXCK0DLL, (u8)~0x3f, pll->pi[f][i]); } /* Program clkset1's register for Kcoarse, Tap, PI, DBEn and DBSel */ static void sdram_p_clkset1(const struct pllparam *pll, u8 f, u8 i) { /* FIXME: This is actually a dword write! */ - MCHBAR16_AND_OR(C0CKTX, ~0x00030880, + mchbar16_and_or(C0CKTX, (u16)~0x00030880, (pll->clkdelay[f][i] << 16) | (pll->dben[f][i] << 11) | (pll->dbsel[f][i] << 7)); - MCHBAR8_AND_OR(C0TXCK1DLL, ~0x3f, pll->pi[f][i]); + mchbar8_and_or(C0TXCK1DLL, (u8)~0x3f, pll->pi[f][i]); } /* Program CMD0 and CMD1 registers for Kcoarse, Tap, PI, DBEn and DBSel */ @@ -872,14 +873,14 @@ /* Clock Group Index 3 */ reg8 = pll->dbsel[f][i] << 5; reg8 |= pll->dben[f][i] << 6; - MCHBAR8_AND_OR(C0CMDTX1, ~0x60, reg8); + mchbar8_and_or(C0CMDTX1, (u8)~0x60, reg8); reg8 = pll->clkdelay[f][i] << 4; - MCHBAR8_AND_OR(C0CMDTX2, ~0x30, reg8); + mchbar8_and_or(C0CMDTX2, (u8)~0x30, reg8); reg8 = pll->pi[f][i]; - MCHBAR8_AND_OR(C0TXCMD0DLL, ~0x3f, reg8); - MCHBAR8_AND_OR(C0TXCMD1DLL, ~0x3f, reg8); + mchbar8_and_or(C0TXCMD0DLL, (u8)~0x3f, reg8); + mchbar8_and_or(C0TXCMD1DLL, (u8)~0x3f, reg8); } /* Program CTRL registers for Kcoarse, Tap, PI, DBEn and DBSel */ @@ -895,11 +896,11 @@ reg32 |= ((u32) pll->dben[f][i]) << 23; reg32 |= ((u32) pll->clkdelay[f][i]) << 24; reg32 |= ((u32) pll->clkdelay[f][i]) << 27; - MCHBAR32_AND_OR(C0CTLTX2, ~0x01bf0000, reg32); + mchbar32_and_or(C0CTLTX2, (u32)~0x01bf0000, reg32); reg8 = pll->pi[f][i]; - MCHBAR8_AND_OR(C0TXCTL0DLL, ~0x3f, reg8); - MCHBAR8_AND_OR(C0TXCTL1DLL, ~0x3f, reg8); + mchbar8_and_or(C0TXCTL0DLL, (u8)~0x3f, reg8); + mchbar8_and_or(C0TXCTL1DLL, (u8)~0x3f, reg8); /* CTRL2 and CTRL3 */ reg32 = ((u32) pll->dbsel[f][i]) << 12; @@ -908,11 +909,11 @@ reg32 |= ((u32) pll->dben[f][i]) << 9; reg32 |= ((u32) pll->clkdelay[f][i]) << 14; reg32 |= ((u32) pll->clkdelay[f][i]) << 10; - MCHBAR32_AND_OR(C0CMDTX2, ~0xff00, reg32); + mchbar32_and_or(C0CMDTX2, (u32)~0xff00, reg32); reg8 = pll->pi[f][i]; - MCHBAR8_AND_OR(C0TXCTL2DLL, ~0x3f, reg8); - MCHBAR8_AND_OR(C0TXCTL3DLL, ~0x3f, reg8); + mchbar8_and_or(C0TXCTL2DLL, (u8)~0x3f, reg8); + mchbar8_and_or(C0TXCTL3DLL, (u8)~0x3f, reg8); } static void sdram_p_dqs(struct pllparam *pll, u8 f, u8 clk) @@ -934,11 +935,11 @@ & ~((1 << (dqs + 9)) | (1 << dqs))) | reg32; reg32 = ((u32) pll->clkdelay[f][clk]) << ((dqs * 2) + 16); - MCHBAR32_AND_OR(C0DQSDQRyTX3(rank), ~((1 << (dqs * 2 + 17)) | (1 << (dqs * 2 + 16))), + mchbar32_and_or(C0DQSDQRyTX3(rank), ~((1 << (dqs * 2 + 17)) | (1 << (dqs * 2 + 16))), reg32); reg8 = pll->pi[f][clk]; - MCHBAR8_AND_OR(C0TXDQS0R0DLL + j, ~0x3f, reg8); + mchbar8_and_or(C0TXDQS0R0DLL + j, (u8)~0x3f, reg8); } @@ -961,10 +962,10 @@ & ~((1 << (dq + 9)) | (1 << dq))) | reg32; reg32 = ((u32) pll->clkdelay[f][clk]) << (dq*2); - MCHBAR32_AND_OR(C0DQSDQRyTX3(rank), ~((1 << (dq * 2 + 1)) | (1 << (dq * 2))), reg32); + mchbar32_and_or(C0DQSDQRyTX3(rank), ~((1 << (dq * 2 + 1)) | (1 << (dq * 2))), reg32); reg8 = pll->pi[f][clk]; - MCHBAR8_AND_OR(C0TXDQ0R0DLL + j, ~0x3f, reg8); + mchbar8_and_or(C0TXDQ0R0DLL + j, (u8)~0x3f, reg8); } /* WDLL programming: Perform HPLL/MPLL calibration after write levelization */ @@ -1055,8 +1056,8 @@ } /* Disable Dynamic DQS Slave Setting Per Rank */ - MCHBAR8_AND(CSHRDQSCMN, ~(1 << 7)); - MCHBAR16_AND_OR(CSHRPDCTL4, ~0x3fff, 0x1fff); + mchbar8_and(CSHRDQSCMN, (u8)~(1 << 7)); + mchbar16_and_or(CSHRPDCTL4, (u16)~0x3fff, 0x1fff); sdram_p_clkset0(&pll, f, 0); sdram_p_clkset1(&pll, f, 1); @@ -1079,13 +1080,13 @@ s->async = 0; reg8 = 0; - MCHBAR16_OR(CSHRPDCTL, 1 << 15); - MCHBAR8_AND(CSHRPDCTL, ~(1 << 7)); - MCHBAR8_OR(CSHRPDCTL, 1 << 3); - MCHBAR8_OR(CSHRPDCTL, 1 << 2); + mchbar16_or(CSHRPDCTL, 1 << 15); + mchbar8_and(CSHRPDCTL, (u8)~(1 << 7)); + mchbar8_or(CSHRPDCTL, 1 << 3); + mchbar8_or(CSHRPDCTL, 1 << 2); /* Start hardware HMC calibration */ - MCHBAR8_OR(CSHRPDCTL, 1 << 7); + mchbar8_or(CSHRPDCTL, 1 << 7); /* Busy-wait until calibration is done */ while ((MCHBAR8(CSHRPDCTL) & (1 << 2)) == 0) @@ -1110,80 +1111,80 @@ } else { reg32 = 0x00014221; } - MCHBAR32_AND_OR(CSHRMSTRCTL1, ~0x0fffffff, reg32); - MCHBAR32_OR(CSHRMSTRCTL1, 1 << 23); - MCHBAR32_OR(CSHRMSTRCTL1, 1 << 15); - MCHBAR32_AND(CSHRMSTRCTL1, ~(1 << 15)); + mchbar32_and_or(CSHRMSTRCTL1, (u32)~0x0fffffff, reg32); + mchbar32_or(CSHRMSTRCTL1, 1 << 23); + mchbar32_or(CSHRMSTRCTL1, 1 << 15); + mchbar32_and(CSHRMSTRCTL1, (u32)~(1 << 15)); if (s->nodll) { /* Disable the Master DLLs by setting these bits, IN ORDER! */ - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 0); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 2); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 4); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 8); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 10); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 12); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 14); + mchbar16_or(CSHRMSTRCTL0, 1 << 0); + mchbar16_or(CSHRMSTRCTL0, 1 << 2); + mchbar16_or(CSHRMSTRCTL0, 1 << 4); + mchbar16_or(CSHRMSTRCTL0, 1 << 8); + mchbar16_or(CSHRMSTRCTL0, 1 << 10); + mchbar16_or(CSHRMSTRCTL0, 1 << 12); + mchbar16_or(CSHRMSTRCTL0, 1 << 14); } else { /* Enable the Master DLLs by clearing these bits, IN ORDER! */ - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 0)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 2)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 4)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 8)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 10)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 12)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 14)); + mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 0)); + mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 2)); + mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 4)); + mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 8)); + mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 10)); + mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 12)); + mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 14)); } /* Initialize the Transmit DLL PI values in the following sequence. */ if (s->nodll) { - MCHBAR8_AND_OR(CREFPI, ~0x3f, 0x07); + mchbar8_and_or(CREFPI, (u8)~0x3f, 0x07); } else { - MCHBAR8_AND(CREFPI, ~0x3f); + mchbar8_and(CREFPI, (u8)~0x3f); } sdram_calibratepll(s, 0); // XXX check /* Enable all modular Slave DLL */ - MCHBAR16_OR(C0DLLPIEN, 1 << 11); - MCHBAR16_OR(C0DLLPIEN, 1 << 12); + mchbar16_or(C0DLLPIEN, 1 << 11); + mchbar16_or(C0DLLPIEN, 1 << 12); for (i = 0; i < 8; i++) { - MCHBAR16_OR(C0DLLPIEN, (1 << 10) >> i); + mchbar16_or(C0DLLPIEN, (1 << 10) >> i); } /* Enable DQ/DQS output */ - MCHBAR8_OR(C0SLVDLLOUTEN, 1); + mchbar8_or(C0SLVDLLOUTEN, 1); MCHBAR16(CSPDSLVWT) = 0x5005; - MCHBAR16_AND_OR(CSHRPDCTL2, ~0x1f1f, 0x051a); - MCHBAR16_AND_OR(CSHRPDCTL5, ~0xbf3f, 0x9010); + mchbar16_and_or(CSHRPDCTL2, (u16)~0x1f1f, 0x051a); + mchbar16_and_or(CSHRPDCTL5, (u16)~0xbf3f, 0x9010); if (s->nodll) { - MCHBAR8_AND_OR(CSHRPDCTL3, ~0x7f, 0x6b); + mchbar8_and_or(CSHRPDCTL3, (u8)~0x7f, 0x6b); } else { - MCHBAR8_AND_OR(CSHRPDCTL3, ~0x7f, 0x55); + mchbar8_and_or(CSHRPDCTL3, (u8)~0x7f, 0x55); sdram_calibratehwpll(s); } /* Disable Dynamic Diff Amp */ - MCHBAR32_AND(C0STATRDCTRL, ~(1 << 22)); + mchbar32_and(C0STATRDCTRL, (u32)~(1 << 22)); /* Now, start initializing the transmit FIFO */ - MCHBAR8_AND(C0MISCCTL, ~0x02); + mchbar8_and(C0MISCCTL, (u8)~0x02); /* Disable (gate) mdclk and mdclkb */ - MCHBAR8_OR(CSHWRIOBONUS, 0xc0); + mchbar8_or(CSHWRIOBONUS, 0xc0); /* Select mdmclk */ - MCHBAR8_AND(CSHWRIOBONUS, ~(1 << 5)); + mchbar8_and(CSHWRIOBONUS, (u8)~(1 << 5)); /* Ungate mdclk */ - MCHBAR8_AND_OR(CSHWRIOBONUS, ~0xc0, 1 << 6); - MCHBAR8_AND_OR(CSHRFIFOCTL, ~0x3f, 0x1a); + mchbar8_and_or(CSHWRIOBONUS, (u8)~0xc0, 1 << 6); + mchbar8_and_or(CSHRFIFOCTL, (u8)~0x3f, 0x1a); /* Enable the write pointer count */ - MCHBAR8_OR(CSHRFIFOCTL, 1); + mchbar8_or(CSHRFIFOCTL, 1); /* Set the DDR3 Reset Enable bit */ - MCHBAR8_OR(CSHRDDR3CTL, 1); + mchbar8_or(CSHRDDR3CTL, 1); /* Configure DQS-DQ Transmit */ MCHBAR32(CSHRDQSTXPGM) = 0x00551803; @@ -1191,10 +1192,10 @@ reg8 = 0; /* Switch all clocks on anyway */ /* Enable clock groups depending on rank population */ - MCHBAR32_AND_OR(C0CKTX, ~0x3f000000, reg8 << 24); + mchbar32_and_or(C0CKTX, (u32)~0x3f000000, reg8 << 24); /* Enable DDR command output buffers from core */ - MCHBAR8_AND(0x594, ~1); + mchbar8_and(0x594, (u8)~1); reg16 = 0; if (!rank_is_populated(s->dimms, 0, 0)) { @@ -1209,7 +1210,7 @@ if (!rank_is_populated(s->dimms, 0, 3)) { reg16 |= (1 << 11) | (1 << 7) | (1 << 3); } - MCHBAR16_OR(C0CTLTX2, reg16); + mchbar16_or(C0CTLTX2, reg16); } /* Define a shorter name for these to make the lines fit in 96 characters */ @@ -1344,54 +1345,54 @@ FOR_EACH_RCOMP_GROUP(i) { reg8 = rcompupdate[i]; - MCHBAR8_AND_OR(C0RCOMPCTRLx(i), ~1, reg8); - MCHBAR8_AND(C0RCOMPCTRLx(i), ~2); + mchbar8_and_or(C0RCOMPCTRLx(i), (u8)~1, reg8); + mchbar8_and(C0RCOMPCTRLx(i), (u8)~2); reg16 = rcompslew; - MCHBAR16_AND_OR(C0RCOMPCTRLx(i), ~0xf000, reg16 << 12); + mchbar16_and_or(C0RCOMPCTRLx(i), (u16)~0xf000, reg16 << 12); MCHBAR8(C0RCOMPMULTx(i)) = rcompstr[i]; MCHBAR16(C0SCOMPVREFx(i)) = rcompscomp[i]; - MCHBAR8_AND_OR(C0DCOMPx(i), ~0x03, rcompdelay[i]); + mchbar8_and_or(C0DCOMPx(i), (u8)~0x03, rcompdelay[i]); if (i == 2) { /* FIXME: Why are we rewriting this? */ - MCHBAR16_AND_OR(C0RCOMPCTRLx(i), ~0xf000, reg16 << 12); + mchbar16_and_or(C0RCOMPCTRLx(i), (u16)~0xf000, reg16 << 12); MCHBAR8(C0RCOMPMULTx(i)) = rcompstr2[s->dimm_config[0]]; MCHBAR16(C0SCOMPVREFx(i)) = rcompscomp2[s->dimm_config[0]]; - MCHBAR8_AND_OR(C0DCOMPx(i), ~0x03, rcompdelay2[s->dimm_config[0]]); + mchbar8_and_or(C0DCOMPx(i), (u8)~0x03, rcompdelay2[s->dimm_config[0]]); } - MCHBAR16_AND(C0SLEWBASEx(i), ~0x7f7f); + mchbar16_and(C0SLEWBASEx(i), (u16)~0x7f7f); /* FIXME: Why not do a single dword write? */ - MCHBAR16_AND(C0SLEWPULUTx(i), ~0x3f3f); - MCHBAR16_AND(C0SLEWPULUTx(i) + 2, ~0x3f3f); + mchbar16_and(C0SLEWPULUTx(i), (u16)~0x3f3f); + mchbar16_and(C0SLEWPULUTx(i) + 2, (u16)~0x3f3f); /* FIXME: Why not do a single dword write? */ - MCHBAR16_AND(C0SLEWPDLUTx(i), ~0x3f3f); - MCHBAR16_AND(C0SLEWPDLUTx(i) + 2, ~0x3f3f); + mchbar16_and(C0SLEWPDLUTx(i), (u16)~0x3f3f); + mchbar16_and(C0SLEWPDLUTx(i) + 2, (u16)~0x3f3f); } /* FIXME: Hardcoded */ - MCHBAR8_AND_OR(C0ODTRECORDX, ~0x3f, 0x36); - MCHBAR8_AND_OR(C0DQSODTRECORDX, ~0x3f, 0x36); + mchbar8_and_or(C0ODTRECORDX, (u8)~0x3f, 0x36); + mchbar8_and_or(C0DQSODTRECORDX, (u8)~0x3f, 0x36); FOR_EACH_RCOMP_GROUP(i) { - MCHBAR8_AND(C0RCOMPCTRLx(i), ~0x60); - MCHBAR16_AND(C0RCOMPCTRLx(i) + 2, ~0x0706); - MCHBAR16_AND(C0RCOMPOSVx(i), ~0x7f7f); - MCHBAR16_AND(C0SCOMPOFFx(i), ~0x3f3f); - MCHBAR16_AND(C0DCOMPOFFx(i), ~0x1f1f); - MCHBAR8_AND(C0DCOMPOFFx(i) + 2, ~0x1f); + mchbar8_and(C0RCOMPCTRLx(i), (u8)~0x60); + mchbar16_and(C0RCOMPCTRLx(i) + 2, (u16)~0x0706); + mchbar16_and(C0RCOMPOSVx(i), (u16)~0x7f7f); + mchbar16_and(C0SCOMPOFFx(i), (u16)~0x3f3f); + mchbar16_and(C0DCOMPOFFx(i), (u16)~0x1f1f); + mchbar8_and(C0DCOMPOFFx(i) + 2, (u8)~0x1f); } - MCHBAR16_AND(C0ODTRECORDX, ~0xffc0); - MCHBAR16_AND(C0ODTRECORDX + 2, ~0x000f); + mchbar16_and(C0ODTRECORDX, (u16)~0xffc0); + mchbar16_and(C0ODTRECORDX + 2, (u16)~0x000f); /* FIXME: Why not do a single dword write? */ - MCHBAR16_AND(C0DQSODTRECORDX, ~0xffc0); - MCHBAR16_AND(C0DQSODTRECORDX + 2, ~0x000f); + mchbar16_and(C0DQSODTRECORDX, (u16)~0xffc0); + mchbar16_and(C0DQSODTRECORDX + 2, (u16)~0x000f); FOR_EACH_RCOMP_GROUP(i) { MCHBAR16(C0SCOMPOVRx(i)) = rcompf[i]; @@ -1401,33 +1402,33 @@ MCHBAR16(C0DCOMPOVRx(i) + 2) = 0x000C; } - MCHBAR32_AND_OR(DCMEASBUFOVR, ~0x001f1f1f, 0x000c1219); + mchbar32_and_or(DCMEASBUFOVR, (u32)~0x001f1f1f, 0x000c1219); /* FIXME: Why not do a single word write? */ - MCHBAR16_AND_OR(XCOMPSDR0BNS, ~0x1f00, 0x1200); - MCHBAR8_AND_OR(XCOMPSDR0BNS, ~0x1f, 0x12); + mchbar16_and_or(XCOMPSDR0BNS, (u16)~0x1f00, 0x1200); + mchbar8_and_or(XCOMPSDR0BNS, (u8)~0x1f, 0x12); MCHBAR32(COMPCTRL3) = 0x007C9007; MCHBAR32(OFREQDELSEL) = rcomp1; MCHBAR16(XCOMPCMNBNS) = 0x1f7f; MCHBAR32(COMPCTRL2) = rcomp2; - MCHBAR16_AND_OR(XCOMPDFCTRL, ~0x0f, 1); + mchbar16_and_or(XCOMPDFCTRL, (u16)~0x0f, 1); MCHBAR16(ZQCALCTRL) = 0x0134; MCHBAR32(COMPCTRL1) = 0x4C293600; /* FIXME: wtf did these MRC guys smoke */ - MCHBAR8_AND_OR(COMPCTRL1 + 3, ~0x44, (1 << 6) | (1 << 2)); - MCHBAR16_AND(XCOMPSDR0BNS, ~(1 << 13)); - MCHBAR8_AND(XCOMPSDR0BNS, ~(1 << 5)); + mchbar8_and_or(COMPCTRL1 + 3, (u8)~0x44, (1 << 6) | (1 << 2)); + mchbar16_and(XCOMPSDR0BNS, (u16)~(1 << 13)); + mchbar8_and(XCOMPSDR0BNS, (u8)~(1 << 5)); FOR_EACH_RCOMP_GROUP(i) { /* FIXME: This should be an _AND_OR */ - MCHBAR8(C0RCOMPCTRLx(i) + 2) = MCHBAR8(C0RCOMPCTRLx(i)) & ~0x71; + MCHBAR8(C0RCOMPCTRLx(i) + 2) = MCHBAR8(C0RCOMPCTRLx(i)) & (u8)~0x71; } if ((MCHBAR32(COMPCTRL1) & (1 << 30)) == 0) { /* Start COMP */ - MCHBAR8_OR(COMPCTRL1, 1); + mchbar8_or(COMPCTRL1, 1); /* Wait until COMP is done */ while ((MCHBAR8(COMPCTRL1) & 1) != 0) @@ -1443,55 +1444,55 @@ /* FIXME: Why not do a single word write? */ reg16 = (u16)(rcompp - (1 << (srup + 1))) << 8; - MCHBAR16_AND_OR(C0SLEWBASEx(i), ~0x7f00, reg16); + mchbar16_and_or(C0SLEWBASEx(i), (u16)~0x7f00, reg16); reg16 = (u16)(rcompn - (1 << (srun + 1))); - MCHBAR8_AND_OR(C0SLEWBASEx(i), ~0x7f, (u8)reg16); + mchbar8_and_or(C0SLEWBASEx(i), (u8)~0x7f, (u8)reg16); } reg8 = rcompp - (1 << (srup + 1)); for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { - MCHBAR8_AND_OR(C0SLEWPULUTx(0) + i, ~0x3f, rcomplut[j][0]); + mchbar8_and_or(C0SLEWPULUTx(0) + i, (u8)~0x3f, rcomplut[j][0]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { if (s->dimm_config[0] < 3 || s->dimm_config[0] == 5) { - MCHBAR8_AND_OR(C0SLEWPULUTx(2) + i, ~0x3f, rcomplut[j][10]); + mchbar8_and_or(C0SLEWPULUTx(2) + i, (u8)~0x3f, rcomplut[j][10]); } } for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { - MCHBAR8_AND_OR(C0SLEWPULUTx(3) + i, ~0x3f, rcomplut[j][6]); - MCHBAR8_AND_OR(C0SLEWPULUTx(4) + i, ~0x3f, rcomplut[j][6]); + mchbar8_and_or(C0SLEWPULUTx(3) + i, (u8)~0x3f, rcomplut[j][6]); + mchbar8_and_or(C0SLEWPULUTx(4) + i, (u8)~0x3f, rcomplut[j][6]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { - MCHBAR8_AND_OR(C0SLEWPULUTx(5) + i, ~0x3f, rcomplut[j][8]); - MCHBAR8_AND_OR(C0SLEWPULUTx(6) + i, ~0x3f, rcomplut[j][8]); + mchbar8_and_or(C0SLEWPULUTx(5) + i, (u8)~0x3f, rcomplut[j][8]); + mchbar8_and_or(C0SLEWPULUTx(6) + i, (u8)~0x3f, rcomplut[j][8]); } reg8 = rcompn - (1 << (srun + 1)); for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { - MCHBAR8_AND_OR(C0SLEWPDLUTx(0) + i, ~0x3f, rcomplut[j][1]); + mchbar8_and_or(C0SLEWPDLUTx(0) + i, (u8)~0x3f, rcomplut[j][1]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { if (s->dimm_config[0] < 3 || s->dimm_config[0] == 5) { - MCHBAR8_AND_OR(C0SLEWPDLUTx(2) + i, ~0x3f, rcomplut[j][11]); + mchbar8_and_or(C0SLEWPDLUTx(2) + i, (u8)~0x3f, rcomplut[j][11]); } } for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { - MCHBAR8_AND_OR(C0SLEWPDLUTx(3) + i, ~0x3f, rcomplut[j][7]); - MCHBAR8_AND_OR(C0SLEWPDLUTx(4) + i, ~0x3f, rcomplut[j][7]); + mchbar8_and_or(C0SLEWPDLUTx(3) + i, (u8)~0x3f, rcomplut[j][7]); + mchbar8_and_or(C0SLEWPDLUTx(4) + i, (u8)~0x3f, rcomplut[j][7]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { - MCHBAR8_AND_OR(C0SLEWPDLUTx(5) + i, ~0x3f, rcomplut[j][9]); - MCHBAR8_AND_OR(C0SLEWPDLUTx(6) + i, ~0x3f, rcomplut[j][9]); + mchbar8_and_or(C0SLEWPDLUTx(5) + i, (u8)~0x3f, rcomplut[j][9]); + mchbar8_and_or(C0SLEWPDLUTx(6) + i, (u8)~0x3f, rcomplut[j][9]); } } - MCHBAR8_OR(COMPCTRL1, 1); + mchbar8_or(COMPCTRL1, 1); } /* FIXME: The ODT tables are for DDR2 only! */ @@ -1566,24 +1567,24 @@ if ((s->dimm_config[0] < 3) && rank_is_populated(s->dimms, 0, 0)) { if (s->dimms[0].sides > 1) { // 2R/NC - MCHBAR32_AND_OR(C0CKECTRL, ~1, 0x300001); + mchbar32_and_or(C0CKECTRL, (u32)~1, 0x300001); MCHBAR32(C0DRA01) = 0x00000101; MCHBAR32(C0DRB0) = 0x00040002; MCHBAR32(C0DRB2) = w204[s->dimm_config[0]]; } else { // 1R/NC - MCHBAR32_AND_OR(C0CKECTRL, ~1, 0x100001); + mchbar32_and_or(C0CKECTRL, (u32)~1, 0x100001); MCHBAR32(C0DRA01) = 0x00000001; MCHBAR32(C0DRB0) = 0x00020002; MCHBAR32(C0DRB2) = w204[s->dimm_config[0]]; } } else if ((s->dimm_config[0] == 5) && rank_is_populated(s->dimms, 0, 0)) { - MCHBAR32_AND_OR(C0CKECTRL, ~1, 0x300001); + mchbar32_and_or(C0CKECTRL, (u32)~1, 0x300001); MCHBAR32(C0DRA01) = 0x00000101; MCHBAR32(C0DRB0) = 0x00040002; MCHBAR32(C0DRB2) = 0x00040004; } else { - MCHBAR32_AND_OR(C0CKECTRL, ~1, w260[s->dimm_config[0]]); + mchbar32_and_or(C0CKECTRL, (u32)~1, w260[s->dimm_config[0]]); MCHBAR32(C0DRA01) = w208[s->dimm_config[0]]; MCHBAR32(C0DRB0) = w200[s->dimm_config[0]]; MCHBAR32(C0DRB2) = w204[s->dimm_config[0]]; @@ -1652,10 +1653,10 @@ u32 reg32a, reg32b; ok = 0; - MCHBAR8_AND(XCOMPDFCTRL, ~(1 << 3)); - MCHBAR8_AND(COMPCTRL1, ~(1 << 7)); + mchbar8_and(XCOMPDFCTRL, (u8)~(1 << 3)); + mchbar8_and(COMPCTRL1, (u8)~(1 << 7)); for (i = 0; i < 3; i++) { - MCHBAR8_OR(COMPCTRL1, 1); + mchbar8_or(COMPCTRL1, 1); hpet_udelay(1000); while ((MCHBAR8(COMPCTRL1) & 1) != 0) ; @@ -1668,7 +1669,7 @@ reg32a |= (1 << 31) | (1 << 15); MCHBAR32(RCMEASBUFXOVR) = reg32a; } - MCHBAR8_OR(COMPCTRL1, 1); + mchbar8_or(COMPCTRL1, 1); hpet_udelay(1000); while ((MCHBAR8(COMPCTRL1) & 1) != 0) ; @@ -1681,7 +1682,7 @@ reg32 = jval << 3; reg32 |= rank * (1 << 27); - MCHBAR8_AND_OR(C0JEDEC, ~0x3e, jmode); + mchbar8_and_or(C0JEDEC, (u8)~0x3e, jmode); read32((void *)reg32); barrier(); hpet_udelay(1); // 1us @@ -1690,10 +1691,10 @@ static void sdram_zqcl(struct sysinfo *s) { if (s->boot_path == BOOT_PATH_RESUME) { - MCHBAR32_OR(C0CKECTRL, 1 << 27); - MCHBAR8_AND_OR(C0JEDEC, ~0x0e, NORMAL_OP_CMD); - MCHBAR8_AND(C0JEDEC, ~0x30); - MCHBAR32_AND_OR(C0REFRCTRL2, ~(3 << 30), 3 << 30); + mchbar32_or(C0CKECTRL, 1 << 27); + mchbar8_and_or(C0JEDEC, (u8)~0x0e, NORMAL_OP_CMD); + mchbar8_and(C0JEDEC, (u8)~0x30); + mchbar32_and_or(C0REFRCTRL2, (u32)~(3 << 30), 3 << 30); } } @@ -1759,12 +1760,12 @@ reg32 = 0; reg32 |= (4 << 13); reg32 |= (6 << 8); - MCHBAR32_AND_OR(C0DYNRDCTRL, ~0x3ff00, reg32); - MCHBAR8_AND(C0DYNRDCTRL, ~(1 << 7)); - MCHBAR8_OR(C0REFRCTRL + 3, 1); + mchbar32_and_or(C0DYNRDCTRL, (u32)~0x3ff00, reg32); + mchbar8_and(C0DYNRDCTRL, (u8)~(1 << 7)); + mchbar8_or(C0REFRCTRL + 3, 1); if (s->boot_path != BOOT_PATH_RESUME) { - MCHBAR8_AND_OR(C0JEDEC, ~0x0e, NORMAL_OP_CMD); - MCHBAR8_AND(C0JEDEC, ~0x30); + mchbar8_and_or(C0JEDEC, (u8)~0x0e, NORMAL_OP_CMD); + mchbar8_and(C0JEDEC, (u8)~0x30); } else { sdram_zqcl(s); } @@ -1861,10 +1862,10 @@ reg32 |= (1 << r); } reg8 = (u8)(reg32 << 4) & 0xf0; - MCHBAR8_AND_OR(C0CKECTRL + 2, ~0xf0, reg8); + mchbar8_and_or(C0CKECTRL + 2, (u8)~0xf0, reg8); if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) { - MCHBAR8_OR(C0CKECTRL, 1); + mchbar8_or(C0CKECTRL, 1); } addr = C0DRB0; @@ -1885,9 +1886,9 @@ { u8 dqsmatches = 1; while (count--) { - MCHBAR8_AND(C0RSTCTL, ~2); + mchbar8_and(C0RSTCTL, (u8)~2); hpet_udelay(1); - MCHBAR8_OR(C0RSTCTL, 2); + mchbar8_or(C0RSTCTL, 2); hpet_udelay(1); barrier(); read32((void *)strobeaddr); @@ -1906,12 +1907,12 @@ { if (*medium < 3) { (*medium)++; - MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), *medium << (lane * 2)); + mchbar16_and_or(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), *medium << (lane * 2)); } else { *medium = 0; (*coarse)++; - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, *coarse << 16); - MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)(~3 << (lane * 2)), *medium << (lane * 2)); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, *coarse << 16); + mchbar16_and_or(C0RCVMISCCTL2, (u16)(~3 << (lane * 2)), *medium << (lane * 2)); } } @@ -1930,8 +1931,8 @@ u32 strobeaddr = 0; u32 dqshighaddr; - MCHBAR8_AND(C0RSTCTL, ~0x0c); - MCHBAR8_AND(CMNDQFIFORST, ~0x80); + mchbar8_and(C0RSTCTL, (u8)~0x0c); + mchbar8_and(CMNDQFIFORST, (u8)~0x80); PRINTK_DEBUG("rcven 0\n"); for (lane = 0; lane < maxlane; lane++) { @@ -1943,10 +1944,10 @@ pi = 0; medium = 0; - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, coarse << 16); - MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), medium << (lane * 2)); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, coarse << 16); + mchbar16_and_or(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), medium << (lane * 2)); - MCHBAR8_AND(C0RXRCVyDLL(lane), ~0x3f); + mchbar8_and(C0RXRCVyDLL(lane), (u8)~0x3f); savecoarse = coarse; savemedium = medium; @@ -1955,7 +1956,7 @@ PRINTK_DEBUG("rcven 0.1\n"); // XXX comment out - // MCHBAR16_AND_OR(C0RCVMISCCTL1, (u16)~3 << (lane * 2), 1 << (lane * 2)); + // mchbar16_and_or(C0RCVMISCCTL1, (u16)~3 << (lane * 2), 1 << (lane * 2)); while (sampledqs(dqshighaddr, strobeaddr, 0, 3) == 0) { // printk(BIOS_DEBUG, "coarse=%d medium=%d\n", coarse, medium); @@ -1986,8 +1987,8 @@ PRINTK_DEBUG("rcven 0.3\n"); coarse = savecoarse; medium = savemedium; - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, coarse << 16); - MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)~(0x3 << lane * 2), medium << (lane * 2)); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, coarse << 16); + mchbar16_and_or(C0RCVMISCCTL2, (u16)~(0x3 << lane * 2), medium << (lane * 2)); while (sampledqs(dqshighaddr, strobeaddr, 1, 3) == 0) { savepi = pi; @@ -1998,12 +1999,12 @@ break; // } } - MCHBAR8_AND_OR(C0RXRCVyDLL(lane), ~0x3f, pi << s->pioffset); + mchbar8_and_or(C0RXRCVyDLL(lane), (u8)~0x3f, pi << s->pioffset); } PRINTK_DEBUG("rcven 0.4\n"); pi = savepi; - MCHBAR8_AND_OR(C0RXRCVyDLL(lane), ~0x3f, pi << s->pioffset); + mchbar8_and_or(C0RXRCVyDLL(lane), (u8)~0x3f, pi << s->pioffset); rcvenclock(&coarse, &medium, lane); if (sampledqs(dqshighaddr, strobeaddr, 1, 1) == 0) { @@ -2013,7 +2014,7 @@ PRINTK_DEBUG("rcven 0.5\n"); while (sampledqs(dqshighaddr, strobeaddr, 0, 3) == 0) { coarse--; - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, coarse << 16); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, coarse << 16); if (coarse == 0) { PRINTK_DEBUG("Error: DQS did not hit 0\n"); break; @@ -2040,10 +2041,10 @@ do { lane--; offset = lanecoarse[lane] - minlanecoarse; - MCHBAR16_AND_OR(C0COARSEDLY0, (u16)(~(3 << (lane * 2))), offset << (lane * 2)); + mchbar16_and_or(C0COARSEDLY0, (u16)(~(3 << (lane * 2))), offset << (lane * 2)); } while (lane != 0); - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, minlanecoarse << 16); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, minlanecoarse << 16); s->coarsectrl = minlanecoarse; s->coarsedelay = MCHBAR16(C0COARSEDLY0); @@ -2051,14 +2052,14 @@ s->readptrdelay = MCHBAR16(C0RCVMISCCTL1); PRINTK_DEBUG("rcven 2\n"); - MCHBAR8_AND(C0RSTCTL, ~0x0e); - MCHBAR8_OR(C0RSTCTL, 0x02); - MCHBAR8_OR(C0RSTCTL, 0x04); - MCHBAR8_OR(C0RSTCTL, 0x08); + mchbar8_and(C0RSTCTL, (u8)~0x0e); + mchbar8_or(C0RSTCTL, 0x02); + mchbar8_or(C0RSTCTL, 0x04); + mchbar8_or(C0RSTCTL, 0x08); - MCHBAR8_OR(CMNDQFIFORST, 0x80); - MCHBAR8_AND(CMNDQFIFORST, ~0x80); - MCHBAR8_OR(CMNDQFIFORST, 0x80); + mchbar8_or(CMNDQFIFORST, 0x80); + mchbar8_and(CMNDQFIFORST, (u8)~0x80); + mchbar8_or(CMNDQFIFORST, 0x80); PRINTK_DEBUG("rcven 3\n"); } @@ -2138,20 +2139,20 @@ { u8 reg8, ch, r, fsb_freq, ddr_freq; u32 mask32, reg32; - MCHBAR8_OR(C0ADDCSCTRL, 1); - MCHBAR8_OR(C0REFRCTRL + 3, 1); + mchbar8_or(C0ADDCSCTRL, 1); + mchbar8_or(C0REFRCTRL + 3, 1); mask32 = (0x1f << 15) | (0x1f << 10) | (0x1f << 5) | 0x1f; reg32 = (0x1e << 15) | (0x10 << 10) | (0x1e << 5) | 0x10; - MCHBAR32_AND_OR(WRWMCONFIG, ~mask32, reg32); + mchbar32_and_or(WRWMCONFIG, (u32)~mask32, reg32); MCHBAR8(C0DITCTRL + 1) = 2; MCHBAR16(C0DITCTRL + 2) = 0x0804; MCHBAR16(C0DITCTRL + 4) = 0x2010; MCHBAR8(C0DITCTRL + 6) = 0x40; MCHBAR16(C0DITCTRL + 8) = 0x091c; MCHBAR8(C0DITCTRL + 10) = 0xf2; - MCHBAR8_OR(C0BYPCTRL, 1); - MCHBAR8_OR(C0CWBCTRL, 1); - MCHBAR16_OR(C0ARBSPL, 0x0100); + mchbar8_or(C0BYPCTRL, 1); + mchbar8_or(C0CWBCTRL, 1); + mchbar16_or(C0ARBSPL, 0x0100); pci_or_config8(HOST_BRIDGE, 0xf0, 1); MCHBAR32(SBCTL) = 0x00000002; @@ -2162,7 +2163,7 @@ MCHBAR32(HIT2) = 0x07000000; MCHBAR32(HIT3) = 0x01014010; MCHBAR32(HIT4) = 0x0f038000; - pci_and_config8(HOST_BRIDGE, 0xf0, ~1); + pci_and_config8(HOST_BRIDGE, 0xf0, (u8)~1); u32 nranks, curranksize, maxranksize, dra; u8 rankmismatch; @@ -2209,14 +2210,14 @@ die("Invalid number of ranks found, halt\n"); break; } - MCHBAR8_AND_OR(CHDECMISC, ~0xfc, reg8 & 0xfc); - MCHBAR32_AND(NOACFGBUSCTL, ~0x80000000); + mchbar8_and_or(CHDECMISC, (u8)~0xfc, reg8 & 0xfc); + mchbar32_and(NOACFGBUSCTL, (u32)~0x80000000); MCHBAR32(HTBONUS0) = 0x0000000f; - MCHBAR8_OR(C0COREBONUS + 4, 1); + mchbar8_or(C0COREBONUS + 4, 1); - MCHBAR32_AND(HIT3, ~0x0e000000); - MCHBAR32_AND_OR(HIT4, ~0x000c0000, 0x00040000); + mchbar32_and(HIT3, (u32)~0x0e000000); + mchbar32_and_or(HIT4, (u32)~0x000c0000, 0x00040000); u32 clkcx[2][2][3] = { { @@ -2236,20 +2237,20 @@ MCHBAR32(CLKXSSH2X2MD + 4) = clkcx[fsb_freq][ddr_freq][1]; MCHBAR32(CLKXSSH2MCBYP + 4) = clkcx[fsb_freq][ddr_freq][2]; - MCHBAR8_AND(HIT4, ~0x02); + mchbar8_and(HIT4, (u8)~0x02); } static void sdram_periodic_rcomp(void) { - MCHBAR8_AND(COMPCTRL1, ~0x02); + mchbar8_and(COMPCTRL1, (u8)~0x02); while ((MCHBAR32(COMPCTRL1) & 0x80000000) > 0) { ; } - MCHBAR16_AND(CSHRMISCCTL, ~0x3000); - MCHBAR8_OR(CMNDQFIFORST, 0x80); - MCHBAR16_AND_OR(XCOMPDFCTRL, ~0x0f, 0x09); + mchbar16_and(CSHRMISCCTL, (u16)~0x3000); + mchbar8_or(CMNDQFIFORST, 0x80); + mchbar16_and_or(XCOMPDFCTRL, (u16)~0x0f, 0x09); - MCHBAR8_OR(COMPCTRL1, 0x82); + mchbar8_or(COMPCTRL1, 0x82); } static void sdram_new_trd(struct sysinfo *s) @@ -2337,7 +2338,7 @@ } } - MCHBAR16_AND_OR(C0STATRDCTRL, ~0x1f00, trd << 8); + mchbar16_and_or(C0STATRDCTRL, (u16)~0x1f00, trd << 8); } static void sdram_powersettings(struct sysinfo *s) @@ -2347,26 +2348,26 @@ /* Thermal sensor */ MCHBAR8(TSC1) = 0x9b; - MCHBAR32_AND_OR(TSTTP, ~0x00ffffff, 0x1d00); + mchbar32_and_or(TSTTP, (u32)~0x00ffffff, 0x1d00); MCHBAR8(THERM1) = 0x08; MCHBAR8(TSC3) = 0x00; - MCHBAR8_AND_OR(TSC2, ~0x0f, 0x04); - MCHBAR8_AND_OR(THERM1, ~1, 1); - MCHBAR8_AND_OR(TCO, ~0x80, 0x80); + mchbar8_and_or(TSC2, (u8)~0x0f, 0x04); + mchbar8_and_or(THERM1, (u8)~1, 1); + mchbar8_and_or(TCO, (u8)~0x80, 0x80); /* Clock gating */ - MCHBAR32_AND(PMMISC, ~0x00040001); - MCHBAR8_AND(SBCTL3 + 3, ~0x80); - MCHBAR8_AND(CISDCTRL + 3, ~0x80); - MCHBAR16_AND(CICGDIS, ~0x1fff); - MCHBAR32_AND(SBCLKGATECTRL, ~0x0001ffff); - MCHBAR16_AND(HICLKGTCTL, ~0x03ff & 0x06); - MCHBAR32_AND_OR(HTCLKGTCTL, ~0xffffffff, 0x20); - MCHBAR8_AND(TSMISC, ~1); + mchbar32_and(PMMISC, (u32)~0x00040001); + mchbar8_and(SBCTL3 + 3, (u8)~0x80); + mchbar8_and(CISDCTRL + 3, (u8)~0x80); + mchbar16_and(CICGDIS, (u16)~0x1fff); + mchbar32_and(SBCLKGATECTRL, (u32)~0x0001ffff); + mchbar16_and(HICLKGTCTL, (u16)~0x03ff & 0x06); + mchbar32_and_or(HTCLKGTCTL, (u32)~0xffffffff, 0x20); + mchbar8_and(TSMISC, (u8)~1); MCHBAR8(C0WRDPYN) = s->selected_timings.CAS - 1 + 0x15; - MCHBAR16_AND_OR(CLOCKGATINGI, ~0x07fc, 0x0040); - MCHBAR16_AND_OR(CLOCKGATINGII, ~0x0fff, 0x0d00); - MCHBAR16_AND(CLOCKGATINGIII, ~0x0d80); + mchbar16_and_or(CLOCKGATINGI, (u16)~0x07fc, 0x0040); + mchbar16_and_or(CLOCKGATINGII, (u16)~0x0fff, 0x0d00); + mchbar16_and(CLOCKGATINGIII, (u16)~0x0d80); MCHBAR16(GTDPCGC + 2) = 0xffff; /* Sequencing */ @@ -2379,15 +2380,15 @@ MCHBAR32(PMDSLFRC) = (MCHBAR32(PMDSLFRC) & ~0x0001bff7) | 0x00000078; if (s->selected_timings.fsb_clock == FSB_CLOCK_667MHz) - MCHBAR16_AND_OR(PMMSPMRES, ~0x03ff, 0x00c8); + mchbar16_and_or(PMMSPMRES, (u16)~0x03ff, 0x00c8); else - MCHBAR16_AND_OR(PMMSPMRES, ~0x03ff, 0x0100); + mchbar16_and_or(PMMSPMRES, (u16)~0x03ff, 0x0100); j = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 0 : 1; - MCHBAR32_AND_OR(PMCLKRC, ~0x01fff37f, 0x10810700); - MCHBAR8_AND_OR(PMPXPRC, ~0x07, 1); - MCHBAR8_AND(PMBAK, ~0x02); + mchbar32_and_or(PMCLKRC, (u32)~0x01fff37f, 0x10810700); + mchbar8_and_or(PMPXPRC, (u8)~0x07, 1); + mchbar8_and(PMBAK, (u8)~0x02); static const u16 ddr2lut[2][4][2] = { { @@ -2407,8 +2408,8 @@ MCHBAR16(C0C2REG) = 0x7a89; MCHBAR8(SHC2REGII) = 0xaa; MCHBAR16(SHC2REGII + 1) = ddr2lut[j][s->selected_timings.CAS - 3][1]; - MCHBAR16_AND_OR(SHC2REGI, ~0x7fff, ddr2lut[j][s->selected_timings.CAS - 3][0]); - MCHBAR16_AND_OR(CLOCKGATINGIII, ~0xf000, 0xf000); + mchbar16_and_or(SHC2REGI, (u16)~0x7fff, ddr2lut[j][s->selected_timings.CAS - 3][0]); + mchbar16_and_or(CLOCKGATINGIII, (u16)~0xf000, 0xf000); MCHBAR8(CSHWRIOBONUSX) = (MCHBAR8(CSHWRIOBONUSX) & ~0x77) | (4 << 4 | 4); reg32 = s->nodll ? 0x30000000 : 0; @@ -2416,72 +2417,72 @@ /* FIXME: Compacting this results in changes to the binary */ MCHBAR32(C0COREBONUS) = (MCHBAR32(C0COREBONUS) & ~0x0f000000) | 0x20000000 | reg32; - MCHBAR32_AND_OR(CLOCKGATINGI, ~0x00f00000, 0x00f00000); - MCHBAR32_AND_OR(CLOCKGATINGII - 1, ~0x001ff000, 0xbf << 20); - MCHBAR16_AND_OR(SHC3C4REG2, ~0x1f7f, (0x0b << 8) | (7 << 4) | 0x0b); + mchbar32_and_or(CLOCKGATINGI, (u32)~0x00f00000, 0x00f00000); + mchbar32_and_or(CLOCKGATINGII - 1, (u32)~0x001ff000, 0xbf << 20); + mchbar16_and_or(SHC3C4REG2, (u16)~0x1f7f, (0x0b << 8) | (7 << 4) | 0x0b); MCHBAR16(SHC3C4REG3) = 0x3264; - MCHBAR16_AND_OR(SHC3C4REG4, ~0x3f3f, (0x14 << 8) | 0x0a); + mchbar16_and_or(SHC3C4REG4, (u16)~0x3f3f, (0x14 << 8) | 0x0a); - MCHBAR32_OR(C1COREBONUS, 0x80002000); + mchbar32_or(C1COREBONUS, 0x80002000); } static void sdram_programddr(void) { - MCHBAR16_AND_OR(CLOCKGATINGII, ~0x03ff, 0x0100); - MCHBAR16_AND_OR(CLOCKGATINGIII, ~0x003f, 0x0010); - MCHBAR16_AND_OR(CLOCKGATINGI, ~0x7000, 0x2000); + mchbar16_and_or(CLOCKGATINGII, (u16)~0x03ff, 0x0100); + mchbar16_and_or(CLOCKGATINGIII, (u16)~0x003f, 0x0010); + mchbar16_and_or(CLOCKGATINGI, (u16)~0x7000, 0x2000); - MCHBAR8_AND(CSHRPDCTL, ~0x0e); - MCHBAR8_AND(CSHRWRIOMLNS, ~0x0c); - MCHBAR8_AND(C0MISCCTLy(0), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(1), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(2), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(3), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(4), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(5), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(6), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(7), ~0x0e); - MCHBAR8_AND(CSHRWRIOMLNS, ~0x02); + mchbar8_and(CSHRPDCTL, (u8)~0x0e); + mchbar8_and(CSHRWRIOMLNS, (u8)~0x0c); + mchbar8_and(C0MISCCTLy(0), (u8)~0x0e); + mchbar8_and(C0MISCCTLy(1), (u8)~0x0e); + mchbar8_and(C0MISCCTLy(2), (u8)~0x0e); + mchbar8_and(C0MISCCTLy(3), (u8)~0x0e); + mchbar8_and(C0MISCCTLy(4), (u8)~0x0e); + mchbar8_and(C0MISCCTLy(5), (u8)~0x0e); + mchbar8_and(C0MISCCTLy(6), (u8)~0x0e); + mchbar8_and(C0MISCCTLy(7), (u8)~0x0e); + mchbar8_and(CSHRWRIOMLNS, (u8)~0x02); - MCHBAR16_AND(CSHRMISCCTL, ~0x0400); - MCHBAR16_AND(CLOCKGATINGIII, ~0x0dc0); - MCHBAR8_AND(C0WRDPYN, ~0x80); - MCHBAR32_AND(C0COREBONUS, ~(1 << 22)); - MCHBAR16_AND(CLOCKGATINGI, ~0x80fc); - MCHBAR16_AND(CLOCKGATINGII, ~0x0c00); + mchbar16_and(CSHRMISCCTL, (u16)~0x0400); + mchbar16_and(CLOCKGATINGIII, (u16)~0x0dc0); + mchbar8_and(C0WRDPYN, (u8)~0x80); + mchbar32_and(C0COREBONUS, (u32)~(1 << 22)); + mchbar16_and(CLOCKGATINGI, (u16)~0x80fc); + mchbar16_and(CLOCKGATINGII, (u16)~0x0c00); - MCHBAR8_AND(CSHRPDCTL, ~0x0d); - MCHBAR8_AND(C0MISCCTLy(0), ~1); - MCHBAR8_AND(C0MISCCTLy(1), ~1); - MCHBAR8_AND(C0MISCCTLy(2), ~1); - MCHBAR8_AND(C0MISCCTLy(3), ~1); - MCHBAR8_AND(C0MISCCTLy(4), ~1); - MCHBAR8_AND(C0MISCCTLy(5), ~1); - MCHBAR8_AND(C0MISCCTLy(6), ~1); - MCHBAR8_AND(C0MISCCTLy(7), ~1); + mchbar8_and(CSHRPDCTL, (u8)~0x0d); + mchbar8_and(C0MISCCTLy(0), (u8)~1); + mchbar8_and(C0MISCCTLy(1), (u8)~1); + mchbar8_and(C0MISCCTLy(2), (u8)~1); + mchbar8_and(C0MISCCTLy(3), (u8)~1); + mchbar8_and(C0MISCCTLy(4), (u8)~1); + mchbar8_and(C0MISCCTLy(5), (u8)~1); + mchbar8_and(C0MISCCTLy(6), (u8)~1); + mchbar8_and(C0MISCCTLy(7), (u8)~1); - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x00700000, 3 << 20); - MCHBAR32_AND(C0COREBONUS, ~0x00100000); - MCHBAR8_OR(C0DYNSLVDLLEN, 0x1e); - MCHBAR8_OR(C0DYNSLVDLLEN2, 0x03); - MCHBAR32_AND_OR(SHCYCTRKCKEL, ~0x0c000000, 0x04000000); - MCHBAR16_OR(C0STATRDCTRL, 0x6000); - MCHBAR32_OR(C0CKECTRL, 0x00010000); - MCHBAR8_OR(C0COREBONUS, 0x10); - MCHBAR32_OR(CLOCKGATINGI - 1, 0xf << 24); - MCHBAR8_OR(CSHWRIOBONUS, 0x07); - MCHBAR8_OR(C0DYNSLVDLLEN, 0xc0); - MCHBAR8_OR(SHC2REGIII, 7); - MCHBAR16_AND_OR(SHC2MINTM, ~0xffff, 0x0080); - MCHBAR8_AND_OR(SHC2IDLETM, ~0xff, 0x10); - MCHBAR16_OR(C0COREBONUS, 0x01e0); - MCHBAR8_OR(CSHWRIOBONUS, 0x18); - MCHBAR8_OR(CSHRMSTDYNDLLENB, 0x0d); - MCHBAR16_OR(SHC3C4REG1, 0x0a3f); - MCHBAR8_OR(C0STATRDCTRL, 3); - MCHBAR8_AND_OR(C0REFRCTRL2, ~0xff, 0x4a); - MCHBAR8_AND(C0COREBONUS + 4, ~0x60); - MCHBAR16_OR(C0DYNSLVDLLEN, 0x0321); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x00700000, 3 << 20); + mchbar32_and(C0COREBONUS, (u32)~0x00100000); + mchbar8_or(C0DYNSLVDLLEN, 0x1e); + mchbar8_or(C0DYNSLVDLLEN2, 0x03); + mchbar32_and_or(SHCYCTRKCKEL, (u32)~0x0c000000, 0x04000000); + mchbar16_or(C0STATRDCTRL, 0x6000); + mchbar32_or(C0CKECTRL, 0x00010000); + mchbar8_or(C0COREBONUS, 0x10); + mchbar32_or(CLOCKGATINGI - 1, 0xf << 24); + mchbar8_or(CSHWRIOBONUS, 0x07); + mchbar8_or(C0DYNSLVDLLEN, 0xc0); + mchbar8_or(SHC2REGIII, 7); + mchbar16_and_or(SHC2MINTM, (u16)~0xffff, 0x0080); + mchbar8_and_or(SHC2IDLETM, (u8)~0xff, 0x10); + mchbar16_or(C0COREBONUS, 0x01e0); + mchbar8_or(CSHWRIOBONUS, 0x18); + mchbar8_or(CSHRMSTDYNDLLENB, 0x0d); + mchbar16_or(SHC3C4REG1, 0x0a3f); + mchbar8_or(C0STATRDCTRL, 3); + mchbar8_and_or(C0REFRCTRL2, (u8)~0xff, 0x4a); + mchbar8_and(C0COREBONUS + 4, (u8)~0x60); + mchbar16_or(C0DYNSLVDLLEN, 0x0321); } static void sdram_programdqdqs(struct sysinfo *s) @@ -2541,13 +2542,13 @@ if ((tmaxunmask >= reg32) && tmaxpi >= dqdqs_delay) { if (repeat == 2) { - MCHBAR32_AND(C0COREBONUS, ~(1 << 23)); + mchbar32_and(C0COREBONUS, (u32)~(1 << 23)); } feature = 1; repeat = 0; } else { repeat--; - MCHBAR32_OR(C0COREBONUS, 1 << 23); + mchbar32_or(C0COREBONUS, 1 << 23); cwb = 2 * mdclk; } } @@ -2556,10 +2557,10 @@ MCHBAR8(CLOCKGATINGI) = MCHBAR8(CLOCKGATINGI) & ~0x3; return; } - MCHBAR8_OR(CLOCKGATINGI, 3); - MCHBAR16_AND_OR(CLOCKGATINGIII, ~0xf000, pimdclk << 12); - MCHBAR8_AND_OR(CSHWRIOBONUSX, ~0x77, (push << 4) | push); - MCHBAR32_AND_OR(C0COREBONUS, ~0x0f000000, 0x03000000); + mchbar8_or(CLOCKGATINGI, 3); + mchbar16_and_or(CLOCKGATINGIII, (u16)~0xf000, pimdclk << 12); + mchbar8_and_or(CSHWRIOBONUSX, (u8)~0x77, (push << 4) | push); + mchbar32_and_or(C0COREBONUS, (u32)~0x0f000000, 0x03000000); } /** @@ -2592,7 +2593,7 @@ /* Enable HPET */ enable_hpet(); - MCHBAR16_OR(CPCTL, 1 << 15); + mchbar16_or(CPCTL, 1 << 15); sdram_clk_crossing(&si); @@ -2627,16 +2628,16 @@ PRINTK_DEBUG("Done mmap\n"); /* Enable DDR IO buffer */ - MCHBAR8_AND_OR(C0IOBUFACTCTL, ~0x3f, 0x08); - MCHBAR8_OR(C0RSTCTL, 1); + mchbar8_and_or(C0IOBUFACTCTL, (u8)~0x3f, 0x08); + mchbar8_or(C0RSTCTL, 1); sdram_rcompupdate(&si); PRINTK_DEBUG("Done RCOMP update\n"); - MCHBAR8_OR(HIT4, 2); + mchbar8_or(HIT4, 2); if (si.boot_path != BOOT_PATH_RESUME) { - MCHBAR32_OR(C0CKECTRL, 1 << 27); + mchbar32_or(C0CKECTRL, 1 << 27); sdram_jedecinit(&si); PRINTK_DEBUG("Done MRS\n"); @@ -2649,7 +2650,7 @@ PRINTK_DEBUG("Done zqcl\n"); if (si.boot_path != BOOT_PATH_RESUME) { - MCHBAR32_OR(C0REFRCTRL2, 3 << 30); + mchbar32_or(C0REFRCTRL2, 3 << 30); } sdram_dradrb(&si); @@ -2680,7 +2681,7 @@ PRINTK_DEBUG("Done periodic RCOMP\n"); /* Set init done */ - MCHBAR32_OR(C0REFRCTRL2, 1 << 30); + mchbar32_or(C0REFRCTRL2, 1 << 30); /* Tell ICH7 that we're done */ pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~(1 << 7)); -- To view, visit https://review.coreboot.org/c/coreboot/+/45517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fa844a8a13a75d6d802ca48f72c513bfa16d0a5 Gerrit-Change-Number: 45517 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 74

Change in coreboot[master]: src/drivers/spi: Use common 'SPI_OPCODE_*'
by HAOUAS Elyes (Code Review) 15 Feb '21

15 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45092 ) Change subject: src/drivers/spi: Use common 'SPI_OPCODE_*' ...................................................................... src/drivers/spi: Use common 'SPI_OPCODE_*' Change-Id: Ie0ec13ba56c813ffc5a62c3013f32221061ae94d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/spi/adesto.c M src/drivers/spi/amic.c M src/drivers/spi/atmel.c M src/drivers/spi/eon.c M src/drivers/spi/gigadevice.c M src/drivers/spi/macronix.c M src/drivers/spi/spansion.c M src/drivers/spi/sst.c M src/drivers/spi/stmicro.c M src/include/spi_flash.h 10 files changed, 20 insertions(+), 128 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/45092/1 diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index 6538905..9e786e0 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -12,20 +12,6 @@ #include "spi_flash_internal.h" -/* at25dfxx-specific commands */ -#define CMD_AT25DF_WREN 0x06 /* Write Enable */ -#define CMD_AT25DF_WRDI 0x04 /* Write Disable */ -#define CMD_AT25DF_RDSR 0x05 /* Read Status Register */ -#define CMD_AT25DF_WRSR 0x01 /* Write Status Register */ -#define CMD_AT25DF_READ 0x03 /* Read Data Bytes */ -#define CMD_AT25DF_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_AT25DF_PP 0x02 /* Page Program */ -#define CMD_AT25DF_SE 0x20 /* Sector (4K) Erase */ -#define CMD_AT25DF_BE 0xd8 /* Block (64K) Erase */ -#define CMD_AT25DF_CE 0xc7 /* Chip Erase */ -#define CMD_AT25DF_DP 0xb9 /* Deep Power-down */ -#define CMD_AT25DF_RES 0xab /* Release from DP, and Read Signature */ - static const struct spi_flash_part_id flash_table[] = { { /* AT25SL128A */ diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index 5e74616..9afa9fb 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -7,20 +7,6 @@ #include "spi_flash_internal.h" -/* A25L-specific commands */ -#define CMD_A25_WREN 0x06 /* Write Enable */ -#define CMD_A25_WRDI 0x04 /* Write Disable */ -#define CMD_A25_RDSR 0x05 /* Read Status Register */ -#define CMD_A25_WRSR 0x01 /* Write Status Register */ -#define CMD_A25_READ 0x03 /* Read Data Bytes */ -#define CMD_A25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_A25_PP 0x02 /* Page Program */ -#define CMD_A25_SE 0x20 /* Sector (4K) Erase */ -#define CMD_A25_BE 0xd8 /* Block (64K) Erase */ -#define CMD_A25_CE 0xc7 /* Chip Erase */ -#define CMD_A25_DP 0xb9 /* Deep Power-down */ -#define CMD_A25_RES 0xab /* Release from DP, and Read Signature */ - static const struct spi_flash_part_id flash_table[] = { { /* A25L16PU */ diff --git a/src/drivers/spi/atmel.c b/src/drivers/spi/atmel.c index 4dcc5b5..ab8b0fa 100644 --- a/src/drivers/spi/atmel.c +++ b/src/drivers/spi/atmel.c @@ -7,20 +7,6 @@ #include "spi_flash_internal.h" -/* M25Pxx-specific commands */ -#define CMD_AT25_WREN 0x06 /* Write Enable */ -#define CMD_AT25_WRDI 0x04 /* Write Disable */ -#define CMD_AT25_RDSR 0x05 /* Read Status Register */ -#define CMD_AT25_WRSR 0x01 /* Write Status Register */ -#define CMD_AT25_READ 0x03 /* Read Data Bytes */ -#define CMD_AT25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_AT25_PP 0x02 /* Page Program */ -#define CMD_AT25_SE 0x20 /* Sector (4K) Erase */ -#define CMD_AT25_BE 0xd8 /* Block (64K) Erase */ -#define CMD_AT25_CE 0xc7 /* Chip Erase */ -#define CMD_AT25_DP 0xb9 /* Deep Power-down */ -#define CMD_AT25_RES 0xab /* Release from DP, and Read Signature */ - static const struct spi_flash_part_id flash_table[] = { { /* AT25X16 */ diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 1212c6b..f6ef3d0 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -7,19 +7,6 @@ #include "spi_flash_internal.h" -/* EN25*-specific commands */ -#define CMD_EN25_WREN 0x06 /* Write Enable */ -#define CMD_EN25_WRDI 0x04 /* Write Disable */ -#define CMD_EN25_RDSR 0x05 /* Read Status Register */ -#define CMD_EN25_WRSR 0x01 /* Write Status Register */ -#define CMD_EN25_READ 0x03 /* Read Data Bytes */ -#define CMD_EN25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_EN25_PP 0x02 /* Page Program */ -#define CMD_EN25_SE 0x20 /* Sector Erase */ -#define CMD_EN25_BE 0xd8 /* Block Erase */ -#define CMD_EN25_DP 0xb9 /* Deep Power-down */ -#define CMD_EN25_RES 0xab /* Release from DP, and Read Signature */ - #define EON_ID_EN25B80 0x2014 #define EON_ID_EN25B16 0x2015 #define EON_ID_EN25B32 0x2016 diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 6c5a167..0d20758 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -7,20 +7,6 @@ #include "spi_flash_internal.h" -/* GD25Pxx-specific commands */ -#define CMD_GD25_WREN 0x06 /* Write Enable */ -#define CMD_GD25_WRDI 0x04 /* Write Disable */ -#define CMD_GD25_RDSR 0x05 /* Read Status Register */ -#define CMD_GD25_WRSR 0x01 /* Write Status Register */ -#define CMD_GD25_READ 0x03 /* Read Data Bytes */ -#define CMD_GD25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_GD25_PP 0x02 /* Page Program */ -#define CMD_GD25_SE 0x20 /* Sector (4K) Erase */ -#define CMD_GD25_BE 0xd8 /* Block (64K) Erase */ -#define CMD_GD25_CE 0xc7 /* Chip Erase */ -#define CMD_GD25_DP 0xb9 /* Deep Power-down */ -#define CMD_GD25_RES 0xab /* Release from DP, and Read Signature */ - static const struct spi_flash_part_id flash_table[] = { { /* GD25T80 */ diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index f3f7e2d..f8f773a 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -7,20 +7,6 @@ #include "spi_flash_internal.h" -/* MX25xx-specific commands */ -#define CMD_MX25XX_WREN 0x06 /* Write Enable */ -#define CMD_MX25XX_WRDI 0x04 /* Write Disable */ -#define CMD_MX25XX_RDSR 0x05 /* Read Status Register */ -#define CMD_MX25XX_WRSR 0x01 /* Write Status Register */ -#define CMD_MX25XX_READ 0x03 /* Read Data Bytes */ -#define CMD_MX25XX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_MX25XX_PP 0x02 /* Page Program */ -#define CMD_MX25XX_SE 0x20 /* Sector Erase */ -#define CMD_MX25XX_BE 0xD8 /* Block Erase */ -#define CMD_MX25XX_CE 0xc7 /* Chip Erase */ -#define CMD_MX25XX_DP 0xb9 /* Deep Power-down */ -#define CMD_MX25XX_RES 0xab /* Release from DP, and Read Signature */ - #define MACRONIX_SR_WIP (1 << 0) /* Write-in-Progress */ static const struct spi_flash_part_id flash_table[] = { diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index fe0e265..ff912bd 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -7,20 +7,6 @@ #include "spi_flash_internal.h" -/* S25FLxx-specific commands */ -#define CMD_S25FLXX_READ 0x03 /* Read Data Bytes */ -#define CMD_S25FLXX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_S25FLXX_READID 0x90 /* Read Manufacture ID and Device ID */ -#define CMD_S25FLXX_WREN 0x06 /* Write Enable */ -#define CMD_S25FLXX_WRDI 0x04 /* Write Disable */ -#define CMD_S25FLXX_RDSR 0x05 /* Read Status Register */ -#define CMD_S25FLXX_WRSR 0x01 /* Write Status Register */ -#define CMD_S25FLXX_PP 0x02 /* Page Program */ -#define CMD_S25FLXX_SE 0xd8 /* Sector Erase */ -#define CMD_S25FLXX_BE 0xc7 /* Bulk Erase */ -#define CMD_S25FLXX_DP 0xb9 /* Deep Power-down */ -#define CMD_S25FLXX_RES 0xab /* Release from DP, and Read Signature */ - #define SPSN_ID_S25FL008A 0x0213 #define SPSN_ID_S25FL016A 0x0214 #define SPSN_ID_S25FL032A 0x0215 diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 887380f..02e5129 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -11,15 +11,8 @@ #include "spi_flash_internal.h" -#define CMD_SST_WREN 0x06 /* Write Enable */ -#define CMD_SST_WRDI 0x04 /* Write Disable */ -#define CMD_SST_RDSR 0x05 /* Read Status Register */ -#define CMD_SST_WRSR 0x01 /* Write Status Register */ #define CMD_SST_EWSR 0x50 /* Enable Write Status Register */ -#define CMD_SST_READ 0x03 /* Read Data Bytes */ -#define CMD_SST_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ #define CMD_SST_BP 0x02 /* Byte Program */ -#define CMD_SST_PP 0x02 /* Page Program */ #define CMD_SST_AAI_WP 0xAD /* Auto Address Increment Word Program */ #define CMD_SST_SE 0x20 /* Sector Erase */ @@ -90,7 +83,7 @@ static int sst_enable_writing(const struct spi_flash *flash) { - int ret = spi_flash_cmd(&flash->spi, CMD_SST_WREN, NULL, 0); + int ret = spi_flash_cmd(&flash->spi, SPI_OPCODE_WREN, NULL, 0); if (ret) printk(BIOS_WARNING, "SF: Enabling Write failed\n"); return ret; @@ -108,7 +101,7 @@ static int sst_disable_writing(const struct spi_flash *flash) { - int ret = spi_flash_cmd(&flash->spi, CMD_SST_WRDI, NULL, 0); + int ret = spi_flash_cmd(&flash->spi, SPI_OPCODE_WRDI, NULL, 0); if (ret) printk(BIOS_WARNING, "SF: Disabling Write failed\n"); return ret; @@ -127,7 +120,7 @@ #if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "BP[%02x]: %p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(&flash->spi, CMD_SST_RDSR), buf, cmd[0], offset); + spi_w8r8(&flash->spi, SPI_OPCODE_RDSR), buf, cmd[0], offset); #endif ret = sst_enable_writing(flash); @@ -170,7 +163,7 @@ for (; actual < len - 1; actual += 2) { #if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "WP[%02x]: %p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(&flash->spi, CMD_SST_RDSR), buf + actual, cmd[0], + spi_w8r8(&flash->spi, SPI_OPCODE_RDSR), buf + actual, cmd[0], offset); #endif @@ -215,21 +208,21 @@ if (ret) return ret; - cmd = CMD_SST_WRSR; + cmd = SPI_OPCODE_WRSR; status = 0; ret = spi_flash_cmd_write(&flash->spi, &cmd, 1, &status, 1); if (ret) printk(BIOS_WARNING, "SF: Unable to set status byte\n"); - printk(BIOS_INFO, "SF: SST: status = %x\n", spi_w8r8(&flash->spi, CMD_SST_RDSR)); + printk(BIOS_INFO, "SF: SST: status = %x\n", spi_w8r8(&flash->spi, SPI_OPCODE_RDSR)); return ret; } static const struct spi_flash_ops_descriptor descai = { .erase_cmd = CMD_SST_SE, - .status_cmd = CMD_SST_RDSR, - .wren_cmd = CMD_SST_WREN, + .status_cmd = SPI_OPCODE_RDSR, + .wren_cmd = SPI_OPCODE_WREN, .ops = { .read = spi_flash_cmd_read, .write = sst_write_ai, diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 4cd8c1b..63b6451 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -7,20 +7,6 @@ #include "spi_flash_internal.h" -/* M25Pxx-specific commands */ -#define CMD_M25PXX_WREN 0x06 /* Write Enable */ -#define CMD_M25PXX_WRDI 0x04 /* Write Disable */ -#define CMD_M25PXX_RDSR 0x05 /* Read Status Register */ -#define CMD_M25PXX_WRSR 0x01 /* Write Status Register */ -#define CMD_M25PXX_READ 0x03 /* Read Data Bytes */ -#define CMD_M25PXX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_M25PXX_PP 0x02 /* Page Program */ -#define CMD_M25PXX_SSE 0x20 /* Subsector Erase */ -#define CMD_M25PXX_SE 0xd8 /* Sector Erase */ -#define CMD_M25PXX_BE 0xc7 /* Bulk Erase */ -#define CMD_M25PXX_DP 0xb9 /* Deep Power-down */ -#define CMD_M25PXX_RES 0xab /* Release from DP, and Read Signature */ - /* * Device ID = (memory_type << 8) + memory_capacity */ diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 1061e99..d5ba116 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -9,8 +9,18 @@ #include <boot/coreboot_tables.h> /* SPI Flash opcodes */ -#define SPI_OPCODE_WREN 0x06 -#define SPI_OPCODE_FAST_READ 0x0b +#define SPI_OPCODE_WREN 0x06 /* Write Enable */ +#define SPI_OPCODE_WRDI 0x04 /* Write Disable */ +#define SPI_OPCODE_RDSR 0x05 /* Read Status Register */ +#define SPI_OPCODE_WRSR 0x01 /* Write Status Register */ +#define SPI_OPCODE_READ 0x03 /* Read Data Bytes */ +#define SPI_OPCODE_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define SPI_OPCODE_PP 0x02 /* Page Program */ +#define SPI_OPCODE_SE 0x20 /* Sector (4K) Erase */ +#define SPI_OPCODE_BE 0xd8 /* Block (64K) Erase */ +#define SPI_OPCODE_CE 0xc7 /* Chip Erase */ +#define SPI_OPCODE_DP 0xb9 /* Deep Power-down */ +#define SPI_OPCODE_RES 0xab /* Release from DP, and Read Signature */ struct spi_flash; -- To view, visit https://review.coreboot.org/c/coreboot/+/45092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0ec13ba56c813ffc5a62c3013f32221061ae94d Gerrit-Change-Number: 45092 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 4

Change in coreboot[master]: mb/51nb/x210/acpi: Convert to to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 15 Feb '21

15 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45772 ) Change subject: mb/51nb/x210/acpi: Convert to to ASL 2.0 syntax ...................................................................... mb/51nb/x210/acpi: Convert to to ASL 2.0 syntax Generated build/dsdt.dsl before and after current patch are same. Change-Id: Ia0354e535229e832cf0e65cb8744a1ee8d5e8a34 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/51nb/x210/acpi/battery.asl M src/mainboard/51nb/x210/acpi/ec.asl M src/mainboard/51nb/x210/acpi/platform.asl 3 files changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/45772/1 diff --git a/src/mainboard/51nb/x210/acpi/battery.asl b/src/mainboard/51nb/x210/acpi/battery.asl index f9022a4..b81af1f 100644 --- a/src/mainboard/51nb/x210/acpi/battery.asl +++ b/src/mainboard/51nb/x210/acpi/battery.asl @@ -37,19 +37,19 @@ Method (_BIF, 0, Serialized) { /* Design Capacity */ - Store (DGCP * 10000 / DGVO, Index (PBIF, 1)) + PBIF [One] = (DGCP * 10000) / DGVO /* Last Full Charge Capacity */ - Store (FLCP * 10000 / DGVO, Index (PBIF, 2)) + PBIF [2] = (FLCP * 10000) / DGVO /* Design Voltage */ - Store (DGVO, Index (PBIF, 4)) + PBIF [4] = DGVO /* Design Capacity of Warning */ - Store (BDW * 10000 / DGVO, Index (PBIF, 5)) + PBIF [5] = (BDW * 10000) / DGVO /* Design Capacity of Low */ - Store (BDL, Index (PBIF, 6)) + PBIF [6] = BDL Return (PBIF) } @@ -70,22 +70,22 @@ * bit 1 = charging * bit 2 = critical level */ - Store (BSTS, Index (PBST, 0)) + PBST [0] = BSTS /* * 1: BATTERY PRESENT RATE */ - Store (BPR, Index (PBST, 1)) + PBST [1] = BPR /* * 2: BATTERY REMAINING CAPACITY */ - Store (BRC * 10000 / DGVO, Index (PBST, 2)) + PBST [2] = (BRC * 10000) / DGVO /* * 3: BATTERY PRESENT VOLTAGE */ - Store (BPV, Index (PBST, 3)) + PBST [3] = BPV Return (PBST) } diff --git a/src/mainboard/51nb/x210/acpi/ec.asl b/src/mainboard/51nb/x210/acpi/ec.asl index 78e156c..fc1aafc 100644 --- a/src/mainboard/51nb/x210/acpi/ec.asl +++ b/src/mainboard/51nb/x210/acpi/ec.asl @@ -45,10 +45,10 @@ Method (_REG, 2, NotSerialized) { /* Initialize AC power state */ - Store (ACIN, \PWRS) + PWRS = ACIN /* Initialize LID switch state */ - Store (LIDC, \LIDS) + LIDS = LIDC } /* KEY_BRIGHTNESSUP */ @@ -79,7 +79,7 @@ /* Lid event */ Method (_Q0E) { - Store (LIDC, \LIDS) + LIDS = LIDC Notify (LID0, 0x80) } diff --git a/src/mainboard/51nb/x210/acpi/platform.asl b/src/mainboard/51nb/x210/acpi/platform.asl index 6cf3f32..3415767 100644 --- a/src/mainboard/51nb/x210/acpi/platform.asl +++ b/src/mainboard/51nb/x210/acpi/platform.asl @@ -14,7 +14,7 @@ Method (_PIC, 1) { /* Remember the OS' IRQ routing choice. */ - Store (Arg0, PICM) + PICM = Arg0 } /* @@ -30,7 +30,7 @@ Method (_WAK, 1) { - Store(\_SB.PCI0.LPCB.EC.LIDC, \LIDS) - Store(\_SB.PCI0.LPCB.EC.ACIN, \PWRS) + LIDS = \_SB.PCI0.LPCB.EC.LIDC + PWRS = \_SB.PCI0.LPCB.EC.ACIN Return (Package (){ 0, 0 }) } -- To view, visit https://review.coreboot.org/c/coreboot/+/45772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0354e535229e832cf0e65cb8744a1ee8d5e8a34 Gerrit-Change-Number: 45772 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: sb/intel/i82801ix/acpi: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 15 Feb '21

15 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45735 ) Change subject: sb/intel/i82801ix/acpi: Convert to ASL 2.0 syntax ...................................................................... sb/intel/i82801ix/acpi: Convert to ASL 2.0 syntax Change-Id: I198f8df954f423ca5e19a7ee740ab062108ad14b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801ix/acpi/ich9.asl M src/southbridge/intel/i82801ix/acpi/lpc.asl M src/southbridge/intel/i82801ix/acpi/usb.asl 3 files changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/45735/1 diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl index 25a756e..11595d2 100644 --- a/src/southbridge/intel/i82801ix/acpi/ich9.asl +++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl @@ -174,7 +174,7 @@ Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) @@ -183,7 +183,7 @@ { /* Unrecognized UUID */ CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + CDW1|= 4 Return (Arg3) } } diff --git a/src/southbridge/intel/i82801ix/acpi/lpc.asl b/src/southbridge/intel/i82801ix/acpi/lpc.asl index b93fa96..1f9e701 100644 --- a/src/southbridge/intel/i82801ix/acpi/lpc.asl +++ b/src/southbridge/intel/i82801ix/acpi/lpc.asl @@ -73,7 +73,7 @@ If (HPTE) { // Note: Ancient versions of Windows don't want // to see the HPET in order to work right - If (LGreaterEqual(OSYS, 2001)) { + If (OSYS >= 2001) { Return (0xf) // Enable and show device } Else { Return (0xb) // Enable and don't show device @@ -87,16 +87,16 @@ { If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - If (Lequal(HPAS, 1)) { - Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) + If (HPAS == 1) { + HPT0 = CONFIG_HPET_ADDRESS + 0x1000 } - If (Lequal(HPAS, 2)) { - Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) + If (HPAS == 2) { + HPT0 = CONFIG_HPET_ADDRESS + 0x2000 } - If (Lequal(HPAS, 3)) { - Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) + If (HPAS == 3) { + HPT0 = CONFIG_HPET_ADDRESS + 0x3000 } } diff --git a/src/southbridge/intel/i82801ix/acpi/usb.asl b/src/southbridge/intel/i82801ix/acpi/usb.asl index 55929af..f55ed66 100644 --- a/src/southbridge/intel/i82801ix/acpi/usb.asl +++ b/src/southbridge/intel/i82801ix/acpi/usb.asl @@ -21,9 +21,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U1WE) + U1WE = 3 } Else { - Store (0, U1WE) + U1WE = 0 } } @@ -60,9 +60,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U2WE) + U2WE = 3 } Else { - Store (0, U2WE) + U2WE = 0 } } @@ -100,9 +100,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U3WE) + U3WE = 3 } Else { - Store (0, U3WE) + U3WE = 0 } } @@ -175,9 +175,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U1WE) + U1WE = 3 } Else { - Store (0, U1WE) + U1WE = 0 } } @@ -214,9 +214,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U2WE) + U2WE = 3 } Else { - Store (0, U2WE) + U2WE = 0 } } @@ -254,9 +254,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U3WE) + U3WE = 3 } Else { - Store (0, U3WE) + U3WE = 0 } } -- To view, visit https://review.coreboot.org/c/coreboot/+/45735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I198f8df954f423ca5e19a7ee740ab062108ad14b Gerrit-Change-Number: 45735 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: sb/intel/i82801jx/acpi: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 15 Feb '21

15 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45734 ) Change subject: sb/intel/i82801jx/acpi: Convert to ASL 2.0 syntax ...................................................................... sb/intel/i82801jx/acpi: Convert to ASL 2.0 syntax Change-Id: I93becba4cbb43625096c631b4a013d3db3fbff67 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/i82801jx/acpi/lpc.asl M src/southbridge/intel/i82801jx/acpi/usb.asl 3 files changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/45734/1 diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl index e62f8a1..b4b7f83 100644 --- a/src/southbridge/intel/i82801jx/acpi/ich10.asl +++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl @@ -175,7 +175,7 @@ Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) @@ -184,7 +184,7 @@ { /* Unrecognized UUID */ CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + CDW1|= 4 Return (Arg3) } } diff --git a/src/southbridge/intel/i82801jx/acpi/lpc.asl b/src/southbridge/intel/i82801jx/acpi/lpc.asl index b93fa96..1f9e701 100644 --- a/src/southbridge/intel/i82801jx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801jx/acpi/lpc.asl @@ -73,7 +73,7 @@ If (HPTE) { // Note: Ancient versions of Windows don't want // to see the HPET in order to work right - If (LGreaterEqual(OSYS, 2001)) { + If (OSYS >= 2001) { Return (0xf) // Enable and show device } Else { Return (0xb) // Enable and don't show device @@ -87,16 +87,16 @@ { If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - If (Lequal(HPAS, 1)) { - Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) + If (HPAS == 1) { + HPT0 = CONFIG_HPET_ADDRESS + 0x1000 } - If (Lequal(HPAS, 2)) { - Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) + If (HPAS == 2) { + HPT0 = CONFIG_HPET_ADDRESS + 0x2000 } - If (Lequal(HPAS, 3)) { - Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) + If (HPAS == 3) { + HPT0 = CONFIG_HPET_ADDRESS + 0x3000 } } diff --git a/src/southbridge/intel/i82801jx/acpi/usb.asl b/src/southbridge/intel/i82801jx/acpi/usb.asl index 55929af..f55ed66 100644 --- a/src/southbridge/intel/i82801jx/acpi/usb.asl +++ b/src/southbridge/intel/i82801jx/acpi/usb.asl @@ -21,9 +21,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U1WE) + U1WE = 3 } Else { - Store (0, U1WE) + U1WE = 0 } } @@ -60,9 +60,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U2WE) + U2WE = 3 } Else { - Store (0, U2WE) + U2WE = 0 } } @@ -100,9 +100,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U3WE) + U3WE = 3 } Else { - Store (0, U3WE) + U3WE = 0 } } @@ -175,9 +175,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U1WE) + U1WE = 3 } Else { - Store (0, U1WE) + U1WE = 0 } } @@ -214,9 +214,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U2WE) + U2WE = 3 } Else { - Store (0, U2WE) + U2WE = 0 } } @@ -254,9 +254,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U3WE) + U3WE = 3 } Else { - Store (0, U3WE) + U3WE = 0 } } -- To view, visit https://review.coreboot.org/c/coreboot/+/45734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93becba4cbb43625096c631b4a013d3db3fbff67 Gerrit-Change-Number: 45734 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: trogdor: fix EC/SPI communication after qclib
by mturney mturney (Code Review) 13 Feb '21

13 Feb '21

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37482 ) Change subject: trogdor: fix EC/SPI communication after qclib ...................................................................... trogdor: fix EC/SPI communication after qclib Change-Id: Id36ff5f81adb495ad762ce74e224add03520260d Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M src/mainboard/google/trogdor/mainboard.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/37482/1 diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index 8849911..6b79004 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -20,6 +20,8 @@ #include <timestamp.h> #include <soc/usb.h> #include <soc/qupv3_fw_config.h> +#include <soc/qcom_qup_se.h> +#include <soc/spi_qup_qcom.h> static struct usb_board_data usb0_board_data = { .pll_bias_control_2 = 0x22, @@ -36,6 +38,9 @@ { setup_usb(); qupv3_fw_init(); + qup_spi_init(QUPV3_0_SE0, 1010 * KHz); /* EC SPI */ + qup_spi_init(QUPV3_1_SE0, 1010 * KHz); /* H1 SPI */ + } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/37482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id36ff5f81adb495ad762ce74e224add03520260d Gerrit-Change-Number: 37482 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: [WIP] mainboard: Add MSI H81M-P33
by Angel Pons (Code Review) 13 Feb '21

13 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41260 ) Change subject: [WIP] mainboard: Add MSI H81M-P33 ...................................................................... [WIP] mainboard: Add MSI H81M-P33 Untested and missing SuperIO support. (NCT5532D) Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0xff, id=0xc563, rev=0x00 Change-Id: I9e47747a99c65e488487fbbcac1de15b9bf5c235 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/msi/h81m-p33/Kconfig A src/mainboard/msi/h81m-p33/Kconfig.name A src/mainboard/msi/h81m-p33/Makefile.inc A src/mainboard/msi/h81m-p33/acpi/ec.asl A src/mainboard/msi/h81m-p33/acpi/platform.asl A src/mainboard/msi/h81m-p33/acpi/superio.asl A src/mainboard/msi/h81m-p33/acpi_tables.c A src/mainboard/msi/h81m-p33/board_info.txt A src/mainboard/msi/h81m-p33/devicetree.cb A src/mainboard/msi/h81m-p33/dsdt.asl A src/mainboard/msi/h81m-p33/gma-mainboard.ads A src/mainboard/msi/h81m-p33/gpio.c A src/mainboard/msi/h81m-p33/hda_verb.c A src/mainboard/msi/h81m-p33/romstage.c 14 files changed, 470 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/41260/1 diff --git a/src/mainboard/msi/h81m-p33/Kconfig b/src/mainboard/msi/h81m-p33/Kconfig new file mode 100644 index 0000000..d8ad2b0 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/Kconfig @@ -0,0 +1,31 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_MSI_H81M_P33 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_HASWELL + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + +config MAINBOARD_DIR + string + default msi/h81m-p33 + +config MAINBOARD_PART_NUMBER + string + default "H81M-P33" + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/msi/h81m-p33/Kconfig.name b/src/mainboard/msi/h81m-p33/Kconfig.name new file mode 100644 index 0000000..ac4bd28 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_MSI_H81M_P33 + bool "H81M-P33 (MS-7817 v1.2)" diff --git a/src/mainboard/msi/h81m-p33/Makefile.inc b/src/mainboard/msi/h81m-p33/Makefile.inc new file mode 100644 index 0000000..ea035d3 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/msi/h81m-p33/acpi/ec.asl b/src/mainboard/msi/h81m-p33/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/acpi/ec.asl diff --git a/src/mainboard/msi/h81m-p33/acpi/platform.asl b/src/mainboard/msi/h81m-p33/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/msi/h81m-p33/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/msi/h81m-p33/acpi/superio.asl b/src/mainboard/msi/h81m-p33/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/acpi/superio.asl diff --git a/src/mainboard/msi/h81m-p33/acpi_tables.c b/src/mainboard/msi/h81m-p33/acpi_tables.c new file mode 100644 index 0000000..f00b3e7 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/acpi_tables.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/msi/h81m-p33/board_info.txt b/src/mainboard/msi/h81m-p33/board_info.txt new file mode 100644 index 0000000..be6bff8 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/board_info.txt @@ -0,0 +1,4 @@ +Category: desktop +ROM protocol: SPI +Flashrom support: n +FIXME: check category, , put ROM package, ROM socketed, Release year diff --git a/src/mainboard/msi/h81m-p33/devicetree.cb b/src/mainboard/msi/h81m-p33/devicetree.cb new file mode 100644 index 0000000..98f4104 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/devicetree.cb @@ -0,0 +1,67 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/haswell + + register "gpu_ddi_e_connected" = "1" + + device cpu_cluster 0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + + device domain 0 on + subsystemid 0x1462 0x7817 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # iGPU + device pci 03.0 off end # Mini-HD audio + + chip southbridge/intel/lynxpoint + register "gen1_dec" = "0x001c0a01" + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x80" + register "pirqc_routing" = "0x83" + register "pirqd_routing" = "0x8a" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x85" + register "pirqh_routing" = "0x8b" + register "sata_ahci" = "1" + register "sata_port_map" = "0x3f" + + device pci 14.0 on end # xHCI Controller + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT + device pci 19.0 off end # Intel GbE + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # HD Audio + device pci 1c.0 on end # RP #1: PCIe x1 + device pci 1c.1 off end # RP #2 + device pci 1c.2 on end # RP #3: RTL8111 GbE NIC + device pci 1c.3 off end # RP #4 + device pci 1c.4 off end # RP #5 + device pci 1c.5 off end # RP #6 + device pci 1c.6 off end # RP #7 + device pci 1c.7 off end # RP #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + # FIXME: SuperIO + end + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/msi/h81m-p33/dsdt.asl b/src/mainboard/msi/h81m-p33/dsdt.asl new file mode 100644 index 0000000..f2a3003 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/dsdt.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/msi/h81m-p33/gma-mainboard.ads b/src/mainboard/msi/h81m-p33/gma-mainboard.ads new file mode 100644 index 0000000..8483695 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- FIXME: Only one is actually HDMI + HDMI2, + HDMI3, + Analog, -- VGA + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/msi/h81m-p33/gpio.c b/src/mainboard/msi/h81m-p33/gpio.c new file mode 100644 index 0000000..6553f42 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/gpio.c @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/msi/h81m-p33/hda_verb.c b/src/mainboard/msi/h81m-p33/hda_verb.c new file mode 100644 index 0000000..23e64b7 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/hda_verb.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x1462d817, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1462d817), + AZALIA_PIN_CFG(0, 0x11, 0x4037c040), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19030), + AZALIA_PIN_CFG(0, 0x19, 0x02a19040), + AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4025c603), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/msi/h81m-p33/romstage.c b/src/mainboard/msi/h81m-p33/romstage.c new file mode 100644 index 0000000..1fc56e1 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/romstage.c @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <arch/romstage.h> +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/pei_data.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/lynxpoint/pch.h> + +static const struct rcba_config_instruction rcba_config[] = { + RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), + RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), + RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), + RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), + RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)), + RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +void mainboard_config_superio(void) +{ +} + +void mainboard_romstage_entry(void) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 1, /* desktop/server */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* FIXME: check this */ + .ec_present = 0, + .gbe_enable = 0, /* FIXME: check this */ + .dimm_channel0_disabled = 0, + .dimm_channel1_disabled = 0, + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + }, + .usb3_ports = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = rcba_config, + }; + + romstage_common(&romstage_params); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e47747a99c65e488487fbbcac1de15b9bf5c235 Gerrit-Change-Number: 41260 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 21

Change in coreboot[master]: soc/amd/{picasso,stoneyridge}/romstage.c: Use post_codes macros
by HAOUAS Elyes (Code Review) 11 Feb '21

11 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45526 ) Change subject: soc/amd/{picasso,stoneyridge}/romstage.c: Use post_codes macros ...................................................................... soc/amd/{picasso,stoneyridge}/romstage.c: Use post_codes macros Change-Id: I51782996602a4ae17058e6ff85d4e05f751a2bfd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/romstage.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/45526/1 diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index b967431..09fc987 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -145,7 +145,7 @@ { int s3_resume; - post_code(0x40); + post_code(POST_CONSOLE_BOOT_MSG); console_init(); post_code(0x41); diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 96103ef..0940569 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -69,7 +69,7 @@ bsp_agesa_call(); if (!s3_resume) { - post_code(0x40); + post_code(POST_CONSOLE_BOOT_MSG); do_agesawrapper(AMD_INIT_POST, "amdinitpost"); post_code(0x41); @@ -102,7 +102,7 @@ wrmsr(SYSCFG_MSR, sys_cfg); } else { printk(BIOS_INFO, "S3 detected\n"); - post_code(0x60); + post_code(POST_ENABLING_CACHE); do_agesawrapper(AMD_INIT_RESUME, "amdinitresume"); post_code(0x61); -- To view, visit https://review.coreboot.org/c/coreboot/+/45526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51782996602a4ae17058e6ff85d4e05f751a2bfd Gerrit-Change-Number: 45526 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020