Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41260 )
Change subject: [WIP] mainboard: Add MSI H81M-P33 ......................................................................
[WIP] mainboard: Add MSI H81M-P33
Untested and missing SuperIO support. (NCT5532D)
Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0xff, id=0xc563, rev=0x00
Change-Id: I9e47747a99c65e488487fbbcac1de15b9bf5c235 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/msi/h81m-p33/Kconfig A src/mainboard/msi/h81m-p33/Kconfig.name A src/mainboard/msi/h81m-p33/Makefile.inc A src/mainboard/msi/h81m-p33/acpi/ec.asl A src/mainboard/msi/h81m-p33/acpi/platform.asl A src/mainboard/msi/h81m-p33/acpi/superio.asl A src/mainboard/msi/h81m-p33/acpi_tables.c A src/mainboard/msi/h81m-p33/board_info.txt A src/mainboard/msi/h81m-p33/devicetree.cb A src/mainboard/msi/h81m-p33/dsdt.asl A src/mainboard/msi/h81m-p33/gma-mainboard.ads A src/mainboard/msi/h81m-p33/gpio.c A src/mainboard/msi/h81m-p33/hda_verb.c A src/mainboard/msi/h81m-p33/romstage.c 14 files changed, 470 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/41260/1
diff --git a/src/mainboard/msi/h81m-p33/Kconfig b/src/mainboard/msi/h81m-p33/Kconfig new file mode 100644 index 0000000..d8ad2b0 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/Kconfig @@ -0,0 +1,31 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_MSI_H81M_P33 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_HASWELL + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + +config MAINBOARD_DIR + string + default msi/h81m-p33 + +config MAINBOARD_PART_NUMBER + string + default "H81M-P33" + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/msi/h81m-p33/Kconfig.name b/src/mainboard/msi/h81m-p33/Kconfig.name new file mode 100644 index 0000000..ac4bd28 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_MSI_H81M_P33 + bool "H81M-P33 (MS-7817 v1.2)" diff --git a/src/mainboard/msi/h81m-p33/Makefile.inc b/src/mainboard/msi/h81m-p33/Makefile.inc new file mode 100644 index 0000000..ea035d3 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/msi/h81m-p33/acpi/ec.asl b/src/mainboard/msi/h81m-p33/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/acpi/ec.asl diff --git a/src/mainboard/msi/h81m-p33/acpi/platform.asl b/src/mainboard/msi/h81m-p33/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/msi/h81m-p33/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/msi/h81m-p33/acpi/superio.asl b/src/mainboard/msi/h81m-p33/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/acpi/superio.asl diff --git a/src/mainboard/msi/h81m-p33/acpi_tables.c b/src/mainboard/msi/h81m-p33/acpi_tables.c new file mode 100644 index 0000000..f00b3e7 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/acpi_tables.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/msi/h81m-p33/board_info.txt b/src/mainboard/msi/h81m-p33/board_info.txt new file mode 100644 index 0000000..be6bff8 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/board_info.txt @@ -0,0 +1,4 @@ +Category: desktop +ROM protocol: SPI +Flashrom support: n +FIXME: check category, , put ROM package, ROM socketed, Release year diff --git a/src/mainboard/msi/h81m-p33/devicetree.cb b/src/mainboard/msi/h81m-p33/devicetree.cb new file mode 100644 index 0000000..98f4104 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/devicetree.cb @@ -0,0 +1,67 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/haswell + + register "gpu_ddi_e_connected" = "1" + + device cpu_cluster 0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + + device domain 0 on + subsystemid 0x1462 0x7817 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # iGPU + device pci 03.0 off end # Mini-HD audio + + chip southbridge/intel/lynxpoint + register "gen1_dec" = "0x001c0a01" + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x80" + register "pirqc_routing" = "0x83" + register "pirqd_routing" = "0x8a" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x85" + register "pirqh_routing" = "0x8b" + register "sata_ahci" = "1" + register "sata_port_map" = "0x3f" + + device pci 14.0 on end # xHCI Controller + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT + device pci 19.0 off end # Intel GbE + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # HD Audio + device pci 1c.0 on end # RP #1: PCIe x1 + device pci 1c.1 off end # RP #2 + device pci 1c.2 on end # RP #3: RTL8111 GbE NIC + device pci 1c.3 off end # RP #4 + device pci 1c.4 off end # RP #5 + device pci 1c.5 off end # RP #6 + device pci 1c.6 off end # RP #7 + device pci 1c.7 off end # RP #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + # FIXME: SuperIO + end + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/msi/h81m-p33/dsdt.asl b/src/mainboard/msi/h81m-p33/dsdt.asl new file mode 100644 index 0000000..f2a3003 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/dsdt.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/msi/h81m-p33/gma-mainboard.ads b/src/mainboard/msi/h81m-p33/gma-mainboard.ads new file mode 100644 index 0000000..8483695 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- FIXME: Only one is actually HDMI + HDMI2, + HDMI3, + Analog, -- VGA + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/msi/h81m-p33/gpio.c b/src/mainboard/msi/h81m-p33/gpio.c new file mode 100644 index 0000000..6553f42 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/gpio.c @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/msi/h81m-p33/hda_verb.c b/src/mainboard/msi/h81m-p33/hda_verb.c new file mode 100644 index 0000000..23e64b7 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/hda_verb.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x1462d817, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1462d817), + AZALIA_PIN_CFG(0, 0x11, 0x4037c040), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19030), + AZALIA_PIN_CFG(0, 0x19, 0x02a19040), + AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4025c603), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/msi/h81m-p33/romstage.c b/src/mainboard/msi/h81m-p33/romstage.c new file mode 100644 index 0000000..1fc56e1 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/romstage.c @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <arch/romstage.h> +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/pei_data.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/lynxpoint/pch.h> + +static const struct rcba_config_instruction rcba_config[] = { + RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), + RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), + RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), + RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), + RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)), + RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +void mainboard_config_superio(void) +{ +} + +void mainboard_romstage_entry(void) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 1, /* desktop/server */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* FIXME: check this */ + .ec_present = 0, + .gbe_enable = 0, /* FIXME: check this */ + .dimm_channel0_disabled = 0, + .dimm_channel1_disabled = 0, + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + }, + .usb3_ports = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = rcba_config, + }; + + romstage_common(&romstage_params); +}
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41260
to look at the new patch set (#2).
Change subject: [WIP] mainboard: Add MSI H81M-P33 ......................................................................
[WIP] mainboard: Add MSI H81M-P33
Untested.
Change-Id: I9e47747a99c65e488487fbbcac1de15b9bf5c235 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/msi/h81m-p33/Kconfig A src/mainboard/msi/h81m-p33/Kconfig.name A src/mainboard/msi/h81m-p33/Makefile.inc A src/mainboard/msi/h81m-p33/acpi/ec.asl A src/mainboard/msi/h81m-p33/acpi/platform.asl A src/mainboard/msi/h81m-p33/acpi/superio.asl A src/mainboard/msi/h81m-p33/acpi_tables.c A src/mainboard/msi/h81m-p33/board_info.txt A src/mainboard/msi/h81m-p33/bootblock.c A src/mainboard/msi/h81m-p33/devicetree.cb A src/mainboard/msi/h81m-p33/dsdt.asl A src/mainboard/msi/h81m-p33/gma-mainboard.ads A src/mainboard/msi/h81m-p33/gpio.c A src/mainboard/msi/h81m-p33/hda_verb.c A src/mainboard/msi/h81m-p33/romstage.c 15 files changed, 552 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/41260/2
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41260
to look at the new patch set (#3).
Change subject: [WIP] mainboard: Add MSI H81M-P33 ......................................................................
[WIP] mainboard: Add MSI H81M-P33
Untested.
Change-Id: I9e47747a99c65e488487fbbcac1de15b9bf5c235 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/msi/h81m-p33/Kconfig A src/mainboard/msi/h81m-p33/Kconfig.name A src/mainboard/msi/h81m-p33/Makefile.inc A src/mainboard/msi/h81m-p33/acpi/ec.asl A src/mainboard/msi/h81m-p33/acpi/platform.asl A src/mainboard/msi/h81m-p33/acpi/superio.asl A src/mainboard/msi/h81m-p33/acpi_tables.c A src/mainboard/msi/h81m-p33/board_info.txt A src/mainboard/msi/h81m-p33/bootblock.c A src/mainboard/msi/h81m-p33/data.vbt A src/mainboard/msi/h81m-p33/devicetree.cb A src/mainboard/msi/h81m-p33/dsdt.asl A src/mainboard/msi/h81m-p33/gma-mainboard.ads A src/mainboard/msi/h81m-p33/gpio.c A src/mainboard/msi/h81m-p33/hda_verb.c A src/mainboard/msi/h81m-p33/romstage.c 16 files changed, 553 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/41260/3
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41260
to look at the new patch set (#4).
Change subject: mb/msi/h81m-p33: Add new mainboard ......................................................................
mb/msi/h81m-p33: Add new mainboard
This is a µATX mainboard with a LGA1150 socket and two DDR3 DIMM slots.
Working: - Both DIMM slots - Serial port to emit spam - Some USB ports - Integrated graphics (libgfxinit) - DVI and VGA - Realtek GbE - All PCIe ports - At least one SATA port - RAM initialization with MRC binary - Flashing with flashrom - S3 suspend/resume - Rear audio output - VBT - SeaBIOS to boot Arch Linux
Untested: - PS/2 mouse - The other audio jacks - EHCI debug - Front USB headers - Non-Linux OSes - TPM header
Change-Id: I9e47747a99c65e488487fbbcac1de15b9bf5c235 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/msi/h81m-p33/Kconfig A src/mainboard/msi/h81m-p33/Kconfig.name A src/mainboard/msi/h81m-p33/Makefile.inc A src/mainboard/msi/h81m-p33/acpi/ec.asl A src/mainboard/msi/h81m-p33/acpi/platform.asl A src/mainboard/msi/h81m-p33/acpi/superio.asl A src/mainboard/msi/h81m-p33/acpi_tables.c A src/mainboard/msi/h81m-p33/board_info.txt A src/mainboard/msi/h81m-p33/bootblock.c A src/mainboard/msi/h81m-p33/data.vbt A src/mainboard/msi/h81m-p33/devicetree.cb A src/mainboard/msi/h81m-p33/dsdt.asl A src/mainboard/msi/h81m-p33/gma-mainboard.ads A src/mainboard/msi/h81m-p33/gpio.c A src/mainboard/msi/h81m-p33/hda_verb.c A src/mainboard/msi/h81m-p33/romstage.c 16 files changed, 516 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/41260/4
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41260 )
Change subject: mb/msi/h81m-p33: Add new mainboard ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41260/4/src/mainboard/msi/h81m-p33/... File src/mainboard/msi/h81m-p33/romstage.c:
https://review.coreboot.org/c/coreboot/+/41260/4/src/mainboard/msi/h81m-p33/... PS4, Line 3: #include <stdint.h> maybe not used
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41260 )
Change subject: mb/msi/h81m-p33: Add new mainboard ......................................................................
Patch Set 4: Code-Review+1
(2 comments)
Very nice!
Did you use autoport?
https://review.coreboot.org/c/coreboot/+/41260/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41260/4//COMMIT_MSG@25 PS4, Line 25: - SeaBIOS to boot Arch Linux Versions?
https://review.coreboot.org/c/coreboot/+/41260/4/src/mainboard/msi/h81m-p33/... File src/mainboard/msi/h81m-p33/acpi/platform.asl:
https://review.coreboot.org/c/coreboot/+/41260/4/src/mainboard/msi/h81m-p33/... PS4, Line 9: Return(Package(){0, 0}) Add spaces?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41260 )
Change subject: mb/msi/h81m-p33: Add new mainboard ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41260/4/src/mainboard/msi/h81m-p33/... File src/mainboard/msi/h81m-p33/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/41260/4/src/mainboard/msi/h81m-p33/... PS4, Line 12: FIXME HMMMMM
https://review.coreboot.org/c/coreboot/+/41260/4/src/mainboard/msi/h81m-p33/... File src/mainboard/msi/h81m-p33/romstage.c:
https://review.coreboot.org/c/coreboot/+/41260/4/src/mainboard/msi/h81m-p33/... PS4, Line 3: #include <stdint.h>
maybe not used
stdint.h:21:typedef unsigned long uintptr_t;
romstage.c:20: .mchbar = (uintptr_t)DEFAULT_MCHBAR,
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41260
to look at the new patch set (#5).
Change subject: mb/msi/h81m-p33: Add new mainboard ......................................................................
mb/msi/h81m-p33: Add new mainboard
This is a µATX mainboard with a LGA1150 socket and two DDR3 DIMM slots.
Working: - Both DIMM slots - Serial port to emit spam - Some USB ports - Integrated graphics (libgfxinit) - DVI - Realtek GbE - All PCIe ports - At least one SATA port - RAM initialization with MRC binary - Flashing with flashrom - S3 suspend/resume - Rear audio output - VBT - SeaBIOS to boot Arch Linux
Broken: VGA
Untested: - PS/2 mouse - The other audio jacks - EHCI debug - Front USB headers - Non-Linux OSes - TPM header
Change-Id: I9e47747a99c65e488487fbbcac1de15b9bf5c235 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/msi/h81m-p33/Kconfig A src/mainboard/msi/h81m-p33/Kconfig.name A src/mainboard/msi/h81m-p33/Makefile.inc A src/mainboard/msi/h81m-p33/acpi/ec.asl A src/mainboard/msi/h81m-p33/acpi/platform.asl A src/mainboard/msi/h81m-p33/acpi/superio.asl A src/mainboard/msi/h81m-p33/acpi_tables.c A src/mainboard/msi/h81m-p33/board_info.txt A src/mainboard/msi/h81m-p33/bootblock.c A src/mainboard/msi/h81m-p33/data.vbt A src/mainboard/msi/h81m-p33/devicetree.cb A src/mainboard/msi/h81m-p33/dsdt.asl A src/mainboard/msi/h81m-p33/gma-mainboard.ads A src/mainboard/msi/h81m-p33/gpio.c A src/mainboard/msi/h81m-p33/hda_verb.c A src/mainboard/msi/h81m-p33/romstage.c 16 files changed, 516 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/41260/5
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41260 )
Change subject: mb/msi/h81m-p33: Add new mainboard ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41260/4/src/mainboard/msi/h81m-p33/... File src/mainboard/msi/h81m-p33/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/41260/4/src/mainboard/msi/h81m-p33/... PS4, Line 12: FIXME
HMMMMM
Done
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41260
to look at the new patch set (#7).
Change subject: mb/msi/h81m-p33: Add new mainboard ......................................................................
mb/msi/h81m-p33: Add new mainboard
This is a µATX mainboard with a LGA1150 socket and two DDR3 DIMM slots.
Working: - Both DIMM slots - Serial port to emit spam - Some USB ports - Integrated graphics (libgfxinit) - DVI - Realtek GbE - All PCIe ports - At least one SATA port - RAM initialization with MRC binary - Flashing with flashrom - S3 suspend/resume - VBT - SeaBIOS master to boot Arch Linux
Broken: - VGA port: libgfxinit will hang if it tries to initialize it, as it is missing several programming steps. Linux can bring it up, though. - Rear audio output
Untested: - PS/2 mouse - The other audio jacks - EHCI debug - Front USB headers - Non-Linux OSes - TPM header
Change-Id: I9e47747a99c65e488487fbbcac1de15b9bf5c235 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/msi/h81m-p33/Kconfig A src/mainboard/msi/h81m-p33/Kconfig.name A src/mainboard/msi/h81m-p33/Makefile.inc A src/mainboard/msi/h81m-p33/acpi/ec.asl A src/mainboard/msi/h81m-p33/acpi/platform.asl A src/mainboard/msi/h81m-p33/acpi/superio.asl A src/mainboard/msi/h81m-p33/acpi_tables.c A src/mainboard/msi/h81m-p33/board_info.txt A src/mainboard/msi/h81m-p33/bootblock.c A src/mainboard/msi/h81m-p33/data.vbt A src/mainboard/msi/h81m-p33/devicetree.cb A src/mainboard/msi/h81m-p33/dsdt.asl A src/mainboard/msi/h81m-p33/gma-mainboard.ads A src/mainboard/msi/h81m-p33/gpio.c A src/mainboard/msi/h81m-p33/hda_verb.c A src/mainboard/msi/h81m-p33/romstage.c 16 files changed, 519 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/41260/7
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41260 )
Change subject: mb/msi/h81m-p33: Add new mainboard ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41260/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41260/4//COMMIT_MSG@25 PS4, Line 25: - SeaBIOS to boot Arch Linux
Versions?
Added SeaBIOS version, Arch Linux doesn't really have versions, and the kernel version changes rather often
https://review.coreboot.org/c/coreboot/+/41260/4/src/mainboard/msi/h81m-p33/... File src/mainboard/msi/h81m-p33/acpi/platform.asl:
https://review.coreboot.org/c/coreboot/+/41260/4/src/mainboard/msi/h81m-p33/... PS4, Line 9: Return(Package(){0, 0})
Add spaces?
What for? I'm not sure if we have any coding style for ASL. Since I don't really care about ASL formatting, maybe we could auto-format them?
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41260
to look at the new patch set (#8).
Change subject: mb/msi/h81m-p33: Add new mainboard ......................................................................
mb/msi/h81m-p33: Add new mainboard
This is a µATX mainboard with a LGA1150 socket and two DDR3 DIMM slots.
Working: - Both DIMM slots - Serial port to emit spam - Some USB ports - Integrated graphics (libgfxinit) - DVI - Realtek GbE - All PCIe ports - At least one SATA port - RAM initialization with MRC binary - Flashing with flashrom - S3 suspend/resume - VBT - SeaBIOS to boot Arch Linux
Broken: - Rear audio output
Untested: - PS/2 mouse - The other audio jacks - EHCI debug - Front USB headers - Non-Linux OSes - TPM header - VGA
Change-Id: I9e47747a99c65e488487fbbcac1de15b9bf5c235 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/msi/h81m-p33/Kconfig A src/mainboard/msi/h81m-p33/Kconfig.name A src/mainboard/msi/h81m-p33/Makefile.inc A src/mainboard/msi/h81m-p33/acpi/ec.asl A src/mainboard/msi/h81m-p33/acpi/platform.asl A src/mainboard/msi/h81m-p33/acpi/superio.asl A src/mainboard/msi/h81m-p33/board_info.txt A src/mainboard/msi/h81m-p33/bootblock.c A src/mainboard/msi/h81m-p33/data.vbt A src/mainboard/msi/h81m-p33/devicetree.cb A src/mainboard/msi/h81m-p33/dsdt.asl A src/mainboard/msi/h81m-p33/gma-mainboard.ads A src/mainboard/msi/h81m-p33/gpio.c A src/mainboard/msi/h81m-p33/hda_verb.c A src/mainboard/msi/h81m-p33/romstage.c 15 files changed, 463 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/41260/8
Attention is currently required from: Nico Huber, Martin Roth, Angel Pons, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41260 )
Change subject: mb/msi/h81m-p33: Add new mainboard ......................................................................
Patch Set 8: Code-Review+2
Attention is currently required from: Nico Huber, Martin Roth, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41260 )
Change subject: mb/msi/h81m-p33: Add new mainboard ......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/41260/comment/79fff547_1ebf851b PS8, Line 27: - Rear audio output Doesn't work with vendor firmware either. I suspect hardware issues.
Attention is currently required from: Nico Huber, Martin Roth, Angel Pons, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41260 )
Change subject: mb/msi/h81m-p33: Add new mainboard ......................................................................
Patch Set 8: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/41260/comment/e4bb480d_afe0e11e PS8, Line 24: - SeaBIOS to boot Arch Linux The used versions would be nice to have documented?
https://review.coreboot.org/c/coreboot/+/41260/comment/77caf59f_9dd7bc0e PS8, Line 27: - Rear audio output
Doesn't work with vendor firmware either. I suspect hardware issues.
Could you please add that note to the commit message?
Attention is currently required from: Nico Huber, Martin Roth, Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Paul Menzel, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41260
to look at the new patch set (#9).
Change subject: mb/msi/h81m-p33: Add new mainboard ......................................................................
mb/msi/h81m-p33: Add new mainboard
This is a µATX mainboard with a LGA1150 socket and two DDR3 DIMM slots.
Working: - Both DIMM slots - Serial port to emit spam - Some USB ports - Integrated graphics (libgfxinit) - DVI - Realtek GbE - All PCIe ports - At least one SATA port - RAM initialization with MRC binary - Flashing with flashrom - S3 suspend/resume - VBT - SeaBIOS 1.14 to boot Arch Linux (kernel linux-5.10.15.arch1-1)
Broken: - Audio. It doesn't work on stock firmware either. I suspect the codec hardware on my board is dead.
Untested: - PS/2 mouse - EHCI debug - Front USB headers - Non-Linux OSes - TPM header - VGA
Change-Id: I9e47747a99c65e488487fbbcac1de15b9bf5c235 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/msi/h81m-p33/Kconfig A src/mainboard/msi/h81m-p33/Kconfig.name A src/mainboard/msi/h81m-p33/Makefile.inc A src/mainboard/msi/h81m-p33/acpi/ec.asl A src/mainboard/msi/h81m-p33/acpi/platform.asl A src/mainboard/msi/h81m-p33/acpi/superio.asl A src/mainboard/msi/h81m-p33/board_info.txt A src/mainboard/msi/h81m-p33/bootblock.c A src/mainboard/msi/h81m-p33/data.vbt A src/mainboard/msi/h81m-p33/devicetree.cb A src/mainboard/msi/h81m-p33/dsdt.asl A src/mainboard/msi/h81m-p33/gma-mainboard.ads A src/mainboard/msi/h81m-p33/gpio.c A src/mainboard/msi/h81m-p33/hda_verb.c A src/mainboard/msi/h81m-p33/romstage.c 15 files changed, 463 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/41260/9
Attention is currently required from: Nico Huber, Martin Roth, Paul Menzel, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41260 )
Change subject: mb/msi/h81m-p33: Add new mainboard ......................................................................
Patch Set 9:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/41260/comment/1157981b_537c2308 PS8, Line 24: - SeaBIOS to boot Arch Linux
The used versions would be nice to have documented?
Done
https://review.coreboot.org/c/coreboot/+/41260/comment/b9123d56_527c98e6 PS8, Line 27: - Rear audio output
Could you please add that note to the commit message?
Done
Attention is currently required from: Nico Huber, Martin Roth, Paul Menzel, Angel Pons, Patrick Rudolph. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41260 )
Change subject: mb/msi/h81m-p33: Add new mainboard ......................................................................
Patch Set 9:
(1 comment)
File src/mainboard/msi/h81m-p33/romstage.c:
https://review.coreboot.org/c/coreboot/+/41260/comment/7e851b13_91ae7ce2 PS9, Line 55: memcpy <string.h> ?
Attention is currently required from: Nico Huber, Martin Roth, Paul Menzel, Patrick Rudolph, HAOUAS Elyes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41260 )
Change subject: mb/msi/h81m-p33: Add new mainboard ......................................................................
Patch Set 9:
(1 comment)
File src/mainboard/msi/h81m-p33/romstage.c:
https://review.coreboot.org/c/coreboot/+/41260/comment/82b2672c_9e478f7e PS9, Line 55: memcpy
<string. […]
It's missing from many boards. I have a better idea.
Attention is currently required from: Nico Huber, Martin Roth, Paul Menzel, Angel Pons, Patrick Rudolph. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41260 )
Change subject: mb/msi/h81m-p33: Add new mainboard ......................................................................
Patch Set 9: Code-Review+1
(1 comment)
File src/mainboard/msi/h81m-p33/romstage.c:
https://review.coreboot.org/c/coreboot/+/41260/comment/cf5ea735_0d7d026e PS9, Line 55: memcpy
It's missing from many boards. I have a better idea.
maybe: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY|memcpy|memmove|memset|memcmp|memchr|strdup|strconcat|strnlen|strlen|strchr|strncpy|strcpy|strcmp|strncmp|strspn|strcspn|strstr|strtok_r|strtok|atol|strrchr|skip_atoi|snprintf' -- src/)|grep '>'
Attention is currently required from: Nico Huber, Martin Roth, Paul Menzel, Patrick Rudolph, HAOUAS Elyes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41260 )
Change subject: mb/msi/h81m-p33: Add new mainboard ......................................................................
Patch Set 10:
(1 comment)
File src/mainboard/msi/h81m-p33/romstage.c:
https://review.coreboot.org/c/coreboot/+/41260/comment/c7ad8ce1_abdcc55f PS9, Line 55: memcpy
maybe: […]
I made CB:50538 instead, which I wanted to do anyway.
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41260 )
Change subject: mb/msi/h81m-p33: Add new mainboard ......................................................................
mb/msi/h81m-p33: Add new mainboard
This is a µATX mainboard with a LGA1150 socket and two DDR3 DIMM slots.
Working: - Both DIMM slots - Serial port to emit spam - Some USB ports - Integrated graphics (libgfxinit) - DVI - Realtek GbE - All PCIe ports - At least one SATA port - RAM initialization with MRC binary - Flashing with flashrom - S3 suspend/resume - VBT - SeaBIOS 1.14 to boot Arch Linux (kernel linux-5.10.15.arch1-1)
Broken: - Audio. It doesn't work on stock firmware either. I suspect the codec hardware on my board is dead.
Untested: - PS/2 mouse - EHCI debug - Front USB headers - Non-Linux OSes - TPM header - VGA
Change-Id: I9e47747a99c65e488487fbbcac1de15b9bf5c235 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/41260 Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Tested-by: build bot (Jenkins) no-reply@coreboot.org --- A src/mainboard/msi/h81m-p33/Kconfig A src/mainboard/msi/h81m-p33/Kconfig.name A src/mainboard/msi/h81m-p33/Makefile.inc A src/mainboard/msi/h81m-p33/acpi/ec.asl A src/mainboard/msi/h81m-p33/acpi/platform.asl A src/mainboard/msi/h81m-p33/acpi/superio.asl A src/mainboard/msi/h81m-p33/board_info.txt A src/mainboard/msi/h81m-p33/bootblock.c A src/mainboard/msi/h81m-p33/data.vbt A src/mainboard/msi/h81m-p33/devicetree.cb A src/mainboard/msi/h81m-p33/dsdt.asl A src/mainboard/msi/h81m-p33/gma-mainboard.ads A src/mainboard/msi/h81m-p33/gpio.c A src/mainboard/msi/h81m-p33/hda_verb.c A src/mainboard/msi/h81m-p33/romstage.c 15 files changed, 463 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve HAOUAS Elyes: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved
diff --git a/src/mainboard/msi/h81m-p33/Kconfig b/src/mainboard/msi/h81m-p33/Kconfig new file mode 100644 index 0000000..185c340 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/Kconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_MSI_H81M_P33 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_HASWELL + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6779D + +config MAINBOARD_DIR + string + default msi/h81m-p33 + +config MAINBOARD_PART_NUMBER + string + default "H81M-P33" + +endif diff --git a/src/mainboard/msi/h81m-p33/Kconfig.name b/src/mainboard/msi/h81m-p33/Kconfig.name new file mode 100644 index 0000000..ac4bd28 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_MSI_H81M_P33 + bool "H81M-P33 (MS-7817 v1.2)" diff --git a/src/mainboard/msi/h81m-p33/Makefile.inc b/src/mainboard/msi/h81m-p33/Makefile.inc new file mode 100644 index 0000000..d9a8d18 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/Makefile.inc @@ -0,0 +1,5 @@ +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += bootblock.c diff --git a/src/mainboard/msi/h81m-p33/acpi/ec.asl b/src/mainboard/msi/h81m-p33/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/acpi/ec.asl diff --git a/src/mainboard/msi/h81m-p33/acpi/platform.asl b/src/mainboard/msi/h81m-p33/acpi/platform.asl new file mode 100644 index 0000000..b3233b7 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method (_PTS, 1) +{ +} + +Method (_WAK, 1) +{ + Return (Package () { 0, 0 }) +} diff --git a/src/mainboard/msi/h81m-p33/acpi/superio.asl b/src/mainboard/msi/h81m-p33/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/msi/h81m-p33/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/msi/h81m-p33/board_info.txt b/src/mainboard/msi/h81m-p33/board_info.txt new file mode 100644 index 0000000..17f17e0 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.msi.com/Motherboard/H81M-P33/Specification +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/msi/h81m-p33/bootblock.c b/src/mainboard/msi/h81m-p33/bootblock.c new file mode 100644 index 0000000..142ff43 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/bootblock.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pnp_ops.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> + +#define GLOBAL_DEV PNP_DEV(0x4e, 0) +#define SERIAL_DEV PNP_DEV(0x4e, NCT6779D_SP1) +#define ACPI_DEV PNP_DEV(0x4e, NCT6779D_ACPI) + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0x30); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x70); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x08); + pnp_write_config(GLOBAL_DEV, 0x1d, 0x00); + pnp_write_config(GLOBAL_DEV, 0x22, 0xff); + pnp_write_config(GLOBAL_DEV, 0x24, 0x04); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x08); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + + /* Enable keyboard wakeup, 3VSBSW# is not connected */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x08); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/msi/h81m-p33/data.vbt b/src/mainboard/msi/h81m-p33/data.vbt new file mode 100644 index 0000000..ad8556a --- /dev/null +++ b/src/mainboard/msi/h81m-p33/data.vbt Binary files differ diff --git a/src/mainboard/msi/h81m-p33/devicetree.cb b/src/mainboard/msi/h81m-p33/devicetree.cb new file mode 100644 index 0000000..e079770 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/devicetree.cb @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/haswell + register "gpu_ddi_e_connected" = "1" + device cpu_cluster 0 on + chip cpu/intel/haswell + device lapic 0 on end + device lapic 0xacac off end + end + end + device domain 0 on + subsystemid 0x1462 0x7817 inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # iGPU + device pci 03.0 off end # Mini-HD audio + chip southbridge/intel/lynxpoint + register "gen1_dec" = "0x000c0291" + register "sata_port_map" = "0x33" + device pci 14.0 on end # xHCI Controller + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT + device pci 19.0 off end # Intel GbE + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # HD Audio + device pci 1c.0 on end # RP #1 + device pci 1c.1 off end # RP #2 + device pci 1c.2 on end # RP #3: RTL8111 GbE NIC + device pci 1c.3 on end # RP #4: PCIe x1 + device pci 1c.4 off end # RP #5 + device pci 1c.5 off end # RP #6 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6779d + device pnp 4e.1 off end # Parallel + device pnp 4e.2 on # UART A + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.3 off end # UART B, IR + device pnp 4e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 4e.6 off end # CIR + device pnp 4e.7 off end # GPIO6-8 + device pnp 4e.8 off end # WDT1, GPIO0, GPIO1 + device pnp 4e.108 on end # GPIO0 + device pnp 4e.9 off end # GPIO1-8 + device pnp 4e.109 off end # GPIO1 + device pnp 4e.209 off end # GPIO2 + device pnp 4e.309 off end # GPIO3 + device pnp 4e.409 off end # GPIO4 + device pnp 4e.509 off end # GPIO5 + device pnp 4e.609 off end # GPIO6 + device pnp 4e.709 off end # GPIO7 + device pnp 4e.a on end # ACPI + device pnp 4e.b on # H/W Monitor, FP LED + io 0x60 = 0x290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 4e.d off end # WDT1 + device pnp 4e.e off end # CIR Wake-up + device pnp 4e.f off end # Push-pull/Open-drain + device pnp 4e.14 off end # Port 80 UART + device pnp 4e.16 off end # Deep Sleep + end + end + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/msi/h81m-p33/dsdt.asl b/src/mainboard/msi/h81m-p33/dsdt.asl new file mode 100644 index 0000000..9c55945 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/msi/h81m-p33/gma-mainboard.ads b/src/mainboard/msi/h81m-p33/gma-mainboard.ads new file mode 100644 index 0000000..be04a94 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI2, -- DVI + HDMI3, -- HDMI + Analog, -- VGA + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/msi/h81m-p33/gpio.c b/src/mainboard/msi/h81m-p33/gpio.c new file mode 100644 index 0000000..424d75e --- /dev/null +++ b/src/mainboard/msi/h81m-p33/gpio.c @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; diff --git a/src/mainboard/msi/h81m-p33/hda_verb.c b/src/mainboard/msi/h81m-p33/hda_verb.c new file mode 100644 index 0000000..735c026 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/hda_verb.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek ALC887-VD */ + 0x1462d817, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1462d817), + AZALIA_PIN_CFG(0, 0x11, 0x4037c040), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19030), + AZALIA_PIN_CFG(0, 0x19, 0x02a19040), + AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4025c603), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/msi/h81m-p33/romstage.c b/src/mainboard/msi/h81m-p33/romstage.c new file mode 100644 index 0000000..6321eeb --- /dev/null +++ b/src/mainboard/msi/h81m-p33/romstage.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +} + +void mb_get_spd_map(uint8_t spd_map[4]) +{ + spd_map[0] = 0xa0; + spd_map[2] = 0xa4; +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + }; + + struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, + }; + + memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); + memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); +}
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Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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HAOUAS Elyes (Code Review)
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Paul Menzel (Code Review)