HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45574 )
Change subject: nb/intel/haswell: Use common MCHBAR accessor functions ......................................................................
nb/intel/haswell: Use common MCHBAR accessor functions
This change the binary using "BUILD_TIMELESS=1" for lenovo/t440p baord.
Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/haswell/haswell_init.c M src/northbridge/intel/haswell/Makefile.inc M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/raminit.c 8 files changed, 19 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45574/1
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 5f3debb..86c69f8 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -14,6 +14,7 @@ #include <cpu/intel/turbo.h> #include <cpu/x86/name.h> #include <delay.h> +#include <northbridge/intel/common/mchbar_ops.h> #include <northbridge/intel/haswell/haswell.h> #include <southbridge/intel/lynxpoint/pch.h> #include <cpu/intel/common/common.h> diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index b2fd530..8f9f33d 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -11,14 +11,17 @@
ramstage-y += acpi.c ramstage-y += minihd.c +ramstage-y += ../common/mchbar_ops.c
romstage-y += memmap.c romstage-y += raminit.c romstage-y += romstage.c romstage-y += early_init.c romstage-y += report_platform.c +romstage-y += ../common/mchbar_ops.c
smm-y += finalize.c +smm-y += ../common/mchbar_ops.c
# We don't ship that, but booting without it is bound to fail cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index cc4487c..81ed757 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -7,6 +7,7 @@ #include <device/device.h> #include <device/pci_ops.h> #include "haswell.h" +#include <northbridge/intel/common/mchbar_ops.h> #include <southbridge/intel/lynxpoint/pch.h>
unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 9db6a9d..b1fe430 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -5,6 +5,7 @@ #include <device/mmio.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <northbridge/intel/common/mchbar_ops.h>
#include "haswell.h"
diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 93c89ce..ebce6e9 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <device/pci_ops.h> +#include <northbridge/intel/common/mchbar_ops.h> + #include "haswell.h"
void intel_northbridge_haswell_finalize_smm(void) @@ -17,13 +19,13 @@ pci_or_config32(HOST_BRIDGE, 0xb8, 1 << 0); /* TSEGMB */ pci_or_config32(HOST_BRIDGE, 0xbc, 1 << 0); /* TOLUD */
- MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ - MCHBAR32_OR(SAPMCTL, 1UL << 31); /* SA PM */ - MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(REQLIM, 1UL << 31); - MCHBAR32_OR(DMIVCLIM, 1UL << 31); - MCHBAR32_OR(CRDTLCK, 1 << 0); + mchbar32_set(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ + mchbar32_set(SAPMCTL, 1UL << 31); /* SA PM */ + mchbar32_set(UMAGFXCTL, 1 << 0); /* UMA GFX */ + mchbar32_set(VTDTRKLCK, 1 << 0); /* VTDTRK */ + mchbar32_set(REQLIM, 1UL << 31); + mchbar32_set(DMIVCLIM, 1UL << 31); + mchbar32_set(CRDTLCK, 1 << 0);
/* Memory Controller Lockdown */ MCHBAR8(MC_LOCK) = 0x8f; diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 44ea9b9..5cacec6 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -27,22 +27,8 @@
/* * MCHBAR + * As there are many registers, define them on a separate file */ - -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) - -/* As there are many registers, define them on a separate file */ #include "registers/mchbar.h"
#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index e1c26d1..fd4a238 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -12,6 +12,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <boot/tables.h> +#include <northbridge/intel/common/mchbar_ops.h>
#include "chip.h" #include "haswell.h" diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 9c6c00f..f382db5 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -16,6 +16,8 @@ #include <spd.h> #include <security/vboot/vboot_common.h> #include <commonlib/region.h> +#include <northbridge/intel/common/mchbar_ops.h> + #include "raminit.h" #include "pei_data.h" #include "haswell.h"
Hello Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45574
to look at the new patch set (#2).
Change subject: nb/intel/haswell: Use common MCHBAR accessor functions ......................................................................
nb/intel/haswell: Use common MCHBAR accessor functions
This change the binary using "BUILD_TIMELESS=1" for lenovo/t440p baord.
Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/haswell/haswell_init.c M src/northbridge/intel/haswell/Makefile.inc M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/raminit.c 9 files changed, 20 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45574/2
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45574
to look at the new patch set (#3).
Change subject: nb/intel/haswell: Use common MCHBAR accessor functions ......................................................................
nb/intel/haswell: Use common MCHBAR accessor functions
This changes the binary using "BUILD_TIMELESS=1" for lenovo/t440p baord.
Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/haswell/haswell_init.c M src/northbridge/intel/haswell/Makefile.inc M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/raminit.c 9 files changed, 20 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45574/3
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45574 )
Change subject: nb/intel/haswell: Use common MCHBAR accessor functions ......................................................................
Patch Set 4:
This change is ready for review.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45574
to look at the new patch set (#5).
Change subject: nb/intel/haswell: Use common MCHBAR accessor functions ......................................................................
nb/intel/haswell: Use common MCHBAR accessor functions
The binary "BUILD_TIMELESS=1" for lenovo/t440p baord remained the same.
Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/haswell/haswell_init.c M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/raminit.c 7 files changed, 16 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45574/5
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45574 )
Change subject: nb/intel/haswell: Use common MCHBAR accessor functions ......................................................................
Patch Set 5: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/45574/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45574/5//COMMIT_MSG@9 PS5, Line 9: baord board
https://review.coreboot.org/c/coreboot/+/45574/5//COMMIT_MSG@9 PS5, Line 9: remained I don't think this should be past tense. I generally write this as:
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad T440p does not change.
I sometimes replace "does not change" with "remains identical". Feel free to use "lenovo/t440p" to refer to the mainboard, too.
https://review.coreboot.org/c/coreboot/+/45574/5/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/haswell.h:
https://review.coreboot.org/c/coreboot/+/45574/5/src/northbridge/intel/haswe... PS5, Line 31: */ Please don't fuse these comments together.
One might as well drop these comments in a separate patch. They aren't useful.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45574
to look at the new patch set (#6).
Change subject: nb/intel/haswell: Use common MCHBAR accessor functions ......................................................................
nb/intel/haswell: Use common MCHBAR accessor functions
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad T440p does not change.
Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/haswell/haswell_init.c M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/raminit.c 7 files changed, 16 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45574/6
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45574
to look at the new patch set (#7).
Change subject: nb/intel/haswell: Use common MCHBAR accessor functions ......................................................................
nb/intel/haswell: Use common MCHBAR accessor functions
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad T440p does not change.
Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/haswell/haswell_init.c M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/raminit.c 7 files changed, 15 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45574/7
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45574
to look at the new patch set (#8).
Change subject: [WIP]nb/intel/haswell: Use common MCHBAR accessor functions ......................................................................
[WIP]nb/intel/haswell: Use common MCHBAR accessor functions
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad T440p does not change.
Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/haswell/haswell_init.c M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/raminit.c 7 files changed, 15 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45574/8
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45574
to look at the new patch set (#9).
Change subject: nb/intel/haswell: Use common MCHBAR accessor functions ......................................................................
nb/intel/haswell: Use common MCHBAR accessor functions
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad T440p does not change.
Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/haswell/finalize.c 1 file changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45574/9
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45574
to look at the new patch set (#16).
Change subject: nb/intel/haswell: Use common MCHBAR accessor functions ......................................................................
nb/intel/haswell: Use common MCHBAR accessor functions
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad T440p does not change.
Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/haswell/finalize.c 1 file changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45574/16
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45574 )
Change subject: nb/intel/haswell: Use common MCHBAR accessor functions ......................................................................
Patch Set 16:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45574/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45574/5//COMMIT_MSG@9 PS5, Line 9: baord
board
Done
https://review.coreboot.org/c/coreboot/+/45574/5//COMMIT_MSG@9 PS5, Line 9: remained
I don't think this should be past tense. I generally write this as: […]
Done
https://review.coreboot.org/c/coreboot/+/45574/5/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/haswell.h:
https://review.coreboot.org/c/coreboot/+/45574/5/src/northbridge/intel/haswe... PS5, Line 31: */
Please don't fuse these comments together. […]
Done
HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/45574 )
Change subject: nb/intel/haswell: Use common MCHBAR accessor functions ......................................................................
Abandoned
HAOUAS Elyes has restored this change. ( https://review.coreboot.org/c/coreboot/+/45574 )
Change subject: nb/intel/haswell: Use common MCHBAR accessor functions ......................................................................
Restored
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45574
to look at the new patch set (#20).
Change subject: nb/intel/haswell: Get rid of MCHBAR32_OR macro ......................................................................
nb/intel/haswell: Get rid of MCHBAR32_OR macro
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad T440p does not change.
Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/haswell/finalize.c 1 file changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45574/20
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45574
to look at the new patch set (#21).
Change subject: nb/intel/haswell: Get rid of MCHBAR32_OR macro ......................................................................
nb/intel/haswell: Get rid of MCHBAR32_OR macro
Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/haswell.h 2 files changed, 7 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45574/21
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45574
to look at the new patch set (#22).
Change subject: nb/intel/haswell: Get rid of MCHBAR32_OR macro ......................................................................
nb/intel/haswell: Get rid of MCHBAR32_OR macro
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad T440p does not change.
Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/haswell.h 2 files changed, 7 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45574/22
HAOUAS Elyes has removed Angel Pons from this change. ( https://review.coreboot.org/c/coreboot/+/45574 )
Change subject: nb/intel/haswell: Get rid of MCHBAR32_OR macro ......................................................................
Removed reviewer Angel Pons.
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45574 )
Change subject: nb/intel/haswell: Get rid of MCHBAR32_OR macro ......................................................................
Patch Set 24: Code-Review+2
Patrick Georgi has uploaded a new patch set (#25) to the change originally created by HAOUAS Elyes. ( https://review.coreboot.org/c/coreboot/+/45574 )
Change subject: nb/intel/haswell: Get rid of MCHBAR*_* macros ......................................................................
nb/intel/haswell: Get rid of MCHBAR*_* macros
Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Signed-off-by: Patrick Georgi pgeorgi@google.com --- M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/haswell.h 2 files changed, 8 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45574/25
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45574 )
Change subject: nb/intel/haswell: Get rid of MCHBAR*_* macros ......................................................................
Patch Set 31: Code-Review+2
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Frans Hendriks, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45574
to look at the new patch set (#35).
Change subject: nb/intel/haswell: Get rid of MCHBAR*_* macros ......................................................................
nb/intel/haswell: Get rid of MCHBAR*_* macros
Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Signed-off-by: Patrick Georgi pgeorgi@google.com --- M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/haswell.h 2 files changed, 8 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45574/35
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Frans Hendriks, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45574
to look at the new patch set (#37).
Change subject: nb/intel/haswell: Get rid of MCHBAR*_* macros ......................................................................
nb/intel/haswell: Get rid of MCHBAR*_* macros
Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/haswell.h 2 files changed, 8 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45574/37
HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/45574 )
Change subject: nb/intel/haswell: Get rid of MCHBAR*_* macros ......................................................................
Abandoned
-
Angel Pons (Code Review) -
Frans Hendriks (Code Review)
-
HAOUAS Elyes (Code Review)
-
Patrick Georgi (Code Review)