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Change in coreboot[master]: cpu/intel/broadwell: Add header files
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41936 ) Change subject: cpu/intel/broadwell: Add header files ...................................................................... cpu/intel/broadwell: Add header files Relocate CPU-related headers from soc to cpu namespace. Note that the code in soc/intel/common expects to find the `soc/msr.h` header. And yes, some prototypes are now in the wrong place. This will be fixed in the next commits, once the soc/intel/broadwell subfolder is no more. With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical. Change-Id: Ia9e860fbb02e2fd3c894236abbb784c21f231bbf Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/broadwell/acpi.c M src/cpu/intel/broadwell/bootblock.c A src/cpu/intel/broadwell/broadwell.h M src/cpu/intel/broadwell/broadwell_early_init.c M src/cpu/intel/broadwell/cpu.c M src/cpu/intel/broadwell/cpu_info.c M src/cpu/intel/broadwell/smmrelocate.c M src/cpu/intel/broadwell/tsc_freq.c M src/northbridge/intel/broadwell/igd.c M src/northbridge/intel/broadwell/report_platform.c M src/soc/intel/broadwell/include/soc/cpu.h M src/soc/intel/broadwell/include/soc/msr.h M src/southbridge/intel/wildcatpoint/pcie.c M src/southbridge/intel/wildcatpoint/xhci.c 14 files changed, 122 insertions(+), 132 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/41936/1 diff --git a/src/cpu/intel/broadwell/acpi.c b/src/cpu/intel/broadwell/acpi.c index 316b85a..db5a232 100644 --- a/src/cpu/intel/broadwell/acpi.c +++ b/src/cpu/intel/broadwell/acpi.c @@ -16,10 +16,9 @@ #include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/gnvs.h> #include <soc/acpi.h> -#include <soc/cpu.h> +#include <cpu/intel/broadwell/broadwell.h> #include <soc/iomap.h> #include <soc/lpc.h> -#include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/systemagent.h> diff --git a/src/cpu/intel/broadwell/bootblock.c b/src/cpu/intel/broadwell/bootblock.c index 79f859b..3b041fe 100644 --- a/src/cpu/intel/broadwell/bootblock.c +++ b/src/cpu/intel/broadwell/bootblock.c @@ -7,7 +7,7 @@ #include <cpu/x86/mtrr.h> #include <halt.h> #include <soc/rcba.h> -#include <soc/msr.h> +#include <cpu/intel/broadwell/broadwell.h> #include <delay.h> static void set_flex_ratio_to_tdp_nominal(void) diff --git a/src/cpu/intel/broadwell/broadwell.h b/src/cpu/intel/broadwell/broadwell.h new file mode 100644 index 0000000..5654e0a --- /dev/null +++ b/src/cpu/intel/broadwell/broadwell.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _BROADWELL_CPU_H_ +#define _BROADWELL_CPU_H_ + +#include <device/device.h> + +/* CPU types */ +#define HASWELL_FAMILY_ULT 0x40650 +#define BROADWELL_FAMILY_ULT 0x306d0 + +/* Supported CPUIDs */ +#define CPUID_HASWELL_A0 0x306c1 +#define CPUID_HASWELL_B0 0x306c2 +#define CPUID_HASWELL_C0 0x306c3 +#define CPUID_HASWELL_ULT_B0 0x40650 +#define CPUID_HASWELL_ULT 0x40651 +#define CPUID_HASWELL_HALO 0x40661 +#define CPUID_BROADWELL_C0 0x306d2 +#define CPUID_BROADWELL_D0 0x306d3 +#define CPUID_BROADWELL_E0 0x306d4 + +/* CPU bus clock is fixed at 100MHz */ +#define CPU_BCLK 100 + +/* Latency times in units of 1024ns. */ +#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 +#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 +#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 +#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 +#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 +#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef + +#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ + (((1 << ((base)*5)) * (limit)) / 1000) +#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ + C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ + (IRTL_1024_NS >> 10)) + +/* MSR definitions */ +#define MSR_PIC_MSG_CONTROL 0x2e +#define MSR_CORE_THREAD_COUNT 0x35 +#define MSR_PLATFORM_INFO 0xce +#define PLATFORM_INFO_SET_TDP (1 << 29) +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PMG_IO_CAPTURE_BASE 0xe4 +#define MSR_FEATURE_CONFIG 0x13c +#define SMM_MCA_CAP_MSR 0x17d +#define SMM_CPU_SVRSTR_BIT 57 +#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) +#define MSR_FLEX_RATIO 0x194 +#define FLEX_RATIO_LOCK (1 << 20) +#define FLEX_RATIO_EN (1 << 16) +#define MSR_MISC_PWR_MGMT 0x1aa +#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) +#define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_TEMPERATURE_TARGET 0x1a2 +#define MSR_PRMRR_PHYS_BASE 0x1f4 +#define MSR_PRMRR_PHYS_MASK 0x1f5 +#define MSR_POWER_CTL 0x1fc +#define MSR_LT_LOCK_MEMORY 0x2e7 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 +#define SMM_FEATURE_CONTROL_MSR 0x4e0 +#define SMM_CPU_SAVE_EN (1 << 1) + +#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a +#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b +#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c +#define MSR_C_STATE_LATENCY_CONTROL_3 0x633 +#define MSR_C_STATE_LATENCY_CONTROL_4 0x634 +#define MSR_C_STATE_LATENCY_CONTROL_5 0x635 +#define IRTL_VALID (1 << 15) +#define IRTL_1_NS (0 << 10) +#define IRTL_32_NS (1 << 10) +#define IRTL_1024_NS (2 << 10) +#define IRTL_32768_NS (3 << 10) +#define IRTL_1048576_NS (4 << 10) +#define IRTL_33554432_NS (5 << 10) +#define IRTL_RESPONSE_MASK (0x3ff) +#define MSR_COUNTER_24_MHZ 0x637 + +#define MSR_VR_CURRENT_CONFIG 0x601 +#define MSR_VR_MISC_CONFIG 0x603 +#define MSR_PKG_POWER_SKU_UNIT 0x606 +#define MSR_PKG_POWER_SKU 0x614 +#define MSR_DDR_RAPL_LIMIT 0x618 +#define MSR_VR_MISC_CONFIG2 0x636 +#define MSR_PP0_POWER_LIMIT 0x638 +#define MSR_PP1_POWER_LIMIT 0x640 + +#define MSR_CONFIG_TDP_NOMINAL 0x648 +#define MSR_CONFIG_TDP_LEVEL1 0x649 +#define MSR_CONFIG_TDP_LEVEL2 0x64a +#define MSR_CONFIG_TDP_CONTROL 0x64b +#define MSR_TURBO_ACTIVATION_RATIO 0x64c + +/* SMM save state MSRs */ +#define SMBASE_MSR 0xc20 +#define IEDBASE_MSR 0xc22 + +/* MTRR_CAP_MSR bits */ +#define SMRR_SUPPORTED (1 << 11) +#define PRMRR_SUPPORTED (1 << 12) + +/* CPU identification */ +u32 cpu_family_model(void); +u32 cpu_stepping(void); +int cpu_is_ult(void); + +#endif diff --git a/src/cpu/intel/broadwell/broadwell_early_init.c b/src/cpu/intel/broadwell/broadwell_early_init.c index 7364876..ad1ce6d 100644 --- a/src/cpu/intel/broadwell/broadwell_early_init.c +++ b/src/cpu/intel/broadwell/broadwell_early_init.c @@ -3,8 +3,7 @@ #include <arch/cpu.h> #include <console/console.h> #include <cpu/x86/msr.h> -#include <soc/cpu.h> -#include <soc/msr.h> +#include <cpu/intel/broadwell/broadwell.h> #include <soc/romstage.h> u32 cpu_family_model(void) diff --git a/src/cpu/intel/broadwell/cpu.c b/src/cpu/intel/broadwell/cpu.c index 1923301..cbb96bc 100644 --- a/src/cpu/intel/broadwell/cpu.c +++ b/src/cpu/intel/broadwell/cpu.c @@ -17,8 +17,7 @@ #include <cpu/x86/smm.h> #include <delay.h> #include <intelblocks/cpulib.h> -#include <soc/cpu.h> -#include <soc/msr.h> +#include <cpu/intel/broadwell/broadwell.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/rcba.h> diff --git a/src/cpu/intel/broadwell/cpu_info.c b/src/cpu/intel/broadwell/cpu_info.c index 5542f17..f4a8dad 100644 --- a/src/cpu/intel/broadwell/cpu_info.c +++ b/src/cpu/intel/broadwell/cpu_info.c @@ -2,8 +2,7 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> -#include <soc/cpu.h> -#include <soc/msr.h> +#include <cpu/intel/broadwell/broadwell.h> #include <soc/systemagent.h> u32 cpu_family_model(void) diff --git a/src/cpu/intel/broadwell/smmrelocate.c b/src/cpu/intel/broadwell/smmrelocate.c index 660a688..3f334d7 100644 --- a/src/cpu/intel/broadwell/smmrelocate.c +++ b/src/cpu/intel/broadwell/smmrelocate.c @@ -14,8 +14,7 @@ #include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <smp/node.h> -#include <soc/cpu.h> -#include <soc/msr.h> +#include <cpu/intel/broadwell/broadwell.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> diff --git a/src/cpu/intel/broadwell/tsc_freq.c b/src/cpu/intel/broadwell/tsc_freq.c index 4a8a343..c467328 100644 --- a/src/cpu/intel/broadwell/tsc_freq.c +++ b/src/cpu/intel/broadwell/tsc_freq.c @@ -2,8 +2,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> -#include <soc/cpu.h> -#include <soc/msr.h> +#include <cpu/intel/broadwell/broadwell.h> unsigned long tsc_freq_mhz(void) { diff --git a/src/northbridge/intel/broadwell/igd.c b/src/northbridge/intel/broadwell/igd.c index 41167b1..5f6673f 100644 --- a/src/northbridge/intel/broadwell/igd.c +++ b/src/northbridge/intel/broadwell/igd.c @@ -15,7 +15,7 @@ #include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/libgfxinit.h> #include <drivers/intel/gma/opregion.h> -#include <soc/cpu.h> +#include <cpu/intel/broadwell/broadwell.h> #include <soc/pm.h> #include <soc/ramstage.h> #include <soc/systemagent.h> diff --git a/src/northbridge/intel/broadwell/report_platform.c b/src/northbridge/intel/broadwell/report_platform.c index 1029395..88228f9 100644 --- a/src/northbridge/intel/broadwell/report_platform.c +++ b/src/northbridge/intel/broadwell/report_platform.c @@ -6,7 +6,7 @@ #include <device/pci.h> #include <string.h> #include <cpu/x86/msr.h> -#include <soc/cpu.h> +#include <cpu/intel/broadwell/broadwell.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/romstage.h> diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h index 9167736..e69de29 100644 --- a/src/soc/intel/broadwell/include/soc/cpu.h +++ b/src/soc/intel/broadwell/include/soc/cpu.h @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _BROADWELL_CPU_H_ -#define _BROADWELL_CPU_H_ - -#include <device/device.h> - -/* CPU types */ -#define HASWELL_FAMILY_ULT 0x40650 -#define BROADWELL_FAMILY_ULT 0x306d0 - -/* Supported CPUIDs */ -#define CPUID_HASWELL_A0 0x306c1 -#define CPUID_HASWELL_B0 0x306c2 -#define CPUID_HASWELL_C0 0x306c3 -#define CPUID_HASWELL_ULT_B0 0x40650 -#define CPUID_HASWELL_ULT 0x40651 -#define CPUID_HASWELL_HALO 0x40661 -#define CPUID_BROADWELL_C0 0x306d2 -#define CPUID_BROADWELL_D0 0x306d3 -#define CPUID_BROADWELL_E0 0x306d4 - -/* CPU bus clock is fixed at 100MHz */ -#define CPU_BCLK 100 - -/* Latency times in units of 1024ns. */ -#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 -#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 -#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 -#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 -#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 -#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef - -#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ - (((1 << ((base)*5)) * (limit)) / 1000) -#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ - C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ - (IRTL_1024_NS >> 10)) - -/* CPU identification */ -u32 cpu_family_model(void); -u32 cpu_stepping(void); -int cpu_is_ult(void); - -#endif diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index 1e47b44..af717a2 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -1,73 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _BROADWELL_MSR_H_ -#define _BROADWELL_MSR_H_ - #include <intelblocks/msr.h> - -#define MSR_PIC_MSG_CONTROL 0x2e -#define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 -#define MSR_FEATURE_CONFIG 0x13c -#define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) -#define MSR_FLEX_RATIO 0x194 -#define FLEX_RATIO_LOCK (1 << 20) -#define FLEX_RATIO_EN (1 << 16) -#define MSR_MISC_PWR_MGMT 0x1aa -#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) -#define MSR_TURBO_RATIO_LIMIT 0x1ad -#define MSR_TEMPERATURE_TARGET 0x1a2 -#define MSR_PRMRR_PHYS_BASE 0x1f4 -#define MSR_PRMRR_PHYS_MASK 0x1f5 -#define MSR_POWER_CTL 0x1fc -#define MSR_LT_LOCK_MEMORY 0x2e7 -#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 -#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 -#define SMM_FEATURE_CONTROL_MSR 0x4e0 -#define SMM_CPU_SAVE_EN (1 << 1) - -#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a -#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b -#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c -#define MSR_C_STATE_LATENCY_CONTROL_3 0x633 -#define MSR_C_STATE_LATENCY_CONTROL_4 0x634 -#define MSR_C_STATE_LATENCY_CONTROL_5 0x635 -#define IRTL_VALID (1 << 15) -#define IRTL_1_NS (0 << 10) -#define IRTL_32_NS (1 << 10) -#define IRTL_1024_NS (2 << 10) -#define IRTL_32768_NS (3 << 10) -#define IRTL_1048576_NS (4 << 10) -#define IRTL_33554432_NS (5 << 10) -#define IRTL_RESPONSE_MASK (0x3ff) -#define MSR_COUNTER_24_MHZ 0x637 - -#define MSR_VR_CURRENT_CONFIG 0x601 -#define MSR_VR_MISC_CONFIG 0x603 -#define MSR_PKG_POWER_SKU_UNIT 0x606 -#define MSR_PKG_POWER_SKU 0x614 -#define MSR_DDR_RAPL_LIMIT 0x618 -#define MSR_VR_MISC_CONFIG2 0x636 -#define MSR_PP0_POWER_LIMIT 0x638 -#define MSR_PP1_POWER_LIMIT 0x640 - -#define MSR_CONFIG_TDP_NOMINAL 0x648 -#define MSR_CONFIG_TDP_LEVEL1 0x649 -#define MSR_CONFIG_TDP_LEVEL2 0x64a -#define MSR_CONFIG_TDP_CONTROL 0x64b -#define MSR_TURBO_ACTIVATION_RATIO 0x64c - -/* SMM save state MSRs */ -#define SMBASE_MSR 0xc20 -#define IEDBASE_MSR 0xc22 - -/* MTRR_CAP_MSR bits */ -#define SMRR_SUPPORTED (1<<11) -#define PRMRR_SUPPORTED (1<<12) - -#endif diff --git a/src/southbridge/intel/wildcatpoint/pcie.c b/src/southbridge/intel/wildcatpoint/pcie.c index 9eb14d9..2ec714f 100644 --- a/src/southbridge/intel/wildcatpoint/pcie.c +++ b/src/southbridge/intel/wildcatpoint/pcie.c @@ -14,7 +14,7 @@ #include <soc/pci_devs.h> #include <soc/rcba.h> #include <soc/intel/broadwell/chip.h> -#include <soc/cpu.h> +#include <cpu/intel/broadwell/broadwell.h> #include <delay.h> /* Low Power variant has 6 root ports. */ diff --git a/src/southbridge/intel/wildcatpoint/xhci.c b/src/southbridge/intel/wildcatpoint/xhci.c index 319c9b1..7541fef 100644 --- a/src/southbridge/intel/wildcatpoint/xhci.c +++ b/src/southbridge/intel/wildcatpoint/xhci.c @@ -9,7 +9,7 @@ #include <device/pci_ops.h> #include <soc/ramstage.h> #include <soc/xhci.h> -#include <soc/cpu.h> +#include <cpu/intel/broadwell/broadwell.h> #ifdef __SIMPLE_DEVICE__ static u8 *usb_xhci_mem_base(pci_devfn_t dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/41936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9e860fbb02e2fd3c894236abbb784c21f231bbf Gerrit-Change-Number: 41936 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: northbridge/intel/broadwell: Add header files
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41937 ) Change subject: northbridge/intel/broadwell: Add header files ...................................................................... northbridge/intel/broadwell: Add header files Relocate northbridge-related headers from soc to the northbridge scope. Note that code in soc/intel/common expects to find `soc/systemagent.h`. And yes, some prototypes are now in the wrong place. This will be fixed in the next commits, once the soc/intel/broadwell subfolder is no more. With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical. Change-Id: Ia262c8734d59ed5530a9a87bb1cb0b7a86f91708 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/broadwell/acpi.c M src/cpu/intel/broadwell/broadwell_early_init.c M src/cpu/intel/broadwell/cpu.c M src/cpu/intel/broadwell/cpu_info.c M src/cpu/intel/broadwell/romstage.c M src/cpu/intel/broadwell/smmrelocate.c M src/mainboard/google/auron/romstage.c M src/mainboard/google/auron/variant.h M src/mainboard/google/auron/variants/auron_paine/pei_data.c M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/pei_data.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/buddy/pei_data.c M src/mainboard/google/auron/variants/buddy/spd/spd.c M src/mainboard/google/auron/variants/gandof/pei_data.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/pei_data.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/auron/variants/samus/pei_data.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/auron/variants/samus/variant.c M src/mainboard/google/jecht/romstage.c M src/mainboard/google/jecht/spd/spd.c M src/mainboard/google/jecht/variants/guado/pei_data.c M src/mainboard/google/jecht/variants/jecht/pei_data.c M src/mainboard/google/jecht/variants/rikku/pei_data.c M src/mainboard/google/jecht/variants/tidus/pei_data.c M src/mainboard/intel/wtm2/pei_data.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/romstage.c M src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c M src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c M src/northbridge/intel/broadwell/bootblock.c A src/northbridge/intel/broadwell/broadwell.h M src/northbridge/intel/broadwell/finalize.c M src/northbridge/intel/broadwell/igd.c R src/northbridge/intel/broadwell/igd.h M src/northbridge/intel/broadwell/memmap.c M src/northbridge/intel/broadwell/minihd.c M src/northbridge/intel/broadwell/pei_data.c R src/northbridge/intel/broadwell/pei_data.h R src/northbridge/intel/broadwell/pei_wrapper.h M src/northbridge/intel/broadwell/raminit.c M src/northbridge/intel/broadwell/refcode.c M src/northbridge/intel/broadwell/report_platform.c M src/northbridge/intel/broadwell/romstage.c R src/northbridge/intel/broadwell/romstage.h M src/northbridge/intel/broadwell/systemagent.c M src/soc/intel/broadwell/include/soc/systemagent.h M src/southbridge/intel/wildcatpoint/bootblock.c M src/southbridge/intel/wildcatpoint/early_pch.c M src/southbridge/intel/wildcatpoint/early_smbus.c M src/southbridge/intel/wildcatpoint/power_state.c 55 files changed, 215 insertions(+), 205 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/41937/1 diff --git a/src/cpu/intel/broadwell/acpi.c b/src/cpu/intel/broadwell/acpi.c index db5a232..c052034 100644 --- a/src/cpu/intel/broadwell/acpi.c +++ b/src/cpu/intel/broadwell/acpi.c @@ -21,7 +21,7 @@ #include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/pm.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/broadwell.h> #include <soc/intel/broadwell/chip.h> #include <intelblocks/cpulib.h> diff --git a/src/cpu/intel/broadwell/broadwell_early_init.c b/src/cpu/intel/broadwell/broadwell_early_init.c index ad1ce6d..4fd23f6 100644 --- a/src/cpu/intel/broadwell/broadwell_early_init.c +++ b/src/cpu/intel/broadwell/broadwell_early_init.c @@ -4,7 +4,7 @@ #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/intel/broadwell/broadwell.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/romstage.h> u32 cpu_family_model(void) { diff --git a/src/cpu/intel/broadwell/cpu.c b/src/cpu/intel/broadwell/cpu.c index cbb96bc..f8189dd 100644 --- a/src/cpu/intel/broadwell/cpu.c +++ b/src/cpu/intel/broadwell/cpu.c @@ -21,7 +21,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/rcba.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/broadwell.h> #include <soc/intel/broadwell/chip.h> #include <cpu/intel/common/common.h> diff --git a/src/cpu/intel/broadwell/cpu_info.c b/src/cpu/intel/broadwell/cpu_info.c index f4a8dad..975a104 100644 --- a/src/cpu/intel/broadwell/cpu_info.c +++ b/src/cpu/intel/broadwell/cpu_info.c @@ -3,7 +3,7 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/broadwell/broadwell.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/broadwell.h> u32 cpu_family_model(void) { diff --git a/src/cpu/intel/broadwell/romstage.c b/src/cpu/intel/broadwell/romstage.c index 54d6134..03a7e96 100644 --- a/src/cpu/intel/broadwell/romstage.c +++ b/src/cpu/intel/broadwell/romstage.c @@ -12,9 +12,9 @@ #include <timestamp.h> #include <soc/gpio.h> #include <soc/me.h> -#include <soc/pei_data.h> +#include <northbridge/intel/broadwell/pei_data.h> #include <soc/pm.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/romstage.h> #include <soc/spi.h> void fill_postcar_frame(struct postcar_frame *pcf) diff --git a/src/cpu/intel/broadwell/smmrelocate.c b/src/cpu/intel/broadwell/smmrelocate.c index 3f334d7..ea38d15 100644 --- a/src/cpu/intel/broadwell/smmrelocate.c +++ b/src/cpu/intel/broadwell/smmrelocate.c @@ -16,7 +16,7 @@ #include <smp/node.h> #include <cpu/intel/broadwell/broadwell.h> #include <soc/pci_devs.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/broadwell.h> static void update_save_state(int cpu, uintptr_t curr_smbase, diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c index ed17800..1540299 100644 --- a/src/mainboard/google/auron/romstage.c +++ b/src/mainboard/google/auron/romstage.c @@ -2,9 +2,9 @@ #include <console/console.h> #include <ec/google/chromeec/ec.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> +#include <northbridge/intel/broadwell/romstage.h> #include <variant/spd.h> #include "variant.h" diff --git a/src/mainboard/google/auron/variant.h b/src/mainboard/google/auron/variant.h index 095096b..9853aa2 100644 --- a/src/mainboard/google/auron/variant.h +++ b/src/mainboard/google/auron/variant.h @@ -4,7 +4,7 @@ #define VARIANT_H #include <device/device.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/romstage.h> int variant_smbios_data(struct device *dev, int *handle, unsigned long *current); diff --git a/src/mainboard/google/auron/variants/auron_paine/pei_data.c b/src/mainboard/google/auron/variants/auron_paine/pei_data.c index c2a22ae..88c1c28 100644 --- a/src/mainboard/google/auron/variants/auron_paine/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_paine/pei_data.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c index da00ad9..e937651 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c @@ -5,8 +5,8 @@ #include <endian.h> #include <string.h> #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> #include <variant/spd.h> diff --git a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c index c2a22ae..88c1c28 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c index da00ad9..e937651 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c @@ -5,8 +5,8 @@ #include <endian.h> #include <string.h> #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> #include <variant/spd.h> diff --git a/src/mainboard/google/auron/variants/buddy/pei_data.c b/src/mainboard/google/auron/variants/buddy/pei_data.c index 026853f..823c968 100644 --- a/src/mainboard/google/auron/variants/buddy/pei_data.c +++ b/src/mainboard/google/auron/variants/buddy/pei_data.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/google/auron/variants/buddy/spd/spd.c b/src/mainboard/google/auron/variants/buddy/spd/spd.c index 4dd1de6..fa15b34 100644 --- a/src/mainboard/google/auron/variants/buddy/spd/spd.c +++ b/src/mainboard/google/auron/variants/buddy/spd/spd.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/pei_data.h> +#include <northbridge/intel/broadwell/pei_data.h> #include <variant/spd.h> /* Copy SPD data for on-board memory */ diff --git a/src/mainboard/google/auron/variants/gandof/pei_data.c b/src/mainboard/google/auron/variants/gandof/pei_data.c index c2a22ae..88c1c28 100644 --- a/src/mainboard/google/auron/variants/gandof/pei_data.c +++ b/src/mainboard/google/auron/variants/gandof/pei_data.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c index da00ad9..e937651 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/spd.c +++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c @@ -5,8 +5,8 @@ #include <endian.h> #include <string.h> #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> #include <variant/spd.h> diff --git a/src/mainboard/google/auron/variants/gandof/variant.c b/src/mainboard/google/auron/variants/gandof/variant.c index acf2a2d..bc345da 100644 --- a/src/mainboard/google/auron/variants/gandof/variant.c +++ b/src/mainboard/google/auron/variants/gandof/variant.c @@ -3,7 +3,7 @@ #include <ec/google/chromeec/ec.h> #include <soc/pm.h> #include <smbios.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/romstage.h> #include <variant/onboard.h> #include <mainboard/google/auron/variant.h> diff --git a/src/mainboard/google/auron/variants/lulu/pei_data.c b/src/mainboard/google/auron/variants/lulu/pei_data.c index bbc7125..e88972e 100644 --- a/src/mainboard/google/auron/variants/lulu/pei_data.c +++ b/src/mainboard/google/auron/variants/lulu/pei_data.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c index 0daf308..7cf7e66 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/spd.c +++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c @@ -5,8 +5,8 @@ #include <endian.h> #include <string.h> #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> #include <variant/spd.h> diff --git a/src/mainboard/google/auron/variants/lulu/variant.c b/src/mainboard/google/auron/variants/lulu/variant.c index e8b3174..98424d8 100644 --- a/src/mainboard/google/auron/variants/lulu/variant.c +++ b/src/mainboard/google/auron/variants/lulu/variant.c @@ -3,7 +3,7 @@ #include <ec/google/chromeec/ec.h> #include <soc/pm.h> #include <smbios.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/romstage.h> #include <variant/onboard.h> #include <mainboard/google/auron/variant.h> diff --git a/src/mainboard/google/auron/variants/samus/pei_data.c b/src/mainboard/google/auron/variants/samus/pei_data.c index 9bcf92b..eef54d4 100644 --- a/src/mainboard/google/auron/variants/samus/pei_data.c +++ b/src/mainboard/google/auron/variants/samus/pei_data.c @@ -3,8 +3,8 @@ #include <stdint.h> #include <string.h> #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c index 4684d86..213d4a5 100644 --- a/src/mainboard/google/auron/variants/samus/spd/spd.c +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -5,8 +5,8 @@ #include <endian.h> #include <string.h> #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> #include <variant/spd.h> diff --git a/src/mainboard/google/auron/variants/samus/variant.c b/src/mainboard/google/auron/variants/samus/variant.c index 12f4e86..baa0d52 100644 --- a/src/mainboard/google/auron/variants/samus/variant.c +++ b/src/mainboard/google/auron/variants/samus/variant.c @@ -4,7 +4,7 @@ #include <ec/google/chromeec/ec.h> #include <soc/gpio.h> #include <soc/pm.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/romstage.h> #include <smbios.h> #include <variant/board_version.h> #include <variant/onboard.h> diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index 1f03aed..0b30542 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -3,9 +3,9 @@ #include <bootmode.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> +#include <northbridge/intel/broadwell/romstage.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8772f/it8772f.h> #include <mainboard/google/jecht/spd/spd.h> diff --git a/src/mainboard/google/jecht/spd/spd.c b/src/mainboard/google/jecht/spd/spd.c index 911cf60..342f311 100644 --- a/src/mainboard/google/jecht/spd/spd.c +++ b/src/mainboard/google/jecht/spd/spd.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/pei_data.h> +#include <northbridge/intel/broadwell/pei_data.h> #include <mainboard/google/jecht/spd/spd.h> /* Copy SPD data for on-board memory */ diff --git a/src/mainboard/google/jecht/variants/guado/pei_data.c b/src/mainboard/google/jecht/variants/guado/pei_data.c index ba950d6..1efb768 100644 --- a/src/mainboard/google/jecht/variants/guado/pei_data.c +++ b/src/mainboard/google/jecht/variants/guado/pei_data.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/google/jecht/variants/jecht/pei_data.c b/src/mainboard/google/jecht/variants/jecht/pei_data.c index ba950d6..1efb768 100644 --- a/src/mainboard/google/jecht/variants/jecht/pei_data.c +++ b/src/mainboard/google/jecht/variants/jecht/pei_data.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/google/jecht/variants/rikku/pei_data.c b/src/mainboard/google/jecht/variants/rikku/pei_data.c index ba950d6..1efb768 100644 --- a/src/mainboard/google/jecht/variants/rikku/pei_data.c +++ b/src/mainboard/google/jecht/variants/rikku/pei_data.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/google/jecht/variants/tidus/pei_data.c b/src/mainboard/google/jecht/variants/tidus/pei_data.c index dc13022..6af5d83 100644 --- a/src/mainboard/google/jecht/variants/tidus/pei_data.c +++ b/src/mainboard/google/jecht/variants/tidus/pei_data.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/intel/wtm2/pei_data.c b/src/mainboard/intel/wtm2/pei_data.c index 92101bd..bcf091a 100644 --- a/src/mainboard/intel/wtm2/pei_data.c +++ b/src/mainboard/intel/wtm2/pei_data.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index 9e22250..9fc63cf 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -2,9 +2,9 @@ #include <console/console.h> #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> +#include <northbridge/intel/broadwell/romstage.h> void mainboard_pre_raminit(struct romstage_params *rp) { diff --git a/src/mainboard/purism/librem_bdw/romstage.c b/src/mainboard/purism/librem_bdw/romstage.c index 8fc2f9e..41447c9 100644 --- a/src/mainboard/purism/librem_bdw/romstage.c +++ b/src/mainboard/purism/librem_bdw/romstage.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> +#include <northbridge/intel/broadwell/romstage.h> void mainboard_pre_raminit(struct romstage_params *rp) { diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c b/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c index 1e5d9d9..6fe5584 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c b/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c index c3580b3..2a61fe6 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/northbridge/intel/broadwell/bootblock.c b/src/northbridge/intel/broadwell/bootblock.c index ef55699..be389b7 100644 --- a/src/northbridge/intel/broadwell/bootblock.c +++ b/src/northbridge/intel/broadwell/bootblock.c @@ -3,7 +3,7 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/broadwell.h> void bootblock_early_northbridge_init(void) { diff --git a/src/northbridge/intel/broadwell/broadwell.h b/src/northbridge/intel/broadwell/broadwell.h new file mode 100644 index 0000000..8d71103 --- /dev/null +++ b/src/northbridge/intel/broadwell/broadwell.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __NORTHBRIDGE_INTEL_BROADWELL_BROADWELL_H__ +#define __NORTHBRIDGE_INTEL_BROADWELL_BROADWELL_H__ + +#include <soc/iomap.h> + +#define SA_IGD_OPROM_VENDEV 0x80860406 + +#define IGD_HASWELL_ULT_GT1 0x0a06 +#define IGD_HASWELL_ULT_GT2 0x0a16 +#define IGD_HASWELL_ULT_GT3 0x0a26 +#define IGD_HASWELL_ULX_GT1 0x0a0e +#define IGD_HASWELL_ULX_GT2 0x0a1e +#define IGD_BROADWELL_U_GT1 0x1606 +#define IGD_BROADWELL_U_GT2 0x1616 +#define IGD_BROADWELL_U_GT3_15W 0x1626 +#define IGD_BROADWELL_U_GT3_28W 0x162b +#define IGD_BROADWELL_Y_GT2 0x161e +#define IGD_BROADWELL_H_GT2 0x1612 +#define IGD_BROADWELL_H_GT3 0x1622 + +#define MCH_BROADWELL_ID_U_Y 0x1604 +#define MCH_BROADWELL_REV_D0 0x06 +#define MCH_BROADWELL_REV_E0 0x08 +#define MCH_BROADWELL_REV_F0 0x09 + +/* Device 0:0.0 PCI configuration space */ + +#define EPBAR 0x40 +#define MCHBAR 0x48 +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 +#define GGC 0x50 /* GMCH Graphics Control */ +#define DEVEN 0x54 /* Device Enable */ +#define DEVEN_D7EN (1 << 14) +#define DEVEN_D4EN (1 << 7) +#define DEVEN_D3EN (1 << 5) +#define DEVEN_D2EN (1 << 4) +#define DEVEN_D1F0EN (1 << 3) +#define DEVEN_D1F1EN (1 << 2) +#define DEVEN_D1F2EN (1 << 1) +#define DEVEN_D0EN (1 << 0) +#define DPR 0x5c +#define DPR_EPM (1 << 2) +#define DPR_PRS (1 << 1) +#define DPR_SIZE_MASK 0xff0 + +#define PAM0 0x80 +#define PAM1 0x81 +#define PAM2 0x82 +#define PAM3 0x83 +#define PAM4 0x84 +#define PAM5 0x85 +#define PAM6 0x86 + +#define SMRAM 0x88 /* System Management RAM Control */ +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) +#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ +#define DMAR_LCKDN (1 << 31) +#define PRSCAPDIS (1 << 2) + +#define MESEG_BASE 0x70 /* Management Engine Base. */ +#define MESEG_LIMIT 0x78 /* Management Engine Limit. */ +#define REMAPBASE 0x90 /* Remap base. */ +#define REMAPLIMIT 0x98 /* Remap limit. */ +#define TOM 0xa0 /* Top of DRAM in memory controller space. */ +#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ +#define BDSM 0xb0 /* Base Data Stolen Memory */ +#define BGSM 0xb4 /* Base GTT Stolen Memory */ +#define TSEG 0xb8 /* TSEG base */ +#define TOLUD 0xbc /* Top of Low Used Memory */ +#define SKPAD 0xdc /* Scratchpad Data */ + +/* MCHBAR */ + +#define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + x)) +#define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + x)) +#define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + x)) + +#define MCHBAR_PEI_VERSION 0x5034 +#define BIOS_RESET_CPL 0x5da8 +#define GFXVTBAR 0x5400 +#define EDRAMBAR 0x5408 +#define VTVC0BAR 0x5410 +#define MCH_PAIR 0x5418 +#define GDXCBAR 0x5420 + +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 + +/* PCODE MMIO communications live in the MCHBAR. */ +#define BIOS_MAILBOX_INTERFACE 0x5da4 +#define MAILBOX_RUN_BUSY (1 << 31) +#define MAILBOX_BIOS_CMD_READ_PCS 1 +#define MAILBOX_BIOS_CMD_WRITE_PCS 2 +#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 +#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 +#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa +#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb +#define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 +#define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 +/* Errors are returned back in bits 7:0. */ +#define MAILBOX_BIOS_ERROR_NONE 0 +#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 +#define MAILBOX_BIOS_ERROR_TIMEOUT 2 +#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 +#define MAILBOX_BIOS_ERROR_RESERVED 4 +#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 +#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 +#define MAILBOX_BIOS_ERROR_VR_ERROR 7 +/* Data is passed through bits 31:0 of the data register. */ +#define BIOS_MAILBOX_DATA 0x5da0 + +/* System Agent identification */ +u8 systemagent_revision(void); + +uintptr_t sa_get_tolud_base(void); +uintptr_t sa_get_gsm_base(void); + +#endif diff --git a/src/northbridge/intel/broadwell/finalize.c b/src/northbridge/intel/broadwell/finalize.c index 35ce010..d258694 100644 --- a/src/northbridge/intel/broadwell/finalize.c +++ b/src/northbridge/intel/broadwell/finalize.c @@ -11,7 +11,7 @@ #include <soc/me.h> #include <soc/rcba.h> #include <soc/spi.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/broadwell.h> #include <southbridge/intel/common/spi.h> const struct reg_script system_agent_finalize_script[] = { diff --git a/src/northbridge/intel/broadwell/igd.c b/src/northbridge/intel/broadwell/igd.c index 5f6673f..3e47b53 100644 --- a/src/northbridge/intel/broadwell/igd.c +++ b/src/northbridge/intel/broadwell/igd.c @@ -18,10 +18,10 @@ #include <cpu/intel/broadwell/broadwell.h> #include <soc/pm.h> #include <soc/ramstage.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/broadwell.h> #include <soc/intel/broadwell/chip.h> #include <security/vboot/vbnv.h> -#include <soc/igd.h> +#include <northbridge/intel/broadwell/igd.h> #include <types.h> #define GT_RETRY 1000 diff --git a/src/soc/intel/broadwell/include/soc/igd.h b/src/northbridge/intel/broadwell/igd.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/igd.h rename to src/northbridge/intel/broadwell/igd.h diff --git a/src/northbridge/intel/broadwell/memmap.c b/src/northbridge/intel/broadwell/memmap.c index bada5fd..c062d7d 100644 --- a/src/northbridge/intel/broadwell/memmap.c +++ b/src/northbridge/intel/broadwell/memmap.c @@ -7,7 +7,7 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/broadwell.h> #include <stdint.h> static uintptr_t dpr_region_start(void) diff --git a/src/northbridge/intel/broadwell/minihd.c b/src/northbridge/intel/broadwell/minihd.c index b91d73d..db15dbb 100644 --- a/src/northbridge/intel/broadwell/minihd.c +++ b/src/northbridge/intel/broadwell/minihd.c @@ -8,7 +8,7 @@ #include <device/mmio.h> #include <soc/intel/common/hda_verb.h> #include <soc/ramstage.h> -#include <soc/igd.h> +#include <northbridge/intel/broadwell/igd.h> static const u32 minihd_verb_table[] = { /* coreboot specific header */ diff --git a/src/northbridge/intel/broadwell/pei_data.c b/src/northbridge/intel/broadwell/pei_data.c index efc91fd..41fc475 100644 --- a/src/northbridge/intel/broadwell/pei_data.c +++ b/src/northbridge/intel/broadwell/pei_data.c @@ -2,8 +2,8 @@ #include <console/streams.h> #include <soc/iomap.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> static void ABI_X86 send_to_console(unsigned char b) { diff --git a/src/soc/intel/broadwell/include/soc/pei_data.h b/src/northbridge/intel/broadwell/pei_data.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/pei_data.h rename to src/northbridge/intel/broadwell/pei_data.h diff --git a/src/soc/intel/broadwell/include/soc/pei_wrapper.h b/src/northbridge/intel/broadwell/pei_wrapper.h similarity index 94% rename from src/soc/intel/broadwell/include/soc/pei_wrapper.h rename to src/northbridge/intel/broadwell/pei_wrapper.h index 81e1bd5..44c23d0 100644 --- a/src/soc/intel/broadwell/include/soc/pei_wrapper.h +++ b/src/northbridge/intel/broadwell/pei_wrapper.h @@ -3,7 +3,7 @@ #ifndef _BROADWELL_PEI_WRAPPER_H_ #define _BROADWELL_PEI_WRAPPER_H_ -#include <soc/pei_data.h> +#include <northbridge/intel/broadwell/pei_data.h> typedef int ABI_X86 (*pei_wrapper_entry_t)(struct pei_data *pei_data); diff --git a/src/northbridge/intel/broadwell/raminit.c b/src/northbridge/intel/broadwell/raminit.c index 8c194fc..dca56b6 100644 --- a/src/northbridge/intel/broadwell/raminit.c +++ b/src/northbridge/intel/broadwell/raminit.c @@ -15,11 +15,11 @@ #endif #include <vendorcode/google/chromeos/chromeos.h> #include <soc/iomap.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> #include <soc/pm.h> -#include <soc/romstage.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/romstage.h> +#include <northbridge/intel/broadwell/broadwell.h> /* * Find PEI executable in coreboot filesystem and execute it. diff --git a/src/northbridge/intel/broadwell/refcode.c b/src/northbridge/intel/broadwell/refcode.c index 5e5bc49..5ba43cd 100644 --- a/src/northbridge/intel/broadwell/refcode.c +++ b/src/northbridge/intel/broadwell/refcode.c @@ -9,8 +9,8 @@ #include <program_loading.h> #include <rmodule.h> #include <stage_cache.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <northbridge/intel/broadwell/pei_data.h> +#include <northbridge/intel/broadwell/pei_wrapper.h> #include <soc/pm.h> #include <soc/ramstage.h> diff --git a/src/northbridge/intel/broadwell/report_platform.c b/src/northbridge/intel/broadwell/report_platform.c index 88228f9..1012ce2 100644 --- a/src/northbridge/intel/broadwell/report_platform.c +++ b/src/northbridge/intel/broadwell/report_platform.c @@ -9,8 +9,8 @@ #include <cpu/intel/broadwell/broadwell.h> #include <soc/pch.h> #include <soc/pci_devs.h> -#include <soc/romstage.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/romstage.h> +#include <northbridge/intel/broadwell/broadwell.h> static struct { u32 cpuid; diff --git a/src/northbridge/intel/broadwell/romstage.c b/src/northbridge/intel/broadwell/romstage.c index 6f6db62..efc26d9 100644 --- a/src/northbridge/intel/broadwell/romstage.c +++ b/src/northbridge/intel/broadwell/romstage.c @@ -6,8 +6,8 @@ #include <reg_script.h> #include <soc/iomap.h> #include <soc/pci_devs.h> -#include <soc/romstage.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/romstage.h> +#include <northbridge/intel/broadwell/broadwell.h> static const struct reg_script systemagent_early_init_script[] = { REG_PCI_WRITE32(MCHBAR, MCH_BASE_ADDRESS | 1), diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/northbridge/intel/broadwell/romstage.h similarity index 93% rename from src/soc/intel/broadwell/include/soc/romstage.h rename to src/northbridge/intel/broadwell/romstage.h index 2c7b0a4..275938a 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/northbridge/intel/broadwell/romstage.h @@ -4,7 +4,7 @@ #define _BROADWELL_ROMSTAGE_H_ #include <stdint.h> -#include <soc/pei_data.h> +#include <northbridge/intel/broadwell/pei_data.h> struct chipset_power_state; struct romstage_params { diff --git a/src/northbridge/intel/broadwell/systemagent.c b/src/northbridge/intel/broadwell/systemagent.c index b75c4fe..15110da 100644 --- a/src/northbridge/intel/broadwell/systemagent.c +++ b/src/northbridge/intel/broadwell/systemagent.c @@ -14,7 +14,7 @@ #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> -#include <soc/systemagent.h> +#include <northbridge/intel/broadwell/broadwell.h> u8 systemagent_revision(void) { diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index c2c5cc8..5c93352 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -5,125 +5,6 @@ #include <soc/iomap.h> -#define SA_IGD_OPROM_VENDEV 0x80860406 - -#define IGD_HASWELL_ULT_GT1 0x0a06 -#define IGD_HASWELL_ULT_GT2 0x0a16 -#define IGD_HASWELL_ULT_GT3 0x0a26 -#define IGD_HASWELL_ULX_GT1 0x0a0e -#define IGD_HASWELL_ULX_GT2 0x0a1e -#define IGD_BROADWELL_U_GT1 0x1606 -#define IGD_BROADWELL_U_GT2 0x1616 -#define IGD_BROADWELL_U_GT3_15W 0x1626 -#define IGD_BROADWELL_U_GT3_28W 0x162b -#define IGD_BROADWELL_Y_GT2 0x161e -#define IGD_BROADWELL_H_GT2 0x1612 -#define IGD_BROADWELL_H_GT3 0x1622 - -#define MCH_BROADWELL_ID_U_Y 0x1604 -#define MCH_BROADWELL_REV_D0 0x06 -#define MCH_BROADWELL_REV_E0 0x08 -#define MCH_BROADWELL_REV_F0 0x09 - -/* Device 0:0.0 PCI configuration space */ - -#define EPBAR 0x40 -#define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 -#define GGC 0x50 /* GMCH Graphics Control */ -#define DEVEN 0x54 /* Device Enable */ -#define DEVEN_D7EN (1 << 14) -#define DEVEN_D4EN (1 << 7) -#define DEVEN_D3EN (1 << 5) -#define DEVEN_D2EN (1 << 4) -#define DEVEN_D1F0EN (1 << 3) -#define DEVEN_D1F1EN (1 << 2) -#define DEVEN_D1F2EN (1 << 1) -#define DEVEN_D0EN (1 << 0) -#define DPR 0x5c -#define DPR_EPM (1 << 2) -#define DPR_PRS (1 << 1) -#define DPR_SIZE_MASK 0xff0 - -#define PAM0 0x80 -#define PAM1 0x81 -#define PAM2 0x82 -#define PAM3 0x83 -#define PAM4 0x84 -#define PAM5 0x85 -#define PAM6 0x86 - -#define SMRAM 0x88 /* System Management RAM Control */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -#define CAPID0_A 0xe4 -#define VTD_DISABLE (1 << 23) -#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ -#define DMAR_LCKDN (1 << 31) -#define PRSCAPDIS (1 << 2) - -#define MESEG_BASE 0x70 /* Management Engine Base. */ -#define MESEG_LIMIT 0x78 /* Management Engine Limit. */ -#define REMAPBASE 0x90 /* Remap base. */ -#define REMAPLIMIT 0x98 /* Remap limit. */ -#define TOM 0xa0 /* Top of DRAM in memory controller space. */ -#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ -#define BDSM 0xb0 /* Base Data Stolen Memory */ -#define BGSM 0xb4 /* Base GTT Stolen Memory */ -#define TSEG 0xb8 /* TSEG base */ -#define TOLUD 0xbc /* Top of Low Used Memory */ -#define SKPAD 0xdc /* Scratchpad Data */ - -/* MCHBAR */ - -#define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + x)) -#define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + x)) #define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + x)) -#define MCHBAR_PEI_VERSION 0x5034 -#define BIOS_RESET_CPL 0x5da8 -#define GFXVTBAR 0x5400 -#define EDRAMBAR 0x5408 -#define VTVC0BAR 0x5410 -#define MCH_PAIR 0x5418 -#define GDXCBAR 0x5420 - -#define MCH_PKG_POWER_LIMIT_LO 0x59a0 -#define MCH_PKG_POWER_LIMIT_HI 0x59a4 -#define MCH_DDR_POWER_LIMIT_LO 0x58e0 -#define MCH_DDR_POWER_LIMIT_HI 0x58e4 - -/* PCODE MMIO communications live in the MCHBAR. */ -#define BIOS_MAILBOX_INTERFACE 0x5da4 -#define MAILBOX_RUN_BUSY (1 << 31) -#define MAILBOX_BIOS_CMD_READ_PCS 1 -#define MAILBOX_BIOS_CMD_WRITE_PCS 2 -#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 -#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 -#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa -#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb -#define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 -#define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 -/* Errors are returned back in bits 7:0. */ -#define MAILBOX_BIOS_ERROR_NONE 0 -#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 -#define MAILBOX_BIOS_ERROR_TIMEOUT 2 -#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 -#define MAILBOX_BIOS_ERROR_RESERVED 4 -#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 -#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 -#define MAILBOX_BIOS_ERROR_VR_ERROR 7 -/* Data is passed through bits 31:0 of the data register. */ -#define BIOS_MAILBOX_DATA 0x5da0 - -/* System Agent identification */ -u8 systemagent_revision(void); - -uintptr_t sa_get_tolud_base(void); -uintptr_t sa_get_gsm_base(void); - #endif diff --git a/src/southbridge/intel/wildcatpoint/bootblock.c b/src/southbridge/intel/wildcatpoint/bootblock.c index c7b3e67..61af770 100644 --- a/src/southbridge/intel/wildcatpoint/bootblock.c +++ b/src/southbridge/intel/wildcatpoint/bootblock.c @@ -9,7 +9,7 @@ #include <soc/spi.h> #include <reg_script.h> #include <soc/pm.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/romstage.h> /* * Enable Prefetching and Caching. diff --git a/src/southbridge/intel/wildcatpoint/early_pch.c b/src/southbridge/intel/wildcatpoint/early_pch.c index 9afb4e4..9b73760 100644 --- a/src/southbridge/intel/wildcatpoint/early_pch.c +++ b/src/southbridge/intel/wildcatpoint/early_pch.c @@ -11,7 +11,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/rcba.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/romstage.h> #include <soc/smbus.h> #include <soc/intel/broadwell/chip.h> diff --git a/src/southbridge/intel/wildcatpoint/early_smbus.c b/src/southbridge/intel/wildcatpoint/early_smbus.c index a000255..5da5f4e 100644 --- a/src/southbridge/intel/wildcatpoint/early_smbus.c +++ b/src/southbridge/intel/wildcatpoint/early_smbus.c @@ -6,7 +6,7 @@ #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/smbus.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/romstage.h> static const struct reg_script smbus_init_script[] = { /* Set SMBUS I/O base address */ diff --git a/src/southbridge/intel/wildcatpoint/power_state.c b/src/southbridge/intel/wildcatpoint/power_state.c index 8128458..b9263b4 100644 --- a/src/southbridge/intel/wildcatpoint/power_state.c +++ b/src/southbridge/intel/wildcatpoint/power_state.c @@ -13,7 +13,7 @@ #include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/pm.h> -#include <soc/romstage.h> +#include <northbridge/intel/broadwell/romstage.h> static struct chipset_power_state power_state; -- To view, visit https://review.coreboot.org/c/coreboot/+/41937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia262c8734d59ed5530a9a87bb1cb0b7a86f91708 Gerrit-Change-Number: 41937 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 14

Change in coreboot[master]: southbridge/intel/wildcatpoint: Add header files
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41938 ) Change subject: southbridge/intel/wildcatpoint: Add header files ...................................................................... southbridge/intel/wildcatpoint: Add header files Relocate southbridge-related headers from soc to the southbridge scope. Note that the code in soc/intel/common expects to find `soc/nvs.h`. And yes, some prototypes are now in the wrong place. This will be fixed in the next commits, once the soc/intel/broadwell subfolder is no more. With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical. Change-Id: If2bdef9b44ec8c93c1469074dc51a9964b4101ce Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/broadwell/acpi.c M src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/chip.c M src/cpu/intel/broadwell/cpu.c M src/cpu/intel/broadwell/romstage.c M src/cpu/intel/broadwell/smmrelocate.c M src/mainboard/google/auron/acpi_tables.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/auron/fadt.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/auron/variants/auron_paine/gpio.c M src/mainboard/google/auron/variants/auron_paine/pei_data.c M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/gpio.c M src/mainboard/google/auron/variants/auron_yuna/pei_data.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/buddy/gpio.c M src/mainboard/google/auron/variants/buddy/pei_data.c M src/mainboard/google/auron/variants/buddy/variant.c M src/mainboard/google/auron/variants/gandof/gpio.c M src/mainboard/google/auron/variants/gandof/pei_data.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/gpio.c M src/mainboard/google/auron/variants/lulu/pei_data.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/auron/variants/samus/gpio.c M src/mainboard/google/auron/variants/samus/pei_data.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/auron/variants/samus/variant.c M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/jecht/fadt.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/google/jecht/variants/guado/gpio.c M src/mainboard/google/jecht/variants/guado/pei_data.c M src/mainboard/google/jecht/variants/jecht/gpio.c M src/mainboard/google/jecht/variants/jecht/pei_data.c M src/mainboard/google/jecht/variants/rikku/gpio.c M src/mainboard/google/jecht/variants/rikku/pei_data.c M src/mainboard/google/jecht/variants/tidus/gpio.c M src/mainboard/google/jecht/variants/tidus/pei_data.c M src/mainboard/intel/wtm2/acpi_tables.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/intel/wtm2/fadt.c M src/mainboard/intel/wtm2/gpio.c M src/mainboard/intel/wtm2/pei_data.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/acpi_tables.c M src/mainboard/purism/librem_bdw/fadt.c M src/mainboard/purism/librem_bdw/gpio.c M src/northbridge/intel/broadwell/acpi/broadwell.asl M src/northbridge/intel/broadwell/bootblock.c M src/northbridge/intel/broadwell/broadwell.h M src/northbridge/intel/broadwell/finalize.c M src/northbridge/intel/broadwell/igd.c M src/northbridge/intel/broadwell/memmap.c M src/northbridge/intel/broadwell/minihd.c M src/northbridge/intel/broadwell/pei_data.c M src/northbridge/intel/broadwell/raminit.c M src/northbridge/intel/broadwell/refcode.c M src/northbridge/intel/broadwell/report_platform.c M src/northbridge/intel/broadwell/romstage.c M src/northbridge/intel/broadwell/systemagent.c D src/soc/intel/broadwell/include/soc/cpu.h M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/broadwell/include/soc/systemagent.h R src/southbridge/intel/wildcatpoint/acpi.h M src/southbridge/intel/wildcatpoint/acpi/pch.asl M src/southbridge/intel/wildcatpoint/adsp.c R src/southbridge/intel/wildcatpoint/adsp.h M src/southbridge/intel/wildcatpoint/bootblock.c R src/southbridge/intel/wildcatpoint/device_nvs.h M src/southbridge/intel/wildcatpoint/early_pch.c M src/southbridge/intel/wildcatpoint/early_smbus.c M src/southbridge/intel/wildcatpoint/ehci.c R src/southbridge/intel/wildcatpoint/ehci.h M src/southbridge/intel/wildcatpoint/elog.c M src/southbridge/intel/wildcatpoint/gpio.c R src/southbridge/intel/wildcatpoint/gpio.h M src/southbridge/intel/wildcatpoint/hda.c M src/southbridge/intel/wildcatpoint/iobp.c R src/southbridge/intel/wildcatpoint/iobp.h R src/southbridge/intel/wildcatpoint/iomap.h M src/southbridge/intel/wildcatpoint/lpc.c R src/southbridge/intel/wildcatpoint/lpc.h M src/southbridge/intel/wildcatpoint/me.c R src/southbridge/intel/wildcatpoint/me.h M src/southbridge/intel/wildcatpoint/me_status.c A src/southbridge/intel/wildcatpoint/nvs.h M src/southbridge/intel/wildcatpoint/pch.c R src/southbridge/intel/wildcatpoint/pch.h R src/southbridge/intel/wildcatpoint/pci_devs.h M src/southbridge/intel/wildcatpoint/pcie.c R src/southbridge/intel/wildcatpoint/pm.h M src/southbridge/intel/wildcatpoint/pmutil.c M src/southbridge/intel/wildcatpoint/power_state.c M src/southbridge/intel/wildcatpoint/ramstage.c R src/southbridge/intel/wildcatpoint/ramstage.h R src/southbridge/intel/wildcatpoint/rcba.h M src/southbridge/intel/wildcatpoint/sata.c R src/southbridge/intel/wildcatpoint/sata.h M src/southbridge/intel/wildcatpoint/serialio.c R src/southbridge/intel/wildcatpoint/serialio.h M src/southbridge/intel/wildcatpoint/smbus.c R src/southbridge/intel/wildcatpoint/smbus.h M src/southbridge/intel/wildcatpoint/smi.c M src/southbridge/intel/wildcatpoint/smihandler.c R src/southbridge/intel/wildcatpoint/soc_chip.h R src/southbridge/intel/wildcatpoint/spi.h M src/southbridge/intel/wildcatpoint/uart.c M src/southbridge/intel/wildcatpoint/xhci.c R src/southbridge/intel/wildcatpoint/xhci.h 115 files changed, 280 insertions(+), 279 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/41938/1 diff --git a/src/cpu/intel/broadwell/acpi.c b/src/cpu/intel/broadwell/acpi.c index c052034..bd4eb63 100644 --- a/src/cpu/intel/broadwell/acpi.c +++ b/src/cpu/intel/broadwell/acpi.c @@ -15,14 +15,14 @@ #include <cpu/intel/turbo.h> #include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/gnvs.h> -#include <soc/acpi.h> +#include <southbridge/intel/wildcatpoint/acpi.h> #include <cpu/intel/broadwell/broadwell.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <northbridge/intel/broadwell/broadwell.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> #include <intelblocks/cpulib.h> /* diff --git a/src/cpu/intel/broadwell/bootblock.c b/src/cpu/intel/broadwell/bootblock.c index 3b041fe..3290eee 100644 --- a/src/cpu/intel/broadwell/bootblock.c +++ b/src/cpu/intel/broadwell/bootblock.c @@ -6,7 +6,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <halt.h> -#include <soc/rcba.h> +#include <southbridge/intel/wildcatpoint/rcba.h> #include <cpu/intel/broadwell/broadwell.h> #include <delay.h> diff --git a/src/cpu/intel/broadwell/chip.c b/src/cpu/intel/broadwell/chip.c index 16afcce..443faf4 100644 --- a/src/cpu/intel/broadwell/chip.c +++ b/src/cpu/intel/broadwell/chip.c @@ -2,10 +2,10 @@ #include <device/device.h> #include <device/pci.h> -#include <soc/acpi.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/acpi.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, diff --git a/src/cpu/intel/broadwell/cpu.c b/src/cpu/intel/broadwell/cpu.c index f8189dd..f8132b5 100644 --- a/src/cpu/intel/broadwell/cpu.c +++ b/src/cpu/intel/broadwell/cpu.c @@ -18,11 +18,11 @@ #include <delay.h> #include <intelblocks/cpulib.h> #include <cpu/intel/broadwell/broadwell.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> #include <northbridge/intel/broadwell/broadwell.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> #include <cpu/intel/common/common.h> /* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate diff --git a/src/cpu/intel/broadwell/romstage.c b/src/cpu/intel/broadwell/romstage.c index 03a7e96..35bb592 100644 --- a/src/cpu/intel/broadwell/romstage.c +++ b/src/cpu/intel/broadwell/romstage.c @@ -10,12 +10,12 @@ #include <program_loading.h> #include <romstage_handoff.h> #include <timestamp.h> -#include <soc/gpio.h> -#include <soc/me.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/me.h> #include <northbridge/intel/broadwell/pei_data.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <northbridge/intel/broadwell/romstage.h> -#include <soc/spi.h> +#include <southbridge/intel/wildcatpoint/spi.h> void fill_postcar_frame(struct postcar_frame *pcf) { diff --git a/src/cpu/intel/broadwell/smmrelocate.c b/src/cpu/intel/broadwell/smmrelocate.c index ea38d15..dd96030 100644 --- a/src/cpu/intel/broadwell/smmrelocate.c +++ b/src/cpu/intel/broadwell/smmrelocate.c @@ -15,7 +15,7 @@ #include <console/console.h> #include <smp/node.h> #include <cpu/intel/broadwell/broadwell.h> -#include <soc/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> #include <northbridge/intel/broadwell/broadwell.h> diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c index befe84e..616b51a 100644 --- a/src/mainboard/google/auron/acpi_tables.c +++ b/src/mainboard/google/auron/acpi_tables.c @@ -2,8 +2,8 @@ #include <arch/ioapic.h> #include <acpi/acpi.h> -#include <soc/acpi.h> -#include <soc/nvs.h> +#include <southbridge/intel/wildcatpoint/acpi.h> +#include <southbridge/intel/wildcatpoint/nvs.h> #include <variant/thermal.h> void acpi_create_gnvs(global_nvs_t *gnvs) diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 2827cb1..dbcb25e 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -2,7 +2,7 @@ #include <boot/coreboot_tables.h> #include <vendorcode/google/chromeos/chromeos.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> /* SPI Write protect is GPIO 16 */ #define CROS_WP_GPIO 58 diff --git a/src/mainboard/google/auron/fadt.c b/src/mainboard/google/auron/fadt.c index 653ebb4..e03d31b 100644 --- a/src/mainboard/google/auron/fadt.c +++ b/src/mainboard/google/auron/fadt.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <string.h> -#include <soc/acpi.h> +#include <southbridge/intel/wildcatpoint/acpi.h> #include <version.h> void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index edbd9b6..eff3905 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -4,12 +4,12 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <elog.h> #include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/nvs.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/nvs.h> #include "ec.h" #include <variant/onboard.h> diff --git a/src/mainboard/google/auron/variants/auron_paine/gpio.c b/src/mainboard/google/auron/variants/auron_paine/gpio.c index f2930e0..6a71ece 100644 --- a/src/mainboard/google/auron/variants/auron_paine/gpio.c +++ b/src/mainboard/google/auron/variants/auron_paine/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/auron/variants/auron_paine/pei_data.c b/src/mainboard/google/auron/variants/auron_paine/pei_data.c index 88c1c28..1217e1c 100644 --- a/src/mainboard/google/auron/variants/auron_paine/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_paine/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c index e937651..29f1b67 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c @@ -4,7 +4,7 @@ #include <console/console.h> #include <endian.h> #include <string.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/auron/variants/auron_yuna/gpio.c b/src/mainboard/google/auron/variants/auron_yuna/gpio.c index f2930e0..6a71ece 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/gpio.c +++ b/src/mainboard/google/auron/variants/auron_yuna/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c index 88c1c28..1217e1c 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c index e937651..29f1b67 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c @@ -4,7 +4,7 @@ #include <console/console.h> #include <endian.h> #include <string.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/auron/variants/buddy/gpio.c b/src/mainboard/google/auron/variants/buddy/gpio.c index fcb63a4..8e09897 100644 --- a/src/mainboard/google/auron/variants/buddy/gpio.c +++ b/src/mainboard/google/auron/variants/buddy/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/auron/variants/buddy/pei_data.c b/src/mainboard/google/auron/variants/buddy/pei_data.c index 823c968..5719a58 100644 --- a/src/mainboard/google/auron/variants/buddy/pei_data.c +++ b/src/mainboard/google/auron/variants/buddy/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/auron/variants/buddy/variant.c b/src/mainboard/google/auron/variants/buddy/variant.c index 81bb828..7e5c1fe 100644 --- a/src/mainboard/google/auron/variants/buddy/variant.c +++ b/src/mainboard/google/auron/variants/buddy/variant.c @@ -8,7 +8,7 @@ #include <console/console.h> #include <device/device.h> #include <smbios.h> -#include <soc/pch.h> +#include <southbridge/intel/wildcatpoint/pch.h> #include <variant/onboard.h> #include <mainboard/google/auron/variant.h> diff --git a/src/mainboard/google/auron/variants/gandof/gpio.c b/src/mainboard/google/auron/variants/gandof/gpio.c index 5b7ed82..051d921 100644 --- a/src/mainboard/google/auron/variants/gandof/gpio.c +++ b/src/mainboard/google/auron/variants/gandof/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/auron/variants/gandof/pei_data.c b/src/mainboard/google/auron/variants/gandof/pei_data.c index 88c1c28..1217e1c 100644 --- a/src/mainboard/google/auron/variants/gandof/pei_data.c +++ b/src/mainboard/google/auron/variants/gandof/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c index e937651..29f1b67 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/spd.c +++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c @@ -4,7 +4,7 @@ #include <console/console.h> #include <endian.h> #include <string.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/auron/variants/gandof/variant.c b/src/mainboard/google/auron/variants/gandof/variant.c index bc345da..98f489e 100644 --- a/src/mainboard/google/auron/variants/gandof/variant.c +++ b/src/mainboard/google/auron/variants/gandof/variant.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <ec/google/chromeec/ec.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <smbios.h> #include <northbridge/intel/broadwell/romstage.h> #include <variant/onboard.h> diff --git a/src/mainboard/google/auron/variants/lulu/gpio.c b/src/mainboard/google/auron/variants/lulu/gpio.c index b049bde..aaf865c 100644 --- a/src/mainboard/google/auron/variants/lulu/gpio.c +++ b/src/mainboard/google/auron/variants/lulu/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/auron/variants/lulu/pei_data.c b/src/mainboard/google/auron/variants/lulu/pei_data.c index e88972e..447d0a0 100644 --- a/src/mainboard/google/auron/variants/lulu/pei_data.c +++ b/src/mainboard/google/auron/variants/lulu/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c index 7cf7e66..d4ed494 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/spd.c +++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c @@ -4,7 +4,7 @@ #include <console/console.h> #include <endian.h> #include <string.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/auron/variants/lulu/variant.c b/src/mainboard/google/auron/variants/lulu/variant.c index 98424d8..2d60232 100644 --- a/src/mainboard/google/auron/variants/lulu/variant.c +++ b/src/mainboard/google/auron/variants/lulu/variant.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <ec/google/chromeec/ec.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <smbios.h> #include <northbridge/intel/broadwell/romstage.h> #include <variant/onboard.h> diff --git a/src/mainboard/google/auron/variants/samus/gpio.c b/src/mainboard/google/auron/variants/samus/gpio.c index 12e9e64..1416c46 100644 --- a/src/mainboard/google/auron/variants/samus/gpio.c +++ b/src/mainboard/google/auron/variants/samus/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/auron/variants/samus/pei_data.c b/src/mainboard/google/auron/variants/samus/pei_data.c index eef54d4..bd34d90 100644 --- a/src/mainboard/google/auron/variants/samus/pei_data.c +++ b/src/mainboard/google/auron/variants/samus/pei_data.c @@ -2,7 +2,7 @@ #include <stdint.h> #include <string.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c index 213d4a5..5c45ca9 100644 --- a/src/mainboard/google/auron/variants/samus/spd/spd.c +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -4,7 +4,7 @@ #include <console/console.h> #include <endian.h> #include <string.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/romstage.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/auron/variants/samus/variant.c b/src/mainboard/google/auron/variants/samus/variant.c index baa0d52..2a04a83 100644 --- a/src/mainboard/google/auron/variants/samus/variant.c +++ b/src/mainboard/google/auron/variants/samus/variant.c @@ -2,8 +2,8 @@ #include <console/console.h> #include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <northbridge/intel/broadwell/romstage.h> #include <smbios.h> #include <variant/board_version.h> diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index 50bd1e0..bcf6127 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -5,8 +5,8 @@ #include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <device/device.h> -#include <soc/acpi.h> -#include <soc/nvs.h> +#include <southbridge/intel/wildcatpoint/acpi.h> +#include <southbridge/intel/wildcatpoint/nvs.h> #include <variant/thermal.h> void acpi_create_gnvs(global_nvs_t *gnvs) diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index 86d1e79..23298e7 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -5,8 +5,8 @@ #include <device/device.h> #include <vendorcode/google/chromeos/chromeos.h> #include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/sata.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/sata.h> #include "onboard.h" #define GPIO_SPI_WP 58 diff --git a/src/mainboard/google/jecht/fadt.c b/src/mainboard/google/jecht/fadt.c index 653ebb4..e03d31b 100644 --- a/src/mainboard/google/jecht/fadt.c +++ b/src/mainboard/google/jecht/fadt.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <string.h> -#include <soc/acpi.h> +#include <southbridge/intel/wildcatpoint/acpi.h> #include <version.h> void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c index 3d19f99..b31683f 100644 --- a/src/mainboard/google/jecht/lan.c +++ b/src/mainboard/google/jecht/lan.c @@ -7,7 +7,7 @@ #include <device/pci_ops.h> #include <console/console.h> #include <device/device.h> -#include <soc/pch.h> +#include <southbridge/intel/wildcatpoint/pch.h> #include "onboard.h" static unsigned int search(char *p, u8 *a, unsigned int lengthp, diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c index 7072f8b..f407bcf 100644 --- a/src/mainboard/google/jecht/smihandler.c +++ b/src/mainboard/google/jecht/smihandler.c @@ -3,11 +3,11 @@ #include <acpi/acpi.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/nvs.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/nvs.h> #include "onboard.h" int mainboard_io_trap_handler(int smif) diff --git a/src/mainboard/google/jecht/variants/guado/gpio.c b/src/mainboard/google/jecht/variants/guado/gpio.c index b4ffaa7..d3d44e2 100644 --- a/src/mainboard/google/jecht/variants/guado/gpio.c +++ b/src/mainboard/google/jecht/variants/guado/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/jecht/variants/guado/pei_data.c b/src/mainboard/google/jecht/variants/guado/pei_data.c index 1efb768..d624c83 100644 --- a/src/mainboard/google/jecht/variants/guado/pei_data.c +++ b/src/mainboard/google/jecht/variants/guado/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/jecht/variants/jecht/gpio.c b/src/mainboard/google/jecht/variants/jecht/gpio.c index 92470cd..4aee5df 100644 --- a/src/mainboard/google/jecht/variants/jecht/gpio.c +++ b/src/mainboard/google/jecht/variants/jecht/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/jecht/variants/jecht/pei_data.c b/src/mainboard/google/jecht/variants/jecht/pei_data.c index 1efb768..d624c83 100644 --- a/src/mainboard/google/jecht/variants/jecht/pei_data.c +++ b/src/mainboard/google/jecht/variants/jecht/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/jecht/variants/rikku/gpio.c b/src/mainboard/google/jecht/variants/rikku/gpio.c index b4ffaa7..d3d44e2 100644 --- a/src/mainboard/google/jecht/variants/rikku/gpio.c +++ b/src/mainboard/google/jecht/variants/rikku/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/jecht/variants/rikku/pei_data.c b/src/mainboard/google/jecht/variants/rikku/pei_data.c index 1efb768..d624c83 100644 --- a/src/mainboard/google/jecht/variants/rikku/pei_data.c +++ b/src/mainboard/google/jecht/variants/rikku/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/jecht/variants/tidus/gpio.c b/src/mainboard/google/jecht/variants/tidus/gpio.c index 805b617..9c3d934 100644 --- a/src/mainboard/google/jecht/variants/tidus/gpio.c +++ b/src/mainboard/google/jecht/variants/tidus/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/jecht/variants/tidus/pei_data.c b/src/mainboard/google/jecht/variants/tidus/pei_data.c index 6af5d83..35dc2e7 100644 --- a/src/mainboard/google/jecht/variants/tidus/pei_data.c +++ b/src/mainboard/google/jecht/variants/tidus/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 960dbde..b601ea3 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -5,8 +5,8 @@ #include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <device/device.h> -#include <soc/acpi.h> -#include <soc/nvs.h> +#include <southbridge/intel/wildcatpoint/acpi.h> +#include <southbridge/intel/wildcatpoint/nvs.h> #include "thermal.h" void acpi_create_gnvs(global_nvs_t *gnvs) diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 459560c..c4470c6 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -3,7 +3,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <device/device.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> /* Compile-time settings for recovery mode. */ diff --git a/src/mainboard/intel/wtm2/fadt.c b/src/mainboard/intel/wtm2/fadt.c index 77231e2..b85eba74 100644 --- a/src/mainboard/intel/wtm2/fadt.c +++ b/src/mainboard/intel/wtm2/fadt.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <string.h> -#include <soc/acpi.h> +#include <southbridge/intel/wildcatpoint/acpi.h> #include <version.h> void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) diff --git a/src/mainboard/intel/wtm2/gpio.c b/src/mainboard/intel/wtm2/gpio.c index c779ef0..868e58e 100644 --- a/src/mainboard/intel/wtm2/gpio.c +++ b/src/mainboard/intel/wtm2/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_NATIVE, /* 0: LPSS_UART1_RXD */ diff --git a/src/mainboard/intel/wtm2/pei_data.c b/src/mainboard/intel/wtm2/pei_data.c index bcf091a..8795cf3 100644 --- a/src/mainboard/intel/wtm2/pei_data.c +++ b/src/mainboard/intel/wtm2/pei_data.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index 9fc63cf..cc8e8e4 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> #include <northbridge/intel/broadwell/romstage.h> diff --git a/src/mainboard/purism/librem_bdw/acpi_tables.c b/src/mainboard/purism/librem_bdw/acpi_tables.c index 8383f63..8b719bd 100644 --- a/src/mainboard/purism/librem_bdw/acpi_tables.c +++ b/src/mainboard/purism/librem_bdw/acpi_tables.c @@ -2,8 +2,8 @@ #include <acpi/acpi.h> #include <arch/ioapic.h> -#include <soc/acpi.h> -#include <soc/nvs.h> +#include <southbridge/intel/wildcatpoint/acpi.h> +#include <southbridge/intel/wildcatpoint/nvs.h> void acpi_create_gnvs(global_nvs_t *gnvs) { diff --git a/src/mainboard/purism/librem_bdw/fadt.c b/src/mainboard/purism/librem_bdw/fadt.c index b756fb9..10c9b78 100644 --- a/src/mainboard/purism/librem_bdw/fadt.c +++ b/src/mainboard/purism/librem_bdw/fadt.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <string.h> -#include <soc/acpi.h> +#include <southbridge/intel/wildcatpoint/acpi.h> #include <version.h> void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) diff --git a/src/mainboard/purism/librem_bdw/gpio.c b/src/mainboard/purism/librem_bdw/gpio.c index 57afe56..555b069 100644 --- a/src/mainboard/purism/librem_bdw/gpio.c +++ b/src/mainboard/purism/librem_bdw/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_INPUT, /* 0 */ diff --git a/src/northbridge/intel/broadwell/acpi/broadwell.asl b/src/northbridge/intel/broadwell/acpi/broadwell.asl index 258e6e7..12296cb 100644 --- a/src/northbridge/intel/broadwell/acpi/broadwell.asl +++ b/src/northbridge/intel/broadwell/acpi/broadwell.asl @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/iomap.h> +#include <southbridge/intel/wildcatpoint/iomap.h> Name (_HID, EISAID ("PNP0A08")) // PCIe Name (_CID, EISAID ("PNP0A03")) // PCI diff --git a/src/northbridge/intel/broadwell/bootblock.c b/src/northbridge/intel/broadwell/bootblock.c index be389b7..89ff992 100644 --- a/src/northbridge/intel/broadwell/bootblock.c +++ b/src/northbridge/intel/broadwell/bootblock.c @@ -2,7 +2,7 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> -#include <soc/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> #include <northbridge/intel/broadwell/broadwell.h> void bootblock_early_northbridge_init(void) diff --git a/src/northbridge/intel/broadwell/broadwell.h b/src/northbridge/intel/broadwell/broadwell.h index 8d71103..5f4ad6c 100644 --- a/src/northbridge/intel/broadwell/broadwell.h +++ b/src/northbridge/intel/broadwell/broadwell.h @@ -3,7 +3,7 @@ #ifndef __NORTHBRIDGE_INTEL_BROADWELL_BROADWELL_H__ #define __NORTHBRIDGE_INTEL_BROADWELL_BROADWELL_H__ -#include <soc/iomap.h> +#include <southbridge/intel/wildcatpoint/iomap.h> #define SA_IGD_OPROM_VENDEV 0x80860406 diff --git a/src/northbridge/intel/broadwell/finalize.c b/src/northbridge/intel/broadwell/finalize.c index d258694..ccd3e74 100644 --- a/src/northbridge/intel/broadwell/finalize.c +++ b/src/northbridge/intel/broadwell/finalize.c @@ -6,11 +6,11 @@ #include <cpu/x86/smm.h> #include <reg_script.h> #include <spi-generic.h> -#include <soc/pci_devs.h> -#include <soc/lpc.h> -#include <soc/me.h> -#include <soc/rcba.h> -#include <soc/spi.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/me.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/spi.h> #include <northbridge/intel/broadwell/broadwell.h> #include <southbridge/intel/common/spi.h> diff --git a/src/northbridge/intel/broadwell/igd.c b/src/northbridge/intel/broadwell/igd.c index 3e47b53..6c0da56 100644 --- a/src/northbridge/intel/broadwell/igd.c +++ b/src/northbridge/intel/broadwell/igd.c @@ -16,10 +16,10 @@ #include <drivers/intel/gma/libgfxinit.h> #include <drivers/intel/gma/opregion.h> #include <cpu/intel/broadwell/broadwell.h> -#include <soc/pm.h> -#include <soc/ramstage.h> +#include <southbridge/intel/wildcatpoint/pm.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> #include <northbridge/intel/broadwell/broadwell.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> #include <security/vboot/vbnv.h> #include <northbridge/intel/broadwell/igd.h> #include <types.h> diff --git a/src/northbridge/intel/broadwell/memmap.c b/src/northbridge/intel/broadwell/memmap.c index c062d7d..ca8b105 100644 --- a/src/northbridge/intel/broadwell/memmap.c +++ b/src/northbridge/intel/broadwell/memmap.c @@ -6,7 +6,7 @@ #include <cpu/x86/smm.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <soc/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> #include <northbridge/intel/broadwell/broadwell.h> #include <stdint.h> diff --git a/src/northbridge/intel/broadwell/minihd.c b/src/northbridge/intel/broadwell/minihd.c index db15dbb..7a93b9a 100644 --- a/src/northbridge/intel/broadwell/minihd.c +++ b/src/northbridge/intel/broadwell/minihd.c @@ -7,7 +7,7 @@ #include <device/pci_ops.h> #include <device/mmio.h> #include <soc/intel/common/hda_verb.h> -#include <soc/ramstage.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> #include <northbridge/intel/broadwell/igd.h> static const u32 minihd_verb_table[] = { diff --git a/src/northbridge/intel/broadwell/pei_data.c b/src/northbridge/intel/broadwell/pei_data.c index 41fc475..56166eb 100644 --- a/src/northbridge/intel/broadwell/pei_data.c +++ b/src/northbridge/intel/broadwell/pei_data.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/streams.h> -#include <soc/iomap.h> +#include <southbridge/intel/wildcatpoint/iomap.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> diff --git a/src/northbridge/intel/broadwell/raminit.c b/src/northbridge/intel/broadwell/raminit.c index dca56b6..d40c2a3 100644 --- a/src/northbridge/intel/broadwell/raminit.c +++ b/src/northbridge/intel/broadwell/raminit.c @@ -14,10 +14,10 @@ #include <ec/google/chromeec/ec_commands.h> #endif #include <vendorcode/google/chromeos/chromeos.h> -#include <soc/iomap.h> +#include <southbridge/intel/wildcatpoint/iomap.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <northbridge/intel/broadwell/romstage.h> #include <northbridge/intel/broadwell/broadwell.h> diff --git a/src/northbridge/intel/broadwell/refcode.c b/src/northbridge/intel/broadwell/refcode.c index 5ba43cd..13be8b6 100644 --- a/src/northbridge/intel/broadwell/refcode.c +++ b/src/northbridge/intel/broadwell/refcode.c @@ -11,8 +11,8 @@ #include <stage_cache.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> -#include <soc/pm.h> -#include <soc/ramstage.h> +#include <southbridge/intel/wildcatpoint/pm.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> static pei_wrapper_entry_t load_refcode_from_cache(void) { diff --git a/src/northbridge/intel/broadwell/report_platform.c b/src/northbridge/intel/broadwell/report_platform.c index 1012ce2..3ac4ece 100644 --- a/src/northbridge/intel/broadwell/report_platform.c +++ b/src/northbridge/intel/broadwell/report_platform.c @@ -7,8 +7,8 @@ #include <string.h> #include <cpu/x86/msr.h> #include <cpu/intel/broadwell/broadwell.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> #include <northbridge/intel/broadwell/romstage.h> #include <northbridge/intel/broadwell/broadwell.h> diff --git a/src/northbridge/intel/broadwell/romstage.c b/src/northbridge/intel/broadwell/romstage.c index efc26d9..064c203 100644 --- a/src/northbridge/intel/broadwell/romstage.c +++ b/src/northbridge/intel/broadwell/romstage.c @@ -4,8 +4,8 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <reg_script.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> #include <northbridge/intel/broadwell/romstage.h> #include <northbridge/intel/broadwell/broadwell.h> diff --git a/src/northbridge/intel/broadwell/systemagent.c b/src/northbridge/intel/broadwell/systemagent.c index 15110da..67d78cf 100644 --- a/src/northbridge/intel/broadwell/systemagent.c +++ b/src/northbridge/intel/broadwell/systemagent.c @@ -10,10 +10,10 @@ #include <device/pci_ids.h> #include <intelblocks/power_limit.h> #include <vendorcode/google/chromeos/chromeos.h> -#include <soc/cpu.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> +#include <cpu/intel/broadwell/broadwell.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> #include <northbridge/intel/broadwell/broadwell.h> u8 systemagent_revision(void) diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h deleted file mode 100644 index e69de29..0000000 --- a/src/soc/intel/broadwell/include/soc/cpu.h +++ /dev/null diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 8772a02..56dd799 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -1,56 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _BROADWELL_NVS_H_ -#define _BROADWELL_NVS_H_ - -#include <commonlib/helpers.h> -#include <soc/device_nvs.h> -#include <vendorcode/google/chromeos/gnvs.h> - -typedef struct global_nvs_t { - /* Miscellaneous */ - u16 osys; /* 0x00 - Operating System */ - u8 smif; /* 0x02 - SMI function call ("TRAP") */ - u8 prm0; /* 0x03 - SMI function call parameter */ - u8 prm1; /* 0x04 - SMI function call parameter */ - u8 scif; /* 0x05 - SCI function call (via _L00) */ - u8 prm2; /* 0x06 - SCI function call parameter */ - u8 prm3; /* 0x07 - SCI function call parameter */ - u8 lckf; /* 0x08 - Global Lock function for EC */ - u8 prm4; /* 0x09 - Lock function parameter */ - u8 prm5; /* 0x0a - Lock function parameter */ - u8 pcnt; /* 0x0b - Processor Count */ - u8 ppcm; /* 0x0c - Max PPC State */ - u8 tmps; /* 0x0d - Temperature Sensor ID */ - u8 tlvl; /* 0x0e - Throttle Level Limit */ - u8 flvl; /* 0x0f - Current FAN Level */ - u8 tcrt; /* 0x10 - Critical Threshold */ - u8 tpsv; /* 0x11 - Passive Threshold */ - u8 tmax; /* 0x12 - CPU Tj_max */ - u8 s5u0; /* 0x13 - Enable USB in S5 */ - u8 s3u0; /* 0x14 - Enable USB in S3 */ - u8 s33g; /* 0x15 - Enable 3G in S3 */ - u8 lids; /* 0x16 - LID State */ - u8 pwrs; /* 0x17 - AC Power State */ - u32 cmem; /* 0x18 - 0x1b - CBMEM TOC */ - u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */ - u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ - u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ - u8 unused1[132]; /* 0x30 - 0xb3 - unused */ - - u8 unused2[76]; - - /* ChromeOS specific (0x100 - 0xfff) */ - chromeos_acpi_t chromeos; - - /* Device specific (0x1000) */ - device_nvs_t dev; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - -void acpi_create_gnvs(global_nvs_t *gnvs); - -/* Used in SMM to find the ACPI GNVS address */ -global_nvs_t *smm_get_gnvs(void); - -#endif +#include <southbridge/intel/wildcatpoint/nvs.h> diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index 5c93352..8b6d4f3 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -3,7 +3,7 @@ #ifndef _BROADWELL_SYSTEMAGENT_H_ #define _BROADWELL_SYSTEMAGENT_H_ -#include <soc/iomap.h> +#include <southbridge/intel/wildcatpoint/iomap.h> #define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + x)) diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/southbridge/intel/wildcatpoint/acpi.h similarity index 91% rename from src/soc/intel/broadwell/include/soc/acpi.h rename to src/southbridge/intel/wildcatpoint/acpi.h index 66ad450..618b627 100644 --- a/src/soc/intel/broadwell/include/soc/acpi.h +++ b/src/southbridge/intel/wildcatpoint/acpi.h @@ -4,7 +4,7 @@ #define _BROADWELL_ACPI_H_ #include <acpi/acpi.h> -#include <soc/nvs.h> +#include <southbridge/intel/wildcatpoint/nvs.h> /* P-state configuration */ #define PSS_MAX_ENTRIES 8 diff --git a/src/southbridge/intel/wildcatpoint/acpi/pch.asl b/src/southbridge/intel/wildcatpoint/acpi/pch.asl index 07db9f7..540d262 100644 --- a/src/southbridge/intel/wildcatpoint/acpi/pch.asl +++ b/src/southbridge/intel/wildcatpoint/acpi/pch.asl @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/iomap.h> - Scope (\) { // IO-Trap at 0x800. This is the ACPI->SMI communication interface. diff --git a/src/southbridge/intel/wildcatpoint/adsp.c b/src/southbridge/intel/wildcatpoint/adsp.c index b8699a2..925b1b7 100644 --- a/src/southbridge/intel/wildcatpoint/adsp.c +++ b/src/southbridge/intel/wildcatpoint/adsp.c @@ -7,14 +7,14 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/mmio.h> -#include <soc/adsp.h> -#include <soc/device_nvs.h> -#include <soc/iobp.h> -#include <soc/nvs.h> -#include <soc/pch.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/adsp.h> +#include <southbridge/intel/wildcatpoint/device_nvs.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/nvs.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> static void adsp_init(struct device *dev) { diff --git a/src/soc/intel/broadwell/include/soc/adsp.h b/src/southbridge/intel/wildcatpoint/adsp.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/adsp.h rename to src/southbridge/intel/wildcatpoint/adsp.h diff --git a/src/southbridge/intel/wildcatpoint/bootblock.c b/src/southbridge/intel/wildcatpoint/bootblock.c index 61af770..572ea09 100644 --- a/src/southbridge/intel/wildcatpoint/bootblock.c +++ b/src/southbridge/intel/wildcatpoint/bootblock.c @@ -2,13 +2,13 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/rcba.h> -#include <soc/spi.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/spi.h> #include <reg_script.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <northbridge/intel/broadwell/romstage.h> /* diff --git a/src/soc/intel/broadwell/include/soc/device_nvs.h b/src/southbridge/intel/wildcatpoint/device_nvs.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/device_nvs.h rename to src/southbridge/intel/wildcatpoint/device_nvs.h diff --git a/src/southbridge/intel/wildcatpoint/early_pch.c b/src/southbridge/intel/wildcatpoint/early_pch.c index 9b73760..e8cb8aa 100644 --- a/src/southbridge/intel/wildcatpoint/early_pch.c +++ b/src/southbridge/intel/wildcatpoint/early_pch.c @@ -5,15 +5,15 @@ #include <device/pci_ops.h> #include <device/smbus_host.h> #include <reg_script.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/rcba.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pm.h> +#include <southbridge/intel/wildcatpoint/rcba.h> #include <northbridge/intel/broadwell/romstage.h> -#include <soc/smbus.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/smbus.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> const struct reg_script pch_interrupt_init_script[] = { /* diff --git a/src/southbridge/intel/wildcatpoint/early_smbus.c b/src/southbridge/intel/wildcatpoint/early_smbus.c index 5da5f4e..6f4d226 100644 --- a/src/southbridge/intel/wildcatpoint/early_smbus.c +++ b/src/southbridge/intel/wildcatpoint/early_smbus.c @@ -3,9 +3,9 @@ #include <device/pci_def.h> #include <device/smbus_host.h> #include <reg_script.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/smbus.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/smbus.h> #include <northbridge/intel/broadwell/romstage.h> static const struct reg_script smbus_init_script[] = { diff --git a/src/southbridge/intel/wildcatpoint/ehci.c b/src/southbridge/intel/wildcatpoint/ehci.c index 5b977dd..81ad62d 100644 --- a/src/southbridge/intel/wildcatpoint/ehci.c +++ b/src/southbridge/intel/wildcatpoint/ehci.c @@ -5,8 +5,8 @@ #include <device/pci_ids.h> #include <device/pci_ehci.h> #include <device/pci_ops.h> -#include <soc/ehci.h> -#include <soc/pch.h> +#include <southbridge/intel/wildcatpoint/ehci.h> +#include <southbridge/intel/wildcatpoint/pch.h> static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) diff --git a/src/soc/intel/broadwell/include/soc/ehci.h b/src/southbridge/intel/wildcatpoint/ehci.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/ehci.h rename to src/southbridge/intel/wildcatpoint/ehci.h diff --git a/src/southbridge/intel/wildcatpoint/elog.c b/src/southbridge/intel/wildcatpoint/elog.c index f918958..6e39cd0 100644 --- a/src/southbridge/intel/wildcatpoint/elog.c +++ b/src/southbridge/intel/wildcatpoint/elog.c @@ -5,8 +5,8 @@ #include <console/console.h> #include <stdint.h> #include <elog.h> -#include <soc/lpc.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/pm.h> static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { diff --git a/src/southbridge/intel/wildcatpoint/gpio.c b/src/southbridge/intel/wildcatpoint/gpio.c index ff1f019..62a7335 100644 --- a/src/southbridge/intel/wildcatpoint/gpio.c +++ b/src/southbridge/intel/wildcatpoint/gpio.c @@ -4,9 +4,9 @@ #include <arch/io.h> #include <device/device.h> #include <device/pci.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/pm.h> /* * This function will return a number that indicates which PIRQ diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/southbridge/intel/wildcatpoint/gpio.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/gpio.h rename to src/southbridge/intel/wildcatpoint/gpio.h diff --git a/src/southbridge/intel/wildcatpoint/hda.c b/src/southbridge/intel/wildcatpoint/hda.c index 1640825..0dbe6cd 100644 --- a/src/southbridge/intel/wildcatpoint/hda.c +++ b/src/southbridge/intel/wildcatpoint/hda.c @@ -8,9 +8,9 @@ #include <device/pci_ops.h> #include <device/mmio.h> #include <soc/intel/common/hda_verb.h> -#include <soc/pch.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> static void codecs_init(u8 *base, u32 codec_mask) { diff --git a/src/southbridge/intel/wildcatpoint/iobp.c b/src/southbridge/intel/wildcatpoint/iobp.c index 76a3e58..3332e26 100644 --- a/src/southbridge/intel/wildcatpoint/iobp.c +++ b/src/southbridge/intel/wildcatpoint/iobp.c @@ -2,8 +2,8 @@ #include <console/console.h> #include <delay.h> -#include <soc/iobp.h> -#include <soc/rcba.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/rcba.h> #define IOBP_RETRY 1000 diff --git a/src/soc/intel/broadwell/include/soc/iobp.h b/src/southbridge/intel/wildcatpoint/iobp.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/iobp.h rename to src/southbridge/intel/wildcatpoint/iobp.h diff --git a/src/soc/intel/broadwell/include/soc/iomap.h b/src/southbridge/intel/wildcatpoint/iomap.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/iomap.h rename to src/southbridge/intel/wildcatpoint/iomap.h diff --git a/src/southbridge/intel/wildcatpoint/lpc.c b/src/southbridge/intel/wildcatpoint/lpc.c index 5cfeb5f..b7f1fe3 100644 --- a/src/southbridge/intel/wildcatpoint/lpc.c +++ b/src/southbridge/intel/wildcatpoint/lpc.c @@ -15,17 +15,17 @@ #include <cbmem.h> #include <reg_script.h> #include <string.h> -#include <soc/gpio.h> -#include <soc/iobp.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/nvs.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/nvs.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pm.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> #include <acpi/acpigen.h> #include <southbridge/intel/common/rtc.h> diff --git a/src/soc/intel/broadwell/include/soc/lpc.h b/src/southbridge/intel/wildcatpoint/lpc.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/lpc.h rename to src/southbridge/intel/wildcatpoint/lpc.h diff --git a/src/southbridge/intel/wildcatpoint/me.c b/src/southbridge/intel/wildcatpoint/me.c index 7449902..3b1998e 100644 --- a/src/southbridge/intel/wildcatpoint/me.c +++ b/src/southbridge/intel/wildcatpoint/me.c @@ -20,13 +20,13 @@ #include <string.h> #include <delay.h> #include <elog.h> -#include <soc/me.h> -#include <soc/lpc.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/me.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> #if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/southbridge/intel/wildcatpoint/me.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/me.h rename to src/southbridge/intel/wildcatpoint/me.h diff --git a/src/southbridge/intel/wildcatpoint/me_status.c b/src/southbridge/intel/wildcatpoint/me_status.c index 11b21ac..d11b26c 100644 --- a/src/southbridge/intel/wildcatpoint/me_status.c +++ b/src/southbridge/intel/wildcatpoint/me_status.c @@ -4,8 +4,8 @@ #include <console/console.h> #include <device/pci.h> #include <string.h> -#include <soc/pci_devs.h> -#include <soc/me.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/me.h> #include <delay.h> #define ARRAY_TO_ELEMENT(__array__, __index__, __default__) \ diff --git a/src/southbridge/intel/wildcatpoint/nvs.h b/src/southbridge/intel/wildcatpoint/nvs.h new file mode 100644 index 0000000..b5fca62 --- /dev/null +++ b/src/southbridge/intel/wildcatpoint/nvs.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _BROADWELL_NVS_H_ +#define _BROADWELL_NVS_H_ + +#include <commonlib/helpers.h> +#include <southbridge/intel/wildcatpoint/device_nvs.h> +#include <vendorcode/google/chromeos/gnvs.h> + +typedef struct global_nvs_t { + /* Miscellaneous */ + u16 osys; /* 0x00 - Operating System */ + u8 smif; /* 0x02 - SMI function call ("TRAP") */ + u8 prm0; /* 0x03 - SMI function call parameter */ + u8 prm1; /* 0x04 - SMI function call parameter */ + u8 scif; /* 0x05 - SCI function call (via _L00) */ + u8 prm2; /* 0x06 - SCI function call parameter */ + u8 prm3; /* 0x07 - SCI function call parameter */ + u8 lckf; /* 0x08 - Global Lock function for EC */ + u8 prm4; /* 0x09 - Lock function parameter */ + u8 prm5; /* 0x0a - Lock function parameter */ + u8 pcnt; /* 0x0b - Processor Count */ + u8 ppcm; /* 0x0c - Max PPC State */ + u8 tmps; /* 0x0d - Temperature Sensor ID */ + u8 tlvl; /* 0x0e - Throttle Level Limit */ + u8 flvl; /* 0x0f - Current FAN Level */ + u8 tcrt; /* 0x10 - Critical Threshold */ + u8 tpsv; /* 0x11 - Passive Threshold */ + u8 tmax; /* 0x12 - CPU Tj_max */ + u8 s5u0; /* 0x13 - Enable USB in S5 */ + u8 s3u0; /* 0x14 - Enable USB in S3 */ + u8 s33g; /* 0x15 - Enable 3G in S3 */ + u8 lids; /* 0x16 - LID State */ + u8 pwrs; /* 0x17 - AC Power State */ + u32 cmem; /* 0x18 - 0x1b - CBMEM TOC */ + u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */ + u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ + u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ + u8 unused1[132]; /* 0x30 - 0xb3 - unused */ + + u8 unused2[76]; + + /* ChromeOS specific (0x100 - 0xfff) */ + chromeos_acpi_t chromeos; + + /* Device specific (0x1000) */ + device_nvs_t dev; +} __packed global_nvs_t; +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); + +void acpi_create_gnvs(global_nvs_t *gnvs); + +/* Used in SMM to find the ACPI GNVS address */ +global_nvs_t *smm_get_gnvs(void); + +#endif diff --git a/src/southbridge/intel/wildcatpoint/pch.c b/src/southbridge/intel/wildcatpoint/pch.c index 479323d..1ac2967 100644 --- a/src/southbridge/intel/wildcatpoint/pch.c +++ b/src/southbridge/intel/wildcatpoint/pch.c @@ -5,13 +5,13 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> -#include <soc/iobp.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> -#include <soc/serialio.h> -#include <soc/spi.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/serialio.h> +#include <southbridge/intel/wildcatpoint/spi.h> u8 pch_revision(void) { diff --git a/src/soc/intel/broadwell/include/soc/pch.h b/src/southbridge/intel/wildcatpoint/pch.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/pch.h rename to src/southbridge/intel/wildcatpoint/pch.h diff --git a/src/soc/intel/broadwell/include/soc/pci_devs.h b/src/southbridge/intel/wildcatpoint/pci_devs.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/pci_devs.h rename to src/southbridge/intel/wildcatpoint/pci_devs.h diff --git a/src/southbridge/intel/wildcatpoint/pcie.c b/src/southbridge/intel/wildcatpoint/pcie.c index 2ec714f..4515ffb 100644 --- a/src/southbridge/intel/wildcatpoint/pcie.c +++ b/src/southbridge/intel/wildcatpoint/pcie.c @@ -7,13 +7,13 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <soc/gpio.h> -#include <soc/lpc.h> -#include <soc/iobp.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> -#include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/gpio.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> #include <cpu/intel/broadwell/broadwell.h> #include <delay.h> diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/southbridge/intel/wildcatpoint/pm.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/pm.h rename to src/southbridge/intel/wildcatpoint/pm.h diff --git a/src/southbridge/intel/wildcatpoint/pmutil.c b/src/southbridge/intel/wildcatpoint/pmutil.c index 502a046..b66fb87 100644 --- a/src/southbridge/intel/wildcatpoint/pmutil.c +++ b/src/southbridge/intel/wildcatpoint/pmutil.c @@ -13,11 +13,11 @@ #include <device/pci.h> #include <device/pci_def.h> #include <console/console.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/gpio.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pm.h> +#include <southbridge/intel/wildcatpoint/gpio.h> #include <security/vboot/vbnv.h> /* Print status bits with descriptive names */ diff --git a/src/southbridge/intel/wildcatpoint/power_state.c b/src/southbridge/intel/wildcatpoint/power_state.c index b9263b4..8522caa 100644 --- a/src/southbridge/intel/wildcatpoint/power_state.c +++ b/src/southbridge/intel/wildcatpoint/power_state.c @@ -9,10 +9,10 @@ #include <device/pci_def.h> #include <reg_script.h> #include <string.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <northbridge/intel/broadwell/romstage.h> static struct chipset_power_state power_state; diff --git a/src/southbridge/intel/wildcatpoint/ramstage.c b/src/southbridge/intel/wildcatpoint/ramstage.c index 39550b7..8859261 100644 --- a/src/southbridge/intel/wildcatpoint/ramstage.c +++ b/src/southbridge/intel/wildcatpoint/ramstage.c @@ -4,10 +4,10 @@ #include <cbmem.h> #include <device/device.h> #include <string.h> -#include <soc/nvs.h> -#include <soc/pm.h> -#include <soc/ramstage.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/nvs.h> +#include <southbridge/intel/wildcatpoint/pm.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> #include <soc/intel/common/acpi.h> #include <assert.h> diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/southbridge/intel/wildcatpoint/ramstage.h similarity index 89% rename from src/soc/intel/broadwell/include/soc/ramstage.h rename to src/southbridge/intel/wildcatpoint/ramstage.h index 18a23e1..b50cd19 100644 --- a/src/soc/intel/broadwell/include/soc/ramstage.h +++ b/src/southbridge/intel/wildcatpoint/ramstage.h @@ -4,7 +4,7 @@ #define _BROADWELL_RAMSTAGE_H_ #include <device/device.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> void broadwell_init_pre_device(void *chip_info); void broadwell_init_cpus(struct device *dev); diff --git a/src/soc/intel/broadwell/include/soc/rcba.h b/src/southbridge/intel/wildcatpoint/rcba.h similarity index 98% rename from src/soc/intel/broadwell/include/soc/rcba.h rename to src/southbridge/intel/wildcatpoint/rcba.h index 3bacb9d..9d06992 100644 --- a/src/soc/intel/broadwell/include/soc/rcba.h +++ b/src/southbridge/intel/wildcatpoint/rcba.h @@ -3,7 +3,7 @@ #ifndef _BROADWELL_RCBA_H_ #define _BROADWELL_RCBA_H_ -#include <soc/iomap.h> +#include <southbridge/intel/wildcatpoint/iomap.h> #define RCBA8(x) *((volatile u8 *)(RCBA_BASE_ADDRESS + x)) #define RCBA16(x) *((volatile u16 *)(RCBA_BASE_ADDRESS + x)) diff --git a/src/southbridge/intel/wildcatpoint/sata.c b/src/southbridge/intel/wildcatpoint/sata.c index 5ddccc5..502d586 100644 --- a/src/southbridge/intel/wildcatpoint/sata.c +++ b/src/southbridge/intel/wildcatpoint/sata.c @@ -7,11 +7,11 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <delay.h> -#include <soc/iobp.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> -#include <soc/sata.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/sata.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> static inline u32 sir_read(struct device *dev, int idx) { diff --git a/src/soc/intel/broadwell/include/soc/sata.h b/src/southbridge/intel/wildcatpoint/sata.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/sata.h rename to src/southbridge/intel/wildcatpoint/sata.h diff --git a/src/southbridge/intel/wildcatpoint/serialio.c b/src/southbridge/intel/wildcatpoint/serialio.c index 20a5d9a..3dbbc6e 100644 --- a/src/southbridge/intel/wildcatpoint/serialio.c +++ b/src/southbridge/intel/wildcatpoint/serialio.c @@ -7,14 +7,14 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <soc/iobp.h> -#include <soc/nvs.h> -#include <soc/pci_devs.h> -#include <soc/pch.h> -#include <soc/ramstage.h> -#include <soc/rcba.h> -#include <soc/serialio.h> -#include <soc/intel/broadwell/chip.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/nvs.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/serialio.h> +#include <southbridge/intel/wildcatpoint/soc_chip.h> /* Set D3Hot Power State in ACPI mode */ static void serialio_enable_d3hot(struct resource *res) diff --git a/src/soc/intel/broadwell/include/soc/serialio.h b/src/southbridge/intel/wildcatpoint/serialio.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/serialio.h rename to src/southbridge/intel/wildcatpoint/serialio.h diff --git a/src/southbridge/intel/wildcatpoint/smbus.c b/src/southbridge/intel/wildcatpoint/smbus.c index 562db4e..b8177e5 100644 --- a/src/southbridge/intel/wildcatpoint/smbus.c +++ b/src/southbridge/intel/wildcatpoint/smbus.c @@ -7,9 +7,9 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <soc/iomap.h> -#include <soc/ramstage.h> -#include <soc/smbus.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/smbus.h> #include <device/smbus_host.h> static void pch_smbus_init(struct device *dev) diff --git a/src/soc/intel/broadwell/include/soc/smbus.h b/src/southbridge/intel/wildcatpoint/smbus.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/smbus.h rename to src/southbridge/intel/wildcatpoint/smbus.h diff --git a/src/southbridge/intel/wildcatpoint/smi.c b/src/southbridge/intel/wildcatpoint/smi.c index 1d3860a..1dc8b59 100644 --- a/src/southbridge/intel/wildcatpoint/smi.c +++ b/src/southbridge/intel/wildcatpoint/smi.c @@ -6,9 +6,9 @@ #include <arch/io.h> #include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> -#include <soc/iomap.h> -#include <soc/pch.h> -#include <soc/pm.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pm.h> void smm_southbridge_clear_state(void) { diff --git a/src/southbridge/intel/wildcatpoint/smihandler.c b/src/southbridge/intel/wildcatpoint/smihandler.c index 85d6ae0..98e26ca 100644 --- a/src/southbridge/intel/wildcatpoint/smihandler.c +++ b/src/southbridge/intel/wildcatpoint/smihandler.c @@ -14,12 +14,12 @@ #include <elog.h> #include <halt.h> #include <option.h> -#include <soc/lpc.h> -#include <soc/nvs.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/rcba.h> -#include <soc/xhci.h> +#include <southbridge/intel/wildcatpoint/lpc.h> +#include <southbridge/intel/wildcatpoint/nvs.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pm.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#include <southbridge/intel/wildcatpoint/xhci.h> #include <drivers/intel/gma/i915_reg.h> #include <smmstore.h> diff --git a/src/soc/intel/broadwell/include/soc/soc_chip.h b/src/southbridge/intel/wildcatpoint/soc_chip.h similarity index 80% rename from src/soc/intel/broadwell/include/soc/soc_chip.h rename to src/southbridge/intel/wildcatpoint/soc_chip.h index bbd556e..c59f562 100644 --- a/src/soc/intel/broadwell/include/soc/soc_chip.h +++ b/src/southbridge/intel/wildcatpoint/soc_chip.h @@ -3,6 +3,6 @@ #ifndef _SOC_BROADWELL_SOC_CHIP_H_ #define _SOC_BROADWELL_SOC_CHIP_H_ -#include "../../chip.h" +#include <soc/intel/broadwell/chip.h> #endif /* _SOC_BROADWELL_SOC_CHIP_H_ */ diff --git a/src/soc/intel/broadwell/include/soc/spi.h b/src/southbridge/intel/wildcatpoint/spi.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/spi.h rename to src/southbridge/intel/wildcatpoint/spi.h diff --git a/src/southbridge/intel/wildcatpoint/uart.c b/src/southbridge/intel/wildcatpoint/uart.c index 6b0da2d..8d3e7a7 100644 --- a/src/southbridge/intel/wildcatpoint/uart.c +++ b/src/southbridge/intel/wildcatpoint/uart.c @@ -4,8 +4,8 @@ #include <reg_script.h> #include <stdint.h> #include <uart8250.h> -#include <soc/iobp.h> -#include <soc/serialio.h> +#include <southbridge/intel/wildcatpoint/iobp.h> +#include <southbridge/intel/wildcatpoint/serialio.h> const struct reg_script uart_init[] = { /* Set MMIO BAR */ diff --git a/src/southbridge/intel/wildcatpoint/xhci.c b/src/southbridge/intel/wildcatpoint/xhci.c index 7541fef..cef2bed 100644 --- a/src/southbridge/intel/wildcatpoint/xhci.c +++ b/src/southbridge/intel/wildcatpoint/xhci.c @@ -7,8 +7,8 @@ #include <acpi/acpi.h> #include <device/mmio.h> #include <device/pci_ops.h> -#include <soc/ramstage.h> -#include <soc/xhci.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <southbridge/intel/wildcatpoint/xhci.h> #include <cpu/intel/broadwell/broadwell.h> #ifdef __SIMPLE_DEVICE__ diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/southbridge/intel/wildcatpoint/xhci.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/xhci.h rename to src/southbridge/intel/wildcatpoint/xhci.h -- To view, visit https://review.coreboot.org/c/coreboot/+/41938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2bdef9b44ec8c93c1469074dc51a9964b4101ce Gerrit-Change-Number: 41938 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 5

Change in coreboot[master]: soc/intel/broadwell: Move include folder to northbridge
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41939 ) Change subject: soc/intel/broadwell: Move include folder to northbridge ...................................................................... soc/intel/broadwell: Move include folder to northbridge Since we process soc files before southbridge files, the cppflags override does not work as intended if placed in the southbridge. And yes, some prototypes are now in the wrong place. This will be fixed in the next commits, once the soc/intel/broadwell subfolder is no more. With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical. Change-Id: Iaa773923e37536d92cf54825db3291af2b3d9b54 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/broadwell/Makefile.inc R src/northbridge/intel/broadwell/include/soc/msr.h R src/northbridge/intel/broadwell/include/soc/nvs.h R src/northbridge/intel/broadwell/include/soc/systemagent.h D src/soc/intel/broadwell/Makefile.inc 5 files changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/41939/1 diff --git a/src/northbridge/intel/broadwell/Makefile.inc b/src/northbridge/intel/broadwell/Makefile.inc index cbcc631..51cf4a8 100644 --- a/src/northbridge/intel/broadwell/Makefile.inc +++ b/src/northbridge/intel/broadwell/Makefile.inc @@ -1,5 +1,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_BROADWELL),y) +CPPFLAGS_common += -Isrc/northbridge/intel/broadwell/include + bootblock-y += bootblock.c ramstage-y += finalize.c diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/northbridge/intel/broadwell/include/soc/msr.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/msr.h rename to src/northbridge/intel/broadwell/include/soc/msr.h diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/northbridge/intel/broadwell/include/soc/nvs.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/nvs.h rename to src/northbridge/intel/broadwell/include/soc/nvs.h diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/northbridge/intel/broadwell/include/soc/systemagent.h similarity index 100% rename from src/soc/intel/broadwell/include/soc/systemagent.h rename to src/northbridge/intel/broadwell/include/soc/systemagent.h diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc deleted file mode 100644 index dada3d1..0000000 --- a/src/soc/intel/broadwell/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) - -CPPFLAGS_common += -Isrc/soc/intel/broadwell/include - -endif -- To view, visit https://review.coreboot.org/c/coreboot/+/41939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa773923e37536d92cf54825db3291af2b3d9b54 Gerrit-Change-Number: 41939 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: soc/intel/broadwell: Move chip.h to northbridge
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41941 ) Change subject: soc/intel/broadwell: Move chip.h to northbridge ...................................................................... soc/intel/broadwell: Move chip.h to northbridge We need to update the name of the config struct to make sconfig happy, but this means the resulting binaries are no longer reproducible... But now, soc/intel/broadwell is finally no more. Now we need to clean up the mess that was left after scattering everything into three parts... Change-Id: I199cddb05de460359d1fade21e6171a218377f47 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb R src/northbridge/intel/broadwell/chip.h M src/northbridge/intel/broadwell/igd.c M src/southbridge/intel/wildcatpoint/soc_chip.h 15 files changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/41941/1 diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index a84aa98..4bcf672 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb index 70b1ebd..a53a060 100644 --- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index 67b9131..ed33680 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index f814280..e04744d 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index e35d3a5..6236e43 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index 70b1ebd..a53a060 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 93e96ca..dd61c18 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Enable DDI2 Hotplug with 6ms pulse register "gpu_dp_c_hotplug" = "0x06" diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 19d0c48..bb8df2d 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Disable eDP Hotplug register "gpu_dp_d_hotplug" = "0x00" diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 8d36f04..3b79ea3 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Enable DisplayPort 1 Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index 13b9e5e..543570e 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Enable eDP Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb index d3d0ae7..11ae807 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Port 0 is HDD # Port 3 is M.2 NGFF diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb index c0c8d03..d526ac7 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell # Port 0 is HDD # Port 1 is M.2 NGFF diff --git a/src/soc/intel/broadwell/chip.h b/src/northbridge/intel/broadwell/chip.h similarity index 96% rename from src/soc/intel/broadwell/chip.h rename to src/northbridge/intel/broadwell/chip.h index 45f91d8..9a62630 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/northbridge/intel/broadwell/chip.h @@ -7,7 +7,7 @@ #include <intelblocks/cfg.h> #include <stdint.h> -struct soc_intel_broadwell_config { +struct northbridge_intel_broadwell_config { /* * Interrupt Routing configuration * If bit7 is 1, the interrupt is disabled. @@ -155,6 +155,6 @@ int tcc_offset; }; -typedef struct soc_intel_broadwell_config config_t; +typedef struct northbridge_intel_broadwell_config config_t; #endif diff --git a/src/northbridge/intel/broadwell/igd.c b/src/northbridge/intel/broadwell/igd.c index 6c0da56..b032782 100644 --- a/src/northbridge/intel/broadwell/igd.c +++ b/src/northbridge/intel/broadwell/igd.c @@ -575,7 +575,7 @@ static void gma_generate_ssdt(const struct device *dev) { - const struct soc_intel_broadwell_config *chip = dev->chip_info; + const struct northbridge_intel_broadwell_config *chip = dev->chip_info; drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } diff --git a/src/southbridge/intel/wildcatpoint/soc_chip.h b/src/southbridge/intel/wildcatpoint/soc_chip.h index c59f562..4f8d4af 100644 --- a/src/southbridge/intel/wildcatpoint/soc_chip.h +++ b/src/southbridge/intel/wildcatpoint/soc_chip.h @@ -3,6 +3,6 @@ #ifndef _SOC_BROADWELL_SOC_CHIP_H_ #define _SOC_BROADWELL_SOC_CHIP_H_ -#include <soc/intel/broadwell/chip.h> +#include <northbridge/intel/broadwell/chip.h> #endif /* _SOC_BROADWELL_SOC_CHIP_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I199cddb05de460359d1fade21e6171a218377f47 Gerrit-Change-Number: 41941 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: broadwell: Relocate functions and prototypes
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41942 ) Change subject: broadwell: Relocate functions and prototypes ...................................................................... broadwell: Relocate functions and prototypes Move the code around so that it aligns with Haswell. Change-Id: I3ae1bd0298bbb5b04787ae5bf14f32b77b47046d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/broadwell/Makefile.inc M src/cpu/intel/broadwell/acpi.c M src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/broadwell.h M src/cpu/intel/broadwell/broadwell_early_init.c R src/cpu/intel/broadwell/broadwell_init.c M src/cpu/intel/broadwell/chip.c M src/cpu/intel/broadwell/romstage.c M src/mainboard/google/auron/romstage.c M src/mainboard/google/auron/variant.h M src/northbridge/intel/broadwell/Makefile.inc A src/northbridge/intel/broadwell/acpi.c M src/northbridge/intel/broadwell/broadwell.h R src/northbridge/intel/broadwell/early_init.c A src/northbridge/intel/broadwell/northbridge.c M src/northbridge/intel/broadwell/raminit.c A src/northbridge/intel/broadwell/raminit.h M src/northbridge/intel/broadwell/refcode.c A src/northbridge/intel/broadwell/refcode.h M src/northbridge/intel/broadwell/report_platform.c D src/northbridge/intel/broadwell/romstage.h M src/northbridge/intel/broadwell/systemagent.c M src/southbridge/intel/wildcatpoint/acpi.h M src/southbridge/intel/wildcatpoint/early_pch.c M src/southbridge/intel/wildcatpoint/early_smbus.c M src/southbridge/intel/wildcatpoint/lpc.c M src/southbridge/intel/wildcatpoint/pch.h M src/southbridge/intel/wildcatpoint/power_state.c M src/southbridge/intel/wildcatpoint/ramstage.c M src/southbridge/intel/wildcatpoint/ramstage.h A src/southbridge/intel/wildcatpoint/romstage.h 31 files changed, 824 insertions(+), 762 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/41942/1 diff --git a/src/cpu/intel/broadwell/Makefile.inc b/src/cpu/intel/broadwell/Makefile.inc index 453b879..ad5dc5b 100644 --- a/src/cpu/intel/broadwell/Makefile.inc +++ b/src/cpu/intel/broadwell/Makefile.inc @@ -16,9 +16,10 @@ ramstage-y += acpi.c +ramstage-y += broadwell_init.c + ramstage-y += chip.c -ramstage-y += cpu.c ramstage-y += cpu_info.c smm-y += cpu_info.c diff --git a/src/cpu/intel/broadwell/acpi.c b/src/cpu/intel/broadwell/acpi.c index bd4eb63..a63914c 100644 --- a/src/cpu/intel/broadwell/acpi.c +++ b/src/cpu/intel/broadwell/acpi.c @@ -147,151 +147,26 @@ return cores; } -void acpi_init_gnvs(global_nvs_t *gnvs) +static void generate_C_state_entries(void) { - /* Set unknown wake source */ - gnvs->pm1i = -1; + acpi_cstate_t map[3]; + int *set; + int i; - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); + config_t *config = config_of_soc(); -#if CONFIG(CONSOLE_CBMEM) - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); -#endif + if (config->s0ix_enable) + set = cstate_set_s0ix; + else + set = cstate_set_non_s0ix; -#if CONFIG(CHROMEOS) - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#if CONFIG(EC_GOOGLE_CHROMEEC) - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; -#endif -} + for (i = 0; i < 3; i++) { + memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); + map[i].ctype = i + 1; + } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - MCFG_BASE_ADDRESS, 0, 0, 255); - return current; -} - -void acpi_fill_in_fadt(acpi_fadt_t *fadt) -{ - const uint16_t pmbase = ACPI_BASE_ADDRESS; - - fadt->sci_int = acpi_sci_irq(); - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS(0); - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 32; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - - /* - * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. - * The bit_width field intentionally overflows here. - * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which - * seems to work fine on Linux 5.0 and Windows 10. - */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0; - - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; + /* Generate C-state tables */ + acpigen_write_CST_package(map, ARRAY_SIZE(map)); } static acpi_tstate_t tss_table_fine[] = { @@ -346,28 +221,6 @@ ARRAY_SIZE(tss_table_coarse), tss_table_coarse); } -static void generate_C_state_entries(void) -{ - acpi_cstate_t map[3]; - int *set; - int i; - - config_t *config = config_of_soc(); - - if (config->s0ix_enable) - set = cstate_set_s0ix; - else - set = cstate_set_non_s0ix; - - for (i = 0; i < 3; i++) { - memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); - map[i].ctype = i + 1; - } - - /* Generate C-state tables */ - acpigen_write_CST_package(map, ARRAY_SIZE(map)); -} - static int calculate_power(int tdp, int p1_ratio, int ratio) { u32 m; @@ -540,70 +393,6 @@ acpigen_write_processor_cnot(cores_per_package); } -static unsigned long acpi_fill_dmar(unsigned long current) -{ - struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); - const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff; - const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; - const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1; - const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1; - - /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */ - if (igfx_dev && igfx_dev->enabled && gfxvtbar - && gfxvten && !MCHBAR32(GFXVTBAR + 4)) { - unsigned long tmp = current; - - current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); - current += acpi_create_dmar_ds_pci(current, 0, 2, 0); - - acpi_dmar_drhd_fixup(tmp, current); - - /* Add RMRR entry */ - tmp = current; - - current += acpi_create_dmar_rmrr(current, 0, - sa_get_gsm_base(), sa_get_tolud_base() - 1); - current += acpi_create_dmar_ds_pci(current, 0, 2, 0); - acpi_dmar_rmrr_fixup(tmp, current); - } - - /* VTVC0BAR has to be set, enabled, and in 32-bit space */ - if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { - const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, - DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, - 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); - size_t i; - for (i = 0; i < 8; ++i) - current += acpi_create_dmar_ds_msi_hpet(current, - 0, PCH_HPET_PCI_BUS, - PCH_HPET_PCI_SLOT, i); - acpi_dmar_drhd_fixup(tmp, current); - } - - return current; -} - -unsigned long northbridge_write_acpi_tables(const struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - /* Create DMAR table only if we have VT-d capability. */ - const u32 capid0_a = pci_read_config32(dev, CAPID0_A); - if (capid0_a & VTD_DISABLE) - return current; - - acpi_dmar_t *const dmar = (acpi_dmar_t *)current; - printk(BIOS_DEBUG, "ACPI: * DMAR\n"); - acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); - current += dmar->header.length; - current = acpi_align_current(current); - acpi_add_table(rsdp, dmar); - - return current; -} - unsigned long acpi_madt_irq_overrides(unsigned long current) { int sci = acpi_sci_irq(); diff --git a/src/cpu/intel/broadwell/bootblock.c b/src/cpu/intel/broadwell/bootblock.c index 3290eee..fbaea86 100644 --- a/src/cpu/intel/broadwell/bootblock.c +++ b/src/cpu/intel/broadwell/bootblock.c @@ -7,9 +7,10 @@ #include <cpu/x86/mtrr.h> #include <halt.h> #include <southbridge/intel/wildcatpoint/rcba.h> -#include <cpu/intel/broadwell/broadwell.h> #include <delay.h> +#include <cpu/intel/broadwell/broadwell.h> + static void set_flex_ratio_to_tdp_nominal(void) { msr_t flex_ratio, msr; diff --git a/src/cpu/intel/broadwell/broadwell.h b/src/cpu/intel/broadwell/broadwell.h index 5654e0a..9e62eea 100644 --- a/src/cpu/intel/broadwell/broadwell.h +++ b/src/cpu/intel/broadwell/broadwell.h @@ -108,4 +108,19 @@ u32 cpu_stepping(void); int cpu_is_ult(void); +#include <northbridge/intel/broadwell/pei_data.h> + +struct chipset_power_state; +struct romstage_params { + struct chipset_power_state *power_state; + struct pei_data pei_data; +}; + +void set_max_freq(void); + +void mainboard_pre_raminit(struct romstage_params *params); +void mainboard_post_raminit(struct romstage_params *params); + +void broadwell_init_cpus(struct device *dev); + #endif diff --git a/src/cpu/intel/broadwell/broadwell_early_init.c b/src/cpu/intel/broadwell/broadwell_early_init.c index 4fd23f6..b093ece 100644 --- a/src/cpu/intel/broadwell/broadwell_early_init.c +++ b/src/cpu/intel/broadwell/broadwell_early_init.c @@ -4,7 +4,6 @@ #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/intel/broadwell/broadwell.h> -#include <northbridge/intel/broadwell/romstage.h> u32 cpu_family_model(void) { diff --git a/src/cpu/intel/broadwell/cpu.c b/src/cpu/intel/broadwell/broadwell_init.c similarity index 97% rename from src/cpu/intel/broadwell/cpu.c rename to src/cpu/intel/broadwell/broadwell_init.c index f8132b5..8c74394 100644 --- a/src/cpu/intel/broadwell/cpu.c +++ b/src/cpu/intel/broadwell/broadwell_init.c @@ -1,29 +1,41 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <arch/cpu.h> #include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/mp.h> +#include <cpu/intel/broadwell/broadwell.h> +#include <cpu/intel/common/common.h> #include <cpu/intel/microcode.h> #include <cpu/intel/smm_reloc.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/mp.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <cpu/x86/name.h> #include <cpu/x86/smm.h> #include <delay.h> +#include <device/device.h> #include <intelblocks/cpulib.h> -#include <cpu/intel/broadwell/broadwell.h> +#include <northbridge/intel/broadwell/broadwell.h> +#include <southbridge/intel/wildcatpoint/iomap.h> #include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pm.h> #include <southbridge/intel/wildcatpoint/ramstage.h> #include <southbridge/intel/wildcatpoint/rcba.h> -#include <northbridge/intel/broadwell/broadwell.h> #include <southbridge/intel/wildcatpoint/soc_chip.h> -#include <cpu/intel/common/common.h> +#include <string.h> +#include <types.h> + +/** power_limit_time_sec_to_msr **/ + +/** power_limit_time_msr_to_sec **/ + +/** haswell_family_model **/ + +/** haswell_stepping **/ + +/** haswell_is_ult **/ /* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly @@ -230,6 +242,10 @@ RCBA32(PMSYNC_CONFIG2) = pmsync2; } +/** cpu_config_tdp_levels **/ + +/** set_power_limits **/ + static void configure_c_states(void) { msr_t msr; diff --git a/src/cpu/intel/broadwell/chip.c b/src/cpu/intel/broadwell/chip.c index 443faf4..c769a80 100644 --- a/src/cpu/intel/broadwell/chip.c +++ b/src/cpu/intel/broadwell/chip.c @@ -2,8 +2,11 @@ #include <device/device.h> #include <device/pci.h> +#include <cpu/intel/broadwell/broadwell.h> +#include <northbridge/intel/broadwell/broadwell.h> #include <southbridge/intel/wildcatpoint/acpi.h> #include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/pch.h> #include <southbridge/intel/wildcatpoint/ramstage.h> #include <southbridge/intel/wildcatpoint/soc_chip.h> diff --git a/src/cpu/intel/broadwell/romstage.c b/src/cpu/intel/broadwell/romstage.c index 35bb592..e33ae9f 100644 --- a/src/cpu/intel/broadwell/romstage.c +++ b/src/cpu/intel/broadwell/romstage.c @@ -10,11 +10,14 @@ #include <program_loading.h> #include <romstage_handoff.h> #include <timestamp.h> +#include <cpu/intel/broadwell/broadwell.h> #include <southbridge/intel/wildcatpoint/gpio.h> #include <southbridge/intel/wildcatpoint/me.h> #include <northbridge/intel/broadwell/pei_data.h> #include <southbridge/intel/wildcatpoint/pm.h> -#include <northbridge/intel/broadwell/romstage.h> +#include <northbridge/intel/broadwell/raminit.h> +#include <southbridge/intel/wildcatpoint/romstage.h> +#include <northbridge/intel/broadwell/broadwell.h> #include <southbridge/intel/wildcatpoint/spi.h> void fill_postcar_frame(struct postcar_frame *pcf) diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c index 1540299..cf6b447 100644 --- a/src/mainboard/google/auron/romstage.c +++ b/src/mainboard/google/auron/romstage.c @@ -2,9 +2,9 @@ #include <console/console.h> #include <ec/google/chromeec/ec.h> +#include <cpu/intel/broadwell/broadwell.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> -#include <northbridge/intel/broadwell/romstage.h> #include <variant/spd.h> #include "variant.h" diff --git a/src/mainboard/google/auron/variant.h b/src/mainboard/google/auron/variant.h index 9853aa2..20873f0 100644 --- a/src/mainboard/google/auron/variant.h +++ b/src/mainboard/google/auron/variant.h @@ -4,7 +4,7 @@ #define VARIANT_H #include <device/device.h> -#include <northbridge/intel/broadwell/romstage.h> +#include <cpu/intel/broadwell/broadwell.h> int variant_smbios_data(struct device *dev, int *handle, unsigned long *current); diff --git a/src/northbridge/intel/broadwell/Makefile.inc b/src/northbridge/intel/broadwell/Makefile.inc index 51cf4a8..69ea826 100644 --- a/src/northbridge/intel/broadwell/Makefile.inc +++ b/src/northbridge/intel/broadwell/Makefile.inc @@ -4,6 +4,10 @@ bootblock-y += bootblock.c +ramstage-y += acpi.c + +romstage-y += early_init.c + ramstage-y += finalize.c ramstage-y += igd.c @@ -13,12 +17,13 @@ postcar-y += memmap.c ramstage-y += minihd.c +ramstage-y += northbridge.c + ramstage-y += pei_data.c romstage-y += pei_data.c romstage-y += raminit.c romstage-y += report_platform.c -romstage-y += romstage.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c diff --git a/src/northbridge/intel/broadwell/acpi.c b/src/northbridge/intel/broadwell/acpi.c new file mode 100644 index 0000000..df08537 --- /dev/null +++ b/src/northbridge/intel/broadwell/acpi.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include <console/console.h> +#include <acpi/acpi.h> +#include <device/device.h> +#include <device/pci_ops.h> +#include <northbridge/intel/broadwell/broadwell.h> +#include <southbridge/intel/wildcatpoint/pch.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + MCFG_BASE_ADDRESS, 0, 0, 255); + return current; +} + +static unsigned long acpi_fill_dmar(unsigned long current) +{ + struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff; + const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; + const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1; + const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1; + + /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */ + if (igfx_dev && igfx_dev->enabled && gfxvtbar + && gfxvten && !MCHBAR32(GFXVTBAR + 4)) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + + acpi_dmar_drhd_fixup(tmp, current); + + /* Add RMRR entry */ + tmp = current; + + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + + /* VTVC0BAR has to be set, enabled, and in 32-bit space */ + if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { + const unsigned long tmp = current; + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_ds_ioapic(current, + 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); + size_t i; + for (i = 0; i < 8; ++i) + current += acpi_create_dmar_ds_msi_hpet(current, + 0, PCH_HPET_PCI_BUS, + PCH_HPET_PCI_SLOT, i); + acpi_dmar_drhd_fixup(tmp, current); + } + + return current; +} + +unsigned long northbridge_write_acpi_tables(const struct device *const dev, + unsigned long current, + struct acpi_rsdp *const rsdp) +{ + /* Create DMAR table only if we have VT-d capability. */ + const u32 capid0_a = pci_read_config32(dev, CAPID0_A); + if (capid0_a & VTD_DISABLE) + return current; + + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + + return current; +} diff --git a/src/northbridge/intel/broadwell/broadwell.h b/src/northbridge/intel/broadwell/broadwell.h index 5f4ad6c..1a8e6cf 100644 --- a/src/northbridge/intel/broadwell/broadwell.h +++ b/src/northbridge/intel/broadwell/broadwell.h @@ -126,4 +126,13 @@ uintptr_t sa_get_tolud_base(void); uintptr_t sa_get_gsm_base(void); +void report_platform_info(void); + +void systemagent_early_init(void); + +#include <device/device.h> + +unsigned long northbridge_write_acpi_tables(const struct device *dev, unsigned long current, + struct acpi_rsdp *rsdp); + #endif diff --git a/src/northbridge/intel/broadwell/romstage.c b/src/northbridge/intel/broadwell/early_init.c similarity index 97% rename from src/northbridge/intel/broadwell/romstage.c rename to src/northbridge/intel/broadwell/early_init.c index 064c203..e1bbcc8 100644 --- a/src/northbridge/intel/broadwell/romstage.c +++ b/src/northbridge/intel/broadwell/early_init.c @@ -6,7 +6,6 @@ #include <reg_script.h> #include <southbridge/intel/wildcatpoint/iomap.h> #include <southbridge/intel/wildcatpoint/pci_devs.h> -#include <northbridge/intel/broadwell/romstage.h> #include <northbridge/intel/broadwell/broadwell.h> static const struct reg_script systemagent_early_init_script[] = { diff --git a/src/northbridge/intel/broadwell/northbridge.c b/src/northbridge/intel/broadwell/northbridge.c new file mode 100644 index 0000000..5122fed --- /dev/null +++ b/src/northbridge/intel/broadwell/northbridge.c @@ -0,0 +1,433 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <acpi/acpi.h> +#include <device/pci_ops.h> +#include <stdint.h> +#include <delay.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/power_limit.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <cpu/intel/broadwell/broadwell.h> +#include <southbridge/intel/wildcatpoint/iomap.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <northbridge/intel/broadwell/broadwell.h> + +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, + u32 *len) +{ + u32 pciexbar_reg; + + *base = 0; + *len = 0; + + pciexbar_reg = pci_read_config32(dev, index); + + if (!(pciexbar_reg & (1 << 0))) + return 0; + + switch ((pciexbar_reg >> 1) & 3) { + case 0: // 256MB + *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| + (1 << 28)); + *len = 256 * 1024 * 1024; + return 1; + case 1: // 128M + *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| + (1 << 28)|(1 << 27)); + *len = 128 * 1024 * 1024; + return 1; + case 2: // 64M + *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| + (1 << 28)|(1 << 27)|(1 << 26)); + *len = 64 * 1024 * 1024; + return 1; + } + + return 0; +} + +static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) +{ + u32 bar; + + bar = pci_read_config32(dev, index); + + /* If not enabled don't report it. */ + if (!(bar & 0x1)) + return 0; + + /* Knock down the enable bit. */ + *base = bar & ~1; + + return 1; +} + +/* There are special BARs that actually are programmed in the MCHBAR. These + * Intel special features, but they do consume resources that need to be + * accounted for. */ +static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, + u32 *len) +{ + u32 bar; + + bar = MCHBAR32(index); + + /* If not enabled don't report it. */ + if (!(bar & 0x1)) + return 0; + + /* Knock down the enable bit. */ + *base = bar & ~1; + + return 1; +} + +struct fixed_mmio_descriptor { + unsigned int index; + u32 size; + int (*get_resource)(struct device *dev, unsigned int index, + u32 *base, u32 *size); + const char *description; +}; + +struct fixed_mmio_descriptor mc_fixed_resources[] = { + { PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" }, + { MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" }, + { DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" }, + { EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" }, + { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" }, + { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" }, +}; + +/* + * Add all known fixed MMIO ranges that hang off the host bridge/memory + * controller device. + */ +static void mc_add_fixed_mmio_resources(struct device *dev) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) { + u32 base; + u32 size; + struct resource *resource; + unsigned int index; + + size = mc_fixed_resources[i].size; + index = mc_fixed_resources[i].index; + if (!mc_fixed_resources[i].get_resource(dev, index, + &base, &size)) + continue; + + resource = new_resource(dev, mc_fixed_resources[i].index); + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED; + resource->base = base; + resource->size = size; + printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", + __func__, mc_fixed_resources[i].description, index, + (unsigned long)base, (unsigned long)(base + size - 1)); + } +} + +/* Host Memory Map: + * + * +--------------------------+ TOUUD + * | | + * +--------------------------+ 4GiB + * | PCI Address Space | + * +--------------------------+ TOLUD (also maps into MC address space) + * | iGD | + * +--------------------------+ BDSM + * | GTT | + * +--------------------------+ BGSM + * | TSEG | + * +--------------------------+ TSEGMB + * | Usage DRAM | + * +--------------------------+ 0 + * + * Some of the base registers above can be equal making the size of those + * regions 0. The reason is because the memory controller internally subtracts + * the base registers from each other to determine sizes of the regions. In + * other words, the memory map is in a fixed order no matter what. + */ + +struct map_entry { + int reg; + int is_64_bit; + int is_limit; + const char *description; +}; + +static void read_map_entry(struct device *dev, struct map_entry *entry, + uint64_t *result) +{ + uint64_t value; + uint64_t mask; + + /* All registers are on a 1MiB granularity. */ + mask = ((1ULL<<20)-1); + mask = ~mask; + + value = 0; + + if (entry->is_64_bit) { + value = pci_read_config32(dev, entry->reg + 4); + value <<= 32; + } + + value |= pci_read_config32(dev, entry->reg); + value &= mask; + + if (entry->is_limit) + value |= ~mask; + + *result = value; +} + +#define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ + { \ + .reg = reg_, \ + .is_64_bit = is_64_, \ + .is_limit = is_limit_, \ + .description = desc_, \ + } + +#define MAP_ENTRY_BASE_64(reg_, desc_) \ + MAP_ENTRY(reg_, 1, 0, desc_) +#define MAP_ENTRY_LIMIT_64(reg_, desc_) \ + MAP_ENTRY(reg_, 1, 1, desc_) +#define MAP_ENTRY_BASE_32(reg_, desc_) \ + MAP_ENTRY(reg_, 0, 0, desc_) + +enum { + TOM_REG, + TOUUD_REG, + MESEG_BASE_REG, + MESEG_LIMIT_REG, + REMAP_BASE_REG, + REMAP_LIMIT_REG, + TOLUD_REG, + BGSM_REG, + BDSM_REG, + TSEG_REG, + // Must be last. + NUM_MAP_ENTRIES +}; + +static struct map_entry memory_map[NUM_MAP_ENTRIES] = { + [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), + [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), + [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), + [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), + [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), + [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), + [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), + [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), + [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), + [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), +}; + +static void mc_read_map_entries(struct device *dev, uint64_t *values) +{ + int i; + for (i = 0; i < NUM_MAP_ENTRIES; i++) + read_map_entry(dev, &memory_map[i], &values[i]); +} + +static void mc_report_map_entries(struct device *dev, uint64_t *values) +{ + int i; + for (i = 0; i < NUM_MAP_ENTRIES; i++) { + printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", + memory_map[i].description, values[i]); + } + /* One can validate the BDSM and BGSM against the GGC. */ + printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); +} + +static void mc_add_dram_resources(struct device *dev, int *resource_cnt) +{ + unsigned long base_k, size_k; + unsigned long touud_k; + unsigned long index; + struct resource *resource; + uint64_t mc_values[NUM_MAP_ENTRIES]; + unsigned long dpr_size = 0; + u32 dpr_reg; + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + + /* Read in the MAP registers and report their values. */ + mc_read_map_entries(dev, &mc_values[0]); + mc_report_map_entries(dev, &mc_values[0]); + + /* + * DMA Protected Range can be reserved below TSEG for PCODE patch + * or TXT/BootGuard related data. Rather than report a base address + * the DPR register reports the TOP of the region, which is the same + * as TSEG base. The region size is reported in MiB in bits 11:4. + */ + dpr_reg = pci_read_config32(sa_dev, DPR); + if (dpr_reg & DPR_EPM) { + dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16; + printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size); + } + + /* + * These are the host memory ranges that should be added: + * - 0 -> 0xa0000: cacheable + * - 0xc0000 -> TSEG : cacheable + * - TESG -> BGSM: cacheable with standard MTRRs and reserved + * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved + * - 4GiB -> TOUUD: cacheable + * + * The default SMRAM space is reserved so that the range doesn't + * have to be saved during S3 Resume. Once marked reserved the OS + * cannot use the memory. This is a bit of an odd place to reserve + * the region, but the CPU devices don't have dev_ops->read_resources() + * called on them. + * + * The range 0xa0000 -> 0xc0000 does not have any resources + * associated with it to handle legacy VGA memory. If this range + * is not omitted the mtrr code will setup the area as cacheable + * causing VGA access to not work. + * + * The TSEG region is mapped as cacheable so that one can perform + * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes + * precedence over the existing MTRRs covering this region. + * + * It should be noted that cacheable entry types need to be added in + * order. The reason is that the current MTRR code assumes this and + * falls over itself if it isn't. + * + * The resource index starts low and should not meet or exceed + * PCI_BASE_ADDRESS_0. + */ + index = *resource_cnt; + + /* 0 - > 0xa0000 */ + base_k = 0; + size_k = (0xa0000 >> 10) - base_k; + ram_resource(dev, index++, base_k, size_k); + + /* 0xc0000 -> TSEG - DPR */ + base_k = 0xc0000 >> 10; + size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k; + size_k -= dpr_size >> 10; + ram_resource(dev, index++, base_k, size_k); + + /* TSEG - DPR -> BGSM */ + resource = new_resource(dev, index++); + resource->base = mc_values[TSEG_REG] - dpr_size; + resource->size = mc_values[BGSM_REG] - resource->base; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; + + /* BGSM -> TOLUD */ + resource = new_resource(dev, index++); + resource->base = mc_values[BGSM_REG]; + resource->size = mc_values[TOLUD_REG] - resource->base; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED; + + /* 4GiB -> TOUUD */ + base_k = 4096 * 1024; /* 4GiB */ + touud_k = mc_values[TOUUD_REG] >> 10; + size_k = touud_k - base_k; + if (touud_k > base_k) + ram_resource(dev, index++, base_k, size_k); + + /* Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: legacy VGA + * 0xc0000 - 0xfffff: RAM + */ + mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); + reserved_ram_resource(dev, index++, (0xc0000 >> 10), + (0x100000 - 0xc0000) >> 10); + + if (CONFIG(CHROMEOS)) + chromeos_reserve_ram_oops(dev, index++); + + *resource_cnt = index; +} + +static void systemagent_read_resources(struct device *dev) +{ + int index = 0; + const bool vtd_capable = + !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); + + /* Read standard PCI resources. */ + pci_dev_read_resources(dev); + + /* Add all fixed MMIO resources. */ + mc_add_fixed_mmio_resources(dev); + + /* Add VT-d MMIO resources if capable */ + if (vtd_capable) { + mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, + GFXVT_BASE_SIZE / KiB); + mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, + VTVC0_BASE_SIZE / KiB); + } + + /* Calculate and add DRAM resources. */ + mc_add_dram_resources(dev, &index); +} + +static void systemagent_init(struct device *dev) +{ + struct soc_power_limits_config *config; + u8 bios_reset_cpl, pair; + + /* Enable Power Aware Interrupt Routing */ + pair = MCHBAR8(MCH_PAIR); + pair &= ~0x7; /* Clear 2:0 */ + pair |= 0x4; /* Fixed Priority */ + MCHBAR8(MCH_PAIR) = pair; + + /* + * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU + * that BIOS has initialized memory and power management + */ + bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); + bios_reset_cpl |= 3; + MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; + printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); + + /* Configure turbo power limits 1ms after reset complete bit */ + mdelay(1); + config = config_of_soc(); + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, config); +} + +static struct device_operations systemagent_ops = { + .read_resources = systemagent_read_resources, + .acpi_fill_ssdt = generate_cpu_entries, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = systemagent_init, + .ops_pci = &broadwell_pci_ops, +}; + +static const unsigned short systemagent_ids[] = { + 0x0a04, /* Haswell ULT */ + 0x1604, /* Broadwell-U/Y */ + 0x1610, /* Broadwell-H Desktop */ + 0x1614, /* Broadwell-H Mobile */ + 0 +}; + +static const struct pci_driver systemagent_driver __pci_driver = { + .ops = &systemagent_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = systemagent_ids +}; diff --git a/src/northbridge/intel/broadwell/raminit.c b/src/northbridge/intel/broadwell/raminit.c index d40c2a3..9e8d8ad 100644 --- a/src/northbridge/intel/broadwell/raminit.c +++ b/src/northbridge/intel/broadwell/raminit.c @@ -9,17 +9,54 @@ #include <memory_info.h> #include <mrc_cache.h> #include <string.h> -#if CONFIG(EC_GOOGLE_CHROMEEC) -#include <ec/google/chromeec/ec.h> -#include <ec/google/chromeec/ec_commands.h> -#endif #include <vendorcode/google/chromeos/chromeos.h> #include <southbridge/intel/wildcatpoint/iomap.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> #include <southbridge/intel/wildcatpoint/pm.h> -#include <northbridge/intel/broadwell/romstage.h> #include <northbridge/intel/broadwell/broadwell.h> +#include <northbridge/intel/broadwell/raminit.h> + +/* + * Dump in the log memory controller configuration as read from the memory + * controller registers. + */ +void report_memory_config(void) +{ + u32 addr_decoder_common, addr_decode_ch[2]; + int i; + + addr_decoder_common = MCHBAR32(0x5000); + addr_decode_ch[0] = MCHBAR32(0x5004); + addr_decode_ch[1] = MCHBAR32(0x5008); + + printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", + (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); + printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", + addr_decoder_common & 3, + (addr_decoder_common >> 2) & 3, + (addr_decoder_common >> 4) & 3); + + for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { + u32 ch_conf = addr_decode_ch[i]; + printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", + i, ch_conf); + printk(BIOS_DEBUG, " enhanced interleave mode %s\n", + ((ch_conf >> 22) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " rank interleave %s\n", + ((ch_conf >> 21) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", + ((ch_conf >> 0) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", + ((ch_conf >> 17) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? "" : ", selected"); + printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", + ((ch_conf >> 8) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", + ((ch_conf >> 18) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? ", selected" : ""); + } +} /* * Find PEI executable in coreboot filesystem and execute it. diff --git a/src/northbridge/intel/broadwell/raminit.h b/src/northbridge/intel/broadwell/raminit.h new file mode 100644 index 0000000..7f324b8 --- /dev/null +++ b/src/northbridge/intel/broadwell/raminit.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef RAMINIT_H +#define RAMINIT_H + +#include "pei_data.h" + +void raminit(struct pei_data *pei_data); +void report_memory_config(void); + +#endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/broadwell/refcode.c b/src/northbridge/intel/broadwell/refcode.c index 13be8b6..11df686 100644 --- a/src/northbridge/intel/broadwell/refcode.c +++ b/src/northbridge/intel/broadwell/refcode.c @@ -11,6 +11,7 @@ #include <stage_cache.h> #include <northbridge/intel/broadwell/pei_data.h> #include <northbridge/intel/broadwell/pei_wrapper.h> +#include <northbridge/intel/broadwell/refcode.h> #include <southbridge/intel/wildcatpoint/pm.h> #include <southbridge/intel/wildcatpoint/ramstage.h> diff --git a/src/northbridge/intel/broadwell/refcode.h b/src/northbridge/intel/broadwell/refcode.h new file mode 100644 index 0000000..80219eb --- /dev/null +++ b/src/northbridge/intel/broadwell/refcode.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _BROADWELL_REFCODE_H_ +#define _BROADWELL_REFCODE_H_ + +#if CONFIG(HAVE_REFCODE_BLOB) +void broadwell_run_reference_code(void); +#else +static inline void broadwell_run_reference_code(void) { } +#endif + +#endif /* _BROADWELL_REFCODE_H_ */ diff --git a/src/northbridge/intel/broadwell/report_platform.c b/src/northbridge/intel/broadwell/report_platform.c index 3ac4ece..95d9c99 100644 --- a/src/northbridge/intel/broadwell/report_platform.c +++ b/src/northbridge/intel/broadwell/report_platform.c @@ -9,7 +9,6 @@ #include <cpu/intel/broadwell/broadwell.h> #include <southbridge/intel/wildcatpoint/pch.h> #include <southbridge/intel/wildcatpoint/pci_devs.h> -#include <northbridge/intel/broadwell/romstage.h> #include <northbridge/intel/broadwell/broadwell.h> static struct { @@ -184,44 +183,3 @@ report_pch_info(); report_igd_info(); } - -/* - * Dump in the log memory controller configuration as read from the memory - * controller registers. - */ -void report_memory_config(void) -{ - u32 addr_decoder_common, addr_decode_ch[2]; - int i; - - addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); - - printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); - printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - addr_decoder_common & 3, - (addr_decoder_common >> 2) & 3, - (addr_decoder_common >> 4) & 3); - - for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { - u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", - i, ch_conf); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", - ((ch_conf >> 22) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " rank interleave %s\n", - ((ch_conf >> 21) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", - ((ch_conf >> 17) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? "" : ", selected"); - printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", - ((ch_conf >> 18) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? ", selected" : ""); - } -} diff --git a/src/northbridge/intel/broadwell/romstage.h b/src/northbridge/intel/broadwell/romstage.h deleted file mode 100644 index 275938a..0000000 --- a/src/northbridge/intel/broadwell/romstage.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _BROADWELL_ROMSTAGE_H_ -#define _BROADWELL_ROMSTAGE_H_ - -#include <stdint.h> -#include <northbridge/intel/broadwell/pei_data.h> - -struct chipset_power_state; -struct romstage_params { - struct chipset_power_state *power_state; - struct pei_data pei_data; -}; - -void mainboard_pre_raminit(struct romstage_params *params); -void mainboard_post_raminit(struct romstage_params *params); - -void raminit(struct pei_data *pei_data); - -struct chipset_power_state; -struct chipset_power_state *fill_power_state(void); -void report_platform_info(void); -void report_memory_config(void); - -void set_max_freq(void); - -void systemagent_early_init(void); -void pch_early_init(void); -void pch_uart_init(void); -void intel_early_me_status(void); - -#endif diff --git a/src/northbridge/intel/broadwell/systemagent.c b/src/northbridge/intel/broadwell/systemagent.c index 67d78cf..ee5e836 100644 --- a/src/northbridge/intel/broadwell/systemagent.c +++ b/src/northbridge/intel/broadwell/systemagent.c @@ -1,19 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> -#include <acpi/acpi.h> #include <device/pci_ops.h> -#include <stdint.h> -#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <intelblocks/power_limit.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <cpu/intel/broadwell/broadwell.h> -#include <southbridge/intel/wildcatpoint/iomap.h> #include <southbridge/intel/wildcatpoint/pci_devs.h> -#include <southbridge/intel/wildcatpoint/ramstage.h> #include <northbridge/intel/broadwell/broadwell.h> u8 systemagent_revision(void) @@ -35,419 +26,3 @@ /* Bit 0 is lock bit, not part of address */ return pci_read_config32(sa_dev, BGSM) & ~1; } - -static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, - u32 *len) -{ - u32 pciexbar_reg; - - *base = 0; - *len = 0; - - pciexbar_reg = pci_read_config32(dev, index); - - if (!(pciexbar_reg & (1 << 0))) - return 0; - - switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| - (1 << 28)); - *len = 256 * 1024 * 1024; - return 1; - case 1: // 128M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| - (1 << 28)|(1 << 27)); - *len = 128 * 1024 * 1024; - return 1; - case 2: // 64M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| - (1 << 28)|(1 << 27)|(1 << 26)); - *len = 64 * 1024 * 1024; - return 1; - } - - return 0; -} - -static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) -{ - u32 bar; - - bar = pci_read_config32(dev, index); - - /* If not enabled don't report it. */ - if (!(bar & 0x1)) - return 0; - - /* Knock down the enable bit. */ - *base = bar & ~1; - - return 1; -} - -/* There are special BARs that actually are programmed in the MCHBAR. These - * Intel special features, but they do consume resources that need to be - * accounted for. */ -static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, - u32 *len) -{ - u32 bar; - - bar = MCHBAR32(index); - - /* If not enabled don't report it. */ - if (!(bar & 0x1)) - return 0; - - /* Knock down the enable bit. */ - *base = bar & ~1; - - return 1; -} - -struct fixed_mmio_descriptor { - unsigned int index; - u32 size; - int (*get_resource)(struct device *dev, unsigned int index, - u32 *base, u32 *size); - const char *description; -}; - -struct fixed_mmio_descriptor mc_fixed_resources[] = { - { PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" }, - { MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" }, - { DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" }, - { EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" }, - { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" }, - { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" }, -}; - -/* - * Add all known fixed MMIO ranges that hang off the host bridge/memory - * controller device. - */ -static void mc_add_fixed_mmio_resources(struct device *dev) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) { - u32 base; - u32 size; - struct resource *resource; - unsigned int index; - - size = mc_fixed_resources[i].size; - index = mc_fixed_resources[i].index; - if (!mc_fixed_resources[i].get_resource(dev, index, - &base, &size)) - continue; - - resource = new_resource(dev, mc_fixed_resources[i].index); - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED; - resource->base = base; - resource->size = size; - printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", - __func__, mc_fixed_resources[i].description, index, - (unsigned long)base, (unsigned long)(base + size - 1)); - } -} - -/* Host Memory Map: - * - * +--------------------------+ TOUUD - * | | - * +--------------------------+ 4GiB - * | PCI Address Space | - * +--------------------------+ TOLUD (also maps into MC address space) - * | iGD | - * +--------------------------+ BDSM - * | GTT | - * +--------------------------+ BGSM - * | TSEG | - * +--------------------------+ TSEGMB - * | Usage DRAM | - * +--------------------------+ 0 - * - * Some of the base registers above can be equal making the size of those - * regions 0. The reason is because the memory controller internally subtracts - * the base registers from each other to determine sizes of the regions. In - * other words, the memory map is in a fixed order no matter what. - */ - -struct map_entry { - int reg; - int is_64_bit; - int is_limit; - const char *description; -}; - -static void read_map_entry(struct device *dev, struct map_entry *entry, - uint64_t *result) -{ - uint64_t value; - uint64_t mask; - - /* All registers are on a 1MiB granularity. */ - mask = ((1ULL<<20)-1); - mask = ~mask; - - value = 0; - - if (entry->is_64_bit) { - value = pci_read_config32(dev, entry->reg + 4); - value <<= 32; - } - - value |= pci_read_config32(dev, entry->reg); - value &= mask; - - if (entry->is_limit) - value |= ~mask; - - *result = value; -} - -#define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ - { \ - .reg = reg_, \ - .is_64_bit = is_64_, \ - .is_limit = is_limit_, \ - .description = desc_, \ - } - -#define MAP_ENTRY_BASE_64(reg_, desc_) \ - MAP_ENTRY(reg_, 1, 0, desc_) -#define MAP_ENTRY_LIMIT_64(reg_, desc_) \ - MAP_ENTRY(reg_, 1, 1, desc_) -#define MAP_ENTRY_BASE_32(reg_, desc_) \ - MAP_ENTRY(reg_, 0, 0, desc_) - -enum { - TOM_REG, - TOUUD_REG, - MESEG_BASE_REG, - MESEG_LIMIT_REG, - REMAP_BASE_REG, - REMAP_LIMIT_REG, - TOLUD_REG, - BGSM_REG, - BDSM_REG, - TSEG_REG, - // Must be last. - NUM_MAP_ENTRIES -}; - -static struct map_entry memory_map[NUM_MAP_ENTRIES] = { - [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), - [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), - [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), - [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), - [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), - [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), - [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), - [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), - [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), - [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), -}; - -static void mc_read_map_entries(struct device *dev, uint64_t *values) -{ - int i; - for (i = 0; i < NUM_MAP_ENTRIES; i++) - read_map_entry(dev, &memory_map[i], &values[i]); -} - -static void mc_report_map_entries(struct device *dev, uint64_t *values) -{ - int i; - for (i = 0; i < NUM_MAP_ENTRIES; i++) { - printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", - memory_map[i].description, values[i]); - } - /* One can validate the BDSM and BGSM against the GGC. */ - printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); -} - -static void mc_add_dram_resources(struct device *dev, int *resource_cnt) -{ - unsigned long base_k, size_k; - unsigned long touud_k; - unsigned long index; - struct resource *resource; - uint64_t mc_values[NUM_MAP_ENTRIES]; - unsigned long dpr_size = 0; - u32 dpr_reg; - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - - /* Read in the MAP registers and report their values. */ - mc_read_map_entries(dev, &mc_values[0]); - mc_report_map_entries(dev, &mc_values[0]); - - /* - * DMA Protected Range can be reserved below TSEG for PCODE patch - * or TXT/BootGuard related data. Rather than report a base address - * the DPR register reports the TOP of the region, which is the same - * as TSEG base. The region size is reported in MiB in bits 11:4. - */ - dpr_reg = pci_read_config32(sa_dev, DPR); - if (dpr_reg & DPR_EPM) { - dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16; - printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size); - } - - /* - * These are the host memory ranges that should be added: - * - 0 -> 0xa0000: cacheable - * - 0xc0000 -> TSEG : cacheable - * - TESG -> BGSM: cacheable with standard MTRRs and reserved - * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved - * - 4GiB -> TOUUD: cacheable - * - * The default SMRAM space is reserved so that the range doesn't - * have to be saved during S3 Resume. Once marked reserved the OS - * cannot use the memory. This is a bit of an odd place to reserve - * the region, but the CPU devices don't have dev_ops->read_resources() - * called on them. - * - * The range 0xa0000 -> 0xc0000 does not have any resources - * associated with it to handle legacy VGA memory. If this range - * is not omitted the mtrr code will setup the area as cacheable - * causing VGA access to not work. - * - * The TSEG region is mapped as cacheable so that one can perform - * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes - * precedence over the existing MTRRs covering this region. - * - * It should be noted that cacheable entry types need to be added in - * order. The reason is that the current MTRR code assumes this and - * falls over itself if it isn't. - * - * The resource index starts low and should not meet or exceed - * PCI_BASE_ADDRESS_0. - */ - index = *resource_cnt; - - /* 0 - > 0xa0000 */ - base_k = 0; - size_k = (0xa0000 >> 10) - base_k; - ram_resource(dev, index++, base_k, size_k); - - /* 0xc0000 -> TSEG - DPR */ - base_k = 0xc0000 >> 10; - size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k; - size_k -= dpr_size >> 10; - ram_resource(dev, index++, base_k, size_k); - - /* TSEG - DPR -> BGSM */ - resource = new_resource(dev, index++); - resource->base = mc_values[TSEG_REG] - dpr_size; - resource->size = mc_values[BGSM_REG] - resource->base; - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; - - /* BGSM -> TOLUD */ - resource = new_resource(dev, index++); - resource->base = mc_values[BGSM_REG]; - resource->size = mc_values[TOLUD_REG] - resource->base; - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED; - - /* 4GiB -> TOUUD */ - base_k = 4096 * 1024; /* 4GiB */ - touud_k = mc_values[TOUUD_REG] >> 10; - size_k = touud_k - base_k; - if (touud_k > base_k) - ram_resource(dev, index++, base_k, size_k); - - /* Reserve everything between A segment and 1MB: - * - * 0xa0000 - 0xbffff: legacy VGA - * 0xc0000 - 0xfffff: RAM - */ - mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); - reserved_ram_resource(dev, index++, (0xc0000 >> 10), - (0x100000 - 0xc0000) >> 10); - - if (CONFIG(CHROMEOS)) - chromeos_reserve_ram_oops(dev, index++); - - *resource_cnt = index; -} - -static void systemagent_read_resources(struct device *dev) -{ - int index = 0; - const bool vtd_capable = - !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); - - /* Read standard PCI resources. */ - pci_dev_read_resources(dev); - - /* Add all fixed MMIO resources. */ - mc_add_fixed_mmio_resources(dev); - - /* Add VT-d MMIO resources if capable */ - if (vtd_capable) { - mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, - GFXVT_BASE_SIZE / KiB); - mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, - VTVC0_BASE_SIZE / KiB); - } - - /* Calculate and add DRAM resources. */ - mc_add_dram_resources(dev, &index); -} - -static void systemagent_init(struct device *dev) -{ - struct soc_power_limits_config *config; - u8 bios_reset_cpl, pair; - - /* Enable Power Aware Interrupt Routing */ - pair = MCHBAR8(MCH_PAIR); - pair &= ~0x7; /* Clear 2:0 */ - pair |= 0x4; /* Fixed Priority */ - MCHBAR8(MCH_PAIR) = pair; - - /* - * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU - * that BIOS has initialized memory and power management - */ - bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); - bios_reset_cpl |= 3; - MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; - printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); - - /* Configure turbo power limits 1ms after reset complete bit */ - mdelay(1); - config = config_of_soc(); - set_power_limits(MOBILE_SKU_PL1_TIME_SEC, config); -} - -static struct device_operations systemagent_ops = { - .read_resources = systemagent_read_resources, - .acpi_fill_ssdt = generate_cpu_entries, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = systemagent_init, - .ops_pci = &broadwell_pci_ops, -}; - -static const unsigned short systemagent_ids[] = { - 0x0a04, /* Haswell ULT */ - 0x1604, /* Broadwell-U/Y */ - 0x1610, /* Broadwell-H Desktop */ - 0x1614, /* Broadwell-H Mobile */ - 0 -}; - -static const struct pci_driver systemagent_driver __pci_driver = { - .ops = &systemagent_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = systemagent_ids -}; diff --git a/src/southbridge/intel/wildcatpoint/acpi.h b/src/southbridge/intel/wildcatpoint/acpi.h index 618b627..c747a4b 100644 --- a/src/southbridge/intel/wildcatpoint/acpi.h +++ b/src/southbridge/intel/wildcatpoint/acpi.h @@ -12,9 +12,8 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 -void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); -unsigned long northbridge_write_acpi_tables(const struct device *dev, - unsigned long current, struct acpi_rsdp *rsdp); +void acpi_fill_in_fadt(acpi_fadt_t *fadt); + #endif diff --git a/src/southbridge/intel/wildcatpoint/early_pch.c b/src/southbridge/intel/wildcatpoint/early_pch.c index e8cb8aa..00ad55f 100644 --- a/src/southbridge/intel/wildcatpoint/early_pch.c +++ b/src/southbridge/intel/wildcatpoint/early_pch.c @@ -11,7 +11,7 @@ #include <southbridge/intel/wildcatpoint/pci_devs.h> #include <southbridge/intel/wildcatpoint/pm.h> #include <southbridge/intel/wildcatpoint/rcba.h> -#include <northbridge/intel/broadwell/romstage.h> +#include <southbridge/intel/wildcatpoint/romstage.h> #include <southbridge/intel/wildcatpoint/smbus.h> #include <southbridge/intel/wildcatpoint/soc_chip.h> diff --git a/src/southbridge/intel/wildcatpoint/early_smbus.c b/src/southbridge/intel/wildcatpoint/early_smbus.c index 6f4d226..0b43cc2 100644 --- a/src/southbridge/intel/wildcatpoint/early_smbus.c +++ b/src/southbridge/intel/wildcatpoint/early_smbus.c @@ -6,7 +6,6 @@ #include <southbridge/intel/wildcatpoint/iomap.h> #include <southbridge/intel/wildcatpoint/pci_devs.h> #include <southbridge/intel/wildcatpoint/smbus.h> -#include <northbridge/intel/broadwell/romstage.h> static const struct reg_script smbus_init_script[] = { /* Set SMBUS I/O base address */ diff --git a/src/southbridge/intel/wildcatpoint/lpc.c b/src/southbridge/intel/wildcatpoint/lpc.c index b7f1fe3..e1b2bec 100644 --- a/src/southbridge/intel/wildcatpoint/lpc.c +++ b/src/southbridge/intel/wildcatpoint/lpc.c @@ -15,6 +15,7 @@ #include <cbmem.h> #include <reg_script.h> #include <string.h> +#include <southbridge/intel/wildcatpoint/acpi.h> #include <southbridge/intel/wildcatpoint/gpio.h> #include <southbridge/intel/wildcatpoint/iobp.h> #include <southbridge/intel/wildcatpoint/iomap.h> @@ -595,6 +596,146 @@ } } +void acpi_init_gnvs(global_nvs_t *gnvs) +{ + /* Set unknown wake source */ + gnvs->pm1i = -1; + + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + +#if CONFIG(CONSOLE_CBMEM) + /* Update the mem console pointer. */ + gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); +#endif + +#if CONFIG(CHROMEOS) + /* Initialize Verified Boot data */ + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); +#if CONFIG(EC_GOOGLE_CHROMEEC) + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; +#endif + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; +#endif +} + +void acpi_fill_in_fadt(acpi_fadt_t *fadt) +{ + const uint16_t pmbase = ACPI_BASE_ADDRESS; + + fadt->sci_int = acpi_sci_irq(); + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + PM2_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS(0); + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 32; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + fadt->x_pm_tmr_blk.addrh = 0x0; + + /* + * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. + * The bit_width field intentionally overflows here. + * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which + * seems to work fine on Linux 5.0 and Windows 10. + */ + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0; + + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; +} + static unsigned long broadwell_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) diff --git a/src/southbridge/intel/wildcatpoint/pch.h b/src/southbridge/intel/wildcatpoint/pch.h index 59b5b18..dfe3560 100644 --- a/src/southbridge/intel/wildcatpoint/pch.h +++ b/src/southbridge/intel/wildcatpoint/pch.h @@ -29,5 +29,6 @@ int pch_is_wpt_ulx(void); u32 pch_read_soft_strap(int id); void pch_disable_devfn(struct device *dev); +void broadwell_pch_enable_dev(struct device *dev); #endif diff --git a/src/southbridge/intel/wildcatpoint/power_state.c b/src/southbridge/intel/wildcatpoint/power_state.c index 8522caa..419fd4e 100644 --- a/src/southbridge/intel/wildcatpoint/power_state.c +++ b/src/southbridge/intel/wildcatpoint/power_state.c @@ -13,7 +13,7 @@ #include <southbridge/intel/wildcatpoint/lpc.h> #include <southbridge/intel/wildcatpoint/pci_devs.h> #include <southbridge/intel/wildcatpoint/pm.h> -#include <northbridge/intel/broadwell/romstage.h> +#include <southbridge/intel/wildcatpoint/romstage.h> static struct chipset_power_state power_state; diff --git a/src/southbridge/intel/wildcatpoint/ramstage.c b/src/southbridge/intel/wildcatpoint/ramstage.c index 8859261..5d8ec0e 100644 --- a/src/southbridge/intel/wildcatpoint/ramstage.c +++ b/src/southbridge/intel/wildcatpoint/ramstage.c @@ -4,6 +4,7 @@ #include <cbmem.h> #include <device/device.h> #include <string.h> +#include <northbridge/intel/broadwell/refcode.h> #include <southbridge/intel/wildcatpoint/nvs.h> #include <southbridge/intel/wildcatpoint/pm.h> #include <southbridge/intel/wildcatpoint/ramstage.h> diff --git a/src/southbridge/intel/wildcatpoint/ramstage.h b/src/southbridge/intel/wildcatpoint/ramstage.h index b50cd19..1343dad 100644 --- a/src/southbridge/intel/wildcatpoint/ramstage.h +++ b/src/southbridge/intel/wildcatpoint/ramstage.h @@ -7,14 +7,6 @@ #include <southbridge/intel/wildcatpoint/soc_chip.h> void broadwell_init_pre_device(void *chip_info); -void broadwell_init_cpus(struct device *dev); -void broadwell_pch_enable_dev(struct device *dev); - -#if CONFIG(HAVE_REFCODE_BLOB) -void broadwell_run_reference_code(void); -#else -static inline void broadwell_run_reference_code(void) { } -#endif extern struct pci_operations broadwell_pci_ops; diff --git a/src/southbridge/intel/wildcatpoint/romstage.h b/src/southbridge/intel/wildcatpoint/romstage.h new file mode 100644 index 0000000..d780e99 --- /dev/null +++ b/src/southbridge/intel/wildcatpoint/romstage.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _WILDCATPOINT_ROMSTAGE_H_ +#define _WILDCATPOINT_ROMSTAGE_H_ + +struct chipset_power_state; +struct chipset_power_state *fill_power_state(void); + +void pch_early_init(void); +void pch_uart_init(void); +void intel_early_me_status(void); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/41942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ae1bd0298bbb5b04787ae5bf14f32b77b47046d Gerrit-Change-Number: 41942 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 7

Change in coreboot[master]: broadwell: Align with haswell
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42620 ) Change subject: broadwell: Align with haswell ...................................................................... broadwell: Align with haswell Tested with BUILD_TIMELESS=1, google/buddy does not change. Change-Id: I2ca9eb464b911325acf32aec63b071c4d9ecf6c0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/broadwell/broadwell_init.c M src/cpu/intel/broadwell/smmrelocate.c M src/northbridge/intel/broadwell/acpi.c M src/northbridge/intel/broadwell/bootblock.c M src/northbridge/intel/broadwell/minihd.c M src/northbridge/intel/broadwell/northbridge.c M src/northbridge/intel/broadwell/report_platform.c M src/southbridge/intel/wildcatpoint/bootblock.c M src/southbridge/intel/wildcatpoint/ehci.c M src/southbridge/intel/wildcatpoint/gpio.c M src/southbridge/intel/wildcatpoint/hda.c M src/southbridge/intel/wildcatpoint/iobp.c M src/southbridge/intel/wildcatpoint/lpc.c M src/southbridge/intel/wildcatpoint/me.c M src/southbridge/intel/wildcatpoint/me_status.c M src/southbridge/intel/wildcatpoint/pch.c M src/southbridge/intel/wildcatpoint/pcie.c M src/southbridge/intel/wildcatpoint/pmutil.c M src/southbridge/intel/wildcatpoint/serialio.c M src/southbridge/intel/wildcatpoint/smbus.c M src/southbridge/intel/wildcatpoint/smi.c M src/southbridge/intel/wildcatpoint/smihandler.c M src/southbridge/intel/wildcatpoint/xhci.c 23 files changed, 457 insertions(+), 477 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/42620/1 diff --git a/src/cpu/intel/broadwell/broadwell_init.c b/src/cpu/intel/broadwell/broadwell_init.c index 2ad6aea..5d26232 100644 --- a/src/cpu/intel/broadwell/broadwell_init.c +++ b/src/cpu/intel/broadwell/broadwell_init.c @@ -431,7 +431,7 @@ /* Clear out pending MCEs */ configure_mca(); - /* Enable the local CPU apics */ + /* Enable the local CPU APICs */ enable_lapic_tpr(); setup_lapic(); diff --git a/src/cpu/intel/broadwell/smmrelocate.c b/src/cpu/intel/broadwell/smmrelocate.c index 2a307ef..5599c0b 100644 --- a/src/cpu/intel/broadwell/smmrelocate.c +++ b/src/cpu/intel/broadwell/smmrelocate.c @@ -12,10 +12,10 @@ #include <cpu/intel/em64t101_save_state.h> #include <cpu/intel/smm_reloc.h> #include <console/console.h> -#include <smp/node.h> -#include <cpu/intel/broadwell/broadwell.h> -#include <southbridge/intel/wildcatpoint/pci_devs.h> #include <northbridge/intel/broadwell/broadwell.h> +#include <southbridge/intel/wildcatpoint/pci_devs.h> +#include <smp/node.h> +#include "broadwell.h" static void update_save_state(int cpu, uintptr_t curr_smbase, @@ -141,6 +141,7 @@ { uintptr_t tseg_base; size_t tseg_size; + u32 prmrr_base; u32 prmrr_size; int phys_bits; @@ -254,11 +255,11 @@ void smm_lock(void) { - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* LOCK the SMM memory window and enable normal SMM. * After running this function, only a full reset can * make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); + pci_write_config8(pcidev_path_on_root(SA_DEVFN_ROOT), SMRAM, + D_LCK | G_SMRAME | C_BASE_SEG); } diff --git a/src/northbridge/intel/broadwell/acpi.c b/src/northbridge/intel/broadwell/acpi.c index df08537..1627074 100644 --- a/src/northbridge/intel/broadwell/acpi.c +++ b/src/northbridge/intel/broadwell/acpi.c @@ -25,8 +25,7 @@ const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1; /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */ - if (igfx_dev && igfx_dev->enabled && gfxvtbar - && gfxvten && !MCHBAR32(GFXVTBAR + 4)) { + if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten && !MCHBAR32(GFXVTBAR + 4)) { unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); @@ -45,16 +44,16 @@ /* VTVC0BAR has to be set, enabled, and in 32-bit space */ if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { + const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, - DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, - 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, + PCH_IOAPIC_PCI_SLOT, 0); + size_t i; for (i = 0; i < 8; ++i) - current += acpi_create_dmar_ds_msi_hpet(current, - 0, PCH_HPET_PCI_BUS, - PCH_HPET_PCI_SLOT, i); + current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, + PCH_HPET_PCI_SLOT, i); acpi_dmar_drhd_fixup(tmp, current); } diff --git a/src/northbridge/intel/broadwell/bootblock.c b/src/northbridge/intel/broadwell/bootblock.c index 89ff992..d661f57 100644 --- a/src/northbridge/intel/broadwell/bootblock.c +++ b/src/northbridge/intel/broadwell/bootblock.c @@ -10,16 +10,14 @@ uint32_t reg; /* - * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to - * to true. That way all subsequent non-explicit config accesses use - * MCFG. This code also assumes that bootblock_northbridge_init() is - * the first thing called in the non-asm boot block code. The final - * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. + * The "io" variant of the config access is explicitly used to setup the PCIEXBAR + * because CONFIG_MMCONF_SUPPORT is set to true. That way, all subsequent + * non-explicit config accesses use MCFG. This code also assumes that + * bootblock_northbridge_init() is the first thing called in the non-asm + * boot block code. The final assumption is that no assembly code is using + * the CONFIG_MMCONF_SUPPORT option to do PCI config acceses. * - * The PCIEXBAR is assumed to live in the memory mapped IO space under - * 4GiB. + * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ reg = 0; pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg); diff --git a/src/northbridge/intel/broadwell/minihd.c b/src/northbridge/intel/broadwell/minihd.c index 7a93b9a..9df1047 100644 --- a/src/northbridge/intel/broadwell/minihd.c +++ b/src/northbridge/intel/broadwell/minihd.c @@ -12,30 +12,30 @@ static const u32 minihd_verb_table[] = { /* coreboot specific header */ - 0x80862808, // Codec Vendor / Device ID: Intel Broadwell Mini-HD - 0x80860101, // Subsystem ID - 0x00000004, // Number of jacks + 0x80862808, /* Codec Vendor / Device ID: Intel Broadwell Mini-HD */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of jacks */ /* Enable 3rd Pin and Converter Widget */ 0x00878101, /* Pin Widget 5 - PORT B */ - 0x00571C10, - 0x00571D00, - 0x00571E56, - 0x00571F18, + 0x00571c10, + 0x00571d00, + 0x00571e56, + 0x00571f18, /* Pin Widget 6 - PORT C */ - 0x00671C20, - 0x00671D00, - 0x00671E56, - 0x00671F18, + 0x00671c20, + 0x00671d00, + 0x00671e56, + 0x00671f18, /* Pin Widget 7 - PORT D */ - 0x00771C30, - 0x00771D00, - 0x00771E56, - 0x00771F18, + 0x00771c30, + 0x00771d00, + 0x00771e56, + 0x00771f18, /* Disable 3rd Pin and Converter Widget */ 0x00878100, @@ -48,8 +48,8 @@ static void minihd_init(struct device *dev) { struct resource *res; - u8 *base; u32 reg32; + u8 *base; int codec_mask, i; /* Find base address */ @@ -80,8 +80,7 @@ if (codec_mask) { for (i = 3; i >= 0; i--) { if (codec_mask & (1 << i)) - hda_codec_init(base, i, - sizeof(minihd_verb_table), + hda_codec_init(base, i, sizeof(minihd_verb_table), minihd_verb_table); } } @@ -92,10 +91,10 @@ } static struct device_operations minihd_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .init = &minihd_init, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = minihd_init, .ops_pci = &broadwell_pci_ops, }; diff --git a/src/northbridge/intel/broadwell/northbridge.c b/src/northbridge/intel/broadwell/northbridge.c index 5122fed..dab541a 100644 --- a/src/northbridge/intel/broadwell/northbridge.c +++ b/src/northbridge/intel/broadwell/northbridge.c @@ -16,8 +16,7 @@ #include <southbridge/intel/wildcatpoint/ramstage.h> #include <northbridge/intel/broadwell/broadwell.h> -static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, - u32 *len) +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; @@ -52,35 +51,31 @@ static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { - u32 bar; + u32 bar = pci_read_config32(dev, index); - bar = pci_read_config32(dev, index); - - /* If not enabled don't report it. */ + /* If not enabled don't report it */ if (!(bar & 0x1)) return 0; - /* Knock down the enable bit. */ + /* Knock down the enable bit */ *base = bar & ~1; return 1; } -/* There are special BARs that actually are programmed in the MCHBAR. These - * Intel special features, but they do consume resources that need to be - * accounted for. */ -static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, - u32 *len) +/* + * There are special BARs that actually are programmed in the MCHBAR. These Intel special + * features, but they do consume resources that need to be accounted for. + */ +static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) { - u32 bar; + u32 bar = MCHBAR32(index); - bar = MCHBAR32(index); - - /* If not enabled don't report it. */ + /* If not enabled don't report it */ if (!(bar & 0x1)) return 0; - /* Knock down the enable bit. */ + /* Knock down the enable bit */ *base = bar & ~1; return 1; @@ -89,8 +84,7 @@ struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(struct device *dev, unsigned int index, - u32 *base, u32 *size); + int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); const char *description; }; @@ -103,10 +97,7 @@ { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" }, }; -/* - * Add all known fixed MMIO ranges that hang off the host bridge/memory - * controller device. - */ +/* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */ static void mc_add_fixed_mmio_resources(struct device *dev) { int i; @@ -119,14 +110,13 @@ size = mc_fixed_resources[i].size; index = mc_fixed_resources[i].index; - if (!mc_fixed_resources[i].get_resource(dev, index, - &base, &size)) + if (!mc_fixed_resources[i].get_resource(dev, index, &base, &size)) continue; resource = new_resource(dev, mc_fixed_resources[i].index); - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; + resource->base = base; resource->size = size; printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", @@ -151,10 +141,10 @@ * | Usage DRAM | * +--------------------------+ 0 * - * Some of the base registers above can be equal making the size of those - * regions 0. The reason is because the memory controller internally subtracts - * the base registers from each other to determine sizes of the regions. In - * other words, the memory map is in a fixed order no matter what. + * Some of the base registers above can be equal, making the size of the regions within 0. + * This is because the memory controller internally subtracts the base registers from each + * other to determine sizes of the regions. In other words, the memory map regions are always + * in a fixed order, no matter what sizes they have. */ struct map_entry { @@ -164,14 +154,13 @@ const char *description; }; -static void read_map_entry(struct device *dev, struct map_entry *entry, - uint64_t *result) +static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) { uint64_t value; uint64_t mask; - /* All registers are on a 1MiB granularity. */ - mask = ((1ULL<<20)-1); + /* All registers have a 1MiB granularity */ + mask = ((1ULL << 20) - 1); mask = ~mask; value = 0; @@ -198,12 +187,9 @@ .description = desc_, \ } -#define MAP_ENTRY_BASE_64(reg_, desc_) \ - MAP_ENTRY(reg_, 1, 0, desc_) -#define MAP_ENTRY_LIMIT_64(reg_, desc_) \ - MAP_ENTRY(reg_, 1, 1, desc_) -#define MAP_ENTRY_BASE_32(reg_, desc_) \ - MAP_ENTRY(reg_, 0, 0, desc_) +#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_) +#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_) +#define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_) enum { TOM_REG, @@ -216,28 +202,29 @@ BGSM_REG, BDSM_REG, TSEG_REG, - // Must be last. - NUM_MAP_ENTRIES + /* Must be last */ + NUM_MAP_ENTRIES, }; static struct map_entry memory_map[NUM_MAP_ENTRIES] = { - [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), - [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), - [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), + [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), + [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), + [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), - [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), + [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), - [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), - [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), - [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), - [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), + [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), + [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), + [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), + [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), /* FIXME: typo */ }; static void mc_read_map_entries(struct device *dev, uint64_t *values) { int i; - for (i = 0; i < NUM_MAP_ENTRIES; i++) + for (i = 0; i < NUM_MAP_ENTRIES; i++) { read_map_entry(dev, &memory_map[i], &values[i]); + } } static void mc_report_map_entries(struct device *dev, uint64_t *values) @@ -247,22 +234,20 @@ printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", memory_map[i].description, values[i]); } - /* One can validate the BDSM and BGSM against the GGC. */ + /* One can validate the BDSM and BGSM against the GGC */ printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); } static void mc_add_dram_resources(struct device *dev, int *resource_cnt) { - unsigned long base_k, size_k; - unsigned long touud_k; - unsigned long index; + unsigned long base_k, size_k, touud_k, index; struct resource *resource; uint64_t mc_values[NUM_MAP_ENTRIES]; unsigned long dpr_size = 0; u32 dpr_reg; struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* Read in the MAP registers and report their values. */ + /* Read in the MAP registers and report their values */ mc_read_map_entries(dev, &mc_values[0]); mc_report_map_entries(dev, &mc_values[0]); @@ -280,33 +265,29 @@ /* * These are the host memory ranges that should be added: - * - 0 -> 0xa0000: cacheable - * - 0xc0000 -> TSEG : cacheable - * - TESG -> BGSM: cacheable with standard MTRRs and reserved - * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved - * - 4GiB -> TOUUD: cacheable + * - 0 -> 0xa0000: cacheable + * - 0xc0000 -> TSEG: cacheable + * - TSEG -> BGSM: cacheable with standard MTRRs and reserved + * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved + * - 4GiB -> TOUUD: cacheable * - * The default SMRAM space is reserved so that the range doesn't - * have to be saved during S3 Resume. Once marked reserved the OS - * cannot use the memory. This is a bit of an odd place to reserve - * the region, but the CPU devices don't have dev_ops->read_resources() - * called on them. + * The default SMRAM space is reserved so that the range doesn't have to be saved + * during S3 Resume. Once marked reserved the OS cannot use the memory. This is a + * bit of an odd place to reserve the region, but the CPU devices don't have + * dev_ops->read_resources() called on them. * - * The range 0xa0000 -> 0xc0000 does not have any resources - * associated with it to handle legacy VGA memory. If this range - * is not omitted the mtrr code will setup the area as cacheable - * causing VGA access to not work. + * The range 0xa0000 -> 0xc0000 does not have any resources associated with it to + * handle legacy VGA memory. If this range is not omitted the mtrr code will setup + * the area as cacheable, causing VGA access to not work. * - * The TSEG region is mapped as cacheable so that one can perform - * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes - * precedence over the existing MTRRs covering this region. + * The TSEG region is mapped as cacheable so that one can perform SMRAM relocation + * faster. Once the SMRR is enabled, the SMRR takes precedence over the existing + * MTRRs covering this region. * - * It should be noted that cacheable entry types need to be added in - * order. The reason is that the current MTRR code assumes this and - * falls over itself if it isn't. + * It should be noted that cacheable entry types need to be added in order. The reason + * is that the current MTRR code assumes this and falls over itself if it isn't. * - * The resource index starts low and should not meet or exceed - * PCI_BASE_ADDRESS_0. + * The resource index starts low and should not meet or exceed PCI_BASE_ADDRESS_0. */ index = *resource_cnt; @@ -346,12 +327,11 @@ /* Reserve everything between A segment and 1MB: * - * 0xa0000 - 0xbffff: legacy VGA + * 0xa0000 - 0xbffff: Legacy VGA * 0xc0000 - 0xfffff: RAM */ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); - reserved_ram_resource(dev, index++, (0xc0000 >> 10), - (0x100000 - 0xc0000) >> 10); + reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); if (CONFIG(CHROMEOS)) chromeos_reserve_ram_oops(dev, index++); @@ -359,27 +339,24 @@ *resource_cnt = index; } -static void systemagent_read_resources(struct device *dev) +static void mc_read_resources(struct device *dev) { int index = 0; - const bool vtd_capable = - !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); + const bool vtd_capable = !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); - /* Read standard PCI resources. */ + /* Read standard PCI resources */ pci_dev_read_resources(dev); - /* Add all fixed MMIO resources. */ + /* Add all fixed MMIO resources */ mc_add_fixed_mmio_resources(dev); - /* Add VT-d MMIO resources if capable */ + /* Add VT-d MMIO resources, if capable */ if (vtd_capable) { - mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, - GFXVT_BASE_SIZE / KiB); - mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, - VTVC0_BASE_SIZE / KiB); + mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB); + mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB); } - /* Calculate and add DRAM resources. */ + /* Calculate and add DRAM resources */ mc_add_dram_resources(dev, &index); } @@ -395,7 +372,7 @@ MCHBAR8(MCH_PAIR) = pair; /* - * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU + * Set bits 0 + 1 of BIOS_RESET_CPL to indicate to the CPU * that BIOS has initialized memory and power management */ bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); @@ -410,7 +387,7 @@ } static struct device_operations systemagent_ops = { - .read_resources = systemagent_read_resources, + .read_resources = mc_read_resources, .acpi_fill_ssdt = generate_cpu_entries, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, diff --git a/src/northbridge/intel/broadwell/report_platform.c b/src/northbridge/intel/broadwell/report_platform.c index 95d9c99..c963081 100644 --- a/src/northbridge/intel/broadwell/report_platform.c +++ b/src/northbridge/intel/broadwell/report_platform.c @@ -85,7 +85,7 @@ strcpy(cpu_string, "Platform info not available"); } else { u32 *p = (u32 *)cpu_string; - for (i = 2; i <= 4 ; i++) { + for (i = 2; i <= 4; i++) { cpuidr = cpuid(index + i); *p++ = cpuidr.eax; *p++ = cpuidr.ebx; diff --git a/src/southbridge/intel/wildcatpoint/bootblock.c b/src/southbridge/intel/wildcatpoint/bootblock.c index 572ea09..55bb1c3 100644 --- a/src/southbridge/intel/wildcatpoint/bootblock.c +++ b/src/southbridge/intel/wildcatpoint/bootblock.c @@ -31,7 +31,7 @@ static void enable_port80_on_lpc(void) { /* Enable port 80 POST on LPC. The chipset does this by default, - * but it doesn't appear to hurt anything. */ + but it doesn't appear to hurt anything. */ u32 gcs = RCBA32(GCS); gcs = gcs & ~0x4; RCBA32(GCS) = gcs; diff --git a/src/southbridge/intel/wildcatpoint/ehci.c b/src/southbridge/intel/wildcatpoint/ehci.c index 81ad62d..566b70f 100644 --- a/src/southbridge/intel/wildcatpoint/ehci.c +++ b/src/southbridge/intel/wildcatpoint/ehci.c @@ -8,8 +8,7 @@ #include <southbridge/intel/wildcatpoint/ehci.h> #include <southbridge/intel/wildcatpoint/pch.h> -static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) { u8 access_cntl; diff --git a/src/southbridge/intel/wildcatpoint/gpio.c b/src/southbridge/intel/wildcatpoint/gpio.c index 62a7335..b0c0476 100644 --- a/src/southbridge/intel/wildcatpoint/gpio.c +++ b/src/southbridge/intel/wildcatpoint/gpio.c @@ -13,19 +13,19 @@ * this GPIO maps to. If this is not a PIRQ capable GPIO then * it will return -1. The GPIO to PIRQ mapping is not linear. */ -static int gpio_to_pirq(int gpio) +static int lp_gpio_to_pirq(int gpio) { switch (gpio) { - case 8: return 0; /* PIRQI */ - case 9: return 1; /* PIRQJ */ - case 10: return 2; /* PIRQK */ - case 13: return 3; /* PIRQL */ - case 14: return 4; /* PIRQM */ - case 45: return 5; /* PIRQN */ - case 46: return 6; /* PIRQO */ - case 47: return 7; /* PIRQP */ - case 48: return 8; /* PIRQQ */ - case 49: return 9; /* PIRQR */ + case 8: return 0; /* PIRQI */ + case 9: return 1; /* PIRQJ */ + case 10: return 2; /* PIRQK */ + case 13: return 3; /* PIRQL */ + case 14: return 4; /* PIRQM */ + case 45: return 5; /* PIRQN */ + case 46: return 6; /* PIRQO */ + case 47: return 7; /* PIRQP */ + case 48: return 8; /* PIRQQ */ + case 49: return 9; /* PIRQR */ case 50: return 10; /* PIRQS */ case 51: return 11; /* PIRQT */ case 52: return 12; /* PIRQU */ @@ -36,9 +36,10 @@ }; } -void init_gpios(const struct gpio_config config[]) +void init_gpios(const struct gpio_config map[]) { - const struct gpio_config *entry; + const u16 gpio_base = GPIO_BASE_ADDRESS; + const struct gpio_config *config; u32 owner[3] = {0}; u32 route[3] = {0}; u32 irqen[3] = {0}; @@ -47,56 +48,58 @@ u16 pirq2apic = 0; int set, bit, gpio = 0; - for (entry = config; entry->conf0 != GPIO_LIST_END; entry++, gpio++) { + for (config = map; config->conf0 != GPIO_LIST_END; config++, gpio++) { if (gpio > MAX_GPIO_NUMBER) break; /* Setup Configuration registers 1 and 2 */ - outl(entry->conf0, GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio)); - outl(entry->conf1, GPIO_BASE_ADDRESS + GPIO_CONFIG1(gpio)); + outl(config->conf0, gpio_base + GPIO_CONFIG0(gpio)); + outl(config->conf1, gpio_base + GPIO_CONFIG1(gpio)); /* Determine set and bit based on GPIO number */ set = gpio >> 5; bit = gpio % 32; /* Apply settings to set specific bits */ - owner[set] |= entry->owner << bit; - route[set] |= entry->route << bit; - irqen[set] |= entry->irqen << bit; - reset[set] |= entry->reset << bit; + owner[set] |= config->owner << bit; + route[set] |= config->route << bit; + irqen[set] |= config->irqen << bit; + reset[set] |= config->reset << bit; if (set == 0) - blink |= entry->blink << bit; + blink |= config->blink << bit; /* PIRQ to IO-APIC map */ - if (entry->pirq == GPIO_PIRQ_APIC_ROUTE) { - set = gpio_to_pirq(gpio); + if (config->pirq == GPIO_PIRQ_APIC_ROUTE) { + set = lp_gpio_to_pirq(gpio); if (set >= 0) pirq2apic |= 1 << set; } } for (set = 0; set <= 2; set++) { - outl(owner[set], GPIO_BASE_ADDRESS + GPIO_OWNER(set)); - outl(route[set], GPIO_BASE_ADDRESS + GPIO_ROUTE(set)); - outl(irqen[set], GPIO_BASE_ADDRESS + GPIO_IRQ_IE(set)); - outl(reset[set], GPIO_BASE_ADDRESS + GPIO_RESET(set)); + outl(owner[set], gpio_base + GPIO_OWNER(set)); + outl(route[set], gpio_base + GPIO_ROUTE(set)); + outl(irqen[set], gpio_base + GPIO_IRQ_IE(set)); + outl(reset[set], gpio_base + GPIO_RESET(set)); } - outl(blink, GPIO_BASE_ADDRESS + GPIO_BLINK); - outl(pirq2apic, GPIO_BASE_ADDRESS + GPIO_PIRQ_APIC_EN); + outl(blink, gpio_base + GPIO_BLINK); + outl(pirq2apic, gpio_base + GPIO_PIRQ_APIC_EN); } int get_gpio(int gpio_num) { + const u16 gpio_base = GPIO_BASE_ADDRESS; + if (gpio_num > MAX_GPIO_NUMBER) return 0; - return !!(inl(GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL); + return !!(inl(gpio_base + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL); } /* - * get a number comprised of multiple GPIO values. gpio_num_array points to + * Get a number comprised of multiple GPIO values. gpio_num_array points to * the array of gpio pin numbers to scan, terminated by -1. */ unsigned int get_gpios(const int *gpio_num_array) @@ -116,15 +119,16 @@ void set_gpio(int gpio_num, int value) { + const u16 gpio_base = GPIO_BASE_ADDRESS; u32 conf0; if (gpio_num > MAX_GPIO_NUMBER) return; - conf0 = inl(GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)); + conf0 = inl(gpio_base + GPIO_CONFIG0(gpio_num)); conf0 &= ~GPO_LEVEL_MASK; conf0 |= value << GPO_LEVEL_SHIFT; - outl(conf0, GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)); + outl(conf0, gpio_base + GPIO_CONFIG0(gpio_num)); } int gpio_is_native(int gpio_num) diff --git a/src/southbridge/intel/wildcatpoint/hda.c b/src/southbridge/intel/wildcatpoint/hda.c index 0dbe6cd..68e180d 100644 --- a/src/southbridge/intel/wildcatpoint/hda.c +++ b/src/southbridge/intel/wildcatpoint/hda.c @@ -2,16 +2,22 @@ #include <console/console.h> #include <device/device.h> -#include <device/azalia_device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/mmio.h> +#include <device/azalia_device.h> #include <soc/intel/common/hda_verb.h> #include <southbridge/intel/wildcatpoint/pch.h> #include <southbridge/intel/wildcatpoint/ramstage.h> #include <southbridge/intel/wildcatpoint/rcba.h> +/* FIXME: For alignment with Haswell only */ +static inline bool pch_is_lp(void) +{ + return true; +} + static void codecs_init(u8 *base, u32 codec_mask) { int i; @@ -19,27 +25,31 @@ /* Can support up to 4 codecs */ for (i = 3; i >= 0; i--) { if (codec_mask & (1 << i)) - hda_codec_init(base, i, - cim_verb_data_size, - cim_verb_data); + hda_codec_init(base, i, cim_verb_data_size, cim_verb_data); } if (pc_beep_verbs_size) hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs); } -static void hda_pch_init(struct device *dev, u8 *base) +static void azalia_pch_init(struct device *dev, u8 *base) { u8 reg8; u16 reg16; u32 reg32; - if (RCBA32(0x2030) & (1 << 31)) { + if (RCBA32(0x2030) & (1UL << 31)) { reg32 = pci_read_config32(dev, 0x120); reg32 &= 0xf8ffff01; reg32 |= (1 << 25); reg32 |= RCBA32(0x2030) & 0xfe; pci_write_config32(dev, 0x120, reg32); + + if (!pch_is_lp()) { + reg16 = pci_read_config16(dev, 0x78); + reg16 &= ~(1 << 11); + pci_write_config16(dev, 0x78, reg16); + } } else printk(BIOS_DEBUG, "HDA: V1CTL disabled.\n"); @@ -48,37 +58,66 @@ pci_write_config32(dev, 0x114, reg32); // Set VCi enable bit - if (pci_read_config32(dev, 0x120) & ((1 << 24) | - (1 << 25) | (1 << 26))) { + if (pci_read_config32(dev, 0x120) & ((1 << 24) | (1 << 25) | (1 << 26))) { reg32 = pci_read_config32(dev, 0x120); - reg32 &= ~(1 << 31); + if (pch_is_lp()) + reg32 &= ~(1UL << 31); + else + reg32 |= (1UL << 31); pci_write_config32(dev, 0x120, reg32); } + /* FIXME: Haswell does this, but we don't on Broadwell, c.f. hda_enable() */ +#if 0 + reg8 = pci_read_config8(dev, 0x43); + if (pch_is_lp()) + reg8 &= ~(1 << 6); + else + reg8 |= (1 << 4); + pci_write_config8(dev, 0x43, reg8); +#endif + + if (!pch_is_lp()) { + reg32 = pci_read_config32(dev, 0xc0); + reg32 |= (1 << 17); + pci_write_config32(dev, 0xc0, reg32); + } + /* Additional programming steps */ reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 24); + if (pch_is_lp()) + reg32 |= (1 << 24); + else + reg32 |= (1 << 14); pci_write_config32(dev, 0xc4, reg32); + if (!pch_is_lp()) { + reg32 = pci_read_config32(dev, 0xd0); + reg32 &= ~(1UL << 31); + pci_write_config32(dev, 0xd0, reg32); + } + reg8 = pci_read_config8(dev, 0x40); // Audio Control - reg8 |= 1; // Select HDA mode + reg8 |= 1; // Select Azalia mode pci_write_config8(dev, 0x40, reg8); reg8 = pci_read_config8(dev, 0x4d); // Docking Status reg8 &= ~(1 << 7); // Docking not supported pci_write_config8(dev, 0x4d, reg8); - reg16 = read32(base + 0x0012); - reg16 |= (1 << 0); - write32(base + 0x0012, reg16); + if (pch_is_lp()) { + reg16 = read32(base + 0x0012); + reg16 |= (1 << 0); + write32(base + 0x0012, reg16); - /* disable Auto Voltage Detector */ - reg8 = pci_read_config8(dev, 0x42); - reg8 |= (1 << 2); - pci_write_config8(dev, 0x42, reg8); + /* disable Auto Voltage Detector */ + reg8 = pci_read_config8(dev, 0x42); + reg8 |= (1 << 2); + pci_write_config8(dev, 0x42, reg8); + } } -static void hda_init(struct device *dev) +static void azalia_init(struct device *dev) { u8 *base; struct resource *res; @@ -95,7 +134,7 @@ /* Set Bus Master */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); - hda_pch_init(dev, base); + azalia_pch_init(dev, base); codec_mask = hda_codec_detect(base); @@ -134,11 +173,11 @@ } static struct device_operations hda_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .init = &hda_init, - .enable = &hda_enable, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = azalia_init, + .enable = hda_enable, .ops_pci = &broadwell_pci_ops, }; diff --git a/src/southbridge/intel/wildcatpoint/iobp.c b/src/southbridge/intel/wildcatpoint/iobp.c index 3332e26..72cb111 100644 --- a/src/southbridge/intel/wildcatpoint/iobp.c +++ b/src/southbridge/intel/wildcatpoint/iobp.c @@ -91,8 +91,12 @@ /* Check for successful transaction */ status = RCBA16(IOBPS); - if (status & IOBPS_TX_MASK) + if (status & IOBPS_TX_MASK) { printk(BIOS_ERR, "IOBP: write 0x%08x failed\n", address); + //return; + } + + //printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data); } void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) diff --git a/src/southbridge/intel/wildcatpoint/lpc.c b/src/southbridge/intel/wildcatpoint/lpc.c index 47d3e8f..11c962d 100644 --- a/src/southbridge/intel/wildcatpoint/lpc.c +++ b/src/southbridge/intel/wildcatpoint/lpc.c @@ -4,11 +4,11 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include <option.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> #include <arch/io.h> -#include <device/pci_ops.h> #include <arch/ioapic.h> #include <acpi/acpi.h> #include <cpu/x86/smm.h> @@ -31,6 +31,17 @@ #include <acpi/acpigen.h> #include <southbridge/intel/common/rtc.h> +/* FIXME: For alignment with Haswell only */ +static inline bool pch_is_lp(void) +{ + return true; +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ static void pch_enable_ioapic(struct device *dev) { u32 reg32; @@ -43,11 +54,11 @@ /* affirm full set of redirection table entries ("write once") */ reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); - - /* PCH-LP has 39 redirection entries */ - reg32 &= ~0x00ff0000; - reg32 |= 0x00270000; - + if (pch_is_lp()) { + /* PCH-LP has 39 redirection entries */ + reg32 &= ~0x00ff0000; + reg32 |= 0x00270000; + } io_apic_write(VIO_APIC_VADDR, 0x01, reg32); /* @@ -67,7 +78,8 @@ PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i); } -/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control +/* + * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved * 0x01 - 0001 = Reserved * 0x02 - 0010 = Reserved @@ -103,6 +115,11 @@ pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); + /* + * Eric Biederman once said we should let the OS do this. + * I am not so sure anymore he was right. + */ + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin = 0, int_line = 0; @@ -112,18 +129,10 @@ int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); switch (int_pin) { - case 1: /* INTA# */ - int_line = config->pirqa_routing; - break; - case 2: /* INTB# */ - int_line = config->pirqb_routing; - break; - case 3: /* INTC# */ - int_line = config->pirqc_routing; - break; - case 4: /* INTD# */ - int_line = config->pirqd_routing; - break; + case 1: /* INTA# */ int_line = config->pirqa_routing; break; + case 2: /* INTB# */ int_line = config->pirqb_routing; break; + case 3: /* INTC# */ int_line = config->pirqc_routing; break; + case 4: /* INTD# */ int_line = config->pirqd_routing; break; } if (!int_line) @@ -141,7 +150,8 @@ config_t *config = config_of(dev); int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; - /* Which state do we want to goto after g3 (power restored)? + /* + * Which state do we want to go to after G3 (power restored)? * 0 == S0 Full On * 1 == S5 Soft Off * @@ -411,9 +421,8 @@ static void pch_set_acpi_mode(void) { - if (!acpi_is_wakeup_s3()) { + if (!acpi_is_wakeup_s3()) apm_control(APM_CNT_ACPI_DISABLE); - } } static void lpc_init(struct device *dev) @@ -500,8 +509,7 @@ * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, - int index) +static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index) { struct resource *res; @@ -514,12 +522,11 @@ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, - int index) +static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index) { /* * Check if the register is enabled. If so and the base exceeds the - * device's default claim range add the resource. + * device's default, claim range and add the resource. */ if (reg_value & 1) { u16 base = reg_value & 0xfffc; @@ -540,8 +547,7 @@ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* GPIOBASE */ - pch_lpc_add_io_resource(dev, GPIO_BASE_ADDRESS, - GPIO_BASE_SIZE, GPIO_BASE); + pch_lpc_add_io_resource(dev, GPIO_BASE_ADDRESS, GPIO_BASE_SIZE, GPIO_BASE); /* PMBASE */ pch_lpc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, PMBASE); @@ -572,7 +578,7 @@ memset(gnvs, 0, sizeof(global_nvs_t)); } -static void southcluster_inject_dsdt(const struct device *device) +static void southbridge_inject_dsdt(const struct device *device) { global_nvs_t *gnvs; @@ -641,13 +647,23 @@ fadt->gpe0_blk = pmbase + GPE0_STS(0); fadt->gpe1_blk = 0; - fadt->pm1_evt_len = 4; + /* + * Some of the lengths here are doubled. This is because they describe + * blocks containing two registers, where the size of each register + * is found by halving the block length. See Table 5-34 and section + * 4.8.3 of the ACPI specification for details. + */ + fadt->pm1_evt_len = 2 * 2; fadt->pm1_cnt_len = 2; fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 32; + if (pch_is_lp()) + fadt->gpe0_blk_len = 2 * 16; + else + fadt->gpe0_blk_len = 2 * 8; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; + fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; fadt->flush_size = 1024; @@ -659,55 +675,60 @@ fadt->century = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + fadt->flags = ACPI_FADT_WBINVD | + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_PLATFORM_CLOCK; - fadt->reset_reg.space_id = 1; + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->reset_reg.addrl = 0xcf9; fadt->reset_reg.addrh = 0; + fadt->reset_value = 6; - fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; fadt->x_pm1a_evt_blk.addrh = 0x0; - fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1b_evt_blk.bit_width = 0; fadt->x_pm1b_evt_blk.bit_offset = 0; fadt->x_pm1b_evt_blk.access_size = 0; fadt->x_pm1b_evt_blk.addrl = 0x0; fadt->x_pm1b_evt_blk.addrh = 0x0; - fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1b_cnt_blk.bit_width = 0; fadt->x_pm1b_cnt_blk.bit_offset = 0; fadt->x_pm1b_cnt_blk.access_size = 0; fadt->x_pm1b_cnt_blk.addrl = 0x0; fadt->x_pm1b_cnt_blk.addrh = 0x0; - fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; @@ -725,10 +746,9 @@ fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0; + fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe1_blk.bit_width = 0; fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.access_size = 0; @@ -736,9 +756,9 @@ fadt->x_gpe1_blk.addrh = 0x0; } -static unsigned long broadwell_write_acpi_tables(const struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp) +static unsigned long southbridge_write_acpi_tables(const struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp) { if (CONFIG(INTEL_PCH_UART_CONSOLE)) current = acpi_write_dbg2_pci_uart(rsdp, current, @@ -749,13 +769,13 @@ } static struct device_operations device_ops = { - .read_resources = &pch_lpc_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .acpi_inject_dsdt = southcluster_inject_dsdt, - .write_acpi_tables = broadwell_write_acpi_tables, - .init = &lpc_init, - .scan_bus = &scan_static_bus, + .read_resources = pch_lpc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .acpi_inject_dsdt = southbridge_inject_dsdt, + .write_acpi_tables = southbridge_write_acpi_tables, + .init = lpc_init, + .scan_bus = scan_static_bus, .ops_pci = &broadwell_pci_ops, }; diff --git a/src/southbridge/intel/wildcatpoint/me.c b/src/southbridge/intel/wildcatpoint/me.c index 3b1998e..9520d13 100644 --- a/src/southbridge/intel/wildcatpoint/me.c +++ b/src/southbridge/intel/wildcatpoint/me.c @@ -82,7 +82,6 @@ /* * ME/MEI access helpers using memcpy to avoid aliasing. */ - static inline void mei_read_dword_ptr(void *ptr, int offset) { u32 dword = read32(mei_base_address + offset); @@ -264,8 +263,8 @@ return 0; } -static int mei_send_header(u8 me_address, u8 host_address, - void *header, int header_len, int complete) +static int mei_send_header(u8 me_address, u8 host_address, void *header, int header_len, + int complete) { struct mei_header mei = { .client_address = me_address, @@ -276,8 +275,7 @@ return mei_send_packet(&mei, header); } -static int mei_recv_msg(void *header, int header_bytes, - void *rsp_data, int rsp_bytes) +static int mei_recv_msg(void *header, int header_bytes, void *rsp_data, int rsp_bytes) { struct mei_header mei_rsp; struct mei_csr me, host; @@ -336,8 +334,8 @@ /* Make sure caller passed a buffer with enough space */ if (ndata != (rsp_bytes >> 2)) { - printk(BIOS_ERR, "ME: not enough room in response buffer: " - "%u != %u\n", ndata, rsp_bytes >> 2); + printk(BIOS_ERR, "ME: not enough room in response buffer: %u != %u\n", + ndata, rsp_bytes >> 2); return -1; } @@ -376,8 +374,7 @@ return 0; /* Read header and data */ - if (mei_recv_msg(&mkhi_rsp, sizeof(mkhi_rsp), - rsp_data, rsp_bytes) < 0) + if (mei_recv_msg(&mkhi_rsp, sizeof(mkhi_rsp), rsp_data, rsp_bytes) < 0) return -1; if (!mkhi_rsp.is_response || @@ -434,7 +431,7 @@ } /* - * mbp clear routine. This will wait for the ME to indicate that + * MBP clear routine. This will wait for the ME to indicate that * the MBP has been read and cleared. */ static void intel_me_mbp_clear(struct device *dev) @@ -487,8 +484,7 @@ }; /* Send request and wait for response */ - if (mei_sendrecv_mkhi(&mkhi, &rule_id, sizeof(u32), - &cap_msg, sizeof(cap_msg)) < 0) { + if (mei_sendrecv_mkhi(&mkhi, &rule_id, sizeof(u32), &cap_msg, sizeof(cap_msg)) < 0) { printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); return -1; } @@ -507,20 +503,20 @@ return; } - print_cap("Full Network manageability", cap->full_net); - print_cap("Regular Network manageability", cap->std_net); - print_cap("Manageability", cap->manageability); - print_cap("IntelR Anti-Theft (AT)", cap->intel_at); - print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); - print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); - print_cap("ICC Over Clocking", cap->icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap->pavp); - print_cap("IPV6", cap->ipv6); - print_cap("KVM Remote Control (KVM)", cap->kvm); - print_cap("Outbreak Containment Heuristic (OCH)", cap->och); - print_cap("Virtual LAN (VLAN)", cap->vlan); - print_cap("TLS", cap->tls); - print_cap("Wireless LAN (WLAN)", cap->wlan); + print_cap("Full Network manageability", cap->full_net); + print_cap("Regular Network manageability", cap->std_net); + print_cap("Manageability", cap->manageability); + print_cap("IntelR Anti-Theft (AT)", cap->intel_at); + print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); + print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); + print_cap("ICC Over Clocking", cap->icc_over_clocking); + print_cap("Protected Audio Video Path (PAVP)", cap->pavp); + print_cap("IPV6", cap->ipv6); + print_cap("KVM Remote Control (KVM)", cap->kvm); + print_cap("Outbreak Containment Heuristic (OCH)", cap->och); + print_cap("Virtual LAN (VLAN)", cap->vlan); + print_cap("TLS", cap->tls); + print_cap("Wireless LAN (WLAN)", cap->wlan); } /* Send END OF POST message to the ME */ @@ -602,13 +598,12 @@ u16 reg16; /* S3 path will have hidden this device already */ - if (!mei_base_address || mei_base_address == (u8 *) 0xfffffff0) + if (!mei_base_address || mei_base_address == (u8 *)0xfffffff0) return; /* Make sure IO is disabled */ reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); pci_write_config16(dev, PCI_COMMAND, reg16); /* Hide the PCI device */ @@ -634,6 +629,7 @@ printk(BIOS_ERR, "ME: ICC SET CLOCK ENABLES message failed\n"); return -1; } + printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask); return 0; } diff --git a/src/southbridge/intel/wildcatpoint/me_status.c b/src/southbridge/intel/wildcatpoint/me_status.c index d11b26c..fc65fc9 100644 --- a/src/southbridge/intel/wildcatpoint/me_status.c +++ b/src/southbridge/intel/wildcatpoint/me_status.c @@ -47,7 +47,7 @@ [ME_HFS_STATE_M3] = "M3 without UMA", [ME_HFS_STATE_M0] = "M0 without UMA", [ME_HFS_STATE_BRINGUP] = "Bring up", - [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" + [ME_HFS_STATE_ERROR] = "M0 without UMA but with error", }; /* HFS[19:16] Current Operation Mode Values */ @@ -56,7 +56,7 @@ [ME_HFS_MODE_DEBUG] = "Debug", [ME_HFS_MODE_DIS] = "Soft Temporary Disable", [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", - [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" + [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message", }; /* HFS[15:12] Error Code Values */ @@ -64,7 +64,7 @@ [ME_HFS_ERROR_NONE] = "No Error", [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", [ME_HFS_ERROR_IMAGE] = "Image Failure", - [ME_HFS_ERROR_DEBUG] = "Debug Failure" + [ME_HFS_ERROR_DEBUG] = "Debug Failure", }; /* HFS2[31:28] ME Progress Code */ @@ -75,121 +75,78 @@ [ME_HFS2_PHASE_POLICY] = "Policy Module", [ME_HFS2_PHASE_MODULE_LOAD] = "Module Loading", [ME_HFS2_PHASE_UNKNOWN] = "Unknown", - [ME_HFS2_PHASE_HOST_COMM] = "Host Communication" + [ME_HFS2_PHASE_HOST_COMM] = "Host Communication", }; /* HFS2[27:24] Power Management Event */ static const char *me_pmevent_values[] = { - [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = - "Clean Moff->Mx wake", - [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = - "Moff->Mx wake after an error", - [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = - "Clean global reset", - [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = - "Global reset after an error", - [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = - "Clean Intel ME reset", - [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = - "Intel ME reset due to exception", - [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = - "Pseudo-global reset", - [ME_HFS2_PMEVENT_S0MO_SXM3] = - "S0/M0->Sx/M3", - [ME_HFS2_PMEVENT_SXM3_S0M0] = - "Sx/M3->S0/M0", - [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = - "Non-power cycle reset", - [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = - "Power cycle reset through M3", - [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = - "Power cycle reset through Moff", - [ME_HFS2_PMEVENT_SXMX_SXMOFF] = - "Sx/Mx->Sx/Moff" + [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = "Clean Moff->Mx wake", + [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = "Moff->Mx wake after an error", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = "Clean global reset", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = "Global reset after an error", + [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = "Clean Intel ME reset", + [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = "Intel ME reset due to exception", + [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = "Pseudo-global reset", + [ME_HFS2_PMEVENT_S0MO_SXM3] = "S0/M0->Sx/M3", + [ME_HFS2_PMEVENT_SXM3_S0M0] = "Sx/M3->S0/M0", + [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = "Non-power cycle reset", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = "Power cycle reset through M3", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = "Power cycle reset through Moff", + [ME_HFS2_PMEVENT_SXMX_SXMOFF] = "Sx/Mx->Sx/Moff", }; /* Progress Code 0 states */ static const char *me_progress_rom_values[] = { - [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN", - [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE" + [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN", + [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE", }; /* Progress Code 1 states */ static const char *me_progress_bup_values[] = { - [ME_HFS2_STATE_BUP_INIT] = - "Initialization starts", - [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = - "Disable the host wake event", - [ME_HFS2_STATE_BUP_FLOW_DET] = - "Flow determination start process", - [ME_HFS2_STATE_BUP_VSCC_ERR] = - "Error reading/matching the VSCC table in the descriptor", - [ME_HFS2_STATE_BUP_CHECK_STRAP] = - "Check to see if straps say ME DISABLED", - [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = - "Timeout waiting for PWROK", - [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] = - "Possibly handle BUP manufacturing override strap", - [ME_HFS2_STATE_BUP_M3] = - "Bringup in M3", - [ME_HFS2_STATE_BUP_M0] = - "Bringup in M0", - [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = - "Flow detection error", - [ME_HFS2_STATE_BUP_M3_CLK_ERR] = - "M3 clock switching error", - [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] = - "Host error - CPU reset timeout, DID timeout, memory missing", - [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = - "M3 kernel load", - [ME_HFS2_STATE_BUP_T32_MISSING] = - "T34 missing - cannot program ICC", - [ME_HFS2_STATE_BUP_WAIT_DID] = - "Waiting for DID BIOS message", - [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = - "Waiting for DID BIOS message failure", - [ME_HFS2_STATE_BUP_DID_NO_FAIL] = - "DID reported no error", - [ME_HFS2_STATE_BUP_ENABLE_UMA] = - "Enabling UMA", - [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = - "Enabling UMA error", - [ME_HFS2_STATE_BUP_SEND_DID_ACK] = - "Sending DID Ack to BIOS", - [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = - "Sending DID Ack to BIOS error", - [ME_HFS2_STATE_BUP_M0_CLK] = - "Switching clocks in M0", - [ME_HFS2_STATE_BUP_M0_CLK_ERR] = - "Switching clocks in M0 error", - [ME_HFS2_STATE_BUP_TEMP_DIS] = - "ME in temp disable", - [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = - "M0 kernel load", + [ME_HFS2_STATE_BUP_INIT] = "Initialization starts", + [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = "Disable the host wake event", + [ME_HFS2_STATE_BUP_FLOW_DET] = "Flow determination start process", + [ME_HFS2_STATE_BUP_VSCC_ERR] = "Error reading/matching the VSCC table in the descriptor", + [ME_HFS2_STATE_BUP_CHECK_STRAP] = "Check to see if straps say ME DISABLED", + [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = "Timeout waiting for PWROK", + [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] = "Possibly handle BUP manufacturing override strap", + [ME_HFS2_STATE_BUP_M3] = "Bringup in M3", + [ME_HFS2_STATE_BUP_M0] = "Bringup in M0", + [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = "Flow detection error", + [ME_HFS2_STATE_BUP_M3_CLK_ERR] = "M3 clock switching error", + [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] = "Host error - CPU reset timeout, DID timeout, memory missing", + [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = "M3 kernel load", + [ME_HFS2_STATE_BUP_T32_MISSING] = "T34 missing - cannot program ICC", + [ME_HFS2_STATE_BUP_WAIT_DID] = "Waiting for DID BIOS message", + [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = "Waiting for DID BIOS message failure", + [ME_HFS2_STATE_BUP_DID_NO_FAIL] = "DID reported no error", + [ME_HFS2_STATE_BUP_ENABLE_UMA] = "Enabling UMA", + [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = "Enabling UMA error", + [ME_HFS2_STATE_BUP_SEND_DID_ACK] = "Sending DID Ack to BIOS", + [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = "Sending DID Ack to BIOS error", + [ME_HFS2_STATE_BUP_M0_CLK] = "Switching clocks in M0", + [ME_HFS2_STATE_BUP_M0_CLK_ERR] = "Switching clocks in M0 error", + [ME_HFS2_STATE_BUP_TEMP_DIS] = "ME in temp disable", + [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = "M0 kernel load", }; /* Progress Code 3 states */ static const char *me_progress_policy_values[] = { - [ME_HFS2_STATE_POLICY_ENTRY] = "Entry into Policy Module", - [ME_HFS2_STATE_POLICY_RCVD_S3] = "Received S3 entry", - [ME_HFS2_STATE_POLICY_RCVD_S4] = "Received S4 entry", - [ME_HFS2_STATE_POLICY_RCVD_S5] = "Received S5 entry", - [ME_HFS2_STATE_POLICY_RCVD_UPD] = "Received UPD entry", - [ME_HFS2_STATE_POLICY_RCVD_PCR] = "Received PCR entry", - [ME_HFS2_STATE_POLICY_RCVD_NPCR] = "Received NPCR entry", - [ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE] = "Received host wake", - [ME_HFS2_STATE_POLICY_RCVD_AC_DC] = "Received AC<>DC switch", - [ME_HFS2_STATE_POLICY_RCVD_DID] = "Received DRAM Init Done", - [ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND] = - "VSCC Data not found for flash device", - [ME_HFS2_STATE_POLICY_VSCC_INVALID] = - "VSCC Table is not valid", - [ME_HFS2_STATE_POLICY_FPB_ERR] = - "Flash Partition Boundary is outside address space", - [ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR] = - "ME cannot access the chipset descriptor region", - [ME_HFS2_STATE_POLICY_VSCC_NO_MATCH] = - "Required VSCC values for flash parts do not match", + [ME_HFS2_STATE_POLICY_ENTRY] = "Entry into Policy Module", + [ME_HFS2_STATE_POLICY_RCVD_S3] = "Received S3 entry", + [ME_HFS2_STATE_POLICY_RCVD_S4] = "Received S4 entry", + [ME_HFS2_STATE_POLICY_RCVD_S5] = "Received S5 entry", + [ME_HFS2_STATE_POLICY_RCVD_UPD] = "Received UPD entry", + [ME_HFS2_STATE_POLICY_RCVD_PCR] = "Received PCR entry", + [ME_HFS2_STATE_POLICY_RCVD_NPCR] = "Received NPCR entry", + [ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE] = "Received host wake", + [ME_HFS2_STATE_POLICY_RCVD_AC_DC] = "Received AC<>DC switch", + [ME_HFS2_STATE_POLICY_RCVD_DID] = "Received DRAM Init Done", + [ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND] = "VSCC Data not found for flash device", + [ME_HFS2_STATE_POLICY_VSCC_INVALID] = "VSCC Table is not valid", + [ME_HFS2_STATE_POLICY_FPB_ERR] = "Flash Partition Boundary is outside address space", + [ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR] = "ME cannot access the chipset descriptor region", + [ME_HFS2_STATE_POLICY_VSCC_NO_MATCH] = "Required VSCC values for flash parts do not match", }; void intel_me_status(void) diff --git a/src/southbridge/intel/wildcatpoint/pch.c b/src/southbridge/intel/wildcatpoint/pch.c index 1ac2967..efee415 100644 --- a/src/southbridge/intel/wildcatpoint/pch.c +++ b/src/southbridge/intel/wildcatpoint/pch.c @@ -185,8 +185,7 @@ /* Ensure memory, io, and bus master are all disabled */ reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); pci_write_config16(dev, PCI_COMMAND, reg16); /* Disable this device if possible */ diff --git a/src/southbridge/intel/wildcatpoint/pcie.c b/src/southbridge/intel/wildcatpoint/pcie.c index 4515ffb..4f9a34a 100644 --- a/src/southbridge/intel/wildcatpoint/pcie.c +++ b/src/southbridge/intel/wildcatpoint/pcie.c @@ -18,7 +18,7 @@ #include <delay.h> /* Low Power variant has 6 root ports. */ -#define NUM_ROOT_PORTS 6 +#define MAX_NUM_ROOT_PORTS 6 struct root_port_config { /* RPFN is a write-once register so keep a copy until it is written */ @@ -34,7 +34,7 @@ int coalesce; int gbe_port; int num_ports; - struct device *ports[NUM_ROOT_PORTS]; + struct device *ports[MAX_NUM_ROOT_PORTS]; }; static struct root_port_config rpc; @@ -110,7 +110,7 @@ if (root_port_is_first(dev)) { rpc.orig_rpfn = RCBA32(RPFN); rpc.new_rpfn = rpc.orig_rpfn; - rpc.num_ports = NUM_ROOT_PORTS; + rpc.num_ports = MAX_NUM_ROOT_PORTS; rpc.gbe_port = -1; /* RP0 f5[3:0] = 0101b*/ pci_update_config8(dev, 0xf5, ~0xa, 0x5); @@ -338,8 +338,7 @@ } } - printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", - rpc.orig_rpfn, rpc.new_rpfn); + printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", rpc.orig_rpfn, rpc.new_rpfn); RCBA32(RPFN) = rpc.new_rpfn; } @@ -372,8 +371,7 @@ /* Check Root Port Configuration. */ switch (rp) { case 2: - /* Root Port 2 is disabled for all lane configurations - * but config 00b (4x1 links). */ + /* Root Port 2 is disabled for all lane configs except 00b (4x1 links). */ if ((rpc.strpfusecfg1 >> 14) & 0x3) { root_port_mark_disable(dev); return; @@ -387,8 +385,7 @@ } break; case 4: - /* Root Port 4 is disabled in configs 11b (1x4 links) - * and 10b (2x2 links). */ + /* Root Port 4 is disabled in configs 11b (1x4 links) and 10b (2x2 links). */ if ((rpc.strpfusecfg1 >> 14) & 0x2) { root_port_mark_disable(dev); return; @@ -473,8 +470,7 @@ if (do_aspm) { /* Set ASPM bits in MPC2 register. */ - pci_update_config32(dev, 0xd4, ~(0x3 << 2), - (1 << 4) | (0x2 << 2)); + pci_update_config32(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2)); /* Set unique clock exit latency in MPC register. */ pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18)); @@ -583,6 +579,7 @@ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Set Cache Line Size to 0x10 */ + // This has no effect but the OS might expect it pci_write_config8(dev, 0x0c, 0x10); reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); diff --git a/src/southbridge/intel/wildcatpoint/pmutil.c b/src/southbridge/intel/wildcatpoint/pmutil.c index b66fb87..3024efd 100644 --- a/src/southbridge/intel/wildcatpoint/pmutil.c +++ b/src/southbridge/intel/wildcatpoint/pmutil.c @@ -90,10 +90,10 @@ static u16 print_pm1_status(u16 pm1_sts) { const char *pm1_sts_bits[] = { - [0] = "TMROF", - [4] = "BM", - [5] = "GBL", - [8] = "PWRBTN", + [0] = "TMROF", + [4] = "BM", + [5] = "GBL", + [8] = "PWRBTN", [10] = "RTC", [11] = "PRBTNOR", [14] = "PCIEXPWAK", @@ -122,7 +122,6 @@ outw(events, ACPI_BASE_ADDRESS + PM1_EN); } - /* * SMI */ @@ -130,7 +129,7 @@ /* Clear and return SMI status register */ static u32 reset_smi_status(void) { - u32 smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS); + const u32 smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS); outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS); return smi_sts; } @@ -139,13 +138,13 @@ static u32 print_smi_status(u32 smi_sts) { const char *smi_sts_bits[] = { - [2] = "BIOS", - [3] = "LEGACY_USB", - [4] = "SLP_SMI", - [5] = "APM", - [6] = "SWSMI_TMR", - [8] = "PM1", - [9] = "GPE0", + [2] = "BIOS", + [3] = "LEGACY_USB", + [4] = "SLP_SMI", + [5] = "APM", + [6] = "SWSMI_TMR", + [8] = "PM1", + [9] = "GPE0", [10] = "GPI", [11] = "MCSMI", [12] = "DEVMON", @@ -193,7 +192,6 @@ outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); } - /* * ALT_GP_SMI */ @@ -270,13 +268,13 @@ static u32 print_tco_status(u32 tco_sts) { const char *tco_sts_bits[] = { - [0] = "NMI2SMI", - [1] = "SW_TCO", - [2] = "TCO_INT", - [3] = "TIMEOUT", - [7] = "NEWCENTURY", - [8] = "BIOSWR", - [9] = "DMISCI", + [0] = "NMI2SMI", + [1] = "SW_TCO", + [2] = "TCO_INT", + [3] = "TIMEOUT", + [7] = "NEWCENTURY", + [8] = "BIOSWR", + [9] = "DMISCI", [10] = "DMISMI", [12] = "DMISERR", [13] = "SLVSEL", @@ -318,7 +316,7 @@ */ /* Clear a GPE0 status and return events that are enabled and active */ -static u32 reset_gpe(u16 sts_reg, u16 en_reg) +static u32 reset_gpe_status(u16 sts_reg, u16 en_reg) { u32 gpe0_sts = inl(ACPI_BASE_ADDRESS + sts_reg); u32 gpe0_en = inl(ACPI_BASE_ADDRESS + en_reg); @@ -359,11 +357,11 @@ u32 clear_gpe_status(void) { const char *gpe0_sts_3_bits[] = { - [1] = "HOTPLUG", - [2] = "SWGPE", - [6] = "TCO_SCI", - [7] = "SMB_WAK", - [9] = "PCI_EXP", + [1] = "HOTPLUG", + [2] = "SWGPE", + [6] = "TCO_SCI", + [7] = "SMB_WAK", + [9] = "PCI_EXP", [10] = "BATLOW", [11] = "PME", [12] = "ME", @@ -372,10 +370,10 @@ [18] = "WADT" }; - print_gpe_gpio(reset_gpe(GPE0_STS(GPE_31_0), GPE0_EN(GPE_31_0)), 0); - print_gpe_gpio(reset_gpe(GPE0_STS(GPE_63_32), GPE0_EN(GPE_63_32)), 32); - print_gpe_gpio(reset_gpe(GPE0_STS(GPE_94_64), GPE0_EN(GPE_94_64)), 64); - return print_gpe_status(reset_gpe(GPE0_STS(GPE_STD), GPE0_EN(GPE_STD)), + print_gpe_gpio(reset_gpe_status(GPE0_STS(GPE_31_0), GPE0_EN(GPE_31_0)), 0); + print_gpe_gpio(reset_gpe_status(GPE0_STS(GPE_63_32), GPE0_EN(GPE_63_32)), 32); + print_gpe_gpio(reset_gpe_status(GPE0_STS(GPE_94_64), GPE0_EN(GPE_94_64)), 64); + return print_gpe_status(reset_gpe_status(GPE0_STS(GPE_STD), GPE0_EN(GPE_STD)), gpe0_sts_3_bits); } diff --git a/src/southbridge/intel/wildcatpoint/serialio.c b/src/southbridge/intel/wildcatpoint/serialio.c index 3dbbc6e..613f2ac 100644 --- a/src/southbridge/intel/wildcatpoint/serialio.c +++ b/src/southbridge/intel/wildcatpoint/serialio.c @@ -271,10 +271,10 @@ } static struct device_operations device_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &serialio_set_resources, - .enable_resources = &pci_dev_enable_resources, - .init = &serialio_init, + .read_resources = pci_dev_read_resources, + .set_resources = serialio_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = serialio_init, .ops_pci = &broadwell_pci_ops, }; diff --git a/src/southbridge/intel/wildcatpoint/smbus.c b/src/southbridge/intel/wildcatpoint/smbus.c index b8177e5..5cfd277 100644 --- a/src/southbridge/intel/wildcatpoint/smbus.c +++ b/src/southbridge/intel/wildcatpoint/smbus.c @@ -1,16 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <device/device.h> #include <device/path.h> #include <device/smbus.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <device/smbus_host.h> #include <southbridge/intel/wildcatpoint/iomap.h> #include <southbridge/intel/wildcatpoint/ramstage.h> #include <southbridge/intel/wildcatpoint/smbus.h> -#include <device/smbus_host.h> static void pch_smbus_init(struct device *dev) { @@ -54,8 +53,8 @@ } static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, }; static void smbus_read_resources(struct device *dev) diff --git a/src/southbridge/intel/wildcatpoint/smi.c b/src/southbridge/intel/wildcatpoint/smi.c index 75eeb02d..c6f8361 100644 --- a/src/southbridge/intel/wildcatpoint/smi.c +++ b/src/southbridge/intel/wildcatpoint/smi.c @@ -39,7 +39,8 @@ enable_pm1(pm1_events); disable_gpe(PME_B0_EN); - /* Enable SMI generation: + /* + * Enable SMI generation: * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) diff --git a/src/southbridge/intel/wildcatpoint/smihandler.c b/src/southbridge/intel/wildcatpoint/smihandler.c index 98e26ca..782ba14 100644 --- a/src/southbridge/intel/wildcatpoint/smihandler.c +++ b/src/southbridge/intel/wildcatpoint/smihandler.c @@ -69,12 +69,12 @@ for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u16 reg16; - pci_devfn_t dev = PCI_DEV(bus, slot, func); + val = pci_read_config32(dev, PCI_VENDOR_ID); if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) + val == 0x0000ffff || val == 0xffff0000) continue; /* Disable Bus Mastering for this one device */ @@ -86,7 +86,7 @@ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); hdr &= 0x7f; if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { + hdr == PCI_HEADER_TYPE_CARDBUS) { unsigned int buses; buses = pci_read_config32(dev, PCI_PRIMARY_BUS); busmaster_disable_on_bus((buses >> 8) & 0xff); @@ -96,10 +96,9 @@ } /* - * Turn off the backlight if it is on, and wait for the specified - * backlight off delay. This will allow panel power timings to meet - * spec and prevent brief garbage on the screen when turned off - * during firmware with power button triggered SMI. + * Turn off the backlight if it is on, and wait for the specified backlight off delay. + * This will allow panel power timings to meet spec and prevent brief garbage on the + * screen when turned off during firmware with power button triggered SMI. */ static void backlight_off(void) { @@ -255,11 +254,11 @@ for (node = 0; node < CONFIG_MAX_CPUS; node++) { state = smm_get_save_state(node); - /* Check for Synchronous IO (bit0==1) */ + /* Check for Synchronous IO (bit0 == 1) */ if (!(state->io_misc_info & (1 << 0))) continue; - /* Make sure it was a write (bit4==0) */ + /* Make sure it was a write (bit4 == 0) */ if (state->io_misc_info & (1 << 4)) continue; @@ -372,11 +371,9 @@ { u16 pm1_sts = clear_pm1_status(); - /* While OSPM is not active, poweroff immediately - * on a power button event. - */ + /* While OSPM is not active, poweroff immediately on a power button event */ if (pm1_sts & PWRBTN_STS) { - /* power button pressed */ + /* Power button pressed */ elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); disable_pm1_control(-1UL); enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10)); @@ -431,8 +428,7 @@ * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCH_DEV_LPC, BIOS_CNTL, - (bios_cntl & ~1)); + pci_write_config32(PCH_DEV_LPC, BIOS_CNTL, bios_cntl & ~1); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ @@ -454,6 +450,7 @@ static void southbridge_smi_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) + u32 trap_sts, trap_cycle; u32 data, mask = 0; int i; @@ -475,13 +472,12 @@ return; } - /* IOTRAP(2) currently unused - * IOTRAP(1) currently unused */ + /* IOTRAP(2) currently unused */ + /* IOTRAP(1) currently unused */ /* IOTRAP(0) SMIC */ if (IOTRAP(0)) { - // It's a write - if (!(trap_cycle & (1 << 24))) { + if (!(trap_cycle & (1 << 24))) { // It's a write printk(BIOS_DEBUG, "SMI1 command\n"); data = RCBA32(0x1e18); data &= mask; @@ -492,15 +488,15 @@ // Fall through to debug } - printk(BIOS_DEBUG, " trapped io address = 0x%x\n", - trap_cycle & 0xfffc); - for (i = 0; i < 4; i++) + printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); + + for (i = 0; i < 4; i++) { if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + } printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); - printk(BIOS_DEBUG, " read/write: %s\n", - (trap_cycle & (1 << 24)) ? "read" : "write"); + printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); if (!(trap_cycle & (1 << 24))) { /* Write Cycle */ @@ -549,16 +545,14 @@ /** * @brief Interrupt handler for SMI# - * - * @param smm_revision revision of the smm state save map */ - void southbridge_smi_handler(void) { int i; u32 smi_sts; - /* We need to clear the SMI status registers, or we won't see what's + /* + * We need to clear the SMI status registers, or we won't see what's * happening in the following calls. */ smi_sts = clear_smi_status(); @@ -570,8 +564,7 @@ southbridge_smi[i](); } else { printk(BIOS_DEBUG, - "SMI_STS[%d] occurred, but no " - "handler available.\n", i); + "SMI_STS[%d] occurred, but no handler available.\n", i); } } } diff --git a/src/southbridge/intel/wildcatpoint/xhci.c b/src/southbridge/intel/wildcatpoint/xhci.c index cef2bed..2469cfd 100644 --- a/src/southbridge/intel/wildcatpoint/xhci.c +++ b/src/southbridge/intel/wildcatpoint/xhci.c @@ -185,7 +185,7 @@ } #else /* !__SIMPLE_DEVICE__ */ -static void xhci_init(struct device *dev) +static void usb_xhci_init(struct device *dev) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); u16 reg16; @@ -207,8 +207,8 @@ .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .init = usb_xhci_init, .ops_pci = &broadwell_pci_ops, - .init = xhci_init, }; static const unsigned short pci_device_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/42620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ca9eb464b911325acf32aec63b071c4d9ecf6c0 Gerrit-Change-Number: 42620 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 9

Change in coreboot[master]: lynxpoint/wildcatpoint: Factor out IOBP
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42625 ) Change subject: lynxpoint/wildcatpoint: Factor out IOBP ...................................................................... lynxpoint/wildcatpoint: Factor out IOBP Change-Id: Id1abb8ce630c8232812f3a892224b37f55273b4a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/iobp.c M src/southbridge/intel/lynxpoint/iobp.h M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/wildcatpoint/Makefile.inc D src/southbridge/intel/wildcatpoint/iobp.c M src/southbridge/intel/wildcatpoint/iobp.h 6 files changed, 36 insertions(+), 152 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/42625/1 diff --git a/src/southbridge/intel/lynxpoint/iobp.c b/src/southbridge/intel/lynxpoint/iobp.c index 3df6940..ee5518e 100644 --- a/src/southbridge/intel/lynxpoint/iobp.c +++ b/src/southbridge/intel/lynxpoint/iobp.c @@ -2,8 +2,8 @@ #include <console/console.h> #include <delay.h> -#include "pch.h" -#include "iobp.h" +#include <southbridge/intel/lynxpoint/iobp.h> +#include <southbridge/intel/lynxpoint/pch.h> #define IOBP_RETRY 1000 @@ -109,3 +109,31 @@ pch_iobp_write(address, data); } + +void pch_iobp_exec(u32 addr, u16 op_code, u8 route_id, u32 *data, u8 *resp) +{ + if (!data || !resp) + return; + + *resp = -1; + if (!iobp_poll()) + return; + + /* RCBA2330[31:0] = Address */ + RCBA32(IOBPIRI) = addr; + /* RCBA2338[15:8] = opcode */ + RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x00ff) | op_code; + /* RCBA233A[15:8] = 0xf0 RCBA233A[7:0] = Route ID */ + RCBA16(IOBPU) = IOBPU_MAGIC | route_id; + + if (op_code == IOBP_PCICFG_WRITE) + RCBA32(IOBPD) = *data; + /* Set RCBA2338[0] to trigger IOBP transaction*/ + RCBA16(IOBPS) = RCBA16(IOBPS) | 0x1; + + if (!iobp_poll()) + return; + + *resp = (RCBA16(IOBPS) & IOBPS_TX_MASK) >> 1; + *data = RCBA32(IOBPD); +} diff --git a/src/southbridge/intel/lynxpoint/iobp.h b/src/southbridge/intel/lynxpoint/iobp.h index c8669ba..458e6be 100644 --- a/src/southbridge/intel/lynxpoint/iobp.h +++ b/src/southbridge/intel/lynxpoint/iobp.h @@ -8,5 +8,6 @@ u32 pch_iobp_read(u32 address); void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); +void pch_iobp_exec(u32 addr, u16 op_dcode, u8 route_id, u32 *data, u8 *resp); #endif diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index f9a5562..291a554 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -521,6 +521,8 @@ #define IOBPS_WRITE 0x0700 #define IOBPU 0x233a #define IOBPU_MAGIC 0xf000 +#define IOBP_PCICFG_READ 0x0400 +#define IOBP_PCICFG_WRITE 0x0500 #define D31IP 0x3100 /* 32bit */ #define D31IP_TTIP 24 /* Thermal Throttle Pin */ diff --git a/src/southbridge/intel/wildcatpoint/Makefile.inc b/src/southbridge/intel/wildcatpoint/Makefile.inc index 49a2094..b98493b 100644 --- a/src/southbridge/intel/wildcatpoint/Makefile.inc +++ b/src/southbridge/intel/wildcatpoint/Makefile.inc @@ -11,8 +11,8 @@ romstage-y += gpio.c smm-y += gpio.c ramstage-y += hda.c -ramstage-y += iobp.c -romstage-y += iobp.c +ramstage-y += ../lynxpoint/iobp.c +romstage-y += ../lynxpoint/iobp.c ramstage-y += lpc.c ramstage-y += me.c ramstage-y += me_status.c diff --git a/src/southbridge/intel/wildcatpoint/iobp.c b/src/southbridge/intel/wildcatpoint/iobp.c deleted file mode 100644 index 51dd8a6..0000000 --- a/src/southbridge/intel/wildcatpoint/iobp.c +++ /dev/null @@ -1,139 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <delay.h> -#include <southbridge/intel/wildcatpoint/iobp.h> -#include <southbridge/intel/wildcatpoint/rcba.h> - -#define IOBP_RETRY 1000 - -static inline int iobp_poll(void) -{ - unsigned int try; - - for (try = IOBP_RETRY; try > 0; try--) { - u16 status = RCBA16(IOBPS); - if ((status & IOBPS_READY) == 0) - return 1; - udelay(10); - } - - printk(BIOS_ERR, "IOBP: timeout waiting for transaction to complete\n"); - return 0; -} - -u32 pch_iobp_read(u32 address) -{ - u16 status; - - if (!iobp_poll()) - return 0; - - /* Set the address */ - RCBA32(IOBPIRI) = address; - - /* READ OPCODE */ - status = RCBA16(IOBPS); - status &= ~IOBPS_MASK; - status |= IOBPS_READ; - RCBA16(IOBPS) = status; - - /* Undocumented magic */ - RCBA16(IOBPU) = IOBPU_MAGIC; - - /* Set ready bit */ - status = RCBA16(IOBPS); - status |= IOBPS_READY; - RCBA16(IOBPS) = status; - - if (!iobp_poll()) - return 0; - - /* Check for successful transaction */ - status = RCBA16(IOBPS); - if (status & IOBPS_TX_MASK) { - printk(BIOS_ERR, "IOBP: read 0x%08x failed\n", address); - return 0; - } - - /* Read IOBP data */ - return RCBA32(IOBPD); -} - -void pch_iobp_write(u32 address, u32 data) -{ - u16 status; - - if (!iobp_poll()) - return; - - /* Set the address */ - RCBA32(IOBPIRI) = address; - - /* WRITE OPCODE */ - status = RCBA16(IOBPS); - status &= ~IOBPS_MASK; - status |= IOBPS_WRITE; - RCBA16(IOBPS) = status; - - RCBA32(IOBPD) = data; - - /* Undocumented magic */ - RCBA16(IOBPU) = IOBPU_MAGIC; - - /* Set ready bit */ - status = RCBA16(IOBPS); - status |= IOBPS_READY; - RCBA16(IOBPS) = status; - - if (!iobp_poll()) - return; - - /* Check for successful transaction */ - status = RCBA16(IOBPS); - if (status & IOBPS_TX_MASK) { - printk(BIOS_ERR, "IOBP: write 0x%08x failed\n", address); - return; - } - - printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data); -} - -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) -{ - u32 data = pch_iobp_read(address); - - /* Update the data */ - data &= andvalue; - data |= orvalue; - - pch_iobp_write(address, data); -} - -void pch_iobp_exec(u32 addr, u16 op_code, u8 route_id, u32 *data, u8 *resp) -{ - if (!data || !resp) - return; - - *resp = -1; - if (!iobp_poll()) - return; - - /* RCBA2330[31:0] = Address */ - RCBA32(IOBPIRI) = addr; - /* RCBA2338[15:8] = opcode */ - RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x00ff) | op_code; - /* RCBA233A[15:8] = 0xf0 RCBA233A[7:0] = Route ID */ - RCBA16(IOBPU) = IOBPU_MAGIC | route_id; - - if (op_code == IOBP_PCICFG_WRITE) - RCBA32(IOBPD) = *data; - /* Set RCBA2338[0] to trigger IOBP transaction*/ - RCBA16(IOBPS) = RCBA16(IOBPS) | 0x1; - - if (!iobp_poll()) - return; - - *resp = (RCBA16(IOBPS) & IOBPS_TX_MASK) >> 1; - *data = RCBA32(IOBPD); -} diff --git a/src/southbridge/intel/wildcatpoint/iobp.h b/src/southbridge/intel/wildcatpoint/iobp.h index e3a6993..a0bdd33 100644 --- a/src/southbridge/intel/wildcatpoint/iobp.h +++ b/src/southbridge/intel/wildcatpoint/iobp.h @@ -1,11 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _BROADWELL_IOBP_H_ -#define _BROADWELL_IOBP_H_ - -u32 pch_iobp_read(u32 address); -void pch_iobp_write(u32 address, u32 data); -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -void pch_iobp_exec(u32 addr, u16 op_dcode, u8 route_id, u32 *data, u8 *resp); - -#endif +#include <southbridge/intel/lynxpoint/iobp.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/42625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1abb8ce630c8232812f3a892224b37f55273b4a Gerrit-Change-Number: 42625 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 4

Change in coreboot[master]: Merge Haswell and Broadwell files
by Angel Pons (Code Review) 31 Oct '20

31 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42626 ) Change subject: Merge Haswell and Broadwell files ...................................................................... Merge Haswell and Broadwell files Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains the same. Change-Id: I72e8efc465ebe44ea9b1baaca2a317a29eb9506d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/broadwell/Makefile.inc M src/cpu/intel/broadwell/acpi.c D src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/broadwell_init.c D src/cpu/intel/broadwell/smmrelocate.c M src/cpu/intel/haswell/acpi.c A src/cpu/intel/haswell/acpi_common.c M src/cpu/intel/haswell/bootblock.c A src/cpu/intel/haswell/cstate_def.c M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c A src/cpu/intel/haswell/hsw_bdw_init_common.c M src/cpu/intel/haswell/smmrelocate.c M src/northbridge/intel/broadwell/Makefile.inc M src/northbridge/intel/broadwell/acpi/broadwell.asl D src/northbridge/intel/broadwell/bootblock.c M src/northbridge/intel/broadwell/broadwell.h M src/northbridge/intel/broadwell/igd.c D src/northbridge/intel/broadwell/minihd.c M src/northbridge/intel/broadwell/northbridge.c R src/northbridge/intel/haswell/acpi/ctdp.asl M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/haswell/bootblock.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c A src/northbridge/intel/haswell/northbridge_common.c M src/northbridge/intel/haswell/report_platform.c M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/wildcatpoint/bootblock.c M src/southbridge/intel/wildcatpoint/iomap.h M src/southbridge/intel/wildcatpoint/pch.c M src/southbridge/intel/wildcatpoint/spi.h 36 files changed, 1,129 insertions(+), 2,636 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/42626/1 diff --git a/src/cpu/intel/broadwell/Makefile.inc b/src/cpu/intel/broadwell/Makefile.inc index ad5dc5b..4b89975 100644 --- a/src/cpu/intel/broadwell/Makefile.inc +++ b/src/cpu/intel/broadwell/Makefile.inc @@ -6,7 +6,7 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common -bootblock-y += bootblock.c +bootblock-y += ../haswell/bootblock.c bootblock-y += ../../../cpu/intel/car/bootblock.c bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S bootblock-y += ../../../cpu/x86/early_reset.S @@ -25,7 +25,7 @@ romstage-y += romstage.c -ramstage-y += smmrelocate.c +ramstage-y += ../haswell/smmrelocate.c bootblock-y += tsc_freq.c ramstage-y += tsc_freq.c diff --git a/src/cpu/intel/broadwell/acpi.c b/src/cpu/intel/broadwell/acpi.c index a63914c..f96c260 100644 --- a/src/cpu/intel/broadwell/acpi.c +++ b/src/cpu/intel/broadwell/acpi.c @@ -25,99 +25,8 @@ #include <southbridge/intel/wildcatpoint/soc_chip.h> #include <intelblocks/cpulib.h> -/* - * List of supported C-states in this processor. Only the ULT parts support C8, - * C9, and C10. - */ -enum { - C_STATE_C0, /* 0 */ - C_STATE_C1, /* 1 */ - C_STATE_C1E, /* 2 */ - C_STATE_C3, /* 3 */ - C_STATE_C6_SHORT_LAT, /* 4 */ - C_STATE_C6_LONG_LAT, /* 5 */ - C_STATE_C7_SHORT_LAT, /* 6 */ - C_STATE_C7_LONG_LAT, /* 7 */ - C_STATE_C7S_SHORT_LAT, /* 8 */ - C_STATE_C7S_LONG_LAT, /* 9 */ - C_STATE_C8, /* 10 */ - C_STATE_C9, /* 11 */ - C_STATE_C10, /* 12 */ - NUM_C_STATES -}; - -#define MWAIT_RES(state, sub_state) \ - { \ - .addrl = (((state) << 4) | (sub_state)), \ - .space_id = ACPI_ADDRESS_SPACE_FIXED, \ - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ - } - -static acpi_cstate_t cstate_map[NUM_C_STATES] = { - [C_STATE_C0] = { }, - [C_STATE_C1] = { - .latency = 0, - .power = 1000, - .resource = MWAIT_RES(0, 0), - }, - [C_STATE_C1E] = { - .latency = 0, - .power = 1000, - .resource = MWAIT_RES(0, 1), - }, - [C_STATE_C3] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), - .power = 900, - .resource = MWAIT_RES(1, 0), - }, - [C_STATE_C6_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 800, - .resource = MWAIT_RES(2, 0), - }, - [C_STATE_C6_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 800, - .resource = MWAIT_RES(2, 1), - }, - [C_STATE_C7_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 700, - .resource = MWAIT_RES(3, 0), - }, - [C_STATE_C7_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 700, - .resource = MWAIT_RES(3, 1), - }, - [C_STATE_C7S_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 700, - .resource = MWAIT_RES(3, 2), - }, - [C_STATE_C7S_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 700, - .resource = MWAIT_RES(3, 3), - }, - [C_STATE_C8] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(3), - .power = 600, - .resource = MWAIT_RES(4, 0), - }, - [C_STATE_C9] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(4), - .power = 500, - .resource = MWAIT_RES(5, 0), - }, - [C_STATE_C10] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(5), - .power = 400, - .resource = MWAIT_RES(6, 0), - }, -}; +/* FIXME: For verification purposes only */ +#include <cpu/intel/haswell/cstate_def.c> static int cstate_set_s0ix[3] = { C_STATE_C1E, @@ -131,22 +40,6 @@ C_STATE_C7S_LONG_LAT }; -static int get_cores_per_package(void) -{ - struct cpuinfo_x86 c; - struct cpuid_result result; - int cores = 1; - - get_fms(&c, cpuid_eax(1)); - if (c.x86 != 6) - return 1; - - result = cpuid_ext(0xb, 1); - cores = result.ebx & 0xff; - - return cores; -} - static void generate_C_state_entries(void) { acpi_cstate_t map[3]; @@ -169,229 +62,13 @@ acpigen_write_CST_package(map, ARRAY_SIZE(map)); } -static acpi_tstate_t tss_table_fine[] = { - { 100, 1000, 0, 0x00, 0 }, - { 94, 940, 0, 0x1f, 0 }, - { 88, 880, 0, 0x1e, 0 }, - { 82, 820, 0, 0x1d, 0 }, - { 75, 760, 0, 0x1c, 0 }, - { 69, 700, 0, 0x1b, 0 }, - { 63, 640, 0, 0x1a, 0 }, - { 57, 580, 0, 0x19, 0 }, - { 50, 520, 0, 0x18, 0 }, - { 44, 460, 0, 0x17, 0 }, - { 38, 400, 0, 0x16, 0 }, - { 32, 340, 0, 0x15, 0 }, - { 25, 280, 0, 0x14, 0 }, - { 19, 220, 0, 0x13, 0 }, - { 13, 160, 0, 0x12, 0 }, -}; - -static acpi_tstate_t tss_table_coarse[] = { - { 100, 1000, 0, 0x00, 0 }, - { 88, 875, 0, 0x1f, 0 }, - { 75, 750, 0, 0x1e, 0 }, - { 63, 625, 0, 0x1d, 0 }, - { 50, 500, 0, 0x1c, 0 }, - { 38, 375, 0, 0x1b, 0 }, - { 25, 250, 0, 0x1a, 0 }, - { 13, 125, 0, 0x19, 0 }, -}; - -static void generate_T_state_entries(int core, int cores_per_package) +static inline void get_pmbase(void) { - /* Indicate SW_ALL coordination for T-states */ - acpigen_write_TSD_package(core, cores_per_package, SW_ALL); - - /* Indicate FFixedHW so OS will use MSR */ - acpigen_write_empty_PTC(); - - /* Set a T-state limit that can be modified in NVS */ - acpigen_write_TPC("\\TLVL"); - - /* - * CPUID.(EAX=6):EAX[5] indicates support - * for extended throttle levels. - */ - if (cpuid_eax(6) & (1 << 5)) - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_fine), tss_table_fine); - else - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_coarse), tss_table_coarse); + return ACPI_BASE_ADDRESS; } -static int calculate_power(int tdp, int p1_ratio, int ratio) -{ - u32 m; - u32 power; - - /* - * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 - * - * Power = (ratio / p1_ratio) * m * tdp - */ - - m = (110000 - ((p1_ratio - ratio) * 625)) / 11; - m = (m * m) / 1000; - - power = ((ratio * 100000 / p1_ratio) / 100); - power *= (m / 100) * (tdp / 1000); - power /= 1000; - - return (int)power; -} - -static void generate_P_state_entries(int core, int cores_per_package) -{ - int ratio_min, ratio_max, ratio_turbo, ratio_step; - int coord_type, power_max, power_unit, num_entries; - int ratio, power, clock, clock_max; - msr_t msr; - - /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) - coord_type = SW_ANY; - else - coord_type = HW_ALL; - - /* Get bus ratio limits and calculate clock speeds */ - msr = rdmsr(MSR_PLATFORM_INFO); - ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ - - /* Determine if this CPU has configurable TDP */ - if (cpu_config_tdp_levels()) { - /* Set max ratio to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - ratio_max = msr.lo & 0xff; - } else { - /* Max Non-Turbo Ratio */ - ratio_max = (msr.lo >> 8) & 0xff; - } - clock_max = ratio_max * CPU_BCLK; - - /* Calculate CPU TDP in mW */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 2 << ((msr.lo & 0xf) - 1); - msr = rdmsr(MSR_PKG_POWER_SKU); - power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; - - /* Write _PCT indicating use of FFixedHW */ - acpigen_write_empty_PCT(); - - /* Write _PPC with no limit on supported P-state */ - acpigen_write_PPC_NVS(); - - /* Write PSD indicating configured coordination type */ - acpigen_write_PSD_package(core, 1, coord_type); - - /* Add P-state entries in _PSS table */ - acpigen_write_name("_PSS"); - - /* Determine ratio points */ - ratio_step = PSS_RATIO_STEP; - num_entries = (ratio_max - ratio_min) / ratio_step; - while (num_entries > PSS_MAX_ENTRIES-1) { - ratio_step <<= 1; - num_entries >>= 1; - } - - /* P[T] is Turbo state if enabled */ - if (get_turbo_state() == TURBO_ENABLED) { - /* _PSS package count including Turbo */ - acpigen_write_package(num_entries + 2); - - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - ratio_turbo = msr.lo & 0xff; - - /* Add entry for Turbo ratio */ - acpigen_write_PSS_package( - clock_max + 1, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_turbo << 8, /*control*/ - ratio_turbo << 8); /*status*/ - } else { - /* _PSS package count without Turbo */ - acpigen_write_package(num_entries + 1); - } - - /* First regular entry is max non-turbo ratio */ - acpigen_write_PSS_package( - clock_max, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_max << 8, /*control*/ - ratio_max << 8); /*status*/ - - /* Generate the remaining entries */ - for (ratio = ratio_min + ((num_entries - 1) * ratio_step); - ratio >= ratio_min; ratio -= ratio_step) { - - /* Calculate power at this ratio */ - power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * CPU_BCLK; - - acpigen_write_PSS_package( - clock, /*MHz*/ - power, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio << 8, /*control*/ - ratio << 8); /*status*/ - } - - /* Fix package length */ - acpigen_pop_len(); -} - -void generate_cpu_entries(const struct device *device) -{ - int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; - int totalcores = dev_count_cpu(); - int cores_per_package = get_cores_per_package(); - int numcpus = totalcores/cores_per_package; - - printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", - numcpus, cores_per_package); - - for (cpuID = 1; cpuID <= numcpus; cpuID++) { - for (coreID = 1; coreID <= cores_per_package; coreID++) { - if (coreID > 1) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor \_SB.CPUx */ - acpigen_write_processor( - (cpuID - 1) * cores_per_package+coreID - 1, - pcontrol_blk, plen); - - /* Generate P-state tables */ - generate_P_state_entries( - coreID - 1, cores_per_package); - - /* Generate C-state tables */ - generate_C_state_entries(); - - /* Generate T-state tables */ - generate_T_state_entries( - cpuID - 1, cores_per_package); - - acpigen_pop_len(); - } - } - - /* PPKG is usually used for thermal management - of the first and only package. */ - acpigen_write_processor_package("PPKG", 0, cores_per_package); - - /* Add a method to notify processor nodes */ - acpigen_write_processor_cnot(cores_per_package); -} +/* FIXME: For verification purposes only */ +#include <cpu/intel/haswell/acpi_common.c> unsigned long acpi_madt_irq_overrides(unsigned long current) { diff --git a/src/cpu/intel/broadwell/bootblock.c b/src/cpu/intel/broadwell/bootblock.c deleted file mode 100644 index 72f8205..0000000 --- a/src/cpu/intel/broadwell/bootblock.c +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <stdint.h> -#include <arch/bootblock.h> -#include <arch/io.h> -#include <cpu/x86/msr.h> -#include <halt.h> -#include <southbridge/intel/wildcatpoint/rcba.h> -#include <delay.h> - -#include <cpu/intel/broadwell/broadwell.h> - -static void set_flex_ratio_to_tdp_nominal(void) -{ - msr_t flex_ratio, msr; - u32 soft_reset; - u8 nominal_ratio; - - /* Check for Flex Ratio support */ - flex_ratio = rdmsr(MSR_FLEX_RATIO); - if (!(flex_ratio.lo & FLEX_RATIO_EN)) - return; - - /* Check for >0 configurable TDPs */ - msr = rdmsr(MSR_PLATFORM_INFO); - if (((msr.hi >> 1) & 3) == 0) - return; - - /* Use nominal TDP ratio for flex ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - nominal_ratio = msr.lo & 0xff; - - /* See if flex ratio is already set to nominal TDP ratio */ - if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio) - return; - - /* Set flex ratio to nominal TDP ratio */ - flex_ratio.lo &= ~0xff00; - flex_ratio.lo |= nominal_ratio << 8; - flex_ratio.lo |= FLEX_RATIO_LOCK; - wrmsr(MSR_FLEX_RATIO, flex_ratio); - - /* Set flex ratio in soft reset data register bits 11:6. - * RCBA region is enabled in southbridge bootblock */ - soft_reset = RCBA32(SOFT_RESET_DATA); - soft_reset &= ~(0x3f << 6); - soft_reset |= (nominal_ratio & 0x3f) << 6; - RCBA32(SOFT_RESET_DATA) = soft_reset; - - /* Set soft reset control to use register value */ - RCBA32_OR(SOFT_RESET_CTRL, 1); - - /* Delay before reset to avoid potential TPM lockout */ - mdelay(30); - - /* Issue warm reset, will be "CPU only" due to soft reset data */ - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); -} - -void bootblock_early_cpu_init(void) -{ - /* Set flex ratio and reset if needed */ - set_flex_ratio_to_tdp_nominal(); -} diff --git a/src/cpu/intel/broadwell/broadwell_init.c b/src/cpu/intel/broadwell/broadwell_init.c index 5d26232..7c0ce54 100644 --- a/src/cpu/intel/broadwell/broadwell_init.c +++ b/src/cpu/intel/broadwell/broadwell_init.c @@ -36,80 +36,12 @@ /** haswell_is_ult **/ -/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate - * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly - * when a core is woken up. */ -static int pcode_ready(void) -{ - int wait_count; - const int delay_step = 10; +/* FIXME: For verification purposes only */ +#include <cpu/intel/haswell/hsw_bdw_init_common.c> - wait_count = 0; - do { - if (!(MCHBAR32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY)) - return 0; - wait_count += delay_step; - udelay(delay_step); - } while (wait_count < 1000); +/** cpu_config_tdp_levels **/ - return -1; -} - -static void calibrate_24mhz_bclk(void) -{ - int err_code; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); - return; - } - - /* A non-zero value initiates the PCODE calibration. */ - MCHBAR32(BIOS_MAILBOX_DATA) = ~0; - MCHBAR32(BIOS_MAILBOX_INTERFACE) = - MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); - return; - } - - err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; - - printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", - err_code); - - /* Read the calibrated value. */ - MCHBAR32(BIOS_MAILBOX_INTERFACE) = - MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n"); - return; - } - - printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", - MCHBAR32(BIOS_MAILBOX_DATA)); -} - -static u32 pcode_mailbox_read(u32 command) -{ - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); - return 0; - } - - /* Send command and start transaction */ - MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); - return 0; - } - - /* Read mailbox */ - return MCHBAR32(BIOS_MAILBOX_DATA); -} +/** set_power_limits **/ static int pcode_mailbox_write(u32 command, u32 data) { @@ -195,56 +127,6 @@ pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f); } -static void configure_pch_power_sharing(void) -{ - u32 pch_power, pch_power_ext, pmsync, pmsync2; - int i; - - /* Read PCH Power levels from PCODE */ - pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER); - pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT); - - printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n", - pch_power, pch_power_ext); - - pmsync = RCBA32(PMSYNC_CONFIG); - pmsync2 = RCBA32(PMSYNC_CONFIG2); - - /* Program PMSYNC_TPR_CONFIG PCH power limit values - * pmsync[0:4] = mailbox[0:5] - * pmsync[8:12] = mailbox[6:11] - * pmsync[16:20] = mailbox[12:17] - */ - for (i = 0; i < 3; i++) { - u32 level = pch_power & 0x3f; - pch_power >>= 6; - pmsync &= ~(0x1f << (i * 8)); - pmsync |= (level & 0x1f) << (i * 8); - } - RCBA32(PMSYNC_CONFIG) = pmsync; - - /* Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values - * pmsync2[0:4] = mailbox[23:18] - * pmsync2[8:12] = mailbox_ext[6:11] - * pmsync2[16:20] = mailbox_ext[12:17] - * pmsync2[24:28] = mailbox_ext[18:22] - */ - pmsync2 &= ~0x1f; - pmsync2 |= pch_power & 0x1f; - - for (i = 1; i < 4; i++) { - u32 level = pch_power_ext & 0x3f; - pch_power_ext >>= 6; - pmsync2 &= ~(0x1f << (i * 8)); - pmsync2 |= (level & 0x1f) << (i * 8); - } - RCBA32(PMSYNC_CONFIG2) = pmsync2; -} - -/** cpu_config_tdp_levels **/ - -/** set_power_limits **/ - static void configure_c_states(void) { msr_t msr; @@ -321,50 +203,6 @@ } } -static void configure_misc(void) -{ - msr_t msr; - - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ - msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLE, msr); - - /* Disable Thermal interrupts */ - msr.lo = 0; - msr.hi = 0; - wrmsr(IA32_THERM_INTERRUPT, msr); - - /* Enable package critical interrupt only */ - msr.lo = 1 << 4; - msr.hi = 0; - wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); -} - -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - -static void configure_dca_cap(void) -{ - uint32_t feature_flag; - msr_t msr; - - /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - feature_flag = cpu_get_feature_flags_ecx(); - if (feature_flag & CPUID_DCA) { - msr = rdmsr(IA32_PLATFORM_DCA_CAP); - msr.lo |= 1; - wrmsr(IA32_PLATFORM_DCA_CAP, msr); - } -} - static void set_max_ratio(void) { msr_t msr, perf_ctl; @@ -409,22 +247,6 @@ printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy); } -static void configure_mca(void) -{ - msr_t msr; - int i; - int num_banks; - - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & 0xff; - msr.lo = msr.hi = 0; - /* TODO(adurbin): This should only be done on a cold boot. Also, some - * of these banks are core vs package scope. For now every CPU clears - * every bank. */ - for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); -} - /* All CPUs including BSP will run the following function. */ static void cpu_core_init(struct device *cpu) { @@ -457,9 +279,6 @@ enable_turbo(); } -/* MP initialization support. */ -static const void *microcode_patch; - static void pre_mp_init(void) { /* Setup MTRRs based on physical address size. */ @@ -471,37 +290,6 @@ configure_pch_power_sharing(); } -static int get_cpu_count(void) -{ - msr_t msr; - int num_threads; - int num_cores; - - msr = rdmsr(MSR_CORE_THREAD_COUNT); - num_threads = (msr.lo >> 0) & 0xffff; - num_cores = (msr.lo >> 16) & 0xffff; - printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", - num_cores, num_threads); - - return num_threads; -} - -static void get_microcode_info(const void **microcode, int *parallel) -{ - microcode_patch = intel_microcode_find(); - *microcode = microcode_patch; - *parallel = 1; -} - -static void per_cpu_smm_trigger(void) -{ - /* Relocate the SMM handler. */ - smm_relocate(); - - /* After SMM relocation a 2nd microcode load is required. */ - intel_microcode_load_unlocked(microcode_patch); -} - static void post_mp_init(void) { /* Set Max Ratio */ diff --git a/src/cpu/intel/broadwell/smmrelocate.c b/src/cpu/intel/broadwell/smmrelocate.c deleted file mode 100644 index 5599c0b..0000000 --- a/src/cpu/intel/broadwell/smmrelocate.c +++ /dev/null @@ -1,265 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <types.h> -#include <string.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <cpu/x86/mp.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> -#include <cpu/intel/smm_reloc.h> -#include <console/console.h> -#include <northbridge/intel/broadwell/broadwell.h> -#include <southbridge/intel/wildcatpoint/pci_devs.h> -#include <smp/node.h> -#include "broadwell.h" - - -static void update_save_state(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase, - struct smm_relocation_params *relo_params) -{ - u32 smbase; - u32 iedbase; - - /* The relocated handler runs with all CPUs concurrently. Therefore - * stagger the entry points adjusting SMBASE downwards by save state - * size * CPU num. */ - smbase = staggered_smbase; - iedbase = relo_params->ied_base; - - printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", - smbase, iedbase); - - /* All threads need to set IEDBASE and SMBASE to the relocated - * handler region. However, the save state location depends on the - * smm_save_state_in_msrs field in the relocation parameters. If - * smm_save_state_in_msrs is non-zero then the CPUs are relocating - * the SMM handler in parallel, and each CPUs save state area is - * located in their respective MSR space. If smm_save_state_in_msrs - * is zero then the SMM relocation is happening serially so the - * save state is at the same default location for all CPUs. */ - if (relo_params->smm_save_state_in_msrs) { - msr_t smbase_msr; - msr_t iedbase_msr; - - smbase_msr.lo = smbase; - smbase_msr.hi = 0; - - /* According the BWG the IEDBASE MSR is in bits 63:32. It's - * not clear why it differs from the SMBASE MSR. */ - iedbase_msr.lo = 0; - iedbase_msr.hi = iedbase; - - wrmsr(SMBASE_MSR, smbase_msr); - wrmsr(IEDBASE_MSR, iedbase_msr); - } else { - em64t101_smm_state_save_area_t *save_state; - - save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - - sizeof(*save_state)); - - save_state->smbase = smbase; - save_state->iedbase = iedbase; - } -} - -/* Returns 1 if SMM MSR save state was set. */ -static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params) -{ - msr_t smm_mca_cap; - - smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR); - if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) { - msr_t smm_feature_control; - - smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); - smm_feature_control.hi = 0; - smm_feature_control.lo |= SMM_CPU_SAVE_EN; - wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); - relo_params->smm_save_state_in_msrs = 1; - } - return relo_params->smm_save_state_in_msrs; -} - -/* The relocation work is actually performed in SMM context, but the code - * resides in the ramstage module. This occurs by trampolining from the default - * SMRAM entry point to here. */ -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - msr_t mtrr_cap; - struct smm_relocation_params *relo_params = &smm_reloc_params; - - printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); - - /* Determine if the processor supports saving state in MSRs. If so, - * enable it before the non-BSPs run so that SMM relocation can occur - * in parallel in the non-BSP CPUs. */ - if (cpu == 0) { - /* If smm_save_state_in_msrs is 1 then that means this is the - * 2nd time through the relocation handler for the BSP. - * Parallel SMM handler relocation is taking place. However, - * it is desired to access other CPUs save state in the real - * SMM handler. Therefore, disable the SMM save state in MSRs - * feature. */ - if (relo_params->smm_save_state_in_msrs) { - msr_t smm_feature_control; - - smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); - smm_feature_control.lo &= ~SMM_CPU_SAVE_EN; - wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); - } else if (bsp_setup_msr_save_state(relo_params)) - /* Just return from relocation handler if MSR save - * state is enabled. In that case the BSP will come - * back into the relocation handler to setup the new - * SMBASE as well disabling SMM save state in MSRs. */ - return; - } - - /* Make appropriate changes to the save state map. */ - update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); - - /* Write PRMRR and SMRR MSRs based on indicated support. */ - mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (mtrr_cap.lo & SMRR_SUPPORTED) - write_smrr(relo_params); - - if (mtrr_cap.lo & PRMRR_SUPPORTED) { - write_prmrr(relo_params); - /* UNCORE_PRMRR msrs are package level. Therefore, only - * configure these MSRs on the BSP. */ - if (cpu == 0) - write_uncore_prmrr(relo_params); - } -} - -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - - u32 prmrr_base; - u32 prmrr_size; - int phys_bits; - /* All range registers are aligned to 4KiB */ - const u32 rmask = ~((1 << 12) - 1); - - /* Some of the range registers are dependent on the number of physical - * address bits supported. */ - phys_bits = cpuid_eax(0x80000008) & 0xff; - - /* The range bounded by the TSEGMB and BGSM registers encompasses the - * SMRAM range as well as the IED range. However, the SMRAM available - * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB. - */ - smm_region(&tseg_base, &tseg_size); - - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; - - smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); - - /* The PRMRR and UNCORE_PRMRR are at IEDBASE + 2MiB */ - prmrr_base = (params->ied_base + (2 << 20)) & rmask; - prmrr_size = params->ied_size - (2 << 20); - - /* PRMRR has 46 bits of valid address aligned to 4KiB. It's dependent - * on the number of physical address bits supported. */ - params->prmrr_base.lo = prmrr_base | MTRR_TYPE_WRBACK; - params->prmrr_base.hi = 0; - params->prmrr_mask.lo = (~(prmrr_size - 1) & rmask) - | MTRR_PHYS_MASK_VALID; - params->prmrr_mask.hi = (1 << (phys_bits - 32)) - 1; - - /* UNCORE_PRMRR has 39 bits of valid address aligned to 4KiB. */ - params->uncore_prmrr_base.lo = prmrr_base; - params->uncore_prmrr_base.hi = 0; - params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) | - MTRR_PHYS_MASK_VALID; - params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1; -} - -static void setup_ied_area(struct smm_relocation_params *params) -{ - char *ied_base; - - struct ied_header ied = { - .signature = "INTEL RSVD", - .size = params->ied_size, - .reserved = {0}, - }; - - ied_base = (void *)params->ied_base; - - /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); - - /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + (1 << 20), 0, (32 << 10)); -} - -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - - setup_ied_area(&smm_reloc_params); - - *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); -} - -void smm_initialize(void) -{ - /* Clear the SMM state in the southbridge. */ - smm_southbridge_clear_state(); - - /* - * Run the relocation handler for on the BSP to check and set up - * parallel SMM relocation. - */ - smm_initiate_relocation(); - - if (smm_reloc_params.smm_save_state_in_msrs) - printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); -} - -/* The default SMM entry can happen in parallel or serially. If the - * default SMM entry is done in parallel the BSP has already setup - * the saving state to each CPU's MSRs. At least one save state size - * is required for the initial SMM entry for the BSP to determine if - * parallel SMM relocation is even feasible. */ -void smm_relocate(void) -{ - /* - * If smm_save_state_in_msrs is non-zero then parallel SMM relocation - * shall take place. Run the relocation handler a second time on the - * BSP to do * the final move. For APs, a relocation handler always - * needs to be run. - */ - if (smm_reloc_params.smm_save_state_in_msrs) - smm_initiate_relocation_parallel(); - else if (!boot_cpu()) - smm_initiate_relocation(); -} - -void smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(pcidev_path_on_root(SA_DEVFN_ROOT), SMRAM, - D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 676acce..0deb358 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -14,22 +14,6 @@ #include <southbridge/intel/lynxpoint/pch.h> -static int get_cores_per_package(void) -{ - struct cpuinfo_x86 c; - struct cpuid_result result; - int cores = 1; - - get_fms(&c, cpuid_eax(1)); - if (c.x86 != 6) - return 1; - - result = cpuid_ext(0xb, 1); - cores = result.ebx & 0xff; - - return cores; -} - static void generate_cstate_entries(acpi_cstate_t *cstates, int c1, int c2, int c3) { @@ -109,229 +93,8 @@ acpigen_pop_len(); } -static acpi_tstate_t tss_table_fine[] = { - { 100, 1000, 0, 0x00, 0 }, - { 94, 940, 0, 0x1f, 0 }, - { 88, 880, 0, 0x1e, 0 }, - { 82, 820, 0, 0x1d, 0 }, - { 75, 760, 0, 0x1c, 0 }, - { 69, 700, 0, 0x1b, 0 }, - { 63, 640, 0, 0x1a, 0 }, - { 57, 580, 0, 0x19, 0 }, - { 50, 520, 0, 0x18, 0 }, - { 44, 460, 0, 0x17, 0 }, - { 38, 400, 0, 0x16, 0 }, - { 32, 340, 0, 0x15, 0 }, - { 25, 280, 0, 0x14, 0 }, - { 19, 220, 0, 0x13, 0 }, - { 13, 160, 0, 0x12, 0 }, -}; - -static acpi_tstate_t tss_table_coarse[] = { - { 100, 1000, 0, 0x00, 0 }, - { 88, 875, 0, 0x1f, 0 }, - { 75, 750, 0, 0x1e, 0 }, - { 63, 625, 0, 0x1d, 0 }, - { 50, 500, 0, 0x1c, 0 }, - { 38, 375, 0, 0x1b, 0 }, - { 25, 250, 0, 0x1a, 0 }, - { 13, 125, 0, 0x19, 0 }, -}; - -static void generate_T_state_entries(int core, int cores_per_package) -{ - /* Indicate SW_ALL coordination for T-states */ - acpigen_write_TSD_package(core, cores_per_package, SW_ALL); - - /* Indicate FFixedHW so OS will use MSR */ - acpigen_write_empty_PTC(); - - /* Set a T-state limit that can be modified in NVS */ - acpigen_write_TPC("\\TLVL"); - - /* - * CPUID.(EAX=6):EAX[5] indicates support - * for extended throttle levels. - */ - if (cpuid_eax(6) & (1 << 5)) - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_fine), tss_table_fine); - else - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_coarse), tss_table_coarse); -} - -static int calculate_power(int tdp, int p1_ratio, int ratio) -{ - u32 m; - u32 power; - - /* - * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 - * - * Power = (ratio / p1_ratio) * m * tdp - */ - - m = (110000 - ((p1_ratio - ratio) * 625)) / 11; - m = (m * m) / 1000; - - power = ((ratio * 100000 / p1_ratio) / 100); - power *= (m / 100) * (tdp / 1000); - power /= 1000; - - return (int)power; -} - -static void generate_P_state_entries(int core, int cores_per_package) -{ - int ratio_min, ratio_max, ratio_turbo, ratio_step; - int coord_type, power_max, power_unit, num_entries; - int ratio, power, clock, clock_max; - msr_t msr; - - /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) - coord_type = SW_ANY; - else - coord_type = HW_ALL; - - /* Get bus ratio limits and calculate clock speeds */ - msr = rdmsr(MSR_PLATFORM_INFO); - ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ - - /* Determine if this CPU has configurable TDP */ - if (cpu_config_tdp_levels()) { - /* Set max ratio to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - ratio_max = msr.lo & 0xff; - } else { - /* Max Non-Turbo Ratio */ - ratio_max = (msr.lo >> 8) & 0xff; - } - clock_max = ratio_max * HASWELL_BCLK; - - /* Calculate CPU TDP in mW */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 2 << ((msr.lo & 0xf) - 1); - msr = rdmsr(MSR_PKG_POWER_SKU); - power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; - - /* Write _PCT indicating use of FFixedHW */ - acpigen_write_empty_PCT(); - - /* Write _PPC with no limit on supported P-state */ - acpigen_write_PPC_NVS(); - - /* Write PSD indicating configured coordination type */ - acpigen_write_PSD_package(core, 1, coord_type); - - /* Add P-state entries in _PSS table */ - acpigen_write_name("_PSS"); - - /* Determine ratio points */ - ratio_step = PSS_RATIO_STEP; - num_entries = (ratio_max - ratio_min) / ratio_step; - while (num_entries > PSS_MAX_ENTRIES-1) { - ratio_step <<= 1; - num_entries >>= 1; - } - - /* P[T] is Turbo state if enabled */ - if (get_turbo_state() == TURBO_ENABLED) { - /* _PSS package count including Turbo */ - acpigen_write_package(num_entries + 2); - - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - ratio_turbo = msr.lo & 0xff; - - /* Add entry for Turbo ratio */ - acpigen_write_PSS_package( - clock_max + 1, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_turbo << 8, /*control*/ - ratio_turbo << 8); /*status*/ - } else { - /* _PSS package count without Turbo */ - acpigen_write_package(num_entries + 1); - } - - /* First regular entry is max non-turbo ratio */ - acpigen_write_PSS_package( - clock_max, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_max << 8, /*control*/ - ratio_max << 8); /*status*/ - - /* Generate the remaining entries */ - for (ratio = ratio_min + ((num_entries - 1) * ratio_step); - ratio >= ratio_min; ratio -= ratio_step) { - - /* Calculate power at this ratio */ - power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * HASWELL_BCLK; - - acpigen_write_PSS_package( - clock, /*MHz*/ - power, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio << 8, /*control*/ - ratio << 8); /*status*/ - } - - /* Fix package length */ - acpigen_pop_len(); -} - -void generate_cpu_entries(const struct device *device) -{ - int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6; - int totalcores = dev_count_cpu(); - int cores_per_package = get_cores_per_package(); - int numcpus = totalcores/cores_per_package; - - printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", - numcpus, cores_per_package); - - for (cpuID = 1; cpuID <= numcpus; cpuID++) { - for (coreID = 1; coreID <= cores_per_package; coreID++) { - if (coreID > 1) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor \_SB.CPUx */ - acpigen_write_processor( - (cpuID-1)*cores_per_package+coreID-1, - pcontrol_blk, plen); - - /* Generate P-state tables */ - generate_P_state_entries( - coreID-1, cores_per_package); - - /* Generate C-state tables */ - generate_C_state_entries(); - - /* Generate T-state tables */ - generate_T_state_entries( - cpuID-1, cores_per_package); - - acpigen_pop_len(); - } - } - - /* PPKG is usually used for thermal management - of the first and only package. */ - acpigen_write_processor_package("PPKG", 0, cores_per_package); - - /* Add a method to notify processor nodes */ - acpigen_write_processor_cnot(cores_per_package); -} +/* FIXME: For verification purposes only */ +#include <cpu/intel/haswell/acpi_common.c> struct chip_operations cpu_intel_haswell_ops = { CHIP_NAME("Intel Haswell CPU") diff --git a/src/cpu/intel/haswell/acpi_common.c b/src/cpu/intel/haswell/acpi_common.c new file mode 100644 index 0000000..545f319 --- /dev/null +++ b/src/cpu/intel/haswell/acpi_common.c @@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This file is being included from other C files! */ + +static int get_cores_per_package(void) +{ + struct cpuinfo_x86 c; + struct cpuid_result result; + int cores = 1; + + get_fms(&c, cpuid_eax(1)); + if (c.x86 != 6) + return 1; + + result = cpuid_ext(0xb, 1); + cores = result.ebx & 0xff; + + return cores; +} + +static acpi_tstate_t tss_table_fine[] = { + { 100, 1000, 0, 0x00, 0 }, + { 94, 940, 0, 0x1f, 0 }, + { 88, 880, 0, 0x1e, 0 }, + { 82, 820, 0, 0x1d, 0 }, + { 75, 760, 0, 0x1c, 0 }, + { 69, 700, 0, 0x1b, 0 }, + { 63, 640, 0, 0x1a, 0 }, + { 57, 580, 0, 0x19, 0 }, + { 50, 520, 0, 0x18, 0 }, + { 44, 460, 0, 0x17, 0 }, + { 38, 400, 0, 0x16, 0 }, + { 32, 340, 0, 0x15, 0 }, + { 25, 280, 0, 0x14, 0 }, + { 19, 220, 0, 0x13, 0 }, + { 13, 160, 0, 0x12, 0 }, +}; + +static acpi_tstate_t tss_table_coarse[] = { + { 100, 1000, 0, 0x00, 0 }, + { 88, 875, 0, 0x1f, 0 }, + { 75, 750, 0, 0x1e, 0 }, + { 63, 625, 0, 0x1d, 0 }, + { 50, 500, 0, 0x1c, 0 }, + { 38, 375, 0, 0x1b, 0 }, + { 25, 250, 0, 0x1a, 0 }, + { 13, 125, 0, 0x19, 0 }, +}; + +static void generate_T_state_entries(int core, int cores_per_package) +{ + /* Indicate SW_ALL coordination for T-states */ + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + + /* Indicate FFixedHW so OS will use MSR */ + acpigen_write_empty_PTC(); + + /* Set a T-state limit that can be modified in NVS */ + acpigen_write_TPC("\\TLVL"); + + /* + * CPUID.(EAX=6):EAX[5] indicates support + * for extended throttle levels. + */ + if (cpuid_eax(6) & (1 << 5)) + acpigen_write_TSS_package( + ARRAY_SIZE(tss_table_fine), tss_table_fine); + else + acpigen_write_TSS_package( + ARRAY_SIZE(tss_table_coarse), tss_table_coarse); +} + +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + + return (int)power; +} + +#ifndef HASWELL_BCLK +#define HASWELL_BCLK CPU_BCLK +#endif + +static void generate_P_state_entries(int core, int cores_per_package) +{ + int ratio_min, ratio_max, ratio_turbo, ratio_step; + int coord_type, power_max, power_unit, num_entries; + int ratio, power, clock, clock_max; + msr_t msr; + + /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) + coord_type = SW_ANY; + else + coord_type = HW_ALL; + + /* Get bus ratio limits and calculate clock speeds */ + msr = rdmsr(MSR_PLATFORM_INFO); + ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ + + /* Determine if this CPU has configurable TDP */ + if (cpu_config_tdp_levels()) { + /* Set max ratio to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + ratio_max = msr.lo & 0xff; + } else { + /* Max Non-Turbo Ratio */ + ratio_max = (msr.lo >> 8) & 0xff; + } + clock_max = ratio_max * HASWELL_BCLK; + + /* Calculate CPU TDP in mW */ + msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 2 << ((msr.lo & 0xf) - 1); + msr = rdmsr(MSR_PKG_POWER_SKU); + power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; + + /* Write _PCT indicating use of FFixedHW */ + acpigen_write_empty_PCT(); + + /* Write _PPC with no limit on supported P-state */ + acpigen_write_PPC_NVS(); + + /* Write PSD indicating configured coordination type */ + acpigen_write_PSD_package(core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + acpigen_write_name("_PSS"); + + /* Determine ratio points */ + ratio_step = PSS_RATIO_STEP; + num_entries = (ratio_max - ratio_min) / ratio_step; + while (num_entries > PSS_MAX_ENTRIES-1) { + ratio_step <<= 1; + num_entries >>= 1; + } + + /* P[T] is Turbo state if enabled */ + if (get_turbo_state() == TURBO_ENABLED) { + /* _PSS package count including Turbo */ + acpigen_write_package(num_entries + 2); + + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + ratio_turbo = msr.lo & 0xff; + + /* Add entry for Turbo ratio */ + acpigen_write_PSS_package( + clock_max + 1, /*MHz*/ + power_max, /*mW*/ + PSS_LATENCY_TRANSITION, /*lat1*/ + PSS_LATENCY_BUSMASTER, /*lat2*/ + ratio_turbo << 8, /*control*/ + ratio_turbo << 8); /*status*/ + } else { + /* _PSS package count without Turbo */ + acpigen_write_package(num_entries + 1); + } + + /* First regular entry is max non-turbo ratio */ + acpigen_write_PSS_package( + clock_max, /*MHz*/ + power_max, /*mW*/ + PSS_LATENCY_TRANSITION, /*lat1*/ + PSS_LATENCY_BUSMASTER, /*lat2*/ + ratio_max << 8, /*control*/ + ratio_max << 8); /*status*/ + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = ratio * HASWELL_BCLK; + + acpigen_write_PSS_package( + clock, /*MHz*/ + power, /*mW*/ + PSS_LATENCY_TRANSITION, /*lat1*/ + PSS_LATENCY_BUSMASTER, /*lat2*/ + ratio << 8, /*control*/ + ratio << 8); /*status*/ + } + + /* Fix package length */ + acpigen_pop_len(); +} + +void generate_cpu_entries(const struct device *device) +{ + int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6; + int totalcores = dev_count_cpu(); + int cores_per_package = get_cores_per_package(); + int numcpus = totalcores/cores_per_package; + + printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", + numcpus, cores_per_package); + + for (cpuID = 1; cpuID <= numcpus; cpuID++) { + for (coreID = 1; coreID <= cores_per_package; coreID++) { + if (coreID > 1) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor \_SB.CPUx */ + acpigen_write_processor( + (cpuID - 1) * cores_per_package+coreID - 1, + pcontrol_blk, plen); + + /* Generate P-state tables */ + generate_P_state_entries( + coreID - 1, cores_per_package); + + /* Generate C-state tables */ + generate_C_state_entries(); + + /* Generate T-state tables */ + generate_T_state_entries( + cpuID - 1, cores_per_package); + + acpigen_pop_len(); + } + } + + /* PPKG is usually used for thermal management + of the first and only package. */ + acpigen_write_processor_package("PPKG", 0, cores_per_package); + + /* Add a method to notify processor nodes */ + acpigen_write_processor_cnot(cores_per_package); +} diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index c9e3f2a..6b5d85f 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -5,11 +5,17 @@ #include <cpu/x86/msr.h> #include <arch/io.h> #include <halt.h> +#include <delay.h> -#include "haswell.h" - +#if CONFIG(CPU_INTEL_HASWELL) +#include <cpu/intel/haswell/haswell.h> #include <southbridge/intel/lynxpoint/pch.h> +#elif CONFIG(CPU_INTEL_BROADWELL) +#include <cpu/intel/broadwell/broadwell.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#endif + static void set_flex_ratio_to_tdp_nominal(void) { msr_t flex_ratio, msr; @@ -50,6 +56,10 @@ /* Set soft reset control to use register value */ RCBA32_OR(SOFT_RESET_CTRL, 1); + /* Delay before reset to avoid potential TPM lockout */ + if (CONFIG(CPU_INTEL_BROADWELL)) + mdelay(30); + /* Issue warm reset, will be "CPU only" due to soft reset data */ outb(0x0, 0xcf9); outb(0x6, 0xcf9); diff --git a/src/cpu/intel/haswell/cstate_def.c b/src/cpu/intel/haswell/cstate_def.c new file mode 100644 index 0000000..ede75b0 --- /dev/null +++ b/src/cpu/intel/haswell/cstate_def.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This file is being included from other C files! */ + +/* + * List of supported C-states in this processor. Only the ULT parts support C8, + * C9, and C10. + */ +enum { + C_STATE_C0, /* 0 */ + C_STATE_C1, /* 1 */ + C_STATE_C1E, /* 2 */ + C_STATE_C3, /* 3 */ + C_STATE_C6_SHORT_LAT, /* 4 */ + C_STATE_C6_LONG_LAT, /* 5 */ + C_STATE_C7_SHORT_LAT, /* 6 */ + C_STATE_C7_LONG_LAT, /* 7 */ + C_STATE_C7S_SHORT_LAT, /* 8 */ + C_STATE_C7S_LONG_LAT, /* 9 */ + C_STATE_C8, /* 10 */ + C_STATE_C9, /* 11 */ + C_STATE_C10, /* 12 */ + NUM_C_STATES +}; + +#define MWAIT_RES(state, sub_state) \ + { \ + .addrl = (((state) << 4) | (sub_state)), \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ + .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ + } + +static acpi_cstate_t cstate_map[NUM_C_STATES] = { + [C_STATE_C0] = { }, + [C_STATE_C1] = { + .latency = 0, + .power = 1000, + .resource = MWAIT_RES(0, 0), + }, + [C_STATE_C1E] = { + .latency = 0, + .power = 1000, + .resource = MWAIT_RES(0, 1), + }, + [C_STATE_C3] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = 900, + .resource = MWAIT_RES(1, 0), + }, + [C_STATE_C6_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(1), + .power = 800, + .resource = MWAIT_RES(2, 0), + }, + [C_STATE_C6_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(2), + .power = 800, + .resource = MWAIT_RES(2, 1), + }, + [C_STATE_C7_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(1), + .power = 700, + .resource = MWAIT_RES(3, 0), + }, + [C_STATE_C7_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(2), + .power = 700, + .resource = MWAIT_RES(3, 1), + }, + [C_STATE_C7S_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(1), + .power = 700, + .resource = MWAIT_RES(3, 2), + }, + [C_STATE_C7S_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(2), + .power = 700, + .resource = MWAIT_RES(3, 3), + }, + [C_STATE_C8] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(3), + .power = 600, + .resource = MWAIT_RES(4, 0), + }, + [C_STATE_C9] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(4), + .power = 500, + .resource = MWAIT_RES(5, 0), + }, + [C_STATE_C10] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(5), + .power = 400, + .resource = MWAIT_RES(6, 0), + }, +}; diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 7906b83..e47429c 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -29,15 +29,30 @@ #define MSR_LT_LOCK_MEMORY 0x2e7 #define MSR_PIC_MSG_CONTROL 0x2e +#define MSR_CORE_THREAD_COUNT 0x35 #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 - +#define MSR_FEATURE_CONFIG 0x13c +#define SMM_MCA_CAP_MSR 0x17d +#define SMM_CPU_SVRSTR_BIT 57 +#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) +#define MSR_FLEX_RATIO 0x194 +#define FLEX_RATIO_LOCK (1 << 20) +#define FLEX_RATIO_EN (1 << 16) #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_TEMPERATURE_TARGET 0x1a2 +#define MSR_PRMRR_PHYS_BASE 0x1f4 +#define MSR_PRMRR_PHYS_MASK 0x1f5 #define MSR_POWER_CTL 0x1fc +#define MSR_LT_LOCK_MEMORY 0x2e7 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 +#define SMM_FEATURE_CONTROL_MSR 0x4e0 +#define SMM_CPU_SAVE_EN (1 << 1) #define MSR_C_STATE_LATENCY_CONTROL_0 0x60a #define MSR_C_STATE_LATENCY_CONTROL_1 0x60b @@ -77,6 +92,14 @@ #define MSR_CONFIG_TDP_CONTROL 0x64b #define MSR_TURBO_ACTIVATION_RATIO 0x64c +/* SMM save state MSRs */ +#define SMBASE_MSR 0xc20 +#define IEDBASE_MSR 0xc22 + +/* MTRR_CAP_MSR bits */ +#define SMRR_SUPPORTED (1 << 11) +#define PRMRR_SUPPORTED (1 << 12) + /* P-state configuration */ #define PSS_MAX_ENTRIES 8 #define PSS_RATIO_STEP 2 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index e621638..e88c9ef 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -34,99 +34,8 @@ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ (IRTL_1024_NS >> 10)) -/* - * List of supported C-states in this processor. Only the ULT parts support C8, - * C9, and C10. - */ -enum { - C_STATE_C0, /* 0 */ - C_STATE_C1, /* 1 */ - C_STATE_C1E, /* 2 */ - C_STATE_C3, /* 3 */ - C_STATE_C6_SHORT_LAT, /* 4 */ - C_STATE_C6_LONG_LAT, /* 5 */ - C_STATE_C7_SHORT_LAT, /* 6 */ - C_STATE_C7_LONG_LAT, /* 7 */ - C_STATE_C7S_SHORT_LAT, /* 8 */ - C_STATE_C7S_LONG_LAT, /* 9 */ - C_STATE_C8, /* 10 */ - C_STATE_C9, /* 11 */ - C_STATE_C10, /* 12 */ - NUM_C_STATES -}; - -#define MWAIT_RES(state, sub_state) \ - { \ - .addrl = (((state) << 4) | (sub_state)), \ - .space_id = ACPI_ADDRESS_SPACE_FIXED, \ - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ - } - -static acpi_cstate_t cstate_map[NUM_C_STATES] = { - [C_STATE_C0] = { }, - [C_STATE_C1] = { - .latency = 0, - .power = 1000, - .resource = MWAIT_RES(0, 0), - }, - [C_STATE_C1E] = { - .latency = 0, - .power = 1000, - .resource = MWAIT_RES(0, 1), - }, - [C_STATE_C3] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), - .power = 900, - .resource = MWAIT_RES(1, 0), - }, - [C_STATE_C6_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 800, - .resource = MWAIT_RES(2, 0), - }, - [C_STATE_C6_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 800, - .resource = MWAIT_RES(2, 1), - }, - [C_STATE_C7_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 700, - .resource = MWAIT_RES(3, 0), - }, - [C_STATE_C7_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 700, - .resource = MWAIT_RES(3, 1), - }, - [C_STATE_C7S_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 700, - .resource = MWAIT_RES(3, 2), - }, - [C_STATE_C7S_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 700, - .resource = MWAIT_RES(3, 3), - }, - [C_STATE_C8] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(3), - .power = 600, - .resource = MWAIT_RES(4, 0), - }, - [C_STATE_C9] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(4), - .power = 500, - .resource = MWAIT_RES(5, 0), - }, - [C_STATE_C10] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(5), - .power = 400, - .resource = MWAIT_RES(6, 0), - }, -}; +/* FIXME: For verification purposes only */ +#include <cpu/intel/haswell/cstate_def.c> /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { @@ -207,179 +116,9 @@ return ult; } -/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate - * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly - * when a core is woken up. */ -static int pcode_ready(void) -{ - int wait_count; - const int delay_step = 10; - wait_count = 0; - do { - if (!(MCHBAR32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY)) - return 0; - wait_count += delay_step; - udelay(delay_step); - } while (wait_count < 1000); - - return -1; -} - -static void calibrate_24mhz_bclk(void) -{ - int err_code; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); - return; - } - - /* A non-zero value initiates the PCODE calibration. */ - MCHBAR32(BIOS_MAILBOX_DATA) = ~0; - MCHBAR32(BIOS_MAILBOX_INTERFACE) = - MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); - return; - } - - err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; - - printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", - err_code); - - /* Read the calibrated value. */ - MCHBAR32(BIOS_MAILBOX_INTERFACE) = - MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n"); - return; - } - - printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", - MCHBAR32(BIOS_MAILBOX_DATA)); -} - -static u32 pcode_mailbox_read(u32 command) -{ - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); - return 0; - } - - /* Send command and start transaction */ - MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); - return 0; - } - - /* Read mailbox */ - return MCHBAR32(BIOS_MAILBOX_DATA); -} - -static void initialize_vr_config(void) -{ - msr_t msr; - - printk(BIOS_DEBUG, "Initializing VR config.\n"); - - /* Configure VR_CURRENT_CONFIG. */ - msr = rdmsr(MSR_VR_CURRENT_CONFIG); - /* Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid - * on ULT systems. */ - msr.hi &= 0xc0000000; - msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A. */ - msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */ - msr.hi |= (0x0f << (32 - 32)); /* PSI1 threshold - 15A. */ - - if (haswell_is_ult()) - msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */ - /* Leave the max instantaneous current limit (12:0) to default. */ - wrmsr(MSR_VR_CURRENT_CONFIG, msr); - - /* Configure VR_MISC_CONFIG MSR. */ - msr = rdmsr(MSR_VR_MISC_CONFIG); - /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format. */ - msr.hi &= ~(0x3ff << (40 - 32)); - msr.hi |= (0x200 << (40 - 32)); /* 1.0 */ - /* Set IOUT_OFFSET to 0. */ - msr.hi &= ~0xff; - /* Set exit ramp rate to fast. */ - msr.hi |= (1 << (50 - 32)); - /* Set entry ramp rate to slow. */ - msr.hi &= ~(1 << (51 - 32)); - /* Enable decay mode on C-state entry. */ - msr.hi |= (1 << (52 - 32)); - if (haswell_is_ult()) { - /* Set the slow ramp rate to be fast ramp rate / 4 */ - msr.hi &= ~(0x3 << (53 - 32)); - msr.hi |= (0x01 << (53 - 32)); - } - /* Set MIN_VID (31:24) to allow CPU to have full control. */ - msr.lo &= ~0xff000000; - wrmsr(MSR_VR_MISC_CONFIG, msr); - - /* Configure VR_MISC_CONFIG2 MSR. */ - if (haswell_is_ult()) { - msr = rdmsr(MSR_VR_MISC_CONFIG2); - msr.lo &= ~0xffff; - /* Allow CPU to control minimum voltage completely (15:8) and - * set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */ - msr.lo |= 0x006f; - wrmsr(MSR_VR_MISC_CONFIG2, msr); - } -} - -static void configure_pch_power_sharing(void) -{ - u32 pch_power, pch_power_ext, pmsync, pmsync2; - int i; - - /* Read PCH Power levels from PCODE */ - pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER); - pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT); - - printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n", - pch_power, pch_power_ext); - - pmsync = RCBA32(PMSYNC_CONFIG); - pmsync2 = RCBA32(PMSYNC_CONFIG2); - - /* Program PMSYNC_TPR_CONFIG PCH power limit values - * pmsync[0:4] = mailbox[0:5] - * pmsync[8:12] = mailbox[6:11] - * pmsync[16:20] = mailbox[12:17] - */ - for (i = 0; i < 3; i++) { - u32 level = pch_power & 0x3f; - pch_power >>= 6; - pmsync &= ~(0x1f << (i * 8)); - pmsync |= (level & 0x1f) << (i * 8); - } - RCBA32(PMSYNC_CONFIG) = pmsync; - - /* Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values - * pmsync2[0:4] = mailbox[23:18] - * pmsync2[8:12] = mailbox_ext[6:11] - * pmsync2[16:20] = mailbox_ext[12:17] - * pmsync2[24:28] = mailbox_ext[18:22] - */ - pmsync2 &= ~0x1f; - pmsync2 |= pch_power & 0x1f; - - for (i = 1; i < 4; i++) { - u32 level = pch_power_ext & 0x3f; - pch_power_ext >>= 6; - pmsync2 &= ~(0x1f << (i * 8)); - pmsync2 |= (level & 0x1f) << (i * 8); - } - RCBA32(PMSYNC_CONFIG2) = pmsync2; -} +/* FIXME: For verification purposes only */ +#include <cpu/intel/haswell/hsw_bdw_init_common.c> int cpu_config_tdp_levels(void) { @@ -466,6 +205,59 @@ } } +static void initialize_vr_config(void) +{ + msr_t msr; + + printk(BIOS_DEBUG, "Initializing VR config.\n"); + + /* Configure VR_CURRENT_CONFIG. */ + msr = rdmsr(MSR_VR_CURRENT_CONFIG); + /* Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid + * on ULT systems. */ + msr.hi &= 0xc0000000; + msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A. */ + msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */ + msr.hi |= (0x0f << (32 - 32)); /* PSI1 threshold - 15A. */ + + if (haswell_is_ult()) + msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */ + /* Leave the max instantaneous current limit (12:0) to default. */ + wrmsr(MSR_VR_CURRENT_CONFIG, msr); + + /* Configure VR_MISC_CONFIG MSR. */ + msr = rdmsr(MSR_VR_MISC_CONFIG); + /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format. */ + msr.hi &= ~(0x3ff << (40 - 32)); + msr.hi |= (0x200 << (40 - 32)); /* 1.0 */ + /* Set IOUT_OFFSET to 0. */ + msr.hi &= ~0xff; + /* Set exit ramp rate to fast. */ + msr.hi |= (1 << (50 - 32)); + /* Set entry ramp rate to slow. */ + msr.hi &= ~(1 << (51 - 32)); + /* Enable decay mode on C-state entry. */ + msr.hi |= (1 << (52 - 32)); + if (haswell_is_ult()) { + /* Set the slow ramp rate to be fast ramp rate / 4 */ + msr.hi &= ~(0x3 << (53 - 32)); + msr.hi |= (0x01 << (53 - 32)); + } + /* Set MIN_VID (31:24) to allow CPU to have full control. */ + msr.lo &= ~0xff000000; + wrmsr(MSR_VR_MISC_CONFIG, msr); + + /* Configure VR_MISC_CONFIG2 MSR. */ + if (haswell_is_ult()) { + msr = rdmsr(MSR_VR_MISC_CONFIG2); + msr.lo &= ~0xffff; + /* Allow CPU to control minimum voltage completely (15:8) and + * set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */ + msr.lo |= 0x006f; + wrmsr(MSR_VR_MISC_CONFIG2, msr); + } +} + static void configure_c_states(void) { msr_t msr; @@ -556,50 +348,6 @@ } } -static void configure_misc(void) -{ - msr_t msr; - - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ - msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLE, msr); - - /* Disable Thermal interrupts */ - msr.lo = 0; - msr.hi = 0; - wrmsr(IA32_THERM_INTERRUPT, msr); - - /* Enable package critical interrupt only */ - msr.lo = 1 << 4; - msr.hi = 0; - wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); -} - -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - -static void configure_dca_cap(void) -{ - uint32_t feature_flag; - msr_t msr; - - /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - feature_flag = cpu_get_feature_flags_ecx(); - if (feature_flag & CPUID_DCA) { - msr = rdmsr(IA32_PLATFORM_DCA_CAP); - msr.lo |= 1; - wrmsr(IA32_PLATFORM_DCA_CAP, msr); - } -} - static void set_max_ratio(void) { msr_t msr, perf_ctl; @@ -642,22 +390,6 @@ policy); } -static void configure_mca(void) -{ - msr_t msr; - int i; - int num_banks; - - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & 0xff; - msr.lo = msr.hi = 0; - /* TODO(adurbin): This should only be done on a cold boot. Also, some - * of these banks are core vs package scope. For now every CPU clears - * every bank. */ - for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); -} - /* All CPUs including BSP will run the following function. */ static void haswell_init(struct device *cpu) { @@ -693,9 +425,6 @@ enable_turbo(); } -/* MP initialization support. */ -static const void *microcode_patch; - static void pre_mp_init(void) { /* Setup MTRRs based on physical address size. */ @@ -710,37 +439,6 @@ } } -static int get_cpu_count(void) -{ - msr_t msr; - int num_threads; - int num_cores; - - msr = rdmsr(MSR_CORE_THREAD_COUNT); - num_threads = (msr.lo >> 0) & 0xffff; - num_cores = (msr.lo >> 16) & 0xffff; - printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", - num_cores, num_threads); - - return num_threads; -} - -static void get_microcode_info(const void **microcode, int *parallel) -{ - microcode_patch = intel_microcode_find(); - *microcode = microcode_patch; - *parallel = 1; -} - -static void per_cpu_smm_trigger(void) -{ - /* Relocate the SMM handler. */ - smm_relocate(); - - /* After SMM relocation a 2nd microcode load is required. */ - intel_microcode_load_unlocked(microcode_patch); -} - static void post_mp_init(void) { /* Now that all APs have been relocated as well as the BSP let SMIs diff --git a/src/cpu/intel/haswell/hsw_bdw_init_common.c b/src/cpu/intel/haswell/hsw_bdw_init_common.c new file mode 100644 index 0000000..b32ccf9 --- /dev/null +++ b/src/cpu/intel/haswell/hsw_bdw_init_common.c @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This file is being included from other C files! */ + +/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate + * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly + * when a core is woken up. */ +static int pcode_ready(void) +{ + int wait_count; + const int delay_step = 10; + + wait_count = 0; + do { + if (!(MCHBAR32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY)) + return 0; + wait_count += delay_step; + udelay(delay_step); + } while (wait_count < 1000); + + return -1; +} + +static void calibrate_24mhz_bclk(void) +{ + int err_code; + + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); + return; + } + + /* A non-zero value initiates the PCODE calibration. */ + MCHBAR32(BIOS_MAILBOX_DATA) = ~0; + MCHBAR32(BIOS_MAILBOX_INTERFACE) = + MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL; + + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); + return; + } + + err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; + + printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", + err_code); + + /* Read the calibrated value. */ + MCHBAR32(BIOS_MAILBOX_INTERFACE) = + MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION; + + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n"); + return; + } + + printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", + MCHBAR32(BIOS_MAILBOX_DATA)); +} + +static u32 pcode_mailbox_read(u32 command) +{ + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); + return 0; + } + + /* Send command and start transaction */ + MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; + + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); + return 0; + } + + /* Read mailbox */ + return MCHBAR32(BIOS_MAILBOX_DATA); +} + +static void configure_pch_power_sharing(void) +{ + u32 pch_power, pch_power_ext, pmsync, pmsync2; + int i; + + /* Read PCH Power levels from PCODE */ + pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER); + pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT); + + printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n", + pch_power, pch_power_ext); + + pmsync = RCBA32(PMSYNC_CONFIG); + pmsync2 = RCBA32(PMSYNC_CONFIG2); + + /* Program PMSYNC_TPR_CONFIG PCH power limit values + * pmsync[0:4] = mailbox[0:5] + * pmsync[8:12] = mailbox[6:11] + * pmsync[16:20] = mailbox[12:17] + */ + for (i = 0; i < 3; i++) { + u32 level = pch_power & 0x3f; + pch_power >>= 6; + pmsync &= ~(0x1f << (i * 8)); + pmsync |= (level & 0x1f) << (i * 8); + } + RCBA32(PMSYNC_CONFIG) = pmsync; + + /* Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values + * pmsync2[0:4] = mailbox[23:18] + * pmsync2[8:12] = mailbox_ext[6:11] + * pmsync2[16:20] = mailbox_ext[12:17] + * pmsync2[24:28] = mailbox_ext[18:22] + */ + pmsync2 &= ~0x1f; + pmsync2 |= pch_power & 0x1f; + + for (i = 1; i < 4; i++) { + u32 level = pch_power_ext & 0x3f; + pch_power_ext >>= 6; + pmsync2 &= ~(0x1f << (i * 8)); + pmsync2 |= (level & 0x1f) << (i * 8); + } + RCBA32(PMSYNC_CONFIG2) = pmsync2; +} + +static void configure_misc(void) +{ + msr_t msr; + + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + wrmsr(IA32_MISC_ENABLE, msr); + + /* Disable Thermal interrupts */ + msr.lo = 0; + msr.hi = 0; + wrmsr(IA32_THERM_INTERRUPT, msr); + + /* Enable package critical interrupt only */ + msr.lo = 1 << 4; + msr.hi = 0; + wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); +} + +static void enable_lapic_tpr(void) +{ + msr_t msr; + + msr = rdmsr(MSR_PIC_MSG_CONTROL); + msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ + wrmsr(MSR_PIC_MSG_CONTROL, msr); +} + +static void configure_dca_cap(void) +{ + uint32_t feature_flag; + msr_t msr; + + /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ + feature_flag = cpu_get_feature_flags_ecx(); + if (feature_flag & CPUID_DCA) { + msr = rdmsr(IA32_PLATFORM_DCA_CAP); + msr.lo |= 1; + wrmsr(IA32_PLATFORM_DCA_CAP, msr); + } +} + +static void configure_mca(void) +{ + msr_t msr; + int i; + int num_banks; + + msr = rdmsr(IA32_MCG_CAP); + num_banks = msr.lo & 0xff; + msr.lo = msr.hi = 0; + /* TODO(adurbin): This should only be done on a cold boot. Also, some + * of these banks are core vs package scope. For now every CPU clears + * every bank. */ + for (i = 0; i < num_banks; i++) + wrmsr(IA32_MC0_STATUS + (i * 4), msr); +} + +static int get_cpu_count(void) +{ + msr_t msr; + int num_threads; + int num_cores; + + msr = rdmsr(MSR_CORE_THREAD_COUNT); + num_threads = (msr.lo >> 0) & 0xffff; + num_cores = (msr.lo >> 16) & 0xffff; + printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", + num_cores, num_threads); + + return num_threads; +} + +/* MP initialization support. */ +static const void *microcode_patch; + +static void get_microcode_info(const void **microcode, int *parallel) +{ + microcode_patch = intel_microcode_find(); + *microcode = microcode_patch; + *parallel = 1; +} + +static void per_cpu_smm_trigger(void) +{ + /* Relocate the SMM handler. */ + smm_relocate(); + + /* After SMM relocation a 2nd microcode load is required. */ + intel_microcode_load_unlocked(microcode_patch); +} diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 5e4e028..309c4fa 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -12,28 +12,16 @@ #include <cpu/intel/em64t101_save_state.h> #include <cpu/intel/smm_reloc.h> #include <console/console.h> -#include <northbridge/intel/haswell/haswell.h> -#include <southbridge/intel/lynxpoint/pch.h> #include <smp/node.h> -#include "haswell.h" -#define MSR_PRMRR_PHYS_BASE 0x1f4 -#define MSR_PRMRR_PHYS_MASK 0x1f5 -#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 -#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 -#define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) -#define SMM_FEATURE_CONTROL_MSR 0x4e0 -#define SMM_CPU_SAVE_EN (1 << 1) -/* SMM save state MSRs */ -#define SMBASE_MSR 0xc20 -#define IEDBASE_MSR 0xc22 +#if CONFIG(CPU_INTEL_HASWELL) +#include <northbridge/intel/haswell/haswell.h> +#include <cpu/intel/haswell/haswell.h> -#define SMRR_SUPPORTED (1 << 11) -#define PRMRR_SUPPORTED (1 << 12) - - +#elif CONFIG(CPU_INTEL_BROADWELL) +#include <northbridge/intel/broadwell/broadwell.h> +#include <cpu/intel/broadwell/broadwell.h> +#endif static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, @@ -199,7 +187,7 @@ params->uncore_prmrr_base.lo = prmrr_base; params->uncore_prmrr_base.hi = 0; params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) | - MTRR_PHYS_MASK_VALID; + MTRR_PHYS_MASK_VALID; params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1; } diff --git a/src/northbridge/intel/broadwell/Makefile.inc b/src/northbridge/intel/broadwell/Makefile.inc index 69ea826..59b200b 100644 --- a/src/northbridge/intel/broadwell/Makefile.inc +++ b/src/northbridge/intel/broadwell/Makefile.inc @@ -2,7 +2,7 @@ CPPFLAGS_common += -Isrc/northbridge/intel/broadwell/include -bootblock-y += bootblock.c +bootblock-y += ../haswell/bootblock.c ramstage-y += acpi.c @@ -15,7 +15,7 @@ ramstage-y += memmap.c romstage-y += memmap.c postcar-y += memmap.c -ramstage-y += minihd.c +ramstage-y += ../haswell/minihd.c ramstage-y += northbridge.c diff --git a/src/northbridge/intel/broadwell/acpi/broadwell.asl b/src/northbridge/intel/broadwell/acpi/broadwell.asl index 12296cb..2f9c071 100644 --- a/src/northbridge/intel/broadwell/acpi/broadwell.asl +++ b/src/northbridge/intel/broadwell/acpi/broadwell.asl @@ -2,170 +2,7 @@ #include <southbridge/intel/wildcatpoint/iomap.h> -Name (_HID, EISAID ("PNP0A08")) // PCIe -Name (_CID, EISAID ("PNP0A03")) // PCI - -Name (_BBN, 0) - -Device (MCHC) -{ - Name (_ADR, 0x00000000) // 0:0.0 - - OperationRegion (MCHP, PCI_Config, 0x00, 0x100) - Field (MCHP, DWordAcc, NoLock, Preserve) - { - Offset (0x70), // ME Base Address - MEBA, 64, - Offset (0xa0), // Top of Used Memory - TOM, 64, - Offset (0xbc), // Top of Low Used Memory - TLUD, 32, - } -} - -// Current Resource Settings -Name (MCRS, ResourceTemplate() -{ - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xc0000-0xc3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xc4000-0xc7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xc8000-0xcbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xcc000-0xcffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000,,, OPR3) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR4) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR5) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR6) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR7) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PM01) - - // TPM Area (0xfed40000-0xfed44fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000,,, TPMR) -}) - -Method (_CRS, 0, Serialized) -{ - // Find PCI resource area in MCRS - CreateDwordField(MCRS, ^PM01._MIN, PMIN) - CreateDwordField(MCRS, ^PM01._MAX, PMAX) - CreateDwordField(MCRS, ^PM01._LEN, PLEN) - - // Fix up PCI memory region - // Start with Top of Lower Usable DRAM - // Lower 20 bits of TOLUD register need to be masked since they contain lock and - // reserved bits. - Local0 = ^MCHC.TLUD & (0xfff << 20) - Local1 = ^MCHC.MEBA - - // Check if ME base is equal - If (Local0 == Local1) { - // Use Top Of Memory instead - // Lower 20 bits of TOM register need to be masked since they contain lock and - // reserved bits. - Local0 = ^MCHC.TOM & (0x7ffff << 20) - } - - PMIN = Local0 - PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1 - PLEN = (PMAX - PMIN) + 1 - - Return (MCRS) -} +#include <northbridge/intel/haswell/acpi/hostbridge.asl> /* PCI Device Resource Consumption */ Device (PDRC) @@ -193,5 +30,8 @@ /* PCI IRQ assignment */ #include "pci_irqs.asl" -/* Configurable TDP */ -#include "ctdp.asl" +Scope (\_SB.PCI0.MCHC) +{ + /* Configurable TDP */ + #include <northbridge/intel/haswell/acpi/ctdp.asl> +} diff --git a/src/northbridge/intel/broadwell/bootblock.c b/src/northbridge/intel/broadwell/bootblock.c deleted file mode 100644 index d661f57..0000000 --- a/src/northbridge/intel/broadwell/bootblock.c +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/bootblock.h> -#include <device/pci_ops.h> -#include <southbridge/intel/wildcatpoint/pci_devs.h> -#include <northbridge/intel/broadwell/broadwell.h> - -void bootblock_early_northbridge_init(void) -{ - uint32_t reg; - - /* - * The "io" variant of the config access is explicitly used to setup the PCIEXBAR - * because CONFIG_MMCONF_SUPPORT is set to true. That way, all subsequent - * non-explicit config accesses use MCFG. This code also assumes that - * bootblock_northbridge_init() is the first thing called in the non-asm - * boot block code. The final assumption is that no assembly code is using - * the CONFIG_MMCONF_SUPPORT option to do PCI config acceses. - * - * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. - */ - reg = 0; - pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg); - reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ - pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg); -} diff --git a/src/northbridge/intel/broadwell/broadwell.h b/src/northbridge/intel/broadwell/broadwell.h index 1a8e6cf..ed8356d 100644 --- a/src/northbridge/intel/broadwell/broadwell.h +++ b/src/northbridge/intel/broadwell/broadwell.h @@ -25,7 +25,8 @@ #define MCH_BROADWELL_REV_E0 0x08 #define MCH_BROADWELL_REV_F0 0x09 -/* Device 0:0.0 PCI configuration space */ +/* Device 0:0.0 PCI configuration space (Host Bridge) */ +#define HOST_BRIDGE PCI_DEV(0, 0, 0) #define EPBAR 0x40 #define MCHBAR 0x48 @@ -60,24 +61,26 @@ #define D_LCK (1 << 4) #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -#define CAPID0_A 0xe4 -#define VTD_DISABLE (1 << 23) -#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ -#define DMAR_LCKDN (1 << 31) -#define PRSCAPDIS (1 << 2) -#define MESEG_BASE 0x70 /* Management Engine Base. */ -#define MESEG_LIMIT 0x78 /* Management Engine Limit. */ -#define REMAPBASE 0x90 /* Remap base. */ -#define REMAPLIMIT 0x98 /* Remap limit. */ -#define TOM 0xa0 /* Top of DRAM in memory controller space. */ +#define MESEG_BASE 0x70 /* Management Engine Base */ +#define MESEG_LIMIT 0x78 /* Management Engine Limit */ +#define REMAPBASE 0x90 /* Remap base */ +#define REMAPLIMIT 0x98 /* Remap limit */ +#define TOM 0xa0 /* Top of DRAM in memory controller space */ #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ #define BDSM 0xb0 /* Base Data Stolen Memory */ #define BGSM 0xb4 /* Base GTT Stolen Memory */ #define TSEG 0xb8 /* TSEG base */ #define TOLUD 0xbc /* Top of Low Used Memory */ + #define SKPAD 0xdc /* Scratchpad Data */ +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) +#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ +#define DMAR_LCKDN (1 << 31) +#define PRSCAPDIS (1 << 2) + /* MCHBAR */ #define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + x)) @@ -89,7 +92,7 @@ #define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 #define VTVC0BAR 0x5410 -#define MCH_PAIR 0x5418 +#define INTRDIRCTL 0x5418 #define GDXCBAR 0x5420 #define MCH_PKG_POWER_LIMIT_LO 0x59a0 diff --git a/src/northbridge/intel/broadwell/igd.c b/src/northbridge/intel/broadwell/igd.c index b032782..f752638 100644 --- a/src/northbridge/intel/broadwell/igd.c +++ b/src/northbridge/intel/broadwell/igd.c @@ -24,7 +24,7 @@ #include <northbridge/intel/broadwell/igd.h> #include <types.h> -#define GT_RETRY 1000 +#define GTT_RETRY 1000 enum { GT_CDCLK_DEFAULT = 0, GT_CDCLK_337, @@ -43,7 +43,7 @@ /* Enable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GTT_RETRY), /* Enable Counters */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000016), @@ -104,10 +104,10 @@ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000), /* Set RC6 VIDs */ - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY), /* Enable PM Interrupts */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076), @@ -127,13 +127,13 @@ /* Disable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GTT_RETRY), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00000001), /* Enable power well for DP and Audio */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)), REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400, - (1 << 30), (1 << 30), GT_RETRY), + (1 << 30), (1 << 30), GTT_RETRY), REG_SCRIPT_END }; @@ -141,7 +141,7 @@ static const struct reg_script broadwell_early_init_script[] = { /* Enable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GTT_RETRY), /* Enable push bus metric control and shift */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000004), @@ -206,10 +206,10 @@ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x90040000), /* Set RC6 VIDs */ - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY), /* Enable PM Interrupts */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076), @@ -228,12 +228,12 @@ /* Disable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GTT_RETRY), /* Enable power well for DP and Audio */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)), REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400, - (1 << 30), (1 << 30), GT_RETRY), + (1 << 30), (1 << 30), GTT_RETRY), REG_SCRIPT_END }; @@ -267,13 +267,15 @@ } int gtt_poll(u32 reg, u32 mask, u32 value) -{ unsigned int try = GT_RETRY; +{ + unsigned int try = GTT_RETRY; u32 data; while (try--) { data = gtt_read(reg); if ((data & mask) == value) return 1; + udelay(10); } @@ -327,21 +329,22 @@ Reference clock is 24MHz. We can choose either a 16 or a 128 step increment. Use 16 if we would have less than 100 steps otherwise. */ - const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100; + const unsigned int refclock = 24 * 1000 * 1000; + const unsigned int hz_limit = refclock / 128 / 100; unsigned int pwm_increment, pwm_period; u32 south_chicken2; south_chicken2 = gtt_read(SOUTH_CHICKEN2); if (conf->gpu_pch_backlight_pwm_hz > hz_limit) { pwm_increment = 16; - south_chicken2 |= 1 << 5; + south_chicken2 |= LPT_PWM_GRANULARITY; } else { pwm_increment = 128; - south_chicken2 &= ~(1 << 5); + south_chicken2 &= ~LPT_PWM_GRANULARITY; } gtt_write(SOUTH_CHICKEN2, south_chicken2); - pwm_period = 24 * 1000 * 1000 / pwm_increment / conf->gpu_pch_backlight_pwm_hz; + pwm_period = refclock / pwm_increment / conf->gpu_pch_backlight_pwm_hz; /* Start with a 50% duty cycle. */ gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2); @@ -489,7 +492,7 @@ gtt_rmw(0x64810, 0xfffff800, dpdiv); } -static void igd_init(struct device *dev) +static void gma_func0_init(struct device *dev) { int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT); u32 rp1_gfx_freq; @@ -580,11 +583,11 @@ drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static struct device_operations igd_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .init = &igd_init, +static struct device_operations gma_func0_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gma_func0_init, .ops_pci = &broadwell_pci_ops, .acpi_fill_ssdt = gma_generate_ssdt, }; @@ -603,8 +606,8 @@ 0, }; -static const struct pci_driver igd_driver __pci_driver = { - .ops = &igd_ops, - .vendor = PCI_VENDOR_ID_INTEL, +static const struct pci_driver gma_driver __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; diff --git a/src/northbridge/intel/broadwell/minihd.c b/src/northbridge/intel/broadwell/minihd.c deleted file mode 100644 index 9df1047..0000000 --- a/src/northbridge/intel/broadwell/minihd.c +++ /dev/null @@ -1,111 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <device/mmio.h> -#include <soc/intel/common/hda_verb.h> -#include <southbridge/intel/wildcatpoint/ramstage.h> -#include <northbridge/intel/broadwell/igd.h> - -static const u32 minihd_verb_table[] = { - /* coreboot specific header */ - 0x80862808, /* Codec Vendor / Device ID: Intel Broadwell Mini-HD */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of jacks */ - - /* Enable 3rd Pin and Converter Widget */ - 0x00878101, - - /* Pin Widget 5 - PORT B */ - 0x00571c10, - 0x00571d00, - 0x00571e56, - 0x00571f18, - - /* Pin Widget 6 - PORT C */ - 0x00671c20, - 0x00671d00, - 0x00671e56, - 0x00671f18, - - /* Pin Widget 7 - PORT D */ - 0x00771c30, - 0x00771d00, - 0x00771e56, - 0x00771f18, - - /* Disable 3rd Pin and Converter Widget */ - 0x00878100, - - /* Dummy entries to fill out the table */ - 0x00878100, - 0x00878100, -}; - -static void minihd_init(struct device *dev) -{ - struct resource *res; - u32 reg32; - u8 *base; - int codec_mask, i; - - /* Find base address */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) - return; - - base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base); - - /* Set Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* Mini-HD configuration */ - reg32 = read32(base + 0x100c); - reg32 &= 0xfffc0000; - reg32 |= 0x4; - write32(base + 0x100c, reg32); - - reg32 = read32(base + 0x1010); - reg32 &= 0xfffc0000; - reg32 |= 0x4b; - write32(base + 0x1010, reg32); - - /* Init the codec and write the verb table */ - codec_mask = hda_codec_detect(base); - - if (codec_mask) { - for (i = 3; i >= 0; i--) { - if (codec_mask & (1 << i)) - hda_codec_init(base, i, sizeof(minihd_verb_table), - minihd_verb_table); - } - } - - /* Set EM4/EM5 registers */ - write32(base + 0x0100c, igd_get_reg_em4()); - write32(base + 0x01010, igd_get_reg_em5()); -} - -static struct device_operations minihd_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = minihd_init, - .ops_pci = &broadwell_pci_ops, -}; - -static const unsigned short pci_device_ids[] = { - 0x0a0c, /* Haswell */ - 0x160c, /* Broadwell */ - 0 -}; - -static const struct pci_driver minihd_driver __pci_driver = { - .ops = &minihd_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; diff --git a/src/northbridge/intel/broadwell/northbridge.c b/src/northbridge/intel/broadwell/northbridge.c index 480c17a..bf403f6 100644 --- a/src/northbridge/intel/broadwell/northbridge.c +++ b/src/northbridge/intel/broadwell/northbridge.c @@ -16,227 +16,8 @@ #include <southbridge/intel/wildcatpoint/ramstage.h> #include <northbridge/intel/broadwell/broadwell.h> -static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) -{ - u32 pciexbar_reg; - - *base = 0; - *len = 0; - - pciexbar_reg = pci_read_config32(dev, index); - - if (!(pciexbar_reg & (1 << 0))) - return 0; - - switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| - (1 << 28)); - *len = 256 * 1024 * 1024; - return 1; - case 1: // 128M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| - (1 << 28)|(1 << 27)); - *len = 128 * 1024 * 1024; - return 1; - case 2: // 64M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| - (1 << 28)|(1 << 27)|(1 << 26)); - *len = 64 * 1024 * 1024; - return 1; - } - - return 0; -} - -static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) -{ - u32 bar = pci_read_config32(dev, index); - - /* If not enabled don't report it */ - if (!(bar & 0x1)) - return 0; - - /* Knock down the enable bit */ - *base = bar & ~1; - - return 1; -} - -/* - * There are special BARs that actually are programmed in the MCHBAR. These Intel special - * features, but they do consume resources that need to be accounted for. - */ -static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) -{ - u32 bar = MCHBAR32(index); - - /* If not enabled don't report it */ - if (!(bar & 0x1)) - return 0; - - /* Knock down the enable bit */ - *base = bar & ~1; - - return 1; -} - -struct fixed_mmio_descriptor { - unsigned int index; - u32 size; - int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); - const char *description; -}; - -struct fixed_mmio_descriptor mc_fixed_resources[] = { - { PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" }, - { MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" }, - { DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" }, - { EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" }, - { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" }, - { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" }, -}; - -/* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */ -static void mc_add_fixed_mmio_resources(struct device *dev) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) { - u32 base; - u32 size; - struct resource *resource; - unsigned int index; - - size = mc_fixed_resources[i].size; - index = mc_fixed_resources[i].index; - if (!mc_fixed_resources[i].get_resource(dev, index, &base, &size)) - continue; - - resource = new_resource(dev, mc_fixed_resources[i].index); - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | - IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; - - resource->base = base; - resource->size = size; - printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", - __func__, mc_fixed_resources[i].description, index, - (unsigned long)base, (unsigned long)(base + size - 1)); - } -} - -/* Host Memory Map: - * - * +--------------------------+ TOUUD - * | | - * +--------------------------+ 4GiB - * | PCI Address Space | - * +--------------------------+ TOLUD (also maps into MC address space) - * | iGD | - * +--------------------------+ BDSM - * | GTT | - * +--------------------------+ BGSM - * | TSEG | - * +--------------------------+ TSEGMB - * | Usage DRAM | - * +--------------------------+ 0 - * - * Some of the base registers above can be equal, making the size of the regions within 0. - * This is because the memory controller internally subtracts the base registers from each - * other to determine sizes of the regions. In other words, the memory map regions are always - * in a fixed order, no matter what sizes they have. - */ - -struct map_entry { - int reg; - int is_64_bit; - int is_limit; - const char *description; -}; - -static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) -{ - uint64_t value; - uint64_t mask; - - /* All registers have a 1MiB granularity */ - mask = ((1ULL << 20) - 1); - mask = ~mask; - - value = 0; - - if (entry->is_64_bit) { - value = pci_read_config32(dev, entry->reg + 4); - value <<= 32; - } - - value |= pci_read_config32(dev, entry->reg); - value &= mask; - - if (entry->is_limit) - value |= ~mask; - - *result = value; -} - -#define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ - { \ - .reg = reg_, \ - .is_64_bit = is_64_, \ - .is_limit = is_limit_, \ - .description = desc_, \ - } - -#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_) -#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_) -#define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_) - -enum { - TOM_REG, - TOUUD_REG, - MESEG_BASE_REG, - MESEG_LIMIT_REG, - REMAP_BASE_REG, - REMAP_LIMIT_REG, - TOLUD_REG, - BGSM_REG, - BDSM_REG, - TSEG_REG, - /* Must be last */ - NUM_MAP_ENTRIES, -}; - -static struct map_entry memory_map[NUM_MAP_ENTRIES] = { - [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), - [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), - [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), - [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), - [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), - [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), - [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), - [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), - [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), - [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"), -}; - -static void mc_read_map_entries(struct device *dev, uint64_t *values) -{ - int i; - for (i = 0; i < NUM_MAP_ENTRIES; i++) { - read_map_entry(dev, &memory_map[i], &values[i]); - } -} - -static void mc_report_map_entries(struct device *dev, uint64_t *values) -{ - int i; - for (i = 0; i < NUM_MAP_ENTRIES; i++) { - printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", - memory_map[i].description, values[i]); - } - /* One can validate the BDSM and BGSM against the GGC */ - printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); -} +/* FIXME: For verification purposes only */ +#include <northbridge/intel/haswell/northbridge_common.c> static void mc_add_dram_resources(struct device *dev, int *resource_cnt) { @@ -248,8 +29,8 @@ struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* Read in the MAP registers and report their values */ - mc_read_map_entries(dev, &mc_values[0]); - mc_report_map_entries(dev, &mc_values[0]); + mc_read_map_entries(dev, mc_values); + mc_report_map_entries(dev, mc_values); /* * DMA Protected Range can be reserved below TSEG for PCODE patch @@ -339,41 +120,20 @@ *resource_cnt = index; } -static void mc_read_resources(struct device *dev) -{ - int index = 0; - const bool vtd_capable = !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); - - /* Read standard PCI resources */ - pci_dev_read_resources(dev); - - /* Add all fixed MMIO resources */ - mc_add_fixed_mmio_resources(dev); - - /* Add VT-d MMIO resources, if capable */ - if (vtd_capable) { - mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB); - mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB); - } - - /* Calculate and add DRAM resources */ - mc_add_dram_resources(dev, &index); -} - -static void systemagent_init(struct device *dev) +static void northbridge_init(struct device *dev) { struct soc_power_limits_config *config; u8 bios_reset_cpl, pair; /* Enable Power Aware Interrupt Routing */ - pair = MCHBAR8(MCH_PAIR); + pair = MCHBAR8(INTRDIRCTL); pair &= ~0x7; /* Clear 2:0 */ pair |= 0x4; /* Fixed Priority */ - MCHBAR8(MCH_PAIR) = pair; + MCHBAR8(INTRDIRCTL) = pair; /* * Set bits 0 + 1 of BIOS_RESET_CPL to indicate to the CPU - * that BIOS has initialized memory and power management + * that BIOS has initialized memory and power management. */ bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); bios_reset_cpl |= 3; @@ -391,7 +151,7 @@ .acpi_fill_ssdt = generate_cpu_entries, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = systemagent_init, + .init = northbridge_init, .ops_pci = &broadwell_pci_ops, }; diff --git a/src/northbridge/intel/broadwell/acpi/ctdp.asl b/src/northbridge/intel/haswell/acpi/ctdp.asl similarity index 78% rename from src/northbridge/intel/broadwell/acpi/ctdp.asl rename to src/northbridge/intel/haswell/acpi/ctdp.asl index 8391482..59fd37c 100644 --- a/src/northbridge/intel/broadwell/acpi/ctdp.asl +++ b/src/northbridge/intel/haswell/acpi/ctdp.asl @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Scope (\_SB.PCI0.MCHC) -{ Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ Name (CTCC, 0) /* CTDP Current Selection */ Name (CTCN, 0) /* CTDP Nominal Select */ @@ -9,8 +7,7 @@ Name (CTCU, 2) /* CTDP Up Select */ Name (SPL1, 0) /* Saved PL1 value */ - OperationRegion (MCHB, SystemMemory, - Add (MCH_BASE_ADDRESS, 0x5000), 0x1000) + OperationRegion (MCHB, SystemMemory, Add (DEFAULT_MCHBAR, 0x5000), 0x1000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x930), /* PACKAGE_POWER_SKU */ @@ -62,17 +59,16 @@ External (\_SB.CP00._PSS) Method (PSSS, 1, NotSerialized) { - Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_SB.CP00._PSS), Local1) + Local0 = One /* Start at P1 */ + Local1 = SizeOf (\_SB.CP00._PSS) - While (LLess (Local0, Local1)) { + While (Local0 < Local1) { /* Store _PSS entry Control value to Local2 */ - ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_SB.CP00._PSS, Local0)), 4)), 8, Local2) - If (LEqual (Local2, Arg0)) { - Return (Subtract (Local0, 1)) + Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8 + If (Local2 == Arg0) { + Return (Local0 - 1) } - Increment (Local0) + Local0++ } Return (0) @@ -81,9 +77,19 @@ /* Calculate PL2 based on chip type */ Method (CPL2, 1, NotSerialized) { +#if CONFIG(NORTHBRIDGE_INTEL_HASWELL) + If (\ISLP ()) { + /* Haswell ULT PL2 = 25W */ + Return (25 * 8) + } Else { + /* Haswell Mobile PL2 = 1.25 * PL1 */ + Return ((Arg0 * 125) / 100) + } +#elif CONFIG(NORTHBRIDGE_INTEL_BROADWELL) /* Haswell ULT PL2 = 25W */ /* FIXME: update for broadwell */ Return (Multiply (25, 8)) +#endif } /* Set Config TDP Down */ @@ -100,23 +106,23 @@ Store ("Set TDP Down", Debug) /* Set CTC */ - Store (CTCD, CTCS) + CTCS = CTCD /* Set TAR */ - Store (TARD, TARS) + TARS = TARD /* Set PPC limit and notify OS */ - Store (PSSS (TARD), PPCM) + PPCM = PSSS (TARD) PPCN () /* Set PL2 */ - Store (CPL2 (CTDD), PL2V) + PL2V = CPL2 (CTDD) /* Set PL1 */ - Store (CTDD, PL1V) + PL1V = CTDD /* Store the new TDP Down setting */ - Store (CTCD, CTCC) + CTCC = CTCD Release (CTCM) Return (1) @@ -128,7 +134,7 @@ If (Acquire (CTCM, 100)) { Return (0) } - If (LEqual (CTCN, CTCC)) { + If (CTCN == CTCC) { Release (CTCM) Return (0) } @@ -136,23 +142,23 @@ Store ("Set TDP Nominal", Debug) /* Set PL1 */ - Store (CTDN, PL1V) + PL1V = CTDN /* Set PL2 */ - Store (CPL2 (CTDN), PL2V) + PL2V = CPL2 (CTDN) /* Set PPC limit and notify OS */ - Store (PSSS (TARN), PPCM) + PPCM = PSSS (TARN) PPCN () /* Set TAR */ - Store (TARN, TARS) + TARS = TARN /* Set CTC */ - Store (CTCN, CTCS) + CTCS = CTCN /* Store the new TDP Nominal setting */ - Store (CTCN, CTCC) + CTCC = CTCN Release (CTCM) Return (1) @@ -161,7 +167,7 @@ /* Calculate PL1 value based on requested TDP */ Method (TDPP, 1, NotSerialized) { - Return (Multiply (ShiftLeft (Subtract (PUNI, 1), 2), Arg0)) + Return (((PUNI - 1) << 2) * Arg0) } /* Enable Controllable TDP to limit PL1 to requested value */ @@ -174,19 +180,19 @@ Store ("Enable PL1 Limit", Debug) /* Set _PPC to LFM */ - Store (PSSS (LFM_), Local0) - Add (Local0, 1, PPCM) + Local0 = PSSS (LFM_) + PPCM = Local0 + 1 \PPCN () /* Set TAR to LFM-1 */ - Subtract (LFM_, 1, TARS) + TARS = LFM_ - 1 /* Set PL1 to desired value */ - Store (PL1V, SPL1) - Store (TDPP (Arg0), PL1V) + SPL1 = PL1V + PL1V = TDPP (Arg0) /* Set PL1 CLAMP bit */ - Store (One, PL1C) + PL1C = 1 Release (CTCM) Return (1) @@ -202,19 +208,18 @@ Store ("Disable PL1 Limit", Debug) /* Clear PL1 CLAMP bit */ - Store (Zero, PL1C) + PL1C = 0 /* Set PL1 to normal value */ - Store (SPL1, PL1V) + PL1V = SPL1 /* Set TAR to 0 */ - Store (Zero, TARS) + TARS = 0 /* Set _PPC to 0 */ - Store (Zero, PPCM) + PPCM = 0 \PPCN () Release (CTCM) Return (1) } -} diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 4a9debf..7ab47ac 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include "../haswell.h" + #include "hostbridge.asl" #include "peg.asl" #include <southbridge/intel/common/rcba.h> @@ -30,6 +31,6 @@ // Current Resource Settings Method (_CRS, 0, Serialized) { - Return(PDRS) + Return (PDRS) } } diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index dd4b79a..5e694a6 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -1,18 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +Name (_HID, EISAID ("PNP0A08")) // PCIe +Name (_CID, EISAID ("PNP0A03")) // PCI -Name(_HID,EISAID("PNP0A08")) // PCIe -Name(_CID,EISAID("PNP0A03")) // PCI - -Name(_BBN, 0) +Name (_BBN, 0) Device (MCHC) { - Name(_ADR, 0x00000000) // 0:0.0 + Name (_ADR, 0x00000000) // 0:0.0 - OperationRegion(MCHP, PCI_Config, 0x00, 0x100) + OperationRegion (MCHP, PCI_Config, 0x00, 0x100) Field (MCHP, DWordAcc, NoLock, Preserve) { +#if CONFIG(NORTHBRIDGE_INTEL_HASWELL) Offset (0x40), // EPBAR EPEN, 1, // Enable , 11, // @@ -34,10 +34,12 @@ DMEN, 1, // Enable , 11, // DMBR, 24, // DMIBAR +#endif Offset (0x70), // ME Base Address MEBA, 64, +#if CONFIG(NORTHBRIDGE_INTEL_HASWELL) // ... Offset (0x80), // PAM0 @@ -74,6 +76,7 @@ , 2, PM6H, 2, , 2, +#endif Offset (0xa0), // Top of Used Memory TOM, 64, @@ -82,223 +85,9 @@ TLUD, 32, } - Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ - Name (CTCC, 0) /* CTDP Current Selection */ - Name (CTCN, 0) /* CTDP Nominal Select */ - Name (CTCD, 1) /* CTDP Down Select */ - Name (CTCU, 2) /* CTDP Up Select */ - Name (SPL1, 0) /* Saved PL1 value */ - - OperationRegion (MCHB, SystemMemory, Add(DEFAULT_MCHBAR,0x5000), 0x1000) - Field (MCHB, DWordAcc, Lock, Preserve) - { - Offset (0x930), /* PACKAGE_POWER_SKU */ - CTDN, 15, /* CTDP Nominal PL1 */ - Offset (0x938), /* PACKAGE_POWER_SKU_UNIT */ - PUNI, 4, /* Power Units */ - , 4, - EUNI, 5, /* Energy Units */ - , 3, - TUNI, 4, /* Time Units */ - Offset (0x958), /* PLATFORM_INFO */ - , 40, - LFM_, 8, /* Maximum Efficiency Ratio (LFM) */ - Offset (0x9a0), /* TURBO_POWER_LIMIT1 */ - PL1V, 15, /* Power Limit 1 Value */ - PL1E, 1, /* Power Limit 1 Enable */ - PL1C, 1, /* Power Limit 1 Clamp */ - PL1T, 7, /* Power Limit 1 Time */ - Offset (0x9a4), /* TURBO_POWER_LIMIT2 */ - PL2V, 15, /* Power Limit 2 Value */ - PL2E, 1, /* Power Limit 2 Enable */ - PL2C, 1, /* Power Limit 2 Clamp */ - PL2T, 7, /* Power Limit 2 Time */ - Offset (0xf3c), /* CONFIG_TDP_NOMINAL */ - TARN, 8, /* CTDP Nominal Turbo Activation Ratio */ - Offset (0xf40), /* CONFIG_TDP_LEVEL1 */ - CTDD, 15, /* CTDP Down PL1 */ - , 1, - TARD, 8, /* CTDP Down Turbo Activation Ratio */ - Offset (0xf48), /* MSR_CONFIG_TDP_LEVEL2 */ - CTDU, 15, /* CTDP Up PL1 */ - , 1, - TARU, 8, /* CTDP Up Turbo Activation Ratio */ - Offset (0xf50), /* CONFIG_TDP_CONTROL */ - CTCS, 2, /* CTDP Select */ - Offset (0xf54), /* TURBO_ACTIVATION_RATIO */ - TARS, 8, /* Turbo Activation Ratio Select */ - } - - /* - * Search CPU0 _PSS looking for control = arg0 and then - * return previous P-state entry number for new _PPC - * - * Format of _PSS: - * Name (_PSS, Package () { - * Package (6) { freq, power, tlat, blat, control, status } - * } - */ - External (\_SB.CP00._PSS) - Method (PSSS, 1, NotSerialized) - { - Local0 = One /* Start at P1 */ - Local1 = SizeOf (\_SB.CP00._PSS) - - While (Local0 < Local1) { - /* Store _PSS entry Control value to Local2 */ - Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8 - If (Local2 == Arg0) { - Return (Local0 - 1) - } - Local0++ - } - - Return (0) - } - - /* Calculate PL2 based on chip type */ - Method (CPL2, 1, NotSerialized) - { - If (\ISLP ()) { - /* Haswell ULT PL2 = 25W */ - Return (25 * 8) - } Else { - /* Haswell Mobile PL2 = 1.25 * PL1 */ - Return ((Arg0 * 125) / 100) - } - } - - /* Set Config TDP Down */ - Method (STND, 0, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - If (LEqual (CTCD, CTCC)) { - Release (CTCM) - Return (0) - } - - Store ("Set TDP Down", Debug) - - /* Set CTC */ - CTCS = CTCD - - /* Set TAR */ - TARS = TARD - - /* Set PPC limit and notify OS */ - PPCM = PSSS (TARD) - PPCN () - - /* Set PL2 */ - PL2V = CPL2 (CTDD) - - /* Set PL1 */ - PL1V = CTDD - - /* Store the new TDP Down setting */ - CTCC = CTCD - - Release (CTCM) - Return (1) - } - - /* Set Config TDP Nominal from Down */ - Method (STDN, 0, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - If (CTCN == CTCC) { - Release (CTCM) - Return (0) - } - - Store ("Set TDP Nominal", Debug) - - /* Set PL1 */ - PL1V = CTDN - - /* Set PL2 */ - PL2V = CPL2 (CTDN) - - /* Set PPC limit and notify OS */ - PPCM = PSSS (TARN) - PPCN () - - /* Set TAR */ - TARS = TARN - - /* Set CTC */ - CTCS = CTCN - - /* Store the new TDP Nominal setting */ - CTCC = CTCN - - Release (CTCM) - Return (1) - } - - /* Calculate PL1 value based on requested TDP */ - Method (TDPP, 1, NotSerialized) - { - Return (((PUNI - 1) << 2) * Arg0) - } - - /* Enable Controllable TDP to limit PL1 to requested value */ - Method (CTLE, 1, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - - Store ("Enable PL1 Limit", Debug) - - /* Set _PPC to LFM */ - Local0 = PSSS (LFM_) - PPCM = Local0 + 1 - \PPCN () - - /* Set TAR to LFM-1 */ - TARS = LFM_ - 1 - - /* Set PL1 to desired value */ - SPL1 = PL1V - PL1V = TDPP (Arg0) - - /* Set PL1 CLAMP bit */ - PL1C = 1 - - Release (CTCM) - Return (1) - } - - /* Disable Controllable TDP */ - Method (CTLD, 0, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - - Store ("Disable PL1 Limit", Debug) - - /* Clear PL1 CLAMP bit */ - PL1C = 0 - - /* Set PL1 to normal value */ - PL1V = SPL1 - - /* Set TAR to 0 */ - TARS = 0 - - /* Set _PPC to 0 */ - PPCM = 0 - \PPCN () - - Release (CTCM) - Return (1) - } +#if CONFIG(NORTHBRIDGE_INTEL_HASWELL) + #include "ctdp.asl" +#endif } // Current Resource Settings @@ -440,7 +229,7 @@ PMIN = Local0 PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1 - PLEN = PMAX - PMIN + 1 + PLEN = (PMAX - PMIN) + 1 Return (MCRS) } diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 41f18be..391d837 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -2,7 +2,13 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> -#include "haswell.h" + +#if CONFIG(NORTHBRIDGE_INTEL_HASWELL) +#include <northbridge/intel/haswell/haswell.h> + +#elif CONFIG(NORTHBRIDGE_INTEL_BROADWELL) +#include <northbridge/intel/broadwell/broadwell.h> +#endif void bootblock_early_northbridge_init(void) { diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 68072ff..42379d6 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -4,18 +4,18 @@ #include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> -#include <console/console.h> #include <bootmode.h> +#include <console/console.h> #include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <drivers/intel/gma/i915_reg.h> -#include <drivers/intel/gma/i915.h> -#include <drivers/intel/gma/libgfxinit.h> -#include <cpu/intel/haswell/haswell.h> -#include <drivers/intel/gma/opregion.h> #include <string.h> +#include <drivers/intel/gma/i915.h> +#include <drivers/intel/gma/i915_reg.h> +#include <drivers/intel/gma/libgfxinit.h> +#include <drivers/intel/gma/opregion.h> +#include <cpu/intel/haswell/haswell.h> #include <types.h> #include "chip.h" @@ -507,8 +507,8 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init, - .acpi_fill_ssdt = gma_generate_ssdt, .ops_pci = &pci_dev_ops_pci, + .acpi_fill_ssdt = gma_generate_ssdt, }; static const unsigned short pci_device_ids[] = { @@ -527,7 +527,7 @@ 0, }; -static const struct pci_driver pch_lpc __pci_driver = { +static const struct pci_driver gma_driver __pci_driver = { .ops = &gma_func0_ops, .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index bd44168..db4d4d1 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -12,9 +12,14 @@ #define IED_SIZE CONFIG_IED_REGION_SIZE /* Northbridge BARs */ -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ +#define DEFAULT_MCHBAR 0xfed10000 /* 32 KB */ +#define MCH_BASE_SIZE 0x8000 + #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DMI_BASE_SIZE 0x1000 + #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ +#define EP_BASE_SIZE 0x1000 #define GFXVT_BASE_ADDRESS 0xfed90000ULL #define GFXVT_BASE_SIZE 0x1000 @@ -22,6 +27,10 @@ #define VTVC0_BASE_ADDRESS 0xfed91000ULL #define VTVC0_BASE_SIZE 0x1000 +#define EDRAM_BASE_SIZE 0x4000 + +#define GDXC_BASE_SIZE 0x1000 + #include <southbridge/intel/lynxpoint/pch.h> /* Everything below this line is ignored in the DSDT */ diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index de2ce06..00151db 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -6,11 +6,21 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/mmio.h> + +#if CONFIG(NORTHBRIDGE_INTEL_HASWELL) #include <southbridge/intel/lynxpoint/hda_verb.h> +#define HDA_VENDEV_ID 0x80862807 + +#elif CONFIG(NORTHBRIDGE_INTEL_BROADWELL) +#include <soc/intel/common/hda_verb.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <northbridge/intel/broadwell/igd.h> +#define HDA_VENDEV_ID 0x80862808 +#endif static const u32 minihd_verb_table[] = { /* coreboot specific header */ - 0x80862807, /* Codec Vendor / Device ID: Intel Haswell Mini-HD */ + HDA_VENDEV_ID, /* Codec Vendor / Device ID: Intel Haswell/Broadwell Mini-HD */ 0x80860101, /* Subsystem ID */ 4, /* Number of jacks */ @@ -82,6 +92,12 @@ minihd_verb_table); } } + +#if CONFIG(NORTHBRIDGE_INTEL_BROADWELL) + /* Set EM4/EM5 registers */ + write32(base + 0x0100c, igd_get_reg_em4()); + write32(base + 0x01010, igd_get_reg_em5()); +#endif } static struct device_operations minihd_ops = { @@ -92,6 +108,7 @@ .ops_pci = &pci_dev_ops_pci, }; +#if CONFIG(NORTHBRIDGE_INTEL_HASWELL) static const unsigned short pci_device_ids[] = { 0x0a0c, 0x0c0c, 0 }; static const struct pci_driver haswell_minihd __pci_driver = { @@ -99,3 +116,18 @@ .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; + +#elif CONFIG(NORTHBRIDGE_INTEL_BROADWELL) +static const unsigned short pci_device_ids[] = { + 0x0a0c, /* Haswell */ + 0x160c, /* Broadwell */ + 0 +}; + +static const struct pci_driver minihd_driver __pci_driver = { + .ops = &minihd_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; +#endif + diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index ef7742e..cb9fe50 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -16,41 +16,6 @@ #include "chip.h" #include "haswell.h" -static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) -{ - u32 pciexbar_reg, mask; - - *base = 0; - *len = 0; - - pciexbar_reg = pci_read_config32(dev, index); - - if (!(pciexbar_reg & (1 << 0))) - return 0; - - switch ((pciexbar_reg >> 1) & 3) { - case 0: /* 256MB */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); - *base = pciexbar_reg & mask; - *len = 256 * 1024 * 1024; - return 1; - case 1: /* 128M */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); - mask |= (1 << 27); - *base = pciexbar_reg & mask; - *len = 128 * 1024 * 1024; - return 1; - case 2: /* 64M */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); - mask |= (1 << 27) | (1 << 26); - *base = pciexbar_reg & mask; - *len = 64 * 1024 * 1024; - return 1; - } - - return 0; -} - static const char *northbridge_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -79,196 +44,8 @@ .write_acpi_tables = northbridge_write_acpi_tables, }; -static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) -{ - u32 bar = pci_read_config32(dev, index); - - /* If not enabled don't report it */ - if (!(bar & 0x1)) - return 0; - - /* Knock down the enable bit */ - *base = bar & ~1; - - return 1; -} - -/* - * There are special BARs that actually are programmed in the MCHBAR. These Intel special - * features, but they do consume resources that need to be accounted for. - */ -static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) -{ - u32 bar = MCHBAR32(index); - - /* If not enabled don't report it */ - if (!(bar & 0x1)) - return 0; - - /* Knock down the enable bit */ - *base = bar & ~1; - - return 1; -} - -struct fixed_mmio_descriptor { - unsigned int index; - u32 size; - int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); - const char *description; -}; - -#define SIZE_KB(x) ((x) * 1024) -struct fixed_mmio_descriptor mc_fixed_resources[] = { - { PCIEXBAR, SIZE_KB(0), get_pcie_bar, "PCIEXBAR" }, - { MCHBAR, SIZE_KB(32), get_bar, "MCHBAR" }, - { DMIBAR, SIZE_KB(4), get_bar, "DMIBAR" }, - { EPBAR, SIZE_KB(4), get_bar, "EPBAR" }, - { GDXCBAR, SIZE_KB(4), get_bar_in_mchbar, "GDXCBAR" }, - { EDRAMBAR, SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" }, -}; -#undef SIZE_KB - -/* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */ -static void mc_add_fixed_mmio_resources(struct device *dev) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) { - u32 base; - u32 size; - struct resource *resource; - unsigned int index; - - size = mc_fixed_resources[i].size; - index = mc_fixed_resources[i].index; - if (!mc_fixed_resources[i].get_resource(dev, index, &base, &size)) - continue; - - resource = new_resource(dev, mc_fixed_resources[i].index); - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | - IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; - - resource->base = base; - resource->size = size; - printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", - __func__, mc_fixed_resources[i].description, index, - (unsigned long)base, (unsigned long)(base + size - 1)); - } -} - -/* Host Memory Map: - * - * +--------------------------+ TOUUD - * | | - * +--------------------------+ 4GiB - * | PCI Address Space | - * +--------------------------+ TOLUD (also maps into MC address space) - * | iGD | - * +--------------------------+ BDSM - * | GTT | - * +--------------------------+ BGSM - * | TSEG | - * +--------------------------+ TSEGMB - * | Usage DRAM | - * +--------------------------+ 0 - * - * Some of the base registers above can be equal, making the size of the regions within 0. - * This is because the memory controller internally subtracts the base registers from each - * other to determine sizes of the regions. In other words, the memory map regions are always - * in a fixed order, no matter what sizes they have. - */ - -struct map_entry { - int reg; - int is_64_bit; - int is_limit; - const char *description; -}; - -static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) -{ - uint64_t value; - uint64_t mask; - - /* All registers have a 1MiB granularity */ - mask = ((1ULL << 20) - 1); - mask = ~mask; - - value = 0; - - if (entry->is_64_bit) { - value = pci_read_config32(dev, entry->reg + 4); - value <<= 32; - } - - value |= pci_read_config32(dev, entry->reg); - value &= mask; - - if (entry->is_limit) - value |= ~mask; - - *result = value; -} - -#define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ - { \ - .reg = reg_, \ - .is_64_bit = is_64_, \ - .is_limit = is_limit_, \ - .description = desc_, \ - } - -#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_) -#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_) -#define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_) - -enum { - TOM_REG, - TOUUD_REG, - MESEG_BASE_REG, - MESEG_LIMIT_REG, - REMAP_BASE_REG, - REMAP_LIMIT_REG, - TOLUD_REG, - BGSM_REG, - BDSM_REG, - TSEG_REG, - /* Must be last */ - NUM_MAP_ENTRIES, -}; - -static struct map_entry memory_map[NUM_MAP_ENTRIES] = { - [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), - [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), - [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), - [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), - [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), - [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), - [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), - [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), - [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), - [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"), -}; - -static void mc_read_map_entries(struct device *dev, uint64_t *values) -{ - int i; - for (i = 0; i < NUM_MAP_ENTRIES; i++) { - read_map_entry(dev, &memory_map[i], &values[i]); - } -} - -static void mc_report_map_entries(struct device *dev, uint64_t *values) -{ - int i; - for (i = 0; i < NUM_MAP_ENTRIES; i++) { - printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", - memory_map[i].description, values[i]); - } - /* One can validate the BDSM and BGSM against the GGC */ - printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); -} +/* FIXME: For verification purposes only */ +#include <northbridge/intel/haswell/northbridge_common.c> static void mc_add_dram_resources(struct device *dev, int *resource_cnt) { @@ -277,8 +54,8 @@ uint64_t mc_values[NUM_MAP_ENTRIES]; /* Read in the MAP registers and report their values */ - mc_read_map_entries(dev, &mc_values[0]); - mc_report_map_entries(dev, &mc_values[0]); + mc_read_map_entries(dev, mc_values); + mc_report_map_entries(dev, mc_values); /* * These are the host memory ranges that should be added: @@ -357,27 +134,6 @@ *resource_cnt = index; } -static void mc_read_resources(struct device *dev) -{ - int index = 0; - const bool vtd_capable = !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); - - /* Read standard PCI resources */ - pci_dev_read_resources(dev); - - /* Add all fixed MMIO resources */ - mc_add_fixed_mmio_resources(dev); - - /* Add VT-d MMIO resources, if capable */ - if (vtd_capable) { - mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB); - mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB); - } - - /* Calculate and add DRAM resources */ - mc_add_dram_resources(dev, &index); -} - /* * The Mini-HD audio device is disabled whenever the IGD is. This is because it provides * audio over the integrated graphics port(s), which requires the IGD to be functional. @@ -422,7 +178,7 @@ { u8 bios_reset_cpl, pair; - /* Enable Power Aware Interrupt Routing. */ + /* Enable Power Aware Interrupt Routing */ pair = MCHBAR8(INTRDIRCTL); pair &= ~0x7; /* Clear 2:0 */ pair |= 0x4; /* Fixed Priority */ @@ -439,7 +195,7 @@ MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); - /* Configure turbo power limits 1ms after reset complete bit. */ + /* Configure turbo power limits 1ms after reset complete bit */ mdelay(1); set_power_limits(28); diff --git a/src/northbridge/intel/haswell/northbridge_common.c b/src/northbridge/intel/haswell/northbridge_common.c new file mode 100644 index 0000000..21a49ab --- /dev/null +++ b/src/northbridge/intel/haswell/northbridge_common.c @@ -0,0 +1,248 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This file is being included from other C files! */ + +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) +{ + u32 pciexbar_reg; + + *base = 0; + *len = 0; + + pciexbar_reg = pci_read_config32(dev, index); + + if (!(pciexbar_reg & (1 << 0))) + return 0; + + switch ((pciexbar_reg >> 1) & 3) { + case 0: /* 256MB */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)); + *len = 256 * 1024 * 1024; + return 1; + case 1: /* 128M */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28) | + (1 << 27)); + *len = 128 * 1024 * 1024; + return 1; + case 2: /* 64M */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28) | + (1 << 27) | (1 << 26)); + *len = 64 * 1024 * 1024; + return 1; + } + + return 0; +} + +static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) +{ + u32 bar = pci_read_config32(dev, index); + + /* If not enabled don't report it */ + if (!(bar & 1)) + return 0; + + /* Knock down the enable bit */ + *base = bar & ~1; + + return 1; +} + +/* + * There are special BARs that actually are programmed in the MCHBAR. These Intel special + * features, but they do consume resources that need to be accounted for. + */ +static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) +{ + u32 bar = MCHBAR32(index); + + /* If not enabled don't report it */ + if (!(bar & 1)) + return 0; + + /* Knock down the enable bit */ + *base = bar & ~1; + + return 1; +} + +struct fixed_mmio_descriptor { + unsigned int index; + u32 size; + int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); + const char *description; +}; + +struct fixed_mmio_descriptor mc_fixed_resources[] = { + { PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" }, + { MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" }, + { DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" }, + { EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" }, + { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" }, + { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" }, +}; + +/* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */ +static void mc_add_fixed_mmio_resources(struct device *dev) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) { + u32 base; + u32 size; + struct resource *resource; + unsigned int index; + + size = mc_fixed_resources[i].size; + index = mc_fixed_resources[i].index; + if (!mc_fixed_resources[i].get_resource(dev, index, &base, &size)) + continue; + + resource = new_resource(dev, mc_fixed_resources[i].index); + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; + + resource->base = base; + resource->size = size; + printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", + __func__, mc_fixed_resources[i].description, index, + (unsigned long)base, (unsigned long)(base + size - 1)); + } +} + +/* + * Host Memory Map: + * + * +--------------------------+ TOUUD + * | | + * +--------------------------+ 4GiB + * | PCI Address Space | + * +--------------------------+ TOLUD (also maps into MC address space) + * | iGD | + * +--------------------------+ BDSM + * | GTT | + * +--------------------------+ BGSM + * | TSEG | + * +--------------------------+ TSEGMB + * | Usage DRAM | + * +--------------------------+ 0 + * + * Some of the base registers above can be equal, making the size of the regions within 0. + * This is because the memory controller internally subtracts the base registers from each + * other to determine sizes of the regions. In other words, the memory map regions are always + * in a fixed order, no matter what sizes they have. + */ + +struct map_entry { + int reg; + int is_64_bit; + int is_limit; + const char *description; +}; + +static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) +{ + uint64_t value; + uint64_t mask; + + /* All registers have a 1MiB granularity */ + mask = ((1ULL << 20) - 1); + mask = ~mask; + + value = 0; + + if (entry->is_64_bit) { + value = pci_read_config32(dev, entry->reg + 4); + value <<= 32; + } + + value |= pci_read_config32(dev, entry->reg); + value &= mask; + + if (entry->is_limit) + value |= ~mask; + + *result = value; +} + +#define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ + { \ + .reg = reg_, \ + .is_64_bit = is_64_, \ + .is_limit = is_limit_, \ + .description = desc_, \ + } + +#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_) +#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_) +#define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_) + +enum { + TOM_REG, + TOUUD_REG, + MESEG_BASE_REG, + MESEG_LIMIT_REG, + REMAP_BASE_REG, + REMAP_LIMIT_REG, + TOLUD_REG, + BGSM_REG, + BDSM_REG, + TSEG_REG, + /* Must be last */ + NUM_MAP_ENTRIES, +}; + +static struct map_entry memory_map[NUM_MAP_ENTRIES] = { + [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), + [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), + [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), + [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), + [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), + [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), + [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), + [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), + [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), + [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"), +}; + +static void mc_read_map_entries(struct device *dev, uint64_t *values) +{ + int i; + for (i = 0; i < NUM_MAP_ENTRIES; i++) { + read_map_entry(dev, &memory_map[i], &values[i]); + } +} + +static void mc_report_map_entries(struct device *dev, uint64_t *values) +{ + int i; + for (i = 0; i < NUM_MAP_ENTRIES; i++) { + printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", + memory_map[i].description, values[i]); + } + /* One can validate the BDSM and BGSM against the GGC */ + printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); +} + +static void mc_add_dram_resources(struct device *dev, int *resource_cnt); + +static void mc_read_resources(struct device *dev) +{ + int index = 0; + const bool vtd_capable = !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); + + /* Read standard PCI resources */ + pci_dev_read_resources(dev); + + /* Add all fixed MMIO resources */ + mc_add_fixed_mmio_resources(dev); + + /* Add VT-d MMIO resources, if capable */ + if (vtd_capable) { + mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB); + mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB); + } + + /* Calculate and add DRAM resources */ + mc_add_dram_resources(dev, &index); +} diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 8ea4175..d3c078f 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -22,7 +22,7 @@ if (cpuidr.eax < 0x80000004) { strcpy(cpu_string, "Platform info not available"); } else { - u32 *p = (u32*) cpu_string; + u32 *p = (u32 *)cpu_string; for (i = 2; i <= 4; i++) { cpuidr = cpuid(index + i); *p++ = cpuidr.eax; diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 0f59d70..1b6f0b2 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -9,23 +9,16 @@ */ static void enable_spi_prefetch(void) { - u8 reg8; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x1f, 0); - - reg8 = pci_read_config8(dev, 0xdc); + u8 reg8 = pci_read_config8(PCH_DEV_LPC, 0xdc); reg8 &= ~(3 << 2); reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(PCH_DEV_LPC, 0xdc, reg8); } static void map_rcba(void) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - - pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_DEV_LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1); } static void enable_port80_on_lpc(void) diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 291a554..cf2a5f7 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -189,6 +189,7 @@ /* PCI Configuration Space (D31:F0): LPC */ #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) +#define PCH_DEV_LPC PCH_LPC_DEV #define SERIRQ_CNTL 0x64 #define GEN_PMCON_1 0xa0 diff --git a/src/southbridge/intel/wildcatpoint/bootblock.c b/src/southbridge/intel/wildcatpoint/bootblock.c index 55bb1c3..1e27ed6 100644 --- a/src/southbridge/intel/wildcatpoint/bootblock.c +++ b/src/southbridge/intel/wildcatpoint/bootblock.c @@ -25,7 +25,7 @@ static void map_rcba(void) { - pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1); + pci_write_config32(PCH_DEV_LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1); } static void enable_port80_on_lpc(void) @@ -43,18 +43,18 @@ u8 ssfc; /* Observe SPI Descriptor Component Section 0 */ - SPIBAR32(SPIBAR_FDOC) = 0x1000; + SPIBAR32(FDOC) = 0x1000; /* Extract the Write/Erase SPI Frequency from descriptor */ - fdod = SPIBAR32(SPIBAR_FDOD); + fdod = SPIBAR32(FDOD); fdod >>= 24; fdod &= 7; /* Set Software Sequence frequency to match */ - ssfc = SPIBAR8(SPIBAR_SSFC + 2); + ssfc = SPIBAR8(SSFC + 2); ssfc &= ~7; ssfc |= fdod; - SPIBAR8(SPIBAR_SSFC + 2) = ssfc; + SPIBAR8(SSFC + 2) = ssfc; } const struct reg_script pch_early_init_script[] = { diff --git a/src/southbridge/intel/wildcatpoint/iomap.h b/src/southbridge/intel/wildcatpoint/iomap.h index 241569e..37e62bb 100644 --- a/src/southbridge/intel/wildcatpoint/iomap.h +++ b/src/southbridge/intel/wildcatpoint/iomap.h @@ -9,6 +9,9 @@ #define MCH_BASE_ADDRESS 0xfed10000 #define MCH_BASE_SIZE 0x8000 +/* Haswell uses this name */ +#define DEFAULT_MCHBAR MCH_BASE_ADDRESS + #define DMI_BASE_ADDRESS 0xfed18000 #define DMI_BASE_SIZE 0x1000 @@ -24,6 +27,9 @@ #define RCBA_BASE_ADDRESS 0xfed1c000 #define RCBA_BASE_SIZE 0x4000 +/* Lynxpoint uses this name */ +#define DEFAULT_RCBA RCBA_BASE_ADDRESS + #define HPET_BASE_ADDRESS 0xfed00000 #define GFXVT_BASE_ADDRESS 0xfed90000ULL diff --git a/src/southbridge/intel/wildcatpoint/pch.c b/src/southbridge/intel/wildcatpoint/pch.c index efee415..f449c69 100644 --- a/src/southbridge/intel/wildcatpoint/pch.c +++ b/src/southbridge/intel/wildcatpoint/pch.c @@ -48,15 +48,15 @@ { u32 fdoc; - fdoc = SPIBAR32(SPIBAR_FDOC); + fdoc = SPIBAR32(FDOC); fdoc &= ~0x00007ffc; - SPIBAR32(SPIBAR_FDOC) = fdoc; + SPIBAR32(FDOC) = fdoc; fdoc |= 0x00004000; fdoc |= id * 4; - SPIBAR32(SPIBAR_FDOC) = fdoc; + SPIBAR32(FDOC) = fdoc; - return SPIBAR32(SPIBAR_FDOD); + return SPIBAR32(FDOD); } #ifndef __SIMPLE_DEVICE__ diff --git a/src/southbridge/intel/wildcatpoint/spi.h b/src/southbridge/intel/wildcatpoint/spi.h index 726b37e..8851f65 100644 --- a/src/southbridge/intel/wildcatpoint/spi.h +++ b/src/southbridge/intel/wildcatpoint/spi.h @@ -13,9 +13,9 @@ #define SPIBAR32(x) RCBA32(x + SPIBAR_OFFSET) /* Registers within the SPIBAR */ -#define SPIBAR_SSFC 0x91 -#define SPIBAR_FDOC 0xb0 -#define SPIBAR_FDOD 0xb4 +#define SSFC 0x91 +#define FDOC 0xb0 +#define FDOD 0xb4 #define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */ #define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72e8efc465ebe44ea9b1baaca2a317a29eb9506d Gerrit-Change-Number: 42626 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: tigerlake mainboards: switch to devtree aliases for PMC MUX connectors
by Tim Wawrzynczak (Code Review) 31 Oct '20

31 Oct '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45878 ) Change subject: tigerlake mainboards: switch to devtree aliases for PMC MUX connectors ...................................................................... tigerlake mainboards: switch to devtree aliases for PMC MUX connectors Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices can be hooked up together via devicetree aliases. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ib51764da5b3c029f9ac7ac60199a0aedfc7f29b1 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/todor/overridetree.cb M src/mainboard/google/volteer/variants/volteer/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 9 files changed, 67 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/45878/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index e32b2f9..102c2cc 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -47,7 +47,7 @@ register "HeciEnabled" = "1" # FSP configuration - register "SaGv" = "SaGv_Enabled" + register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "0" register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index fc549c7..1b603f0 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -56,6 +56,13 @@ device i2c 15 on end end end # I2C5 0xA0C6 + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device pci 1f.2 hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -66,14 +73,14 @@ register "usb3_port_number" = "1" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 42d3f2f..5fd136a 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -127,6 +127,13 @@ device i2c 15 on end end end # I2C5 0xA0C6 + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device pci 1f.2 hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -137,14 +144,14 @@ register "usb3_port_number" = "1" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "3" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb index 42d3f2f..5fd136a 100644 --- a/src/mainboard/google/volteer/variants/todor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb @@ -127,6 +127,13 @@ device i2c 15 on end end end # I2C5 0xA0C6 + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device pci 1f.2 hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -137,14 +144,14 @@ register "usb3_port_number" = "1" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "3" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 5079493..9615985 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -208,6 +208,13 @@ end end end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -217,14 +224,14 @@ register "usb2_port_number" = "9" register "usb3_port_number" = "1" # SBU & HSL follow CC - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on + device generic 1 alias conn1 on probe DB_USB USB4_GEN2 probe DB_USB USB3_ACTIVE probe DB_USB USB4_GEN3 @@ -235,7 +242,7 @@ register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU & HSL follow CC - device generic 1 on + device generic 1 alias conn1 on probe DB_USB USB3_PASSIVE end end diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 0bb82f1..bf382b7 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -7,6 +7,7 @@ device domain 0 on device pci 05.0 on end # IPU 0x9A19 + device pci 0d.2 on end # tbt_dma0 device pci 15.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -166,6 +167,13 @@ end end end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device pci 1f.2 hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -175,14 +183,14 @@ register "usb2_port_number" = "9" register "usb3_port_number" = "1" # SBU & HSL follow CC - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on + device generic 1 alias conn1 on probe DB_USB USB4_GEN2 probe DB_USB USB3_ACTIVE probe DB_USB USB4_GEN3 @@ -193,12 +201,12 @@ register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU & HSL follow CC - device generic 1 on + device generic 1 alias conn1 on probe DB_USB USB3_PASSIVE end end end end - end # PMC + end end end diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 43296d5..4ec4849 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -120,6 +120,13 @@ device i2c 15 on end end end # I2C5 0xA0C6 + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device pci 1f.2 hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -130,14 +137,14 @@ register "usb3_port_number" = "1" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 5965372..a7ed0bb 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -262,6 +262,8 @@ device pci 1e.3 off end # GSPI1 0xA0AB device pci 1f.0 on chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] device pnp 0c09.0 on end end end # eSPI 0xA080 - A09F @@ -276,14 +278,14 @@ register "usb3_port_number" = "3" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "7" register "usb3_port_number" = "4" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 90e7928..4b3859e 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -258,6 +258,8 @@ device pci 1e.3 off end # GSPI1 0xA0AB device pci 1f.0 on chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] device pnp 0c09.0 on end end end # eSPI 0xA080 - A09F @@ -272,14 +274,14 @@ register "usb3_port_number" = "3" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "5" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/45878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib51764da5b3c029f9ac7ac60199a0aedfc7f29b1 Gerrit-Change-Number: 45878 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020