coreboot-gerrit September 2020

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Change in coreboot[master]: soc/mediatek/mt8192: Add usb host support
by CK HU (Code Review) 12 Oct '20

12 Oct '20

CK HU has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45396 ) Change subject: soc/mediatek/mt8192: Add usb host support ...................................................................... soc/mediatek/mt8192: Add usb host support Add usb host function support Signed-off-by: Tianping Fang <tianping.fang(a)mediatek.com> Signed-off-by: Zhanyong Wang <zhanyong.wang(a)mediatek.com> Change-Id: Icb4cc304654b5fb7cf20b96ab83a22663bfeab63 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/include/soc/usb.h A src/soc/mediatek/mt8192/usb.c 3 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/45396/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc old mode 100644 new mode 100755 index c7dbe51..533eae2 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -32,6 +32,7 @@ ramstage-y += soc.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c +ramstage-y += ../common/usb.c usb.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8192/include/soc/usb.h b/src/soc/mediatek/mt8192/include/soc/usb.h new file mode 100755 index 0000000..3537ba2 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/usb.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef SOC_MEDIATEK_MT8192_USB_H +#define SOC_MEDIATEK_MT8192_USB_H + +#include <soc/usb_common.h> + +struct ssusb_sif_port { + struct sif_u2_phy_com u2phy; + u32 reserved0[64*5]; + struct sif_u3phyd u3phyd; + u32 reserved1[64]; + struct sif_u3phya u3phya; + struct sif_u3phya_da u3phya_da; + u32 reserved2[64 * 3]; +}; +check_member(ssusb_sif_port, u3phyd, 0x600); +check_member(ssusb_sif_port, u3phya, 0x800); +check_member(ssusb_sif_port, u3phya_da, 0x900); +check_member(ssusb_sif_port, reserved2, 0xa00); + +#define USB_PORT_NUMBER 2 + +#endif diff --git a/src/soc/mediatek/mt8192/usb.c b/src/soc/mediatek/mt8192/usb.c new file mode 100755 index 0000000..4beab9c --- /dev/null +++ b/src/soc/mediatek/mt8192/usb.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <soc/addressmap.h> +#include <device/mmio.h> +#include <soc/usb.h> + +#define REG_SPM_POWERON_CONFIG_EN (void *)(SPM_BASE + 0x000) +#define REG_SPM_SSPM_PWR_CON (void *)(SPM_BASE + 0x390) + +void mtk_usb_prepare(void) +{ + /* power on SSUSB SRAM FIFO */ + setbits32(REG_SPM_POWERON_CONFIG_EN, 0xB160001); + clrbits32(REG_SPM_SSPM_PWR_CON, 0x000001FF); +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/45396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb4cc304654b5fb7cf20b96ab83a22663bfeab63 Gerrit-Change-Number: 45396 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

8 25

Change in coreboot[master]: soc/intel/jasperlake: Allow mainboard to override chip configuration
by Karthik Ramasubramanian (Code Review) 12 Oct '20

12 Oct '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45856 ) Change subject: soc/intel/jasperlake: Allow mainboard to override chip configuration ...................................................................... soc/intel/jasperlake: Allow mainboard to override chip configuration Add a weak override function to allow mainboard to override chip configuration like GPIO PM. BUG=None TEST=Build and boot waddledee to OS. Ensure that the suspend/resume sequence works fine. Change-Id: I40fa655b0324dc444182b988f0089587e3877a47 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/jasperlake/include/soc/ramstage.h 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/45856/1 diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index cdd088e..d140213 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -78,6 +78,11 @@ sizeof(config->SerialIoUartMode)); } +__weak void mainboard_update_soc_chip_config(struct soc_intel_jasperlake_config *config) +{ + /* Override settings per board. */ +} + /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { @@ -86,6 +91,9 @@ FSP_S_CONFIG *params = &supd->FspsConfig; struct soc_intel_jasperlake_config *config = config_of_soc(); + /* Allow mainboard to override any chip config */ + mainboard_update_soc_chip_config(config); + /* Parse device tree and fill in FSP UPDs */ parse_devicetree(params); diff --git a/src/soc/intel/jasperlake/include/soc/ramstage.h b/src/soc/intel/jasperlake/include/soc/ramstage.h index 8188fbd..1de8e37 100644 --- a/src/soc/intel/jasperlake/include/soc/ramstage.h +++ b/src/soc/intel/jasperlake/include/soc/ramstage.h @@ -9,6 +9,7 @@ #include <soc/soc_chip.h> void mainboard_silicon_init_params(FSP_S_CONFIG *params); +void mainboard_update_soc_chip_config(struct soc_intel_jasperlake_config *config); void soc_init_pre_device(void *chip_info); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40fa655b0324dc444182b988f0089587e3877a47 Gerrit-Change-Number: 45856 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: security/intel/stm: Add options for STM build
by Eugene Myers (Code Review) 12 Oct '20

12 Oct '20

Hello Eugene Myers, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44686 to review the following change. Change subject: security/intel/stm: Add options for STM build ...................................................................... security/intel/stm: Add options for STM build This patch adds options that support building the STM as a part of the coreboot build. The option defaults are set so that the STM can be built for a majority of coreboot platforms. Change-Id: I80ed7cbcb93468c5ff93d089d77742ce7b671a37 Signed-off-by: Eugene D Myers <cedarhouse(a)comcast.net> --- M src/security/intel/stm/Kconfig 1 file changed, 77 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/44686/1 diff --git a/src/security/intel/stm/Kconfig b/src/security/intel/stm/Kconfig index f7dd363..4d963aa 100644 --- a/src/security/intel/stm/Kconfig +++ b/src/security/intel/stm/Kconfig @@ -1,3 +1,4 @@ + config STM bool "Enable STM" default n @@ -27,20 +28,93 @@ config MSEG_SIZE hex "mseg size" - default 0x400000 + default 0x100000 help - STM only - 0x100000 + The MSEG_SIZE of 0x100000 assumes that: + IED_REGION_SIZE = 0x400000 + SMM_RESERVED_SIZE = 0x200000 + SMM_TSEG_SIZE = 0x800000 + To use STM/PE, a larger MSEG_SIZE is necessary. This can be + done by either increasing SMM_TSEG_SIZE or reducing the + IED_REGION_SIZE and/or SMM_RESERVED_SIZE or some combination + of the three. + NOTE: The authors experience is that these configuration + parameters have to be changed at the soc Konfig for them to + be applied. + Minimum sizes: + STM only - 0x100000 - Supports up to 38 processor threads + - 0x200000 - Supports up to 102 processor threads STM/PE - 0x300000+ depending on the amount of memory needed for the protected execution virtual machine (VM/PE) +config STM_STMPE_ENABLED + bool "STM/PE Enabled" + default n + help + STM/PE provides for additional virtual machines in SMRAM + that provides a protected execution environment for + applications such as introspection, which need to be + protected from malicious code. More information can be + found on the stmpe branch of + ssh://review.coreboot.org/STM + + config BIOS_RESOURCE_LIST_SIZE hex "bios_resource_list_size" default 0x1000 + help + The BIOS resource list defines the resources that the + SMI Handler needs. This list is created during the + coreboot bootup. Unless there has been a lot of elements + added to this list, this value should not change. config STM_BINARY_FILE string "STM binary file" - default "3rdparty/blobs/cpu/intel/stm/stm.bin" + default "payloads/external/stm/STM/Stm/build/StmPkg/Core/stm.bin" + help + Location of the STM binary file. The default location is + where the file will be located when coreboot builds + the STM. + Old location is "3rdparty/blobs/cpu/intel/stm/stm.bin" + +config STM_HEAPSIZE + hex "stm_heapsize" + default 0x46000 + help + The STM_HEAPSIZE defines the heap space that is available + to the STM. The default size assumes a MSEG_SIZE of 0x100000. + For STM/PE this size should be a minimum of 0x246000. + +config STM_UART + hex "stm_uart" + default 0x3F8 + help + Defines the serial port for the STM to send its console + output to. + +config STM_CBMEM_CONSOLE + bool "STM cbmem console" + default n + depends on CONSOLE_CBMEM + help + Places the STM console output into the cbmem. + + +config STM_BUILD + string "stm_build" + default "debug" + help + The default (debug) build will generate runtime console output. + "release" will deactivate the console output. + +config STM_GIT_REPO + string "stm_git_repo" + default "https://review.coreboot.org/STM" + +config STM_GIT_BRANCH + string "stm_git_branch" + default "stmpe" endmenu #STM -- To view, visit https://review.coreboot.org/c/coreboot/+/44686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80ed7cbcb93468c5ff93d089d77742ce7b671a37 Gerrit-Change-Number: 44686 Gerrit-PatchSet: 1 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Eugene Myers <cedarhouse(a)comcast.net> Gerrit-MessageType: newchange

5 19

Change in coreboot[master]: mb/intel/tglrvp: Enable early EC sync
by Anil Kumar K (Code Review) 12 Oct '20

12 Oct '20

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44689 ) Change subject: mb/intel/tglrvp: Enable early EC sync ...................................................................... mb/intel/tglrvp: Enable early EC sync - This change is required to execute EC sync in coreboot instead of depthcharge Bug=none Test=build and boot coreboot on TGLRVP Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I40ae104d4de93c12097e049253a33b23a46c6203 --- M src/mainboard/intel/tglrvp/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/44689/1 diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 3e55f56..eeeecc1 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -28,6 +28,7 @@ select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB + select VBOOT_EARLY_EC_SYNC config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/44689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40ae104d4de93c12097e049253a33b23a46c6203 Gerrit-Change-Number: 44689 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: mb/intel/tglrvp: Enable TPM
by Anil Kumar K (Code Review) 12 Oct '20

12 Oct '20

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44698 ) Change subject: mb/intel/tglrvp: Enable TPM ...................................................................... mb/intel/tglrvp: Enable TPM Bug=none Test=emerge build successful on tglrvpwq Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I4a3aec98f72524e8e2a1834878ef75b9f933ae3e --- M src/drivers/spi/tpm/tpm.c M src/mainboard/intel/tglrvp/Kconfig 2 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/44698/1 diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 4263dce..bc9f06e 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -157,6 +157,8 @@ for (i = 0; i < 3; i++) header.body[i + 1] = (addr >> (8 * (2 - i))) & 0xff; + udelay(100); + /* CS assert wakes up the slave. */ spi_claim_bus(&spi_slave); diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index eeeecc1..e4c29f8 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -18,6 +18,9 @@ select DRIVERS_INTEL_ISH select EC_ACPI select PCIEXP_HOTPLUG + select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_SPI_TPM_CR50 + select SPI_TPM config CHROMEOS bool @@ -100,9 +103,12 @@ config VBOOT select VBOOT_LID_SWITCH - select VBOOT_MOCK_SECDATA config UART_FOR_CONSOLE int default 2 + +config DRIVER_TPM_SPI_BUS + default 0x2 + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/44698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a3aec98f72524e8e2a1834878ef75b9f933ae3e Gerrit-Change-Number: 44698 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newchange

7 20

Change in coreboot[master]: util/intelp2m: Update output fotmat of generated gpio.h
by Maxim Polyakov (Code Review) 12 Oct '20

12 Oct '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45168 ) Change subject: util/intelp2m: Update output fotmat of generated gpio.h ...................................................................... util/intelp2m: Update output fotmat of generated gpio.h Update the format of the generated gpio.h file: For PAD_CFG*() macro: /* GPIO_39 - LPSS_UART0_TXD */ --> (i) /* DW0: 0x44000400, DW1: 0x00003100 */ --> (ii) /* DW0 : PAD_TRIG(OFF) - IGNORED */ --> (iii, iiii) PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), For fields: /* GPIO_39 - LPSS_UART0_TXD */ --> (i) /* DW0: 0x44000400, DW1: 0x00003100 */ --> (ii) /* PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), */ --> (iii) /* DW0 : PAD_TRIG(OFF) - IGNORED */ --> (iiii) _PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), TEST = ./intelp2m -n -file inteltool.log; ./intelp2m -fld cb -file inteltool.log; ./intelp2m -fld fsp -file inteltool.log; ./intelp2m -fld raw -file inteltool.log. Before and after the patch, gpio.h is no different. Change-Id: I760f4aadece786ea455fb7569f42e06fefce2b61 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/intelp2m/description.md M util/intelp2m/fields/cb/cb.go M util/intelp2m/parser/parser.go M util/intelp2m/platforms/common/macro.go 4 files changed, 84 insertions(+), 93 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/45168/1 diff --git a/util/intelp2m/description.md b/util/intelp2m/description.md index add9c2c..0380d1f 100644 --- a/util/intelp2m/description.md +++ b/util/intelp2m/description.md @@ -79,34 +79,13 @@ ``` ```c -/* GPP_A10 - CLKOUT_LPC1 DW0: 0x44000500, DW1: 0x00000000 */ +/* GPP_A10 - CLKOUT_LPC1 */ +/* DW0: 0x44000500, DW1: 0x00000000 */ /* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */ /* DW0 : 0x04000100 - IGNORED */ _PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000000), ``` -### FSP-style macro - -The utility allows to generate macros that include fsp/edk2-palforms style bitfields: - -```bash -(shell)$ ./intelp2m -fld fsp -p lbg -file ../crb-inteltool.log -``` - -```c -{ GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInvOut, GpioOutLow, GpioIntSci | GpioIntLvlEdgDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock }, /* GPIO */ -``` - -```bash -(shell)$ ./intelp2m -iiii -fld fsp -p lbg -file ../crb-inteltool.log -``` - -```c -/* GPP_A12 - GPIO DW0: 0x80880102, DW1: 0x00000000 */ -/* PAD_CFG_GPI_SCI(GPP_A12, NONE, PLTRST, LEVEL, INVERT), */ -{ GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInvOut, GpioOutLow, GpioIntSci | GpioIntLvlEdgDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock }, -``` - ### Macro Check After generating the macro, the utility checks all used @@ -129,17 +108,9 @@ ### Information level The utility can generate additional information about the bit -fields of the DW0 and DW1 configuration registers: - -```c -/* GPIO_39 - LPSS_UART0_TXD (DW0: 0x44000400, DW1: 0x00003100) */ --> (2) -/* PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), */ --> (3) -/* DW0 : PAD_TRIG(OFF) - IGNORED */ --> (4) -_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), -``` - -Using the options -i, -ii, -iii, -iiii you can set the info level -from (1) to (4): +fields of the DW0 and DW1 configuration registers. Using the +options -i, -ii, -iii, -iiii you can set the info level from +1 to 4: ```bash (shell)$./intelp2m -i -file /path/to/inteltool.log @@ -147,33 +118,13 @@ (shell)$./intelp2m -iii -file /path/to/inteltool.log (shell)$./intelp2m -iiii -file /path/to/inteltool.log ``` -(1) : print /* GPIO_39 - LPSS_UART0_TXD */ - -(2) : print initial raw values of configuration registers from -inteltool dump -DW0: 0x44000400, DW1: 0x00003100 - -(3) : print the target macro that will generate if you use the --n option -PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), - -(4) : print decoded fields from (3) as macros -DW0 : PAD_TRIG(OFF) - IGNORED - -### Ignoring Fields - -Utilities can generate the _PAD_CFG_STRUCT macro and exclude fields -from it that are not in the corresponding PAD_CFG_*() macro: - -```bash -(shell)$ ./intelp2m -iiii -fld cb -ign -file /path/to/inteltool.log -``` ```c -/* GPIO_39 - LPSS_UART0_TXD DW0: 0x44000400, DW1: 0x00003100 */ -/* PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), */ -/* DW0 : PAD_TRIG(OFF) - IGNORED */ -_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), +/* GPIO_39 - LPSS_UART0_TXD */ --> (i) +/* DW0: 0x44000400, DW1: 0x00003100 */ --> (ii) +/* PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), */ --> (iii) +/* DW0 : PAD_TRIG(OFF) - IGNORED */ --> (iiii) +_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), ``` If you generate macros without checking, you can see bit fields that @@ -184,19 +135,51 @@ ``` ```c -/* GPIO_39 - LPSS_UART0_TXD DW0: 0x44000400, DW1: 0x00003100 */ +/* GPIO_39 - LPSS_UART0_TXD */ --> (i) +/* DW0: 0x44000400, DW1: 0x00003100 */ --> (ii) +/* DW0 : PAD_TRIG(OFF) - IGNORED */ --> (iii, iiii) PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), -/* DW0 : PAD_TRIG(OFF) - IGNORED */ ``` +### Ignoring Fields + +Utilities can generate the _PAD_CFG_STRUCT macro and exclude fields +from it that are not in the corresponding PAD_CFG_*() macro: ```bash -(shell)$ ./intelp2m -n -file /path/to/inteltool.log +(shell)$ ./intelp2m -iiii -fld cb -ign -file /path/to/inteltool.log ``` ```c /* GPIO_39 - LPSS_UART0_TXD */ -PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), +/* DW0: 0x44000400, DW1: 0x00003100 */ +/* PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), */ +/* DW0 : PAD_TRIG(OFF) - IGNORED */ +_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), ``` + +### FSP-style macro + +The utility allows to generate macros that include fsp/edk2-palforms style bitfields: + +```bash +(shell)$ ./intelp2m -fld fsp -p lbg -file ../crb-inteltool.log +``` + +```c +{ GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInvOut, GpioOutLow, GpioIntSci | GpioIntLvlEdgDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock }, /* GPIO */ +``` + +```bash +(shell)$ ./intelp2m -iiii -fld fsp -p lbg -file ../crb-inteltool.log +``` + +```c +/* GPP_A12 - GPIO */ +/* DW0: 0x80880102, DW1: 0x00000000 */ +/* PAD_CFG_GPI_SCI(GPP_A12, NONE, PLTRST, LEVEL, INVERT), */ +{ GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInvOut, GpioOutLow, GpioIntSci | GpioIntLvlEdgDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock }, +``` + ### Supports Chipsets Sunrise PCH, Lewisburg PCH, Apollo Lake SoC, CannonLake-LP SoCs diff --git a/util/intelp2m/fields/cb/cb.go b/util/intelp2m/fields/cb/cb.go index 61f59c4..0e254dd 100644 --- a/util/intelp2m/fields/cb/cb.go +++ b/util/intelp2m/fields/cb/cb.go @@ -50,7 +50,7 @@ generate( &field { prefix : "PAD_FUNC", - unhide : config.InfoLevelGet() <= 3 || dw0.GetPadMode() != 0, + unhide : config.InfoLevelGet() < 3 || dw0.GetPadMode() != 0, configurator : func() { macro.Padfn() }, }, diff --git a/util/intelp2m/parser/parser.go b/util/intelp2m/parser/parser.go index d4c04cd..c35d4e7 100644 --- a/util/intelp2m/parser/parser.go +++ b/util/intelp2m/parser/parser.go @@ -66,9 +66,9 @@ // macro : string of the generated macro func (info *padInfo) padInfoMacroFprint(macro string) { info.generate(2, "\n") - info.generate(1, "\t/* %s - %s ", info.id, info.function) - info.generate(2, "DW0: 0x%0.8x, DW1: 0x%0.8x ", info.dw0, info.dw1) - info.generate(1, "*/\n") + info.generate(1, "\t/* %s - %s */", info.id, info.function) + info.generate(2, "\n\t/* DW0: 0x%0.8x, DW1: 0x%0.8x */", info.dw0, info.dw1) + info.generate(1, "\n") info.generate(0, "\t%s", macro) if config.InfoLevelGet() == 0 { info.generate(0, "\t/* %s */", info.function) diff --git a/util/intelp2m/platforms/common/macro.go b/util/intelp2m/platforms/common/macro.go index e30ef22..51705bb 100644 --- a/util/intelp2m/platforms/common/macro.go +++ b/util/intelp2m/platforms/common/macro.go @@ -292,32 +292,33 @@ return macro } -// AddToMacroIgnoredMask - Print info about ignored field mask -// title - warning message -func (macro *Macro) AddToMacroIgnoredMask() *Macro { - if config.InfoLevelGet() < 4 || config.IsFspStyleMacro() { +// DecodeIgnored - Add info about ignored field mask +// reg : PAD_CFG_DW0 or PAD_CFG_DW1 register +func (macro *Macro) DecodeIgnored(reg uint8) *Macro { + var decode = map[uint8]func() { + PAD_CFG_DW0: macro.Fields.DecodeDW0, + PAD_CFG_DW1: macro.Fields.DecodeDW1, + } + decodefn, valid := decode[reg] + if !valid || config.IsFspStyleMacro() { return macro } - dw0 := macro.Register(PAD_CFG_DW0) - dw1 := macro.Register(PAD_CFG_DW1) - // Get mask of ignored bit fields. - dw0Ignored := dw0.IgnoredFieldsGet() - dw1Ignored := dw1.IgnoredFieldsGet() - if dw0Ignored != 0 { - dw0temp := dw0.ValueGet() - dw0.ValueSet(dw0Ignored) - macro.Add("\n\t/* DW0 : ") - macro.Fields.DecodeDW0() + dw := macro.Register(reg) + ignored := dw.IgnoredFieldsGet() + if ignored != 0 { + temp := dw.ValueGet() + dw.ValueSet(ignored) + if !config.IsNonCheckingFlagUsed() { + macro.Add("\n\t") + } + regnum := strconv.Itoa(int(reg)) + macro.Add("/* DW" + regnum + " : ") + decodefn() macro.Add(" - IGNORED */") - dw0.ValueSet(dw0temp) - } - if dw1Ignored != 0 { - dw1temp := dw1.ValueGet() - dw1.ValueSet(dw1Ignored) - macro.Add("\n\t/* DW1 : ") - macro.Fields.DecodeDW1() - macro.Add(" - IGNORED */") - dw1.ValueSet(dw1temp) + if config.IsNonCheckingFlagUsed() { + macro.Add("\n\t") + } + dw.ValueSet(temp) } return macro } @@ -338,7 +339,9 @@ reference := macro.Get() macro.Clear() macro.Add("/* ").Add(reference).Add(" */") - macro.AddToMacroIgnoredMask() + if config.InfoLevelGet() >= 4 { + macro.DecodeIgnored(PAD_CFG_DW0).DecodeIgnored(PAD_CFG_DW1) + } macro.Add("\n\t") } if config.AreFieldsIgnored() { @@ -409,8 +412,13 @@ } if config.IsNonCheckingFlagUsed() { - macro.AddToMacroIgnoredMask() - return macro.Get() + body := macro.Get() + if config.InfoLevelGet() >= 3 { + macro.Clear().DecodeIgnored(PAD_CFG_DW0).DecodeIgnored(PAD_CFG_DW1) + comment := macro.Get() + return comment + body + } + return body } return macro.check().Get() -- To view, visit https://review.coreboot.org/c/coreboot/+/45168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I760f4aadece786ea455fb7569f42e06fefce2b61 Gerrit-Change-Number: 45168 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: arch/x86/smbios: Update SMBIOS type 0 ec version
by Tim Chu (Code Review) 12 Oct '20

12 Oct '20

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45138 ) Change subject: arch/x86/smbios: Update SMBIOS type 0 ec version ...................................................................... arch/x86/smbios: Update SMBIOS type 0 ec version Get embedded controller firmware version and update to SMBIOS type 0. Here BMC version is used to represent ec version. TEST=Execute "dmidecode -t 0" to check if the ec version is correct Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: Ibd5ee27a1b8fa4e5bc66e359d3b62e052e19e8a2 --- M src/arch/x86/smbios.c M src/arch/x86/smbios_defaults.c M src/drivers/ipmi/ipmi_kcs_ops.c M src/include/smbios.h 4 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/45138/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 6c92d03..4a3a2e1 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -396,6 +396,7 @@ { struct smbios_type0 *t = (struct smbios_type0 *)*current; int len = sizeof(struct smbios_type0); + u8 ipmi_bmc_major_revision, ipmi_bmc_minor_revision; memset(t, 0, sizeof(struct smbios_type0)); t->type = SMBIOS_BIOS_INFORMATION; @@ -424,6 +425,10 @@ t->system_bios_major_release = coreboot_major_revision; t->system_bios_minor_release = coreboot_minor_revision; + smbios_ec_revision(&ipmi_bmc_major_revision, &ipmi_bmc_minor_revision); + t->ec_major_release = ipmi_bmc_major_revision; + t->ec_minor_release = ipmi_bmc_minor_revision; + t->bios_characteristics = BIOS_CHARACTERISTICS_PCI_SUPPORTED | BIOS_CHARACTERISTICS_SELECTABLE_BOOT | diff --git a/src/arch/x86/smbios_defaults.c b/src/arch/x86/smbios_defaults.c index 22ce7a5..9ff645c 100644 --- a/src/arch/x86/smbios_defaults.c +++ b/src/arch/x86/smbios_defaults.c @@ -63,6 +63,12 @@ return SMBIOS_BOARD_TYPE_UNKNOWN; } +__weak void smbios_ec_revision(uint8_t *ipmi_bmc_major_revision, uint8_t *ipmi_bmc_minor_revision) +{ + *ipmi_bmc_major_revision = 0x0; + *ipmi_bmc_minor_revision = 0x0; +} + /* * System Enclosure or Chassis Types as defined in SMBIOS specification. * The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) but laptop, diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 7fa28e3..aa07aa9 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -28,6 +28,9 @@ static u8 ipmi_revision_major = 0x1; static u8 ipmi_revision_minor = 0x0; +static u8 bmc_revision_major = 0x0; +static u8 bmc_revision_minor = 0x0; + static int ipmi_get_device_id(struct device *dev, struct ipmi_devid_rsp *rsp) { int ret; @@ -144,6 +147,9 @@ ipmi_revision_minor = IPMI_IPMI_VERSION_MINOR(rsp.ipmi_version); ipmi_revision_major = IPMI_IPMI_VERSION_MAJOR(rsp.ipmi_version); + bmc_revision_major = rsp.fw_rev1; + bmc_revision_minor = rsp.fw_rev2; + memcpy(&man_id, rsp.manufacturer_id, sizeof(rsp.manufacturer_id)); @@ -272,6 +278,12 @@ } #endif +void smbios_ec_revision(uint8_t *ipmi_bmc_major_revision, uint8_t *ipmi_bmc_minor_revision) +{ + *ipmi_bmc_major_revision = ((bmc_revision_major / 16) * 10) + (bmc_revision_major % 16); + *ipmi_bmc_minor_revision = ((bmc_revision_minor / 16) * 10) + (bmc_revision_minor % 16); +} + #if CONFIG(GENERATE_SMBIOS_TABLES) static int ipmi_smbios_data(struct device *dev, int *handle, unsigned long *current) diff --git a/src/include/smbios.h b/src/include/smbios.h index 521339e..fdc6b10 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -54,6 +54,9 @@ const char *smbios_chassis_serial_number(void); const char *smbios_processor_serial_number(void); +void smbios_ec_revision(uint8_t *ipmi_bmc_major_revision, + uint8_t *ipmi_bmc_minor_revision); + unsigned int smbios_processor_external_clock(void); unsigned int smbios_processor_characteristics(void); struct cpuid_result; -- To view, visit https://review.coreboot.org/c/coreboot/+/45138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd5ee27a1b8fa4e5bc66e359d3b62e052e19e8a2 Gerrit-Change-Number: 45138 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

7 21

Change in coreboot[master]: arch/x86/smbios: Update SMBIOS type 4 socket designation
by Tim Chu (Code Review) 12 Oct '20

12 Oct '20

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45443 ) Change subject: arch/x86/smbios: Update SMBIOS type 4 socket designation ...................................................................... arch/x86/smbios: Update SMBIOS type 4 socket designation Add socket designation in type 4 smbios. TEST=Execute "dmidecode -t 4" to check if the socket designation is correct Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: Icfdc201bd5b5921816bdce6c009a9db48c997e2e --- M src/arch/x86/smbios.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/45443/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 7516305..0600bf4 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -552,6 +552,8 @@ struct smbios_type4 *t = (struct smbios_type4 *)*current; int len = sizeof(struct smbios_type4); uint16_t characteristics = 0; + uint8_t cnt = 0; + char buf[8]; /* Provide sane defaults even for CPU without CPUID */ res.eax = res.edx = 0; @@ -564,6 +566,10 @@ t->type = SMBIOS_PROCESSOR_INFORMATION; t->handle = handle; t->length = len - 2; + + snprintf(buf, sizeof(buf), "CPU%x", cnt++); + t->socket_designation = smbios_add_string(t->eos, buf); + t->processor_id[0] = res.eax; t->processor_id[1] = res.edx; t->processor_manufacturer = smbios_cpu_vendor(t->eos); -- To view, visit https://review.coreboot.org/c/coreboot/+/45443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfdc201bd5b5921816bdce6c009a9db48c997e2e Gerrit-Change-Number: 45443 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: mb/google/dedede: update devicetree for Boten
by Alec Wang (Code Review) 12 Oct '20

12 Oct '20

Alec Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45732 ) Change subject: mb/google/dedede: update devicetree for Boten ...................................................................... mb/google/dedede: update devicetree for Boten Add trackpad, touchscreen, and usb port to devicetree BUG=b:160664447 BRANCH=NONE TEST=build bios and verify theirs function for boten Signed-off-by: alec.wang <alec.wang(a)lcfc.corp-partner.google.com> Change-Id: I057f7d15d20d1a78acd733cc5463357e9c87afb2 --- M src/mainboard/google/dedede/variants/boten/overridetree.cb 1 file changed, 75 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/45732/1 diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 61dff93..33911d3 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -35,7 +35,82 @@ .speed = I2C_SPEED_FAST, }, }" + + # USB Port Configuration + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Not Used + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # UF Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WF Camera + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""UFCamera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""WFCamera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.1 on end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # I2C 0 + device pci 15.1 off end # I2C 1 + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + end # I2C 2 + device pci 15.3 off end # I2C 3 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/45732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I057f7d15d20d1a78acd733cc5463357e9c87afb2 Gerrit-Change-Number: 45732 Gerrit-PatchSet: 1 Gerrit-Owner: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

4 26

Change in ...coreboot[master]: payloads/iPXE: Enable support for verifying images
by Felix Singer (Code Review) 12 Oct '20

12 Oct '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31087 Change subject: payloads/iPXE: Enable support for verifying images ...................................................................... payloads/iPXE: Enable support for verifying images Change-Id: Ic3356062758dba80f74116ff3ab82b3b9e8375b1 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M payloads/external/iPXE/Makefile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/31087/1 diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index a8b1245..a5bf7be 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -54,6 +54,7 @@ sed 's|#define\s*COMCONSOLE.*|#define COMCONSOLE $(IPXE_UART)|' "$(project_dir)/src/config/serial.h" > "$(project_dir)/src/config/serial.h.tmp" sed 's|#define\s*COMSPEED.*|#define COMSPEED $(CONFIG_TTYS0_BAUD)|' "$(project_dir)/src/config/serial.h.tmp" > "$(project_dir)/src/config/serial.h" endif + sed -ie 's|.*IMAGE_TRUST_CMD|#define IMAGE_TRUST_CMD|g' "$(project_dir)/src/config/general.h" build: config echo " MAKE $(project_name) $(TAG-y)" -- To view, visit https://review.coreboot.org/c/coreboot/+/31087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3356062758dba80f74116ff3ab82b3b9e8375b1 Gerrit-Change-Number: 31087 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

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