coreboot-gerrit September 2020

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Change in coreboot[master]: drivers/intel/gma/acpi: Convert 'configure_brightness_levels.asl' to ...
by HAOUAS Elyes (Code Review) 10 Oct '20

10 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45782 ) Change subject: drivers/intel/gma/acpi: Convert 'configure_brightness_levels.asl' to ASL+ syntax ...................................................................... drivers/intel/gma/acpi: Convert 'configure_brightness_levels.asl' to ASL+ syntax Generated build/dsdt.dsl are same. Change-Id: I8789ee129d1c42a36f30344655286b3c55f4f2c7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/intel/gma/acpi/configure_brightness_levels.asl 1 file changed, 27 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/45782/1 diff --git a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl index 0ab93d8..9db6bfb 100644 --- a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl +++ b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl @@ -42,48 +42,48 @@ */ Method (XBCM, 1, Serialized) { - If (LEqual(ASLS, Zero)) + If (ASLS == 0) { Return (Ones) } - If (LEqual(And(MBOX, 0x4), Zero)) + If ((MBOX & 0x4) == 0) { Return (Ones) } /* Always keep BCLP up to date, even if driver is not ready. It requires a full 8-bit brightness value. 255 = 100% */ - Store (Divide (Multiply (Arg0, 255), 100), Local1) - If (LGreater(Local1, 255)) { - Store (255, Local1) + Local1 = (Arg0 * 255) / 100 + If (Local1 > 255) { + Local1 = 255 } /* also set valid bit */ - Store (Or (Local1, 0x80000000), BCLP) + BCLP = Local1 | 0x80000000 - If (LEqual(ARDY, Zero)) + If (ARDY == 0) { Return (Ones) } /* Request back-light change */ - Store (0x2, ASLC) + ASLC = 0x2 /* Trigger IRQ */ - Store (0x1, ASLE) + ASLE = 0x1 - Store (0x20, Local0) - While (LGreater(Local0, Zero)) + Local0 = 0x20 + While (Local0 > 0) { Sleep (1) - If (LEqual (And (ASLC, 0x2), 0)) { + If ((ASLC & 0x2) == 0) { /* Request has been processed, check status: */ - And (ShiftRight (ASLC, 12), 0x3, Local1) - If (LEqual (Local1, 0)) { + Local1 = (ASLC >> 12) & 0x3 + If (Local1 == 0) { Return (Zero) } Else { Return (Ones) } } - Decrement (Local0) + Local0-- } Return (Ones) @@ -100,12 +100,12 @@ /* Divide round closest */ Method (DRCL, 2) { - Return (Divide (Add (Arg0, Divide (Arg1, 2)), Arg1)) + Return ((Arg0 + (Arg1 / 0x02)) / Arg1) } Method (XBCM, 1, NotSerialized) { - Store (DRCL (Multiply (Arg0, BCLM), 100), BCLV) + BCLV = DRCL ((Arg0 * BCLM), 100) } /* Find value closest to BCLV in BRIG (which must be ordered) */ @@ -117,26 +117,24 @@ Return (Zero) } /* Local0: current percentage */ - Store (DRCL (Multiply (BCLV, 100), BCLM), Local0) + Local0 = DRCL ((BCLV * 0x64), BCLM) /* Local1: loop index (selectable values start at 2 in BRIG) */ - Store (2, Local1) - While (LLess (Local1, Subtract (SizeOf (BRIG), 1))) { + Local1 = 2 + While (Local1 < (SizeOf (BRIG) -1)) { /* Local[23]: adjacent values in BRIG */ - Store (DeRefOf (Index (BRIG, Local1)), Local2) - Store (DeRefOf (Index (BRIG, Add (Local1, 1))), Local3) - - If (LLess (Local0, Local3)) { - If (LOr (LLess (Local0, Local2), - LLess (Subtract (Local0, Local2), - Subtract (Local3, Local0)))) { + Local2 = DerefOf (BRIG [Local1]) + Local3 = DerefOf (BRIG [(Local1 + 1)]) + If (Local0 < Local3) { + If ((Local0 < Local2) || + ((Local0 - Local2) < (Local3 - Local0))) { Return (Local2) } Else { Return (Local3) } } - Increment (Local1) + Local1++ } /* Didn't find greater/equal value: use the last */ @@ -146,7 +144,7 @@ Method (XBCM, 1, NotSerialized) { - If (LEqual(^BOX3.XBCM (Arg0), Ones)) + If (^BOX3.XBCM (Arg0) == Ones) { ^LEGA.XBCM (Arg0) } -- To view, visit https://review.coreboot.org/c/coreboot/+/45782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8789ee129d1c42a36f30344655286b3c55f4f2c7 Gerrit-Change-Number: 45782 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: soc/mediatek: Add function to get clock frequency of MT8192
by CK HU (Code Review) 10 Oct '20

10 Oct '20

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45402 to review the following change. Change subject: soc/mediatek: Add function to get clock frequency of MT8192 ...................................................................... soc/mediatek: Add function to get clock frequency of MT8192 Implement mt_fmeter_get_freq() in MT8192 to get frequency of some pre-defined clocks in the frequency meter. Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> Change-Id: I75df0b040ed7ea73d25724a3c80040f4e731118f --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/include/soc/pll.h M src/soc/mediatek/mt8192/pll.c 3 files changed, 80 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/45402/1 diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index 0f8732f..1787c4b 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -60,4 +60,10 @@ void mt_pll_init(void); void mt_pll_raise_little_cpu_freq(u32 freq); +enum fmeter_type { + FMETER_ABIST = 0, + FMETER_CKGEN +}; +unsigned int mt_fmeter_get_freq(enum fmeter_type type, unsigned int id); + #endif diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index 177bd33..f4a7180 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -299,4 +299,10 @@ DEFINE_BITFIELD(PLLGP1_LVRREF, 18, 17) DEFINE_BITFIELD(PLLGP2_LVRREF, 10, 9) +DEFINE_BITFIELD(CLK_DBG_CFG_ABIST_CK_SEL, 21, 16) +DEFINE_BITFIELD(CLK_DBG_CFG_CKGEN_CK_SEL, 13, 8) +DEFINE_BITFIELD(CLK_DBG_CFG_METER_CK_SEL, 1, 0) +DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24) +DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16) + #endif /* SOC_MEDIATEK_MT8192_PLL_H */ diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index e8849df..94dc469 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -459,3 +459,71 @@ /* disable [4] intermediate clock armpll_divider_pll1_ck */ clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); } + +unsigned int mt_fmeter_get_freq(enum fmeter_type type, unsigned int id) +{ + unsigned int output = 0, i = 0, count, clk_dbg_cfg, clk_misc_cfg_0; + bool timeout = false; + + /* backup */ + clk_dbg_cfg = read32(&mtk_topckgen->clk_dbg_cfg); + clk_misc_cfg_0 = read32(&mtk_topckgen->clk_misc_cfg_0); + + /* set up frequency meter */ + if (type == FMETER_ABIST) { + SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg, + CLK_DBG_CFG_ABIST_CK_SEL, id, + CLK_DBG_CFG_CKGEN_CK_SEL, 0, + CLK_DBG_CFG_METER_CK_SEL, 0); + SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, + CLK_MISC_CFG_0_METER_DIV, 1); + } else if (type == FMETER_CKGEN) { + SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg, + CLK_DBG_CFG_ABIST_CK_SEL, 0, + CLK_DBG_CFG_CKGEN_CK_SEL, id, + CLK_DBG_CFG_METER_CK_SEL, 1); + SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, + CLK_MISC_CFG_0_METER_DIV, 0); + } else + return 0; + + /* enable frequency meter */ + write32(&mtk_topckgen->clk26cali_0, 0x1000); + + /* set load count = 1024-1 */ + SET32_BITFIELDS(&mtk_topckgen->clk26cali_1, + CLK26CALI_1_LOAD_CNT, 0x3ff); + + /* trigger frequency meter */ + setbits32(&mtk_topckgen->clk26cali_0, 0x10); + + /* wait frequency meter until finished */ + while (read32(&mtk_topckgen->clk26cali_0) & 0x10) { + udelay(10); + i++; + if (i > 20) { + timeout = true; + break; + } + } + + count = read32(&mtk_topckgen->clk26cali_1) & 0xffff; + + output = (count * 26000) / 1024; /* KHz */ + + /* disable frequency meter */ + write32(&mtk_topckgen->clk26cali_0, 0x0000); + + /* restore */ + write32(&mtk_topckgen->clk_dbg_cfg, clk_dbg_cfg); + write32(&mtk_topckgen->clk_misc_cfg_0, clk_misc_cfg_0); + + if (!timeout) { + if (type == FMETER_ABIST) + return (output * 2); + else if (type == FMETER_CKGEN) + return output; + } + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75df0b040ed7ea73d25724a3c80040f4e731118f Gerrit-Change-Number: 45402 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

5 19

Change in coreboot[master]: mb/google/dedede: Override GPIO PM configuration
by Karthik Ramasubramanian (Code Review) 10 Oct '20

10 Oct '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45857 ) Change subject: mb/google/dedede: Override GPIO PM configuration ...................................................................... mb/google/dedede: Override GPIO PM configuration If Cr50 is running old firmware version and hence does not ensure long interrupt pulses, override the GPIO PM configuration. BUG=None TEST=Build and boot waddledee to OS. Ensure that the suspend/resume sequence works fine. Change-Id: I455c51d4a63b1b5edadbf00c786ce61b0ba1ff00 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 2 files changed, 20 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/45857/1 diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index cb84e1f..150076f 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -4,9 +4,29 @@ #include <bootstate.h> #include <baseboard/variants.h> #include <device/device.h> +#include <drivers/spi/tpm/tpm.h> #include <ec/ec.h> +#include <security/tpm/tss.h> +#include <soc/ramstage.h> #include <vendorcode/google/chromeos/chromeos.h> +void mainboard_update_soc_chip_config(struct soc_intel_jasperlake_config *cfg) +{ + int ret; + ret = tlcl_lib_init(); + if (ret != VB2_SUCCESS) { + printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret); + return; + } + + if (!cr50_is_long_interrupt_pulse_enabled()) { + /* Disable GPIO PM to allow for shorter IRQ pulses */ + printk(BIOS_INFO, "Override GPIO PM\n"); + cfg->gpio_override_pm = 1; + memset(cfg->gpio_pm, 0, sizeof(cfg->gpio_pm)); + } +} + __weak void variant_isst_override(void) { /* diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 1f72eb1..3ced742 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -129,14 +129,6 @@ # Select eDP for port A register "DdiPortAConfig" = "1" - # Disable PM to allow for shorter irq pulses - register "gpio_override_pm" = "1" - register "gpio_pm[0]" = "0" - register "gpio_pm[1]" = "0" - register "gpio_pm[2]" = "0" - register "gpio_pm[3]" = "0" - register "gpio_pm[4]" = "0" - # Enable HPD for DDI ports B/C register "DdiPortBHpd" = "1" register "DdiPortCHpd" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/45857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I455c51d4a63b1b5edadbf00c786ce61b0ba1ff00 Gerrit-Change-Number: 45857 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: mb/google/octopus: Disable Ambient Light Sensor (ALS)
by Karthik Ramasubramanian (Code Review) 10 Oct '20

10 Oct '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45741 ) Change subject: mb/google/octopus: Disable Ambient Light Sensor (ALS) ...................................................................... mb/google/octopus: Disable Ambient Light Sensor (ALS) ALS is not stuffed in octopus boards. Hence disable ALS ACPI devices. BUG=b:169245831 TEST=Ensure that ALS devices are disabled in ACPI tables. Change-Id: I5ad28f01b0515a41b314116eb2d05c520df0f86e Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/45741/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h index ecc9355..fa86170f 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h @@ -54,9 +54,6 @@ * ACPI related definitions for ASL code. */ -/* Enable EC backed ALS device in ACPI */ -#define EC_ENABLE_ALS_DEVICE - /* Enable LID switch and provide wake pin for EC */ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE -- To view, visit https://review.coreboot.org/c/coreboot/+/45741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ad28f01b0515a41b314116eb2d05c520df0f86e Gerrit-Change-Number: 45741 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: soc/intel/tigerlake: log the memory part name
by Nick Vaccaro (Code Review) 09 Oct '20

09 Oct '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45459 ) Change subject: soc/intel/tigerlake: log the memory part name ...................................................................... soc/intel/tigerlake: log the memory part name THe BIOS log was looking in the spd data for the part name, but part names are stripped from generic SPDs. In those cases, devices define their DRAM Part Name in the CBI, which can be retrieved by calling mainboard_get_dram_part_num(). Add a spd_set_name() call to the spd library to allow logging the memory part name in cases where the name does not exist in the actual SPD data, and call it in cases where the mainboard is overriding the part name. BUG=b:168724473 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer to kernel and verify that the BIOS log shows a part name when logging SPD information: SPD: module part number is K4U6E3S4AA-MGCL Change-Id: I91971e07c450492dbb0588abd1c3c692ee0d3bb0 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/include/spd_bin.h M src/lib/spd_bin.c M src/soc/intel/tigerlake/meminit.c 3 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/45459/1 diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index 11a0084..80c2e62 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -47,6 +47,7 @@ int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index); void dump_spd_info(struct spd_block *blk); void get_spd_smbus(struct spd_block *blk); +void spd_set_name(uint8_t spd[], char part_name[]); /* * get_spd_sn returns the SODIMM serial number. It only supports DDR3 and DDR4. diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 3888896..78c3e98 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -136,8 +136,23 @@ return spd_busw[index]; } +static char *spd_dram_part_name; +static bool spd_part_name_overridden = false; +void spd_set_name(uint8_t spd[], char *part_name) +{ + spd_dram_part_name = part_name; + spd_part_name_overridden = true; +} + static void spd_get_name(const uint8_t spd[], char spd_name[], int dram_type) { + /* If memory part name is overridden, use override copy */ + if (spd_part_name_overridden) { + memcpy(spd_name, spd_dram_part_name, + strlen(spd_dram_part_name)); + return; + } + switch (dram_type) { case SPD_DRAM_DDR3: memcpy(spd_name, &spd[DDR3_SPD_PART_OFF], DDR3_SPD_PART_LEN); diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 0c6f0b0..a027f2f 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <fsp/util.h> #include <soc/meminit.h> +#include <soc/romstage.h> #include <spd_bin.h> #include <string.h> @@ -216,6 +217,9 @@ static void read_md_spd(const struct spd_info *info, uintptr_t *data, size_t *len) { + const char *spd_name; + size_t spd_name_len; + if (info->md_spd_loc == SPD_MEMPTR) { *data = info->data_ptr; *len = info->data_len; @@ -225,6 +229,10 @@ die("Not a valid location(%d) for Memory-down SPD!\n", info->md_spd_loc); } + /* if mainboard overrides module name, use override name */ + if (mainboard_get_dram_part_num(&spd_name, &spd_name_len)) + spd_set_name((uint8_t *) *data, (char *) spd_name); + print_spd_info((uint8_t *) *data); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91971e07c450492dbb0588abd1c3c692ee0d3bb0 Gerrit-Change-Number: 45459 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

5 87

Change in coreboot[master]: src/lib/cbfs: Remove unused macro
by HAOUAS Elyes (Code Review) 09 Oct '20

09 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41781 ) Change subject: src/lib/cbfs: Remove unused macro ...................................................................... src/lib/cbfs: Remove unused macro Change-Id: I1efdb6355bec6f680e0fb1a4f4e19db93b3739a2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/lib/cbfs.c 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/41781/1 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index a3294de..92a6fed 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -17,11 +17,6 @@ #define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) #define LOG(x...) printk(BIOS_INFO, "CBFS: " x) -#if CONFIG(DEBUG_CBFS) -#define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x) -#else -#define DEBUG(x...) -#endif int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) { -- To view, visit https://review.coreboot.org/c/coreboot/+/41781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1efdb6355bec6f680e0fb1a4f4e19db93b3739a2 Gerrit-Change-Number: 41781 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: zork/var/ezkinil: Add micron-MT40A1G16KD-062E-E in SPD table for Ezki...
by Lucas Chen (Code Review) 09 Oct '20

09 Oct '20

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45810 ) Change subject: zork/var/ezkinil: Add micron-MT40A1G16KD-062E-E in SPD table for Ezkinil. ...................................................................... zork/var/ezkinil: Add micron-MT40A1G16KD-062E-E in SPD table for Ezkinil. Current Ram_Id: 0011 MT40A1G16KNR-075-E never be built before. Remove it and change use micron-MT40A1G16KD-062E-E for ram_id:0011. BRANCH=zork BUG=b:159316110 TEST=run gen_part_id then check the generated files. Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Change-Id: I28fc39f17e06ecd39f6567613e6ff5919becb2fd --- M src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc M src/mainboard/google/zork/variants/ezkinil/spd/dram_id.generated.txt M src/mainboard/google/zork/variants/ezkinil/spd/mem_parts_used.txt 3 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/45810/1 diff --git a/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc b/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc index 65eb7b0..12e7fa9 100644 --- a/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc @@ -3,7 +3,7 @@ SPD_SOURCES = SPD_SOURCES += ddr4-spd-3.hex # ID = 0(0b0000) Parts = H5AN8G6NCJR-VKC -SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001) +SPD_SOURCES += ddr4-spd-empty.bin # ID = 1(0b0001) SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = MT40A512M16TB-062E:J -SPD_SOURCES += ddr4-spd-4.hex # ID = 3(0b0011) Parts = MT40A1G16KNR-075:E +SPD_SOURCES += ddr4-spd-7.hex # ID = 3(0b0011) Parts = MT40A1G16KD-062E:E SPD_SOURCES += ddr4-spd-3.hex # ID = 4(0b0100) Parts = K4A8G165WC-BCTD diff --git a/src/mainboard/google/zork/variants/ezkinil/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/ezkinil/spd/dram_id.generated.txt index 99072f6..7e54cc1 100644 --- a/src/mainboard/google/zork/variants/ezkinil/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/ezkinil/spd/dram_id.generated.txt @@ -1,5 +1,5 @@ DRAM Part Name ID to assign H5AN8G6NCJR-VKC 0 (0000) MT40A512M16TB-062E:J 2 (0010) -MT40A1G16KNR-075:E 3 (0011) +MT40A1G16KD-062E:E 3 (0011) K4A8G165WC-BCTD 4 (0100) diff --git a/src/mainboard/google/zork/variants/ezkinil/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/ezkinil/spd/mem_parts_used.txt index a9994a3..b4b1601 100644 --- a/src/mainboard/google/zork/variants/ezkinil/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/ezkinil/spd/mem_parts_used.txt @@ -9,5 +9,5 @@ # Part Name, Fixed ID (optional) H5AN8G6NCJR-VKC,0 MT40A512M16TB-062E:J,2 -MT40A1G16KNR-075:E, 3 +MT40A1G16KD-062E:E,3 K4A8G165WC-BCTD,4 -- To view, visit https://review.coreboot.org/c/coreboot/+/45810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28fc39f17e06ecd39f6567613e6ff5919becb2fd Gerrit-Change-Number: 45810 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/ezkinil: Increase eMMC initial clock frequency
by Raul Rangel (Code Review) 09 Oct '20

09 Oct '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45852 ) Change subject: mb/google/zork/ezkinil: Increase eMMC initial clock frequency ...................................................................... mb/google/zork/ezkinil: Increase eMMC initial clock frequency This will reduce boot time by over 30ms. Some of the initial designs don't have a pull-up resistor on the CMD line. These designs still boot at 400 kHz despite not having the pull-up. BUG=b:158766134 TEST=Boot Ezkinil w/ eMMC to OS. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ida0bbf9bd772ab7d384d5d097fa3b02b846a3efa --- M src/mainboard/google/zork/variants/ezkinil/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/45852/1 diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb index 614d6ab..b0204de 100644 --- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb +++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb @@ -39,6 +39,12 @@ .early_init = true, }" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit -- To view, visit https://review.coreboot.org/c/coreboot/+/45852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida0bbf9bd772ab7d384d5d097fa3b02b846a3efa Gerrit-Change-Number: 45852 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/variants/drawcia: Update TSR1 passive trip temperature
by Sumeet R Pawnikar (Code Review) 09 Oct '20

09 Oct '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45859 ) Change subject: mb/google/dedede/variants/drawcia: Update TSR1 passive trip temperature ...................................................................... mb/google/dedede/variants/drawcia: Update TSR1 passive trip temperature Update TSR1 passive trip temperature BUG=b:169691800 BRANCH=None TEST=Built and tested on dedede system Change-Id: I172391daca981d5591fa9cc5eacad92521dd0dc5 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/45859/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index fa10152..715da7a 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -75,7 +75,7 @@ register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 80, 1000)" register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 4000)" - register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 1000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 51, 1000)" register "policies.passive[3]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000)" register "policies.passive[4]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 60, 1000)" -- To view, visit https://review.coreboot.org/c/coreboot/+/45859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I172391daca981d5591fa9cc5eacad92521dd0dc5 Gerrit-Change-Number: 45859 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Fill VR Configuration Values from devicetree
by Meera Ravindranath (Code Review) 09 Oct '20

09 Oct '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45825 ) Change subject: mb/google/dedede: Fill VR Configuration Values from devicetree ...................................................................... mb/google/dedede: Fill VR Configuration Values from devicetree BUG=b:167472333 TEST=Build and boot dedede and observe the slope and offset values getting updated in the fsp debug log Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I3ea32218040263f0abef9b9dd4c52efb16289fd7 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/45825/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 1f72eb1..22c62e7 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -163,6 +163,15 @@ # register "common_soc_config.<variable_name>" = "value" register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT + # VR config settings + # Imon Slope correction specified in 1/100 increment values. Range is 0-200. + # Eg: 125 = 1.25 + register "ImonSlope" = "100" + + # Imon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. + # For an offset = 12.580, use 12580 + register "ImonOffset" = "0" + # Skip the CPU repalcement check register "SkipCpuReplacementCheck" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/45825 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ea32218040263f0abef9b9dd4c52efb16289fd7 Gerrit-Change-Number: 45825 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

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