coreboot-gerrit September 2020

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Change in coreboot[master]: mb/{51nb/x210,razer/blade_stealth_kbl}/dsdt.asl: decrease DSDT revisi...
by HAOUAS Elyes (Code Review) 13 Oct '20

13 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45783 ) Change subject: mb/{51nb/x210,razer/blade_stealth_kbl}/dsdt.asl: decrease DSDT revision from 0x5 to 0x2 ...................................................................... mb/{51nb/x210,razer/blade_stealth_kbl}/dsdt.asl: decrease DSDT revision from 0x5 to 0x2 DSDT revision 2 is used for ACPI v2 and greater. Change-Id: Ia019358be6574db1b2b06a8a7d52ae996cf45571 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/51nb/x210/dsdt.asl M src/mainboard/razer/blade_stealth_kbl/dsdt.asl 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/45783/1 diff --git a/src/mainboard/51nb/x210/dsdt.asl b/src/mainboard/51nb/x210/dsdt.asl index dde48ab..d56fccb 100644 --- a/src/mainboard/51nb/x210/dsdt.asl +++ b/src/mainboard/51nb/x210/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x05, // DSDT revision: ACPI v5.0 + 0x02, // DSDT revision: ACPI v5.0 OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl index ec3ca79..7ea4f2d 100644 --- a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl +++ b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x05, // DSDT revision: ACPI v5.0 + 0x02, // DSDT revision: ACPI v5.0 "COREv4", // OEM id "COREBOOT", // OEM table id 0x20110725 // OEM revision -- To view, visit https://review.coreboot.org/c/coreboot/+/45783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia019358be6574db1b2b06a8a7d52ae996cf45571 Gerrit-Change-Number: 45783 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/intel/icelake: Select CPU_INTEL_COMMON
by Angel Pons (Code Review) 13 Oct '20

13 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45037 ) Change subject: soc/intel/icelake: Select CPU_INTEL_COMMON ...................................................................... soc/intel/icelake: Select CPU_INTEL_COMMON This is necessary to show the prompt for ENABLE_VMX, whose value is written to a FSP UPD. Otherwise, it is always set to zero. Drop CPU_INTEL_COMMON_SMM since CPU_INTEL_COMMON enables it by default. Tested with BUILD_TIMELESS=1: Without including the config file in the coreboot.rom and ENABLE_VMX not selected, the resulting binary remains identical. Selecting ENABLE_VMX changes a single byte from 0x00 to 0x01. Change-Id: I9b0ca209b60f9804b8f56497046eff96da01cb5c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/icelake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/45037/1 diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 1230675..2aeb6d6 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -15,6 +15,7 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS + select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_M_XIP select GENERIC_GPIO_LIB @@ -34,7 +35,6 @@ select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK - select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK -- To view, visit https://review.coreboot.org/c/coreboot/+/45037 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b0ca209b60f9804b8f56497046eff96da01cb5c Gerrit-Change-Number: 45037 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 13

Change in coreboot[master]: util/superiotool: Add EC registers for IT8728F
by Matt DeVillier (Code Review) 13 Oct '20

13 Oct '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44417 ) Change subject: util/superiotool: Add EC registers for IT8728F ...................................................................... util/superiotool: Add EC registers for IT8728F Add support for dumping registers, default values for EC on ITE IT8128F. Taken from datasheet 'IT8728F V0.4.2' Test: 'superiotool -d -e' on board with IT8728F Super IO Change-Id: I7074b740565edf458d6894c066b61c083a657cb8 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M util/superiotool/ite.c 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/44417/1 diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index 458250a..ff2d8a4 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -1244,6 +1244,31 @@ 0x00,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,EOT}}, {EOT}}}, + {0x8728, "IT8728F", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, + 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d, + 0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x29,0x2a,0x2b, + 0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, + 0x40,0x41,0x42,0x43,0x44,0x45, + 0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5b,0x5c,0x5d,0x5e,0x5f, + 0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x68,0x69,0x6a,0x6b,0x6c,0x6d,0x6e, + 0x70,0x71,0x72,0x73,0x74,0x75,0x76, + 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8a,0x8b,0x8c,0x8d,0x8e,0x8f, + 0x90,0x91,0x92,0x94,0x95,0x96,0x98,0x99,0x9c,0x9d,0x9e,0x9f, + EOT}, + {0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x58,0x0f,0x00,MISC,MISC,MISC, + MISC,MISC,MISC,0x07,0x40,0x00,0x00,0x00,NANA,NANA,NANA,MISC,MISC,MISC, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC, + MISC,MISC,MISC,MISC,MISC,MISC, + 0x00,0x00,0x7f,0x7f,0x7f,0x40,0x00,0x00,0x90,0x00,0x12,0x60,0x00,0x00,0x00, + 0x7f,0x7f,0x7f,0x00,0x00,0x7f,0x0f,0x7f,0x7f,0x7f,0x00,0x00,0x7f,0x0f, + 0x7f,0x7f,0x7f,0x00,0x00,0x7f,0x0f, + NANA,NANA,NANA,NANA,MISC,MISC,MISC,MISC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,NANA, + 0xff,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00,MISC,0x00,MISC, + EOT}}, + {EOT}}}, {0x8783, "IT8783E/F", { {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, -- To view, visit https://review.coreboot.org/c/coreboot/+/44417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7074b740565edf458d6894c066b61c083a657cb8 Gerrit-Change-Number: 44417 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: soc/intel/cannonlake: Align cosmetics with Ice Lake
by Angel Pons (Code Review) 13 Oct '20

13 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45778 ) Change subject: soc/intel/cannonlake: Align cosmetics with Ice Lake ...................................................................... soc/intel/cannonlake: Align cosmetics with Ice Lake Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical. Change-Id: I4d9f882f9f8af1245e937b0d47bc7e993547365f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/cannonlake/acpi/pch_hda.asl M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/me.c M src/soc/intel/cannonlake/sd.c 4 files changed, 46 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/45778/1 diff --git a/src/soc/intel/cannonlake/acpi/pch_hda.asl b/src/soc/intel/cannonlake/acpi/pch_hda.asl index 04e974f..f292901 100644 --- a/src/soc/intel/cannonlake/acpi/pch_hda.asl +++ b/src/soc/intel/cannonlake/acpi/pch_hda.asl @@ -4,7 +4,7 @@ Device (HDAS) { - Name (_ADR, 0x001F0003) + Name (_ADR, 0x001f0003) Name (_DDN, "Audio Controller") Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 36d252e..0c24535 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -54,9 +54,10 @@ static void configure_misc(void) { - config_t *conf = config_of_soc(); msr_t msr; + config_t *conf = config_of_soc(); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ @@ -105,6 +106,33 @@ } } +/* + * The emulated ACPI timer allows replacing of the ACPI timer + * (PM1_TMR) to have no impart on the system. + */ +static void enable_pm_timer_emulation(void) +{ + const struct soc_intel_cannonlake_config *config; + msr_t msr; + + config = config_of_soc(); + + /* Enable PM timer emulation only if ACPI PM timer is disabled */ + if (!config->PmTimerDisabled) + return; + /* + * The derived frequency is calculated as follows: + * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer + * frequency is used. + */ + msr.hi = (3579545ULL << 32) / CTC_FREQ; + /* Set PM1 timer IO port and enable */ + msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | + EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); + wrmsr(MSR_EMULATE_PM_TIMER, msr); +} + static void set_energy_perf_bias(u8 policy) { msr_t msr; @@ -155,33 +183,6 @@ wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } -/* - * The emulated ACPI timer allows replacing of the ACPI timer - * (PM1_TMR) to have no impart on the system. - */ -static void enable_pm_timer_emulation(void) -{ - const struct soc_intel_cannonlake_config *config; - msr_t msr; - - config = config_of_soc(); - - /* Enable PM timer emulation only if ACPI PM timer is disabled */ - if (!config->PmTimerDisabled) - return; - /* - * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. - */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index a51b702..7bbe1ae 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -12,7 +12,7 @@ /* Host Firmware Status Register 2 */ union me_hfsts2 { - uint32_t raw; + uint32_t data; struct { uint32_t nftp_load_failure : 1; uint32_t icc_prog_status : 2; @@ -36,7 +36,7 @@ /* Host Firmware Status Register 4 */ union me_hfsts4 { - uint32_t raw; + uint32_t data; struct { uint32_t rsvd0 : 9; uint32_t enforcement_flow : 1; @@ -52,7 +52,7 @@ /* Host Firmware Status Register 5 */ union me_hfsts5 { - uint32_t raw; + uint32_t data; struct { uint32_t acm_active : 1; uint32_t valid : 1; @@ -71,7 +71,7 @@ /* Host Firmware Status Register 6 */ union me_hfsts6 { - uint32_t raw; + uint32_t data; struct { uint32_t force_boot_guard_acm : 1; uint32_t cpu_debug_disable : 1; @@ -107,24 +107,18 @@ return; hfsts1.data = me_read_config32(PCI_ME_HFSTS1); - hfsts2.raw = me_read_config32(PCI_ME_HFSTS2); + hfsts2.data = me_read_config32(PCI_ME_HFSTS2); hfsts3.data = me_read_config32(PCI_ME_HFSTS3); - hfsts4.raw = me_read_config32(PCI_ME_HFSTS4); - hfsts5.raw = me_read_config32(PCI_ME_HFSTS5); - hfsts6.raw = me_read_config32(PCI_ME_HFSTS6); + hfsts4.data = me_read_config32(PCI_ME_HFSTS4); + hfsts5.data = me_read_config32(PCI_ME_HFSTS5); + hfsts6.data = me_read_config32(PCI_ME_HFSTS6); - printk(BIOS_DEBUG, "ME: HFSTS1 : 0x%08X\n", - hfsts1.data); - printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n", - hfsts2.raw); - printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n", - hfsts3.data); - printk(BIOS_DEBUG, "ME: HFSTS4 : 0x%08X\n", - hfsts4.raw); - printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", - hfsts5.raw); - printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", - hfsts6.raw); + printk(BIOS_DEBUG, "ME: HFSTS1 : 0x%08X\n", hfsts1.data); + printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n", hfsts2.data); + printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n", hfsts3.data); + printk(BIOS_DEBUG, "ME: HFSTS4 : 0x%08X\n", hfsts4.data); + printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", hfsts5.data); + printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.data); printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", hfsts1.fields.mfg_mode ? "YES" : "NO"); @@ -159,5 +153,6 @@ printk(BIOS_DEBUG, "ME: TXT Support : %s\n", hfsts6.fields.txt_support ? "YES" : "NO"); } + BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, dump_me_status, NULL); diff --git a/src/soc/intel/cannonlake/sd.c b/src/soc/intel/cannonlake/sd.c index 7663b2f..46d3852 100644 --- a/src/soc/intel/cannonlake/sd.c +++ b/src/soc/intel/cannonlake/sd.c @@ -3,7 +3,7 @@ #include <intelblocks/sd.h> #include "chip.h" -int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, const struct device *dev) +int sd_fill_soc_gpio_info(struct acpi_gpio *gpio, const struct device *dev) { config_t *config = config_of(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/45778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d9f882f9f8af1245e937b0d47bc7e993547365f Gerrit-Change-Number: 45778 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373
by Srinidhi N Kaushik (Code Review) 13 Oct '20

13 Oct '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45630 ) Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ...................................................................... vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 Update FSP headers for Tiger Lake platform generated based FSP version 3373. Previous version was 3333. Changes Includes below UPDs: ITbtPcieTunnelingForUsb4 SlowSlewRate FastPkgCRampDisable BUG=b: BRANCH=none TEST=build and boot delbin/tglrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I2e28905f8f7241940ea92ac3e83b52ff7948953a --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 2 files changed, 55 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/45630/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 0b3fe7d..28592cd 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -2498,7 +2498,7 @@ /** Offset 0x091C - Reserved **/ - UINT8 Reserved45[4]; + UINT8 Reserved45[12]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -2517,11 +2517,11 @@ **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0920 +/** Offset 0x0928 **/ - UINT8 UnusedUpdSpace25[6]; + UINT8 UnusedUpdSpace27[6]; -/** Offset 0x0926 +/** Offset 0x092E **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 315a0a7..b7ef000 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -923,9 +923,15 @@ **/ UINT8 D3ColdEnable; -/** Offset 0x04B9 - Reserved +/** Offset 0x04B9 - Enable/Disable PCIe tunneling for USB4 + Enable/Disable PCIe tunneling for USB4, default is enable + $EN_DIS **/ - UINT8 Reserved20[8]; + UINT8 ITbtPcieTunnelingForUsb4; + +/** Offset 0x04BA - Reserved +**/ + UINT8 Reserved20[7]; /** Offset 0x04C1 - Enable VMD controller Enable/disable to VMD controller.0: Disable(Default); 1: Enable @@ -1186,9 +1192,19 @@ **/ UINT8 AcousticNoiseMitigation; -/** Offset 0x054B - Reserved +/** Offset 0x054B - Disable Fast Slew Rate for Deep Package C States for VR domains + Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation + feature enabled. 0: False; 1: True + $EN_DIS **/ - UINT8 Reserved28[10]; + UINT8 FastPkgCRampDisable[5]; + +/** Offset 0x0550 - Slew Rate configuration for Deep Package C States for VR domains + Slew Rate configuration for Deep Package C States for VR domains based on Acoustic + Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 + 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 +**/ + UINT8 SlowSlewRate[5]; /** Offset 0x0555 - Enable multi phases silicon initialization A switch to determine MultiPhaseSiInit will be executed or not @@ -1198,7 +1214,7 @@ /** Offset 0x0556 - Reserved **/ - UINT8 Reserved29[10]; + UINT8 Reserved28[10]; /** Offset 0x0560 - AcLoadline PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is @@ -1247,7 +1263,7 @@ /** Offset 0x05A7 - Reserved **/ - UINT8 Reserved30; + UINT8 Reserved29; /** Offset 0x05A8 - Enable or Disable TXT Enable or Disable TXT; 0: Disable; 1: Enable. @@ -1278,7 +1294,7 @@ /** Offset 0x05AD - Reserved **/ - UINT8 Reserved31[3]; + UINT8 Reserved30[3]; /** Offset 0x05B0 - CpuBistData Pointer CPU BIST Data @@ -1299,7 +1315,7 @@ /** Offset 0x05BC - Reserved **/ - UINT8 Reserved32[16]; + UINT8 Reserved31[16]; /** Offset 0x05CC - PpinSupport to view Protected Processor Inventory Number Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this @@ -1340,7 +1356,7 @@ /** Offset 0x05DE - Reserved **/ - UINT8 Reserved33[10]; + UINT8 Reserved32[10]; /** Offset 0x05E8 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. @@ -1360,7 +1376,7 @@ /** Offset 0x05F3 - Reserved **/ - UINT8 Reserved34; + UINT8 Reserved33; /** Offset 0x05F4 - PCH Protect Range Limit Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for @@ -1387,7 +1403,7 @@ /** Offset 0x060A - Reserved **/ - UINT8 Reserved35[3]; + UINT8 Reserved34[3]; /** Offset 0x060D - Enable PCH ISH SPI Cs0 pins assigned Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. @@ -1452,7 +1468,7 @@ /** Offset 0x0622 - Reserved **/ - UINT8 Reserved36; + UINT8 Reserved35; /** Offset 0x0623 - RTC Cmos Memory Lock Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper @@ -1534,7 +1550,7 @@ /** Offset 0x075D - Reserved **/ - UINT8 Reserved37[7]; + UINT8 Reserved36[7]; /** Offset 0x0764 - Touch Host Controller Port 1 Assignment Assign THC Port 1 @@ -1544,7 +1560,7 @@ /** Offset 0x0765 - Reserved **/ - UINT8 Reserved38[7]; + UINT8 Reserved37[7]; /** Offset 0x076C - PCIE RP Pcie Speed Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: @@ -1586,7 +1602,7 @@ /** Offset 0x0814 - Reserved **/ - UINT8 Reserved39[45]; + UINT8 Reserved38[45]; /** Offset 0x0841 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. @@ -1609,7 +1625,7 @@ /** Offset 0x0844 - Reserved **/ - UINT8 Reserved40[2]; + UINT8 Reserved39[2]; /** Offset 0x0846 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. @@ -1805,7 +1821,7 @@ /** Offset 0x0899 - Reserved **/ - UINT8 Reserved41; + UINT8 Reserved40; /** Offset 0x089A - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. @@ -1912,7 +1928,7 @@ /** Offset 0x08C9 - Reserved **/ - UINT8 Reserved42; + UINT8 Reserved41; /** Offset 0x08CA - Thermal Throttling Custimized T0Level Value Custimized T0Level value. @@ -2087,7 +2103,7 @@ /** Offset 0x08EF - Reserved **/ - UINT8 Reserved43; + UINT8 Reserved42; /** Offset 0x08F0 - Thermal Device Temperature Decides the temperature. @@ -2112,7 +2128,7 @@ /** Offset 0x090D - Reserved **/ - UINT8 Reserved44[3]; + UINT8 Reserved43[3]; /** Offset 0x0910 - xHCI High Idle Time LTR override Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting @@ -2174,7 +2190,7 @@ /** Offset 0x0922 - Reserved **/ - UINT8 Reserved45[6]; + UINT8 Reserved44[6]; /** Offset 0x0928 - BgpdtHash[4] BgpdtHash values @@ -2188,7 +2204,7 @@ /** Offset 0x094C - Reserved **/ - UINT8 Reserved46[4]; + UINT8 Reserved45[4]; /** Offset 0x0950 - BiosGuardModulePtr BiosGuardModulePtr default values @@ -2214,7 +2230,7 @@ /** Offset 0x0962 - Reserved **/ - UINT8 Reserved47[6]; + UINT8 Reserved46[6]; /** Offset 0x0968 - SgxEpoch0 SgxEpoch0 default values @@ -2240,7 +2256,7 @@ /** Offset 0x097A - Reserved **/ - UINT8 Reserved48[6]; + UINT8 Reserved47[6]; /** Offset 0x0980 - SVID SDID table Poniter. The address of the table of SVID SDID to customize each SVID SDID entry. This is @@ -2308,7 +2324,7 @@ /** Offset 0x099D - Reserved **/ - UINT8 Reserved49[315]; + UINT8 Reserved48[315]; /** Offset 0x0AD8 - RpPtmBytes **/ @@ -2316,7 +2332,7 @@ /** Offset 0x0ADC - Reserved **/ - UINT8 Reserved50[16]; + UINT8 Reserved49[16]; /** Offset 0x0AEC - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each @@ -2427,7 +2443,7 @@ /** Offset 0x0B44 - Reserved **/ - UINT8 Reserved51[16]; + UINT8 Reserved50[16]; /** Offset 0x0B54 - 1-Core Ratio Limit 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused @@ -2709,7 +2725,7 @@ /** Offset 0x0B82 - Reserved **/ - UINT8 Reserved52; + UINT8 Reserved51; /** Offset 0x0B83 - Enable or Disable Thermal Monitor Enable or Disable Thermal Monitor; 0: Disable; 1: Enable @@ -2847,7 +2863,7 @@ /** Offset 0x0BCF - Reserved **/ - UINT8 Reserved53; + UINT8 Reserved52; /** Offset 0x0BD0 - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. @@ -3085,7 +3101,7 @@ /** Offset 0x0C22 - Reserved **/ - UINT8 Reserved54[17]; + UINT8 Reserved53[17]; /** Offset 0x0C33 - SgxSinitDataFromTpm SgxSinitDataFromTpm default values @@ -3094,7 +3110,7 @@ /** Offset 0x0C34 - Reserved **/ - UINT8 Reserved55[16]; + UINT8 Reserved54[16]; /** Offset 0x0C44 - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): @@ -3228,7 +3244,7 @@ /** Offset 0x0DB9 - Reserved **/ - UINT8 Reserved56[231]; + UINT8 Reserved55[239]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -3243,11 +3259,11 @@ **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0EA0 +/** Offset 0x0EA8 **/ - UINT8 UnusedUpdSpace35[6]; + UINT8 UnusedUpdSpace34[6]; -/** Offset 0x0EA6 +/** Offset 0x0EAE **/ UINT16 UpdTerminator; } FSPS_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/45630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e28905f8f7241940ea92ac3e83b52ff7948953a Gerrit-Change-Number: 45630 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: newchange

8 19

Change in coreboot[master]: cpu/qemu-x86/cache_as_ram_bootblock: Fix wrong instruction
by Patrick Rudolph (Code Review) 13 Oct '20

13 Oct '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45820 ) Change subject: cpu/qemu-x86/cache_as_ram_bootblock: Fix wrong instruction ...................................................................... cpu/qemu-x86/cache_as_ram_bootblock: Fix wrong instruction The shld instruction does an arithmetic shift left on 64bit operants, but it's not the instruction we want, because what it actually does is shifting by cl, and storing the result in address 32. This wasn't notices as the DRAM is up and address 32 is valid. On real hardware when CAR is running this instruction would cause a crash. Replace the instruction with the correct 64bit arithmetic left shift. Change-Id: Iedad9f4b693b1ea05898456eac2050a9389f6f19 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/qemu-x86/cache_as_ram_bootblock.S 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/45820/1 diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 415ed24..eb7d2d9 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -30,7 +30,7 @@ /* Restore the BIST result and timestamps. */ #if defined(__x86_64__) movd %mm2, %rdi - shld %rdi, 32 + shlq $32, %rdi movd %mm1, %rsi or %rsi, %rdi -- To view, visit https://review.coreboot.org/c/coreboot/+/45820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedad9f4b693b1ea05898456eac2050a9389f6f19 Gerrit-Change-Number: 45820 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

6 7

Change in coreboot[master]: nb/intel/i945/acpi: Convert i945.asl to ASL+ Syntax
by HAOUAS Elyes (Code Review) 13 Oct '20

13 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45272 ) Change subject: nb/intel/i945/acpi: Convert i945.asl to ASL+ Syntax ...................................................................... nb/intel/i945/acpi: Convert i945.asl to ASL+ Syntax Change-Id: I332afdcc4a1a7543571d8f9d121d8350347f7153 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/acpi/i945.asl 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/45272/1 diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 789225c..cdc77b5f 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -8,13 +8,13 @@ Method (_OSC, 4) { /* Check for proper PCI/PCIe UUID */ - If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return(Arg3) } Else { CreateDWordField(Arg3, 0, CDW1) - Or(CDW1, 4, CDW1) // Unrecognized UUID, so set bit 2 to 1 + CDW1 = CDW1 | 4 // Unrecognized UUID, so set bit 2 to 1 Return(Arg3) } } @@ -52,22 +52,22 @@ Method (_CRS, 0, Serialized) { //CreateDwordField(PDRS, ^RCRB._BAS, RBR0) - //ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0) + //RBR0 = \_SB.PCI0.LPCB.RCBA << 14 //CreateDwordField(PDRS, ^MCHB._BAS, MBR0) - //ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0) + //MBR0 = \_SB.PCI0.MCHC.MHBR << 14 //CreateDwordField(PDRS, ^DMIB._BAS, DBR0) - //ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0) + //DBR0 = \_SB.PCI0.MCHC.DMBR << 12 //CreateDwordField(PDRS, ^EGPB._BAS, EBR0) - //ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0) + //EBR0 = \_SB.PCI0.MCHC.EPBR << 12 //CreateDwordField(PDRS, ^PCIE._BAS, PBR0) - //ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0) + //PBR0 = \_SB.PCI0.MCHC.PXBR << 26 //CreateDwordField(PDRS, ^PCIE._LEN, PSZ0) - //ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0) + //PSZ0 = 0x10000000 << \_SB.PCI0.MCHC.PXSZ Return(PDRS) } -- To view, visit https://review.coreboot.org/c/coreboot/+/45272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I332afdcc4a1a7543571d8f9d121d8350347f7153 Gerrit-Change-Number: 45272 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ibase/mb899/acpi: Convert platform.asl to ASL+ Syntax
by HAOUAS Elyes (Code Review) 13 Oct '20

13 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45280 ) Change subject: mb/ibase/mb899/acpi: Convert platform.asl to ASL+ Syntax ...................................................................... mb/ibase/mb899/acpi: Convert platform.asl to ASL+ Syntax Change-Id: I947c4228641abc38a5cd75e51fa2f096fda95d6f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/ibase/mb899/acpi/platform.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/45280/1 diff --git a/src/mainboard/ibase/mb899/acpi/platform.asl b/src/mainboard/ibase/mb899/acpi/platform.asl index 30e4d2c..cf73fc1 100644 --- a/src/mainboard/ibase/mb899/acpi/platform.asl +++ b/src/mainboard/ibase/mb899/acpi/platform.asl @@ -20,12 +20,12 @@ // was inserted while a sleep state was active. // Are we going to S3? - If (LEqual(Arg0, 3)) { + If (Arg0 == 3) { // .. } // Are we going to S4? - If (LEqual(Arg0, 4)) { + If (Arg0 == 4) { // .. } -- To view, visit https://review.coreboot.org/c/coreboot/+/45280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I947c4228641abc38a5cd75e51fa2f096fda95d6f Gerrit-Change-Number: 45280 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/getac/p470/acpi: Convert 'gpe.asl' to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 13 Oct '20

13 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45556 ) Change subject: mb/getac/p470/acpi: Convert 'gpe.asl' to ASL 2.0 syntax ...................................................................... mb/getac/p470/acpi: Convert 'gpe.asl' to ASL 2.0 syntax Change-Id: I9f5a89946888be3ed033c2ee079f171a23404e90 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/getac/p470/acpi/gpe.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/45556/1 diff --git a/src/mainboard/getac/p470/acpi/gpe.asl b/src/mainboard/getac/p470/acpi/gpe.asl index e72b980..b9e4056 100644 --- a/src/mainboard/getac/p470/acpi/gpe.asl +++ b/src/mainboard/getac/p470/acpi/gpe.asl @@ -15,7 +15,7 @@ // Software GPE Method (_L02, 0) { - Store (0, GPEC) + GPEC = 0 } // USB1 @@ -42,7 +42,7 @@ // SMBus (Reserved!) Method (_L07, 0) { - // Store (0x20, \_SB.PCI0.SBUS.HSTS) + // \_SB.PCI0.SBUS.HSTS = 0x20 } // COM1/COM2 (RI) -- To view, visit https://review.coreboot.org/c/coreboot/+/45556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f5a89946888be3ed033c2ee079f171a23404e90 Gerrit-Change-Number: 45556 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/asurada: Add USB support
by CK HU (Code Review) 12 Oct '20

12 Oct '20

CK HU has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45397 ) Change subject: mb/google/asurada: Add USB support ...................................................................... mb/google/asurada: Add USB support Change-Id: I35dc4be65f0843c3c74695c443dd958676e6c12c Signed-off-by: CK Hu <ck.hu(a)mediatek.com> --- M src/mainboard/google/asurada/mainboard.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/45397/1 diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index e6040fa..9146d7b 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -1,9 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <device/device.h> +#include <soc/usb.h> static void mainboard_init(struct device *dev) { + setup_usb_host(); } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/45397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35dc4be65f0843c3c74695c443dd958676e6c12c Gerrit-Change-Number: 45397 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-MessageType: newchange

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