Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373
Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45630 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ......................................................................
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373
Update FSP headers for Tiger Lake platform generated based FSP version 3373. Previous version was 3333.
Changes Includes below UPDs: ITbtPcieTunnelingForUsb4 SlowSlewRate FastPkgCRampDisable
BUG=b: BRANCH=none TEST=build and boot delbin/tglrvp
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I2e28905f8f7241940ea92ac3e83b52ff7948953a --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 2 files changed, 55 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/45630/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 0b3fe7d..28592cd 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -2498,7 +2498,7 @@
/** Offset 0x091C - Reserved **/ - UINT8 Reserved45[4]; + UINT8 Reserved45[12]; } FSP_M_CONFIG;
/** Fsp M UPD Configuration @@ -2517,11 +2517,11 @@ **/ FSP_M_CONFIG FspmConfig;
-/** Offset 0x0920 +/** Offset 0x0928 **/ - UINT8 UnusedUpdSpace25[6]; + UINT8 UnusedUpdSpace27[6];
-/** Offset 0x0926 +/** Offset 0x092E **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 315a0a7..b7ef000 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -923,9 +923,15 @@ **/ UINT8 D3ColdEnable;
-/** Offset 0x04B9 - Reserved +/** Offset 0x04B9 - Enable/Disable PCIe tunneling for USB4 + Enable/Disable PCIe tunneling for USB4, default is enable + $EN_DIS **/ - UINT8 Reserved20[8]; + UINT8 ITbtPcieTunnelingForUsb4; + +/** Offset 0x04BA - Reserved +**/ + UINT8 Reserved20[7];
/** Offset 0x04C1 - Enable VMD controller Enable/disable to VMD controller.0: Disable(Default); 1: Enable @@ -1186,9 +1192,19 @@ **/ UINT8 AcousticNoiseMitigation;
-/** Offset 0x054B - Reserved +/** Offset 0x054B - Disable Fast Slew Rate for Deep Package C States for VR domains + Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation + feature enabled. <b>0: False</b>; 1: True + $EN_DIS **/ - UINT8 Reserved28[10]; + UINT8 FastPkgCRampDisable[5]; + +/** Offset 0x0550 - Slew Rate configuration for Deep Package C States for VR domains + Slew Rate configuration for Deep Package C States for VR domains based on Acoustic + Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16 + 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 +**/ + UINT8 SlowSlewRate[5];
/** Offset 0x0555 - Enable multi phases silicon initialization A switch to determine MultiPhaseSiInit will be executed or not @@ -1198,7 +1214,7 @@
/** Offset 0x0556 - Reserved **/ - UINT8 Reserved29[10]; + UINT8 Reserved28[10];
/** Offset 0x0560 - AcLoadline PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is @@ -1247,7 +1263,7 @@
/** Offset 0x05A7 - Reserved **/ - UINT8 Reserved30; + UINT8 Reserved29;
/** Offset 0x05A8 - Enable or Disable TXT Enable or Disable TXT; 0: Disable; <b>1: Enable</b>. @@ -1278,7 +1294,7 @@
/** Offset 0x05AD - Reserved **/ - UINT8 Reserved31[3]; + UINT8 Reserved30[3];
/** Offset 0x05B0 - CpuBistData Pointer CPU BIST Data @@ -1299,7 +1315,7 @@
/** Offset 0x05BC - Reserved **/ - UINT8 Reserved32[16]; + UINT8 Reserved31[16];
/** Offset 0x05CC - PpinSupport to view Protected Processor Inventory Number Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this @@ -1340,7 +1356,7 @@
/** Offset 0x05DE - Reserved **/ - UINT8 Reserved33[10]; + UINT8 Reserved32[10];
/** Offset 0x05E8 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. @@ -1360,7 +1376,7 @@
/** Offset 0x05F3 - Reserved **/ - UINT8 Reserved34; + UINT8 Reserved33;
/** Offset 0x05F4 - PCH Protect Range Limit Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for @@ -1387,7 +1403,7 @@
/** Offset 0x060A - Reserved **/ - UINT8 Reserved35[3]; + UINT8 Reserved34[3];
/** Offset 0x060D - Enable PCH ISH SPI Cs0 pins assigned Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. @@ -1452,7 +1468,7 @@
/** Offset 0x0622 - Reserved **/ - UINT8 Reserved36; + UINT8 Reserved35;
/** Offset 0x0623 - RTC Cmos Memory Lock Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper @@ -1534,7 +1550,7 @@
/** Offset 0x075D - Reserved **/ - UINT8 Reserved37[7]; + UINT8 Reserved36[7];
/** Offset 0x0764 - Touch Host Controller Port 1 Assignment Assign THC Port 1 @@ -1544,7 +1560,7 @@
/** Offset 0x0765 - Reserved **/ - UINT8 Reserved38[7]; + UINT8 Reserved37[7];
/** Offset 0x076C - PCIE RP Pcie Speed Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: @@ -1586,7 +1602,7 @@
/** Offset 0x0814 - Reserved **/ - UINT8 Reserved39[45]; + UINT8 Reserved38[45];
/** Offset 0x0841 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. @@ -1609,7 +1625,7 @@
/** Offset 0x0844 - Reserved **/ - UINT8 Reserved40[2]; + UINT8 Reserved39[2];
/** Offset 0x0846 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. @@ -1805,7 +1821,7 @@
/** Offset 0x0899 - Reserved **/ - UINT8 Reserved41; + UINT8 Reserved40;
/** Offset 0x089A - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. @@ -1912,7 +1928,7 @@
/** Offset 0x08C9 - Reserved **/ - UINT8 Reserved42; + UINT8 Reserved41;
/** Offset 0x08CA - Thermal Throttling Custimized T0Level Value Custimized T0Level value. @@ -2087,7 +2103,7 @@
/** Offset 0x08EF - Reserved **/ - UINT8 Reserved43; + UINT8 Reserved42;
/** Offset 0x08F0 - Thermal Device Temperature Decides the temperature. @@ -2112,7 +2128,7 @@
/** Offset 0x090D - Reserved **/ - UINT8 Reserved44[3]; + UINT8 Reserved43[3];
/** Offset 0x0910 - xHCI High Idle Time LTR override Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting @@ -2174,7 +2190,7 @@
/** Offset 0x0922 - Reserved **/ - UINT8 Reserved45[6]; + UINT8 Reserved44[6];
/** Offset 0x0928 - BgpdtHash[4] BgpdtHash values @@ -2188,7 +2204,7 @@
/** Offset 0x094C - Reserved **/ - UINT8 Reserved46[4]; + UINT8 Reserved45[4];
/** Offset 0x0950 - BiosGuardModulePtr BiosGuardModulePtr default values @@ -2214,7 +2230,7 @@
/** Offset 0x0962 - Reserved **/ - UINT8 Reserved47[6]; + UINT8 Reserved46[6];
/** Offset 0x0968 - SgxEpoch0 SgxEpoch0 default values @@ -2240,7 +2256,7 @@
/** Offset 0x097A - Reserved **/ - UINT8 Reserved48[6]; + UINT8 Reserved47[6];
/** Offset 0x0980 - SVID SDID table Poniter. The address of the table of SVID SDID to customize each SVID SDID entry. This is @@ -2308,7 +2324,7 @@
/** Offset 0x099D - Reserved **/ - UINT8 Reserved49[315]; + UINT8 Reserved48[315];
/** Offset 0x0AD8 - RpPtmBytes **/ @@ -2316,7 +2332,7 @@
/** Offset 0x0ADC - Reserved **/ - UINT8 Reserved50[16]; + UINT8 Reserved49[16];
/** Offset 0x0AEC - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each @@ -2427,7 +2443,7 @@
/** Offset 0x0B44 - Reserved **/ - UINT8 Reserved51[16]; + UINT8 Reserved50[16];
/** Offset 0x0B54 - 1-Core Ratio Limit 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused @@ -2709,7 +2725,7 @@
/** Offset 0x0B82 - Reserved **/ - UINT8 Reserved52; + UINT8 Reserved51;
/** Offset 0x0B83 - Enable or Disable Thermal Monitor Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b> @@ -2847,7 +2863,7 @@
/** Offset 0x0BCF - Reserved **/ - UINT8 Reserved53; + UINT8 Reserved52;
/** Offset 0x0BD0 - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments. @@ -3085,7 +3101,7 @@
/** Offset 0x0C22 - Reserved **/ - UINT8 Reserved54[17]; + UINT8 Reserved53[17];
/** Offset 0x0C33 - SgxSinitDataFromTpm SgxSinitDataFromTpm default values @@ -3094,7 +3110,7 @@
/** Offset 0x0C34 - Reserved **/ - UINT8 Reserved55[16]; + UINT8 Reserved54[16];
/** Offset 0x0C44 - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): @@ -3228,7 +3244,7 @@
/** Offset 0x0DB9 - Reserved **/ - UINT8 Reserved56[231]; + UINT8 Reserved55[239]; } FSP_S_CONFIG;
/** Fsp S UPD Configuration @@ -3243,11 +3259,11 @@ **/ FSP_S_CONFIG FspsConfig;
-/** Offset 0x0EA0 +/** Offset 0x0EA8 **/ - UINT8 UnusedUpdSpace35[6]; + UINT8 UnusedUpdSpace34[6];
-/** Offset 0x0EA6 +/** Offset 0x0EAE **/ UINT16 UpdTerminator; } FSPS_UPD;
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45630 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ......................................................................
Patch Set 1: Code-Review+1
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45630 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45630/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45630/1//COMMIT_MSG@12 PS1, Line 12: Includes include
https://review.coreboot.org/c/coreboot/+/45630/1//COMMIT_MSG@13 PS1, Line 13: ITbtPcieTunnelingForUsb4 : SlowSlewRate : FastPkgCRampDisable Please format it as a list.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45630 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45630/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45630/1//COMMIT_MSG@17 PS1, Line 17: BUG=b: b:153015585
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45630 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45630/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45630/1//COMMIT_MSG@12 PS1, Line 12: Includes
include
Ack
https://review.coreboot.org/c/coreboot/+/45630/1//COMMIT_MSG@13 PS1, Line 13: ITbtPcieTunnelingForUsb4 : SlowSlewRate : FastPkgCRampDisable
Please format it as a list.
Ack
https://review.coreboot.org/c/coreboot/+/45630/1//COMMIT_MSG@17 PS1, Line 17: BUG=b:
b:153015585
@Tim, cros-bug is 169759177. Have more details there
Hello build bot (Jenkins), Furquan Shaikh, Nick Vaccaro, Angel Pons, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45630
to look at the new patch set (#2).
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ......................................................................
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373
Update FSP headers for Tiger Lake platform generated based FSP version 3373. Previous version was 3333.
Changes include below UPDs: 1. ITbtPcieTunnelingForUsb4 2. SlowSlewRate 3. FastPkgCRampDisable
BUG=b:169759177 BRANCH=none TEST=build and boot delbin/tglrvp
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I2e28905f8f7241940ea92ac3e83b52ff7948953a --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 2 files changed, 55 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/45630/2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45630 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ......................................................................
Patch Set 2:
You'll need to rebase on master to get this to build correctly again.
Dossym Nurmukhanov has uploaded a new patch set (#3) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/45630 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ......................................................................
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373
Update FSP headers for Tiger Lake platform generated based FSP version 3373. Previous version was 3333.
Changes include below UPDs: 1. ITbtPcieTunnelingForUsb4 2. SlowSlewRate 3. FastPkgCRampDisable
BUG=b:169759177 BRANCH=none TEST=build and boot delbin/tglrvp
Cq-Depend:chrome-internal:3308203, chrome-internal:3308204, chrome-internal:3284975 Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I2e28905f8f7241940ea92ac3e83b52ff7948953a --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 2 files changed, 55 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/45630/3
Shaunak Saha has uploaded a new patch set (#4) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/45630 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ......................................................................
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373
Update FSP headers for Tiger Lake platform generated based FSP version 3373. Previous version was 3333.
Changes Includes below UPDs: ITbtPcieTunnelingForUsb4 SlowSlewRate FastPkgCRampDisable
BUG=b: BRANCH=none TEST=build and boot delbin/tglrvp
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I2e28905f8f7241940ea92ac3e83b52ff7948953a --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 2 files changed, 55 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/45630/4
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45630 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ......................................................................
Patch Set 4: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/45630/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45630/4//COMMIT_MSG@17 PS4, Line 17: b: b:169759177
Dossym Nurmukhanov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45630 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45630/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45630/4//COMMIT_MSG@21 PS4, Line 21: Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Looks like "Cq-Depend:chrome-internal:3308203, chrome-internal:3308204, chrome-internal:3284975" line was dropped
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Tim Wawrzynczak, Nick Vaccaro, Angel Pons, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45630
to look at the new patch set (#5).
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ......................................................................
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373
Update FSP headers for Tiger Lake platform generated based FSP version 3373. Previous version was 3333.
Changes Includes below UPDs: ITbtPcieTunnelingForUsb4 SlowSlewRate FastPkgCRampDisable
BUG=b:169759177 BRANCH=none TEST=build and boot delbin/tglrvp
Cq-Depend:chrome-internal:3308203, chrome-internal:3308204, chrome-internal:3284975 Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I2e28905f8f7241940ea92ac3e83b52ff7948953a --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 2 files changed, 55 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/45630/5
Dossym Nurmukhanov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45630 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ......................................................................
Patch Set 5: Code-Review+2
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45630 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ......................................................................
Patch Set 5: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/45630/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45630/5//COMMIT_MSG@9 PS5, Line 9: based FSP based on FSP
https://review.coreboot.org/c/coreboot/+/45630/5//COMMIT_MSG@12 PS5, Line 12: Includes include
Dossym Nurmukhanov has uploaded a new patch set (#6) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/45630 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ......................................................................
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373
Update FSP headers for Tiger Lake platform generated based on FSP version 3373. Previous version was 3333.
Changes include below UPDs: ITbtPcieTunnelingForUsb4 SlowSlewRate FastPkgCRampDisable
BUG=b:169759177 BRANCH=none TEST=build and boot delbin/tglrvp
Cq-Depend:chrome-internal:3308203, chrome-internal:3308204, chrome-internal:3284975 Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I2e28905f8f7241940ea92ac3e83b52ff7948953a --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 2 files changed, 55 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/45630/6
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45630 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ......................................................................
Patch Set 6: Code-Review+2
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45630 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ......................................................................
Patch Set 6:
(6 comments)
https://review.coreboot.org/c/coreboot/+/45630/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45630/1//COMMIT_MSG@17 PS1, Line 17: BUG=b:
@Tim, cros-bug is 169759177. […]
Done
https://review.coreboot.org/c/coreboot/+/45630/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45630/4//COMMIT_MSG@17 PS4, Line 17: b:
b:169759177
Done
https://review.coreboot.org/c/coreboot/+/45630/4//COMMIT_MSG@21 PS4, Line 21: Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com
Looks like "Cq-Depend:chrome-internal:3308203, chrome-internal:3308204, chrome-internal:3284975" lin […]
Done
https://review.coreboot.org/c/coreboot/+/45630/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45630/5//COMMIT_MSG@9 PS5, Line 9: based FSP
based on FSP
Done
https://review.coreboot.org/c/coreboot/+/45630/5//COMMIT_MSG@12 PS5, Line 12: Includes
include
Done
https://review.coreboot.org/c/coreboot/+/45630/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45630/6//COMMIT_MSG@21 PS6, Line 21: Cq-Depend:chrome-internal:3308203, chrome-internal:3308204, : chrome-internal:3284975 I'm not sure if the CQ picks them up correctly if the line is broken?
Dossym Nurmukhanov has uploaded a new patch set (#7) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/45630 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ......................................................................
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373
Update FSP headers for Tiger Lake platform generated based on FSP version 3373. Previous version was 3333.
Changes include below UPDs: ITbtPcieTunnelingForUsb4 SlowSlewRate FastPkgCRampDisable
BUG=b:169759177 BRANCH=none TEST=build and boot delbin/tglrvp
Cq-Depend:chrome-internal:3308203, chrome-internal:3308204 Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I2e28905f8f7241940ea92ac3e83b52ff7948953a --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 2 files changed, 55 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/45630/7
Dossym Nurmukhanov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45630 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ......................................................................
Patch Set 7:
(1 comment)
That last CL is not needed actually in Cq-Depend anymore.
https://review.coreboot.org/c/coreboot/+/45630/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45630/6//COMMIT_MSG@21 PS6, Line 21: Cq-Depend:chrome-internal:3308203, chrome-internal:3308204, : chrome-internal:3284975
I'm not sure if the CQ picks them up correctly if the line is broken?
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45630 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373 ......................................................................
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373
Update FSP headers for Tiger Lake platform generated based on FSP version 3373. Previous version was 3333.
Changes include below UPDs: ITbtPcieTunnelingForUsb4 SlowSlewRate FastPkgCRampDisable
BUG=b:169759177 BRANCH=none TEST=build and boot delbin/tglrvp
Cq-Depend:chrome-internal:3308203, chrome-internal:3308204 Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I2e28905f8f7241940ea92ac3e83b52ff7948953a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45630 Reviewed-by: Nick Vaccaro nvaccaro@google.com Reviewed-by: Dossym Nurmukhanov dossym@google.com Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 2 files changed, 55 insertions(+), 39 deletions(-)
Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve Dossym Nurmukhanov: Looks good to me, approved
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 0b3fe7d..28592cd 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -2498,7 +2498,7 @@
/** Offset 0x091C - Reserved **/ - UINT8 Reserved45[4]; + UINT8 Reserved45[12]; } FSP_M_CONFIG;
/** Fsp M UPD Configuration @@ -2517,11 +2517,11 @@ **/ FSP_M_CONFIG FspmConfig;
-/** Offset 0x0920 +/** Offset 0x0928 **/ - UINT8 UnusedUpdSpace25[6]; + UINT8 UnusedUpdSpace27[6];
-/** Offset 0x0926 +/** Offset 0x092E **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 315a0a7..b7ef000 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -923,9 +923,15 @@ **/ UINT8 D3ColdEnable;
-/** Offset 0x04B9 - Reserved +/** Offset 0x04B9 - Enable/Disable PCIe tunneling for USB4 + Enable/Disable PCIe tunneling for USB4, default is enable + $EN_DIS **/ - UINT8 Reserved20[8]; + UINT8 ITbtPcieTunnelingForUsb4; + +/** Offset 0x04BA - Reserved +**/ + UINT8 Reserved20[7];
/** Offset 0x04C1 - Enable VMD controller Enable/disable to VMD controller.0: Disable(Default); 1: Enable @@ -1186,9 +1192,19 @@ **/ UINT8 AcousticNoiseMitigation;
-/** Offset 0x054B - Reserved +/** Offset 0x054B - Disable Fast Slew Rate for Deep Package C States for VR domains + Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation + feature enabled. <b>0: False</b>; 1: True + $EN_DIS **/ - UINT8 Reserved28[10]; + UINT8 FastPkgCRampDisable[5]; + +/** Offset 0x0550 - Slew Rate configuration for Deep Package C States for VR domains + Slew Rate configuration for Deep Package C States for VR domains based on Acoustic + Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16 + 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 +**/ + UINT8 SlowSlewRate[5];
/** Offset 0x0555 - Enable multi phases silicon initialization A switch to determine MultiPhaseSiInit will be executed or not @@ -1198,7 +1214,7 @@
/** Offset 0x0556 - Reserved **/ - UINT8 Reserved29[10]; + UINT8 Reserved28[10];
/** Offset 0x0560 - AcLoadline PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is @@ -1247,7 +1263,7 @@
/** Offset 0x05A7 - Reserved **/ - UINT8 Reserved30; + UINT8 Reserved29;
/** Offset 0x05A8 - Enable or Disable TXT Enable or Disable TXT; 0: Disable; <b>1: Enable</b>. @@ -1278,7 +1294,7 @@
/** Offset 0x05AD - Reserved **/ - UINT8 Reserved31[3]; + UINT8 Reserved30[3];
/** Offset 0x05B0 - CpuBistData Pointer CPU BIST Data @@ -1299,7 +1315,7 @@
/** Offset 0x05BC - Reserved **/ - UINT8 Reserved32[16]; + UINT8 Reserved31[16];
/** Offset 0x05CC - PpinSupport to view Protected Processor Inventory Number Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this @@ -1340,7 +1356,7 @@
/** Offset 0x05DE - Reserved **/ - UINT8 Reserved33[10]; + UINT8 Reserved32[10];
/** Offset 0x05E8 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. @@ -1360,7 +1376,7 @@
/** Offset 0x05F3 - Reserved **/ - UINT8 Reserved34; + UINT8 Reserved33;
/** Offset 0x05F4 - PCH Protect Range Limit Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for @@ -1387,7 +1403,7 @@
/** Offset 0x060A - Reserved **/ - UINT8 Reserved35[3]; + UINT8 Reserved34[3];
/** Offset 0x060D - Enable PCH ISH SPI Cs0 pins assigned Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. @@ -1452,7 +1468,7 @@
/** Offset 0x0622 - Reserved **/ - UINT8 Reserved36; + UINT8 Reserved35;
/** Offset 0x0623 - RTC Cmos Memory Lock Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper @@ -1534,7 +1550,7 @@
/** Offset 0x075D - Reserved **/ - UINT8 Reserved37[7]; + UINT8 Reserved36[7];
/** Offset 0x0764 - Touch Host Controller Port 1 Assignment Assign THC Port 1 @@ -1544,7 +1560,7 @@
/** Offset 0x0765 - Reserved **/ - UINT8 Reserved38[7]; + UINT8 Reserved37[7];
/** Offset 0x076C - PCIE RP Pcie Speed Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: @@ -1586,7 +1602,7 @@
/** Offset 0x0814 - Reserved **/ - UINT8 Reserved39[45]; + UINT8 Reserved38[45];
/** Offset 0x0841 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. @@ -1609,7 +1625,7 @@
/** Offset 0x0844 - Reserved **/ - UINT8 Reserved40[2]; + UINT8 Reserved39[2];
/** Offset 0x0846 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. @@ -1805,7 +1821,7 @@
/** Offset 0x0899 - Reserved **/ - UINT8 Reserved41; + UINT8 Reserved40;
/** Offset 0x089A - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. @@ -1912,7 +1928,7 @@
/** Offset 0x08C9 - Reserved **/ - UINT8 Reserved42; + UINT8 Reserved41;
/** Offset 0x08CA - Thermal Throttling Custimized T0Level Value Custimized T0Level value. @@ -2087,7 +2103,7 @@
/** Offset 0x08EF - Reserved **/ - UINT8 Reserved43; + UINT8 Reserved42;
/** Offset 0x08F0 - Thermal Device Temperature Decides the temperature. @@ -2112,7 +2128,7 @@
/** Offset 0x090D - Reserved **/ - UINT8 Reserved44[3]; + UINT8 Reserved43[3];
/** Offset 0x0910 - xHCI High Idle Time LTR override Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting @@ -2174,7 +2190,7 @@
/** Offset 0x0922 - Reserved **/ - UINT8 Reserved45[6]; + UINT8 Reserved44[6];
/** Offset 0x0928 - BgpdtHash[4] BgpdtHash values @@ -2188,7 +2204,7 @@
/** Offset 0x094C - Reserved **/ - UINT8 Reserved46[4]; + UINT8 Reserved45[4];
/** Offset 0x0950 - BiosGuardModulePtr BiosGuardModulePtr default values @@ -2214,7 +2230,7 @@
/** Offset 0x0962 - Reserved **/ - UINT8 Reserved47[6]; + UINT8 Reserved46[6];
/** Offset 0x0968 - SgxEpoch0 SgxEpoch0 default values @@ -2240,7 +2256,7 @@
/** Offset 0x097A - Reserved **/ - UINT8 Reserved48[6]; + UINT8 Reserved47[6];
/** Offset 0x0980 - SVID SDID table Poniter. The address of the table of SVID SDID to customize each SVID SDID entry. This is @@ -2308,7 +2324,7 @@
/** Offset 0x099D - Reserved **/ - UINT8 Reserved49[315]; + UINT8 Reserved48[315];
/** Offset 0x0AD8 - RpPtmBytes **/ @@ -2316,7 +2332,7 @@
/** Offset 0x0ADC - Reserved **/ - UINT8 Reserved50[16]; + UINT8 Reserved49[16];
/** Offset 0x0AEC - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each @@ -2427,7 +2443,7 @@
/** Offset 0x0B44 - Reserved **/ - UINT8 Reserved51[16]; + UINT8 Reserved50[16];
/** Offset 0x0B54 - 1-Core Ratio Limit 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused @@ -2709,7 +2725,7 @@
/** Offset 0x0B82 - Reserved **/ - UINT8 Reserved52; + UINT8 Reserved51;
/** Offset 0x0B83 - Enable or Disable Thermal Monitor Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b> @@ -2847,7 +2863,7 @@
/** Offset 0x0BCF - Reserved **/ - UINT8 Reserved53; + UINT8 Reserved52;
/** Offset 0x0BD0 - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments. @@ -3085,7 +3101,7 @@
/** Offset 0x0C22 - Reserved **/ - UINT8 Reserved54[17]; + UINT8 Reserved53[17];
/** Offset 0x0C33 - SgxSinitDataFromTpm SgxSinitDataFromTpm default values @@ -3094,7 +3110,7 @@
/** Offset 0x0C34 - Reserved **/ - UINT8 Reserved55[16]; + UINT8 Reserved54[16];
/** Offset 0x0C44 - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): @@ -3228,7 +3244,7 @@
/** Offset 0x0DB9 - Reserved **/ - UINT8 Reserved56[231]; + UINT8 Reserved55[239]; } FSP_S_CONFIG;
/** Fsp S UPD Configuration @@ -3243,11 +3259,11 @@ **/ FSP_S_CONFIG FspsConfig;
-/** Offset 0x0EA0 +/** Offset 0x0EA8 **/ - UINT8 UnusedUpdSpace35[6]; + UINT8 UnusedUpdSpace34[6];
-/** Offset 0x0EA6 +/** Offset 0x0EAE **/ UINT16 UpdTerminator; } FSPS_UPD;
-
Angel Pons (Code Review) -
Dossym Nurmukhanov (Code Review)
-
Nick Vaccaro (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)
-
Shaunak Saha (Code Review)
-
Srinidhi N Kaushik (Code Review)
-
Tim Wawrzynczak (Code Review)