coreboot-gerrit September 2020

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Change in coreboot[master]: soc/intel/jasperlake: Update VR Configuration Values
by Meera Ravindranath (Code Review) 09 Oct '20

09 Oct '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45645 ) Change subject: soc/intel/jasperlake: Update VR Configuration Values ...................................................................... soc/intel/jasperlake: Update VR Configuration Values This patch fixes the CPU Throttling issue observed on Drawlat BRANCH=None BUG=b:167472333 Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I3fa32218040263f0abef8b9dd4c52efb31289fd7 --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/45645/1 diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index cdd088e..6c83503 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -177,6 +177,10 @@ sizeof(params->SataPortsDevSlp)); } + /* VR Configuration */ + params->IccMax[0] = 140; + params->TdcCurrentLimit[0] = 80; + /* SDCard related configuration */ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); params->ScsSdCardEnabled = is_dev_enabled(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/45645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fa32218040263f0abef8b9dd4c52efb31289fd7 Gerrit-Change-Number: 45645 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add locking of IA32_FEATURE_CONTROL and VMX
by Christian Walter (Code Review) 09 Oct '20

09 Oct '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45869 ) Change subject: soc/intel/xeon_sp/cpx: Add locking of IA32_FEATURE_CONTROL and VMX ...................................................................... soc/intel/xeon_sp/cpx: Add locking of IA32_FEATURE_CONTROL and VMX Change-Id: Ib329648f77acecccb0ced1806f61be252d03f2f4 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/cpu.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/45869/1 diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index eb8c0eb..0999f6d 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -16,6 +16,7 @@ #include <soc/msr.h> #include <soc/soc_util.h> #include "chip.h" +#include <cpu/intel/common/common.h> static const void *microcode_patch; @@ -91,6 +92,9 @@ /* Clear out pending MCEs */ xeon_configure_mca(); + + /* Enable Vmx */ + set_vmx_and_lock(); } static struct device_operations cpu_dev_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/45869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib329648f77acecccb0ced1806f61be252d03f2f4 Gerrit-Change-Number: 45869 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/intel/txt: Style fixes
by Christian Walter (Code Review) 09 Oct '20

09 Oct '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45867 ) Change subject: security/intel/txt: Style fixes ...................................................................... security/intel/txt: Style fixes Fix two style issues. First one is to align the #define in txt_registers.h, the second one prints the chipset as hex to make it more readable. Change-Id: Ifafbe0a1161e9fe6e790692002375f45d813b723 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/security/intel/txt/logging.c M src/security/intel/txt/txt_register.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/45867/1 diff --git a/src/security/intel/txt/logging.c b/src/security/intel/txt/logging.c index cf14b55..f329cf9 100644 --- a/src/security/intel/txt/logging.c +++ b/src/security/intel/txt/logging.c @@ -141,7 +141,7 @@ printk(BIOS_INFO, " Header: v%u.%u\n", acm_header->header_version[0], acm_header->header_version[1]); - printk(BIOS_INFO, " Chipset: %u\n", acm_header->chipset_id); + printk(BIOS_INFO, " Chipset: %x\n", acm_header->chipset_id); printk(BIOS_INFO, " Size: %zu\n", acm_size); switch (acm_header->flags) { diff --git a/src/security/intel/txt/txt_register.h b/src/security/intel/txt/txt_register.h index c7f1575..bf087de 100644 --- a/src/security/intel/txt/txt_register.h +++ b/src/security/intel/txt/txt_register.h @@ -23,7 +23,7 @@ */ #define TXT_ESTS_WAKE_ERROR_STS (1 << 6) -#define TXT_ERROR (TXT_BASE + 0x30) +#define TXT_ERROR (TXT_BASE + 0x30) #define ACMERROR_TXT_VALID (1ul << 31) #define ACMERROR_TXT_EXTERNAL (1ul << 30) -- To view, visit https://review.coreboot.org/c/coreboot/+/45867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifafbe0a1161e9fe6e790692002375f45d813b723 Gerrit-Change-Number: 45867 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: Add function to raise the CPU frequency of MT8192
by CK HU (Code Review) 08 Oct '20

08 Oct '20

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45401 to review the following change. Change subject: soc/mediatek: Add function to raise the CPU frequency of MT8192 ...................................................................... soc/mediatek: Add function to raise the CPU frequency of MT8192 Rename all mt_pll_raise_ca53_freq() into mt_pll_raise_little_cpu_freq(). Implement mt_pll_raise_little_cpu_freq() in MT8192. Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> Change-Id: I97d9a61f39f2eb27f0c6f911a9199bf0eaae4fbe --- M src/mainboard/google/kukui/romstage.c M src/mainboard/google/oak/romstage.c M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8173/pll.c M src/soc/mediatek/mt8183/pll.c M src/soc/mediatek/mt8192/include/soc/pll.h M src/soc/mediatek/mt8192/pll.c 7 files changed, 32 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/45401/1 diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 1a2127d..b9c0d2c 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -57,7 +57,7 @@ mt6358_init(); /* Adjust VSIM2 down to 2.7V because it is shared with IT6505. */ pmic_set_vsim2_cali(2700); - mt_pll_raise_ca53_freq(1989 * MHz); + mt_pll_raise_little_cpu_freq(1989 * MHz); pmic_init_scp_voltage(); rtc_boot(); mt_mem_init(&dparam_ops); diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c index e1d3747..2d62980 100644 --- a/src/mainboard/google/oak/romstage.c +++ b/src/mainboard/google/oak/romstage.c @@ -28,9 +28,9 @@ /* Set to maximum frequency */ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5) - mt_pll_raise_ca53_freq(1600 * MHz); + mt_pll_raise_little_cpu_freq(1600 * MHz); else - mt_pll_raise_ca53_freq(1700 * MHz); + mt_pll_raise_little_cpu_freq(1700 * MHz); mtk_mmu_after_dram(); } diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index a1bd96d..0f8732f 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -58,6 +58,6 @@ void mux_set_sel(const struct mux *mux, u32 sel); int pll_set_rate(const struct pll *pll, u32 rate); void mt_pll_init(void); -void mt_pll_raise_ca53_freq(u32 freq); +void mt_pll_raise_little_cpu_freq(u32 freq); #endif diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index 0fe94cf..7133fde 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -417,7 +417,7 @@ } } -void mt_pll_raise_ca53_freq(u32 freq) +void mt_pll_raise_little_cpu_freq(u32 freq) { pll_set_rate(&plls[APMIXED_ARMCA7PLL], freq); /* freq in Hz */ } diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 4570269..0e96f4c 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -362,7 +362,7 @@ setbits32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4); } -void mt_pll_raise_ca53_freq(u32 freq) +void mt_pll_raise_little_cpu_freq(u32 freq) { /* enable [4] intermediate clock armpll_divider_pll1_ck */ setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index c83436e..177bd33 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -253,6 +253,7 @@ MCU_MUX_MASK = 0x3 << 9, MCU_MUX_SRC_PLL = 0x1 << 9, + MCU_MUX_SRC_DIV_PLL1 = 0x2 << 9, }; enum { diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index 40d92fd..e8849df 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -434,3 +434,28 @@ /* enable [14] dramc_pll104m_ck */ setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); } + +void mt_pll_raise_little_cpu_freq(u32 freq) +{ + /* enable [4] intermediate clock armpll_divider_pll1_ck */ + setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); + + /* switch ca55 clock source to intermediate clock */ + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1); + + /* disable armpll_ll frequency output */ + clrbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN); + + /* raise armpll_ll frequency */ + pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq); + + /* enable armpll_ll frequency output */ + setbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN); + udelay(PLL_EN_DELAY); + + /* switch ca55 clock source back to armpll_ll */ + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + + /* disable [4] intermediate clock armpll_divider_pll1_ck */ + clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97d9a61f39f2eb27f0c6f911a9199bf0eaae4fbe Gerrit-Change-Number: 45401 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lynxpoint/broadwell: Relegate IOBP printk to BIOS_SPEW
by Angel Pons (Code Review) 08 Oct '20

08 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45720 ) Change subject: lynxpoint/broadwell: Relegate IOBP printk to BIOS_SPEW ...................................................................... lynxpoint/broadwell: Relegate IOBP printk to BIOS_SPEW There's no need to make so much noise when writing IOBP registers. Change-Id: I1fbb6e409375240544b9b5e810523f9471435f2f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/iobp.c M src/southbridge/intel/lynxpoint/iobp.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/45720/1 diff --git a/src/soc/intel/broadwell/iobp.c b/src/soc/intel/broadwell/iobp.c index ffa61fb..deb4156 100644 --- a/src/soc/intel/broadwell/iobp.c +++ b/src/soc/intel/broadwell/iobp.c @@ -96,7 +96,7 @@ return; } - printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data); + printk(BIOS_SPEW, "IOBP: set 0x%08x to 0x%08x\n", address, data); } void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) diff --git a/src/southbridge/intel/lynxpoint/iobp.c b/src/southbridge/intel/lynxpoint/iobp.c index 3df6940..ad2527f 100644 --- a/src/southbridge/intel/lynxpoint/iobp.c +++ b/src/southbridge/intel/lynxpoint/iobp.c @@ -96,7 +96,7 @@ return; } - printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data); + printk(BIOS_SPEW, "IOBP: set 0x%08x to 0x%08x\n", address, data); } void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) -- To view, visit https://review.coreboot.org/c/coreboot/+/45720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fbb6e409375240544b9b5e810523f9471435f2f Gerrit-Change-Number: 45720 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint/acpi/serialio.asl: Enable DMA channels
by Angel Pons (Code Review) 08 Oct '20

08 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45719 ) Change subject: sb/intel/lynxpoint/acpi/serialio.asl: Enable DMA channels ...................................................................... sb/intel/lynxpoint/acpi/serialio.asl: Enable DMA channels Broadwell does this, so do it on Lynx Point too. Change-Id: I309f0cbf93e3f75b20cdd049d9437841ef61c03a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/serialio.asl 1 file changed, 8 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/45719/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 7acd30d..8956563 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -162,9 +162,8 @@ // DMA channels are only used if Serial IO DMA controller is enabled Name (DBUF, ResourceTemplate () { - // TODO: Need to update IASL to support FixedDMA - //FixedDMA (0x18, 4, Width32Bit, DMA1) // Tx - //FixedDMA (0x19, 5, Width32Bit, DMA2) // Rx + FixedDMA (0x18, 4, Width32Bit, DMA1) // Tx + FixedDMA (0x19, 5, Width32Bit, DMA2) // Rx }) Method (_CRS, 0, NotSerialized) @@ -243,9 +242,8 @@ // DMA channels are only used if Serial IO DMA controller is enabled Name (DBUF, ResourceTemplate () { - // TODO: Need to update IASL to support FixedDMA - //FixedDMA (0x1A, 6, Width32Bit, DMA1) // Tx - //FixedDMA (0x1B, 7, Width32Bit, DMA2) // Rx + FixedDMA (0x1A, 6, Width32Bit, DMA1) // Tx + FixedDMA (0x1B, 7, Width32Bit, DMA2) // Rx }) Method (_CRS, 0, NotSerialized) @@ -358,9 +356,8 @@ // DMA channels are only used if Serial IO DMA controller is enabled Name (DBUF, ResourceTemplate () { - // TODO: Need to update IASL to support FixedDMA - //FixedDMA (0x10, 0, Width32Bit, DMA1) // Tx - //FixedDMA (0x11, 1, Width32Bit, DMA2) // Rx + FixedDMA (0x10, 0, Width32Bit, DMA1) // Tx + FixedDMA (0x11, 1, Width32Bit, DMA2) // Rx }) Method (_CRS, 0, NotSerialized) @@ -408,9 +405,8 @@ // DMA channels are only used if Serial IO DMA controller is enabled Name (DBUF, ResourceTemplate () { - // TODO: Need to update IASL to support FixedDMA - //FixedDMA (0x16, 2, Width32Bit, DMA1) // Tx - //FixedDMA (0x17, 3, Width32Bit, DMA2) // Rx + FixedDMA (0x16, 2, Width32Bit, DMA1) // Tx + FixedDMA (0x17, 3, Width32Bit, DMA2) // Rx }) Method (_CRS, 0, NotSerialized) -- To view, visit https://review.coreboot.org/c/coreboot/+/45719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I309f0cbf93e3f75b20cdd049d9437841ef61c03a Gerrit-Change-Number: 45719 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/intelp2m: Add output files to .gitignore
by Maxim Polyakov (Code Review) 08 Oct '20

08 Oct '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45870 ) Change subject: util/intelp2m: Add output files to .gitignore ...................................................................... util/intelp2m: Add output files to .gitignore Change-Id: I50a783424b0d244eb824db9cd73738108f800003 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M .gitignore 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/45870/1 diff --git a/.gitignore b/.gitignore index 190d3717..2fabfee 100644 --- a/.gitignore +++ b/.gitignore @@ -105,6 +105,8 @@ util/intelmetool/intelmetool util/inteltool/.dependencies util/inteltool/inteltool +util/intelp2m/intelp2m +util/intelp2m/generate/gpio.h util/intelvbttool/intelvbttool util/msrtool/Makefile util/msrtool/Makefile.deps -- To view, visit https://review.coreboot.org/c/coreboot/+/45870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50a783424b0d244eb824db9cd73738108f800003 Gerrit-Change-Number: 45870 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork:Set USB3 typeA port to force gen1 for morphius
by chris wang (Code Review) 08 Oct '20

08 Oct '20

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45334 to review the following change. Change subject: mb/google/zork:Set USB3 typeA port to force gen1 for morphius ...................................................................... mb/google/zork:Set USB3 typeA port to force gen1 for morphius In morphius, the USBA port needs to set to gen1.So set the corresponding setting to usb3 port force gen1 to force USB3 to Gen1. BUG=b:167651308 BRANCH=zork TEST=Build,verify the USB3 speed in gen1 Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I10419b91fe86fe3e06de36ddfe0d1769c1031f8e --- M src/mainboard/google/zork/variants/morphius/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/45334/1 diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index ceacc70..acce883 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -22,6 +22,9 @@ # End : OPN Performance Configuration + # Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1, etc + register "usb3_port_force_gen1" = "0x6" #0110b + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/45334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10419b91fe86fe3e06de36ddfe0d1769c1031f8e Gerrit-Change-Number: 45334 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Add Upd for support force USB3 to Gen1 by port
by chris wang (Code Review) 08 Oct '20

08 Oct '20

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45333 to review the following change. Change subject: soc/amd/picasso: Add Upd for support force USB3 to Gen1 by port ...................................................................... soc/amd/picasso: Add Upd for support force USB3 to Gen1 by port add upd usb3_port_force_gen1 for support USB3 port to gen1 BUG=b:167651308 BRANCH=zork TEST=Build,verify the USB3 speed in gen1 Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff --- M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/45333/1 diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index e3da255..9868220 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -168,7 +168,7 @@ USB_OC_PIN_5 = 0x5, USB_OC_NONE = 0xf, } usb_port_overcurrent_pin[USB_PORT_COUNT]; - + uint32_t usb3_port_force_gen1; /* The array index is the general purpose PCIe clock output number. */ enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; }; diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index b21f237..e36ebd0 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -106,6 +106,7 @@ ASSERT(2 * sizeof(scfg->xhci_oc_pin_select) >= USB_PORT_COUNT); scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1; + scfg->fch_usb_3_port_force_gen1 = cfg->usb3_port_force_gen1; if (cfg->has_usb2_phy_tune_params) { for (i = 0; i < FSPS_UPD_USB2_PORT_COUNT; i++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/45333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Gerrit-Change-Number: 45333 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variant/volteer: Turn I2C3 bus freq closer to 400 k...
by Johnny Li (Code Review) 08 Oct '20

08 Oct '20

Johnny Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43048 ) Change subject: mb/google/volteer/variant/volteer: Turn I2C3 bus freq closer to 400 kHz for camera ...................................................................... mb/google/volteer/variant/volteer: Turn I2C3 bus freq closer to 400 kHz for camera The current I2C3 bus frequency is 341 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C3 to bring the bus frequency closer to 400kHz. BUG=b:153588771 TEST=Verified that I2C3 frequency is 394kHz. Signed-off-by: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Change-Id: Ie3edb04303701460932fb6cd92cc8d8fcf0a4b9b --- M src/mainboard/google/volteer/variants/volteer/overridetree.cb 1 file changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/43048/1 diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 24b869c..3effc6d 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -161,5 +161,49 @@ end end end # PMC + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 153, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" end end -- To view, visit https://review.coreboot.org/c/coreboot/+/43048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3edb04303701460932fb6cd92cc8d8fcf0a4b9b Gerrit-Change-Number: 43048 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020