coreboot-gerrit July 2020

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Change in coreboot[master]: crossgcc: Allow GCC to get asan shadow offset at runtime
by Harshit Sharma (Code Review) 10 Jul '20

10 Jul '20

Harshit Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42794 ) Change subject: crossgcc: Allow GCC to get asan shadow offset at runtime ...................................................................... Patch Set 13: (2 comments) https://review.coreboot.org/c/coreboot/+/42794/11//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42794/11//COMMIT_MSG@15 PS11, Line 15: > Please add more details, why GCC needs to be patched for coreboot, but apparently not for the Linux […] I've added the details in the commit message. Yes it is required in newer GCC versions as well. However, I'll try to convince them to include this change in later versions by initiating a conversation on GCC mailing list. https://review.coreboot.org/c/coreboot/+/42794/11/util/crossgcc/patches/gcc… File util/crossgcc/patches/gcc-8.3.0_asan_shadow_offset_callback.patch: https://review.coreboot.org/c/coreboot/+/42794/11/util/crossgcc/patches/gcc… PS11, Line 1: diff -urN gcc-8.3.0.orig/gcc/asan.c gcc-8.3.0/gcc/asan.c > Please add a patch file created with `git format-patch -1`, which contains a commit message. Now I've created a patch file using git format-patch command. Let me know if it requires any further changes. -- To view, visit https://review.coreboot.org/c/coreboot/+/42794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Gerrit-Change-Number: 42794 Gerrit-PatchSet: 13 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 10 Jul 2020 21:59:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: crossgcc: Allow GCC to get asan shadow offset at runtime
by Harshit Sharma (Code Review) 10 Jul '20

10 Jul '20

Hello build bot (Jenkins), Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42794 to look at the new patch set (#13). Change subject: crossgcc: Allow GCC to get asan shadow offset at runtime ...................................................................... crossgcc: Allow GCC to get asan shadow offset at runtime Unlike Linux kernel which has a static shadow region layout, we have multiple stages in coreboot and thus require a different shadow offset address at each stage. Unfortunately, GCC currently, only supports adding a static shadow offset at compile time using -fasan-shadow-offset flag. For this reason, we enable GCC to determine asan shadow offset address at runtime using a callback function __asan_shadow_offset(). This supersedes the need to specify this address at compile time. GCC then make use of this shadow offset to protect stack buffers and globals by inserting red zones around them. Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Signed-off-by: Harshit Sharma <harshitsharmajs(a)gmail.com> --- A util/crossgcc/patches/gcc-8.3.0_asan_shadow_offset_callback.patch 1 file changed, 97 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/42794/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/42794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Gerrit-Change-Number: 42794 Gerrit-PatchSet: 13 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: crossgcc: Allow GCC to get asan shadow offset at runtime
by Harshit Sharma (Code Review) 10 Jul '20

10 Jul '20

Hello build bot (Jenkins), Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42794 to look at the new patch set (#12). Change subject: crossgcc: Allow GCC to get asan shadow offset at runtime ...................................................................... crossgcc: Allow GCC to get asan shadow offset at runtime Unlike Linux kernel which has a static shadow region layout, we have multiple stages in coreboot and thus require a different shadow offset address at each stage. Unfortunately, GCC currently, only supports adding a static shadow offset at compile time using -fasan-shadow-offset flag. For this reason, we enable GCC to determine asan shadow offset address at runtime using a callback function __asan_shadow_offset(). This supersedes the need to specify this address at compile time. GCC then make use of this shadow offset to protect stack buffers and globals by inserting red zones around them. Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Signed-off-by: Harshit Sharma <harshitsharmajs(a)gmail.com> --- A util/crossgcc/patches/gcc-8.3.0_asan_shadow_offset_callback.patch 1 file changed, 97 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/42794/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/42794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Gerrit-Change-Number: 42794 Gerrit-PatchSet: 12 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/zork: Disable unsupported SOC usb ports
by Rob Barnes (Code Review) 10 Jul '20

10 Jul '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42800 ) Change subject: mb/google/zork: Disable unsupported SOC usb ports ...................................................................... mb/google/zork: Disable unsupported SOC usb ports Disable USB ports that are not supported by the SOC. Handles Dali, Picasso and Pollock. BUG=b:158096224 TEST=Boot Picasso Ezkinil, observe ports disabled Change-Id: Ie37e2ac6a3a26edf77823193e592310eb10b9f9c Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/soc/amd/picasso/chip.c 1 file changed, 30 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/42800/1 diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index c510efe..fb5fb98 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -9,6 +9,7 @@ #include <soc/data_fabric.h> #include <soc/iomap.h> #include <soc/pci_devs.h> +#include <soc/soc_util.h> #include <soc/southbridge.h> #include "chip.h" #include <fsp/api.h> @@ -127,12 +128,40 @@ } } +/** + * Disables USB ports not supported on the SOC variant. + */ +static void disable_unsupported_usb_ports(void) { + struct device *bus_a, *xhci0, *xhci1, *hub, *port; + + bus_a = pcidev_path_on_root(PCI_DEVFN(8, 1)); + xhci0 = pcidev_path_behind(bus_a->link_list, PCI_DEVFN(0,3)); + hub = xhci0->link_list->children; + port = NULL; + while ((port = dev_bus_each_child(hub->link_list, port)) != NULL) { + unsigned int port_id = port->path.usb.port_id; + /* Picasso SOC only has 4 USB ports on XHCI0 */ + if(!soc_is_raven2() && port->enabled && port_id > 3) { + printk(BIOS_INFO,"Disabling XHCI0 USB port %s because it is not supported on this SOC\n", dev_path(port)); + dev_set_enabled(port, 0); + } + } + + xhci1 = pcidev_path_behind(bus_a->link_list, PCI_DEVFN(0,4)); + hub = xhci1->link_list->children; + /* Dali and Pollock do not have USB ports on XHCI1 */ + if(soc_is_raven2() && hub->enabled) { + printk(BIOS_INFO,"Disabling XHCI1 USB hub because it is not supported on this SOC\n"); + disable_children(hub->bus); + } +} + static void soc_init(void *chip_info) { default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables; fsp_silicon_init(acpi_is_wakeup_s3()); - + disable_unsupported_usb_ports(); data_fabric_set_mmio_np(); southbridge_init(chip_info); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie37e2ac6a3a26edf77823193e592310eb10b9f9c Gerrit-Change-Number: 42800 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Select PLATFORM_USES_FSP2_2
by Divya S Sasidharan (Code Review) 10 Jul '20

10 Jul '20

Divya S Sasidharan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41729 ) Change subject: soc/intel/tigerlake: Select PLATFORM_USES_FSP2_2 ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/41729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15252d2db3f8e75d430b84e86cc5141225a3f981 Gerrit-Change-Number: 41729 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Divya S Sasidharan <divya.s.sasidharan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 10 Jul 2020 19:08:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/exception: Print stack on exception
by Raul Rangel (Code Review) 10 Jul '20

10 Jul '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42884 ) Change subject: arch/x86/exception: Print stack on exception ...................................................................... arch/x86/exception: Print stack on exception It's useful to see the stack when an exception happens so you can see the variables on the stack, and also manually recreate the back trace. If you need to recreate the back trace, you will need to add -fno-omit-frame-pointer to the CFLAGS. BUG=b:159081993 TEST=Caused an exception and saw the stack dumped. Then I manually recreated the back trace. 0xcc6fff6c: 0xcc6ce02e <- 0xcc6ce02e is in dev_initialize 0xcc6fff68: 0xcc6fff88 <-- frame 1 0xcc6fff64: 0x00000005 0xcc6fff60: 0x000000dc 0xcc6fff5c: 0x00000000 0xcc6fff58: 0x00000200 0xcc6fff54: 0x00000000 0xcc6fff50: 0x00000400 0xcc6fff4c: 0xcc6d72d4 <- 0xcc6d72d4 is in setup_default_ebdad 0xcc6fff48: 0xcc6fff68 <-ebp 0xcc6fff44: 0x00000005 0xcc6fff40: 0xcc6f571c <-esp Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I3822ea7aa23202ecc98612850402eeb4b1f7b5ef --- M src/arch/x86/exception.c 1 file changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42884/1 diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index 46ba370..3a921c0 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -517,7 +517,18 @@ printk(BIOS_EMERG, "\n%p:\t", code + i); printk(BIOS_EMERG, "%.2x ", code[i]); } - die(""); + + /* Align to 4-byte boundary and up the stack. */ + u32 *ptr = (u32 *)(((uintptr_t)info->esp & ~0x3) + MDUMP_SIZE - 4); + for (i = 0; i < MDUMP_SIZE / sizeof(u32); ++i, --ptr) { + printk(BIOS_EMERG, "\n%p:\t0x%08x", ptr, *ptr); + if ((uintptr_t)ptr == info->ebp) + printk(BIOS_EMERG, " <-ebp"); + else if ((uintptr_t)ptr == info->esp) + printk(BIOS_EMERG, " <-esp"); + } + + die("\n"); #endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/42884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3822ea7aa23202ecc98612850402eeb4b1f7b5ef Gerrit-Change-Number: 42884 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Select PLATFORM_USES_FSP2_2
by Brandon Breitenstein (Code Review) 10 Jul '20

10 Jul '20

Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41729 ) Change subject: soc/intel/tigerlake: Select PLATFORM_USES_FSP2_2 ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/41729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15252d2db3f8e75d430b84e86cc5141225a3f981 Gerrit-Change-Number: 41729 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 10 Jul 2020 19:07:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Avoid NULL pointer dereference
by John Zhao (Code Review) 10 Jul '20

10 Jul '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42837 ) Change subject: soc/amd/picasso: Avoid NULL pointer dereference ...................................................................... soc/amd/picasso: Avoid NULL pointer dereference Coverity detects dereferencing a pointer that might be "NULL" when calling acpigen_write_scope. Add sanity check for scope to prevent NULL pointer dereference. BUG=CID 1429980 TEST=None Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I6214fb83bccb19fe4edad65ce6b862815b8dcec6 --- M src/soc/amd/picasso/root_complex.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/42837/1 diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 4930a0e..807e205 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -134,8 +134,11 @@ static void root_complex_fill_ssdt(const struct device *device) { msr_t msr; + const char *scope = acpi_device_scope(device); + if (!scope) + return; - acpigen_write_scope(acpi_device_scope(device)); + acpigen_write_scope(scope); msr = rdmsr(TOP_MEM); acpigen_write_name_dword("TOM1", msr.lo); -- To view, visit https://review.coreboot.org/c/coreboot/+/42837 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6214fb83bccb19fe4edad65ce6b862815b8dcec6 Gerrit-Change-Number: 42837 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Send OEM IPMI command for CMOS clear on RTC failure
by Jonathan Zhang (Code Review) 10 Jul '20

10 Jul '20

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43005 ) Change subject: mb/ocp/deltalake: Send OEM IPMI command for CMOS clear on RTC failure ...................................................................... Patch Set 13: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/43005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27428c02e99040754e15e07782ec1ad8524def2f Gerrit-Change-Number: 43005 Gerrit-PatchSet: 13 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 10 Jul 2020 16:49:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm: Enable SMM support for Xeon-SP
by Jonathan Zhang (Code Review) 10 Jul '20

10 Jul '20

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41829 ) Change subject: cpu/x86/smm: Enable SMM support for Xeon-SP ...................................................................... Patch Set 8: > Patch Set 8: > > Just wondering if it wouldn't be easier to use some linker script to generate the correct SMRAM layout and then put everything into the SMM rmodule. > > Benefits: > * You would get a build error if you try to use more space than available > * No magic calculations that need to be done, as everything is known at compile time > * Nothin to set up as everything is already in place > > Downside: Bigger SMM rmodule (hopefully compression catches that) This makes sense, there is an existing rmodule type of SMM. -- To view, visit https://review.coreboot.org/c/coreboot/+/41829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78bd74c11ca42fb430f63711b5ec87d4bfe6ca2a Gerrit-Change-Number: 41829 Gerrit-PatchSet: 8 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Eugene Myers <cedarhouse(a)comcast.net> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki.2011(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ron Minnich <rminnich(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 10 Jul 2020 16:32:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit July 2020