coreboot-gerrit July 2020

coreboot-gerrit@coreboot.org

1 participants
3166 discussions

Change in coreboot[master]: mb/google/volteer: remove ripto variant
by Nick Vaccaro (Code Review) 10 Jul '20

10 Jul '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43227 ) Change subject: mb/google/volteer: remove ripto variant ...................................................................... mb/google/volteer: remove ripto variant BUG=b:160711124 TEST="FW_NAME=ripto emerge-volteer coreboot chromeos-bootimage" and verify that the build does not fail. Change-Id: Ic132256a192b8cb77662963bea844f193eb912d9 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name D src/mainboard/google/volteer/variants/ripto/Makefile.inc D src/mainboard/google/volteer/variants/ripto/gpio.c D src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl D src/mainboard/google/volteer/variants/ripto/include/variant/acpi/mipi_camera.asl D src/mainboard/google/volteer/variants/ripto/include/variant/ec.h D src/mainboard/google/volteer/variants/ripto/include/variant/gpio.h D src/mainboard/google/volteer/variants/ripto/memory/Makefile.inc D src/mainboard/google/volteer/variants/ripto/memory/dram_id.generated.txt D src/mainboard/google/volteer/variants/ripto/memory/mem_list_variant.txt D src/mainboard/google/volteer/variants/ripto/overridetree.cb 12 files changed, 0 insertions(+), 581 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/43227/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 0b0e63b..5c6f13c 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -68,7 +68,6 @@ string default "Halvor" if BOARD_GOOGLE_HALVOR default "Malefor" if BOARD_GOOGLE_MALEFOR - default "Ripto" if BOARD_GOOGLE_RIPTO default "Terrador" if BOARD_GOOGLE_TERRADOR default "Trondo" if BOARD_GOOGLE_TRONDO default "Volteer" if BOARD_GOOGLE_VOLTEER @@ -102,7 +101,6 @@ string default "halvor" if BOARD_GOOGLE_HALVOR default "malefor" if BOARD_GOOGLE_MALEFOR - default "ripto" if BOARD_GOOGLE_RIPTO default "terrador" if BOARD_GOOGLE_TERRADOR default "trondo" if BOARD_GOOGLE_TRONDO default "volteer" if BOARD_GOOGLE_VOLTEER diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index cfc4d34..8e6d884 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -10,11 +10,6 @@ select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU -config BOARD_GOOGLE_RIPTO - bool "-> Ripto" - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select VARIANT_HAS_MIPI_CAMERA - config BOARD_GOOGLE_TERRADOR bool "-> Terrador" select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/ripto/Makefile.inc b/src/mainboard/google/volteer/variants/ripto/Makefile.inc deleted file mode 100644 index 13269db..0000000 --- a/src/mainboard/google/volteer/variants/ripto/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -bootblock-y += gpio.c - -ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/ripto/gpio.c b/src/mainboard/google/volteer/variants/ripto/gpio.c deleted file mode 100644 index 9a7ca94..0000000 --- a/src/mainboard/google/volteer/variants/ripto/gpio.c +++ /dev/null @@ -1,454 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <commonlib/helpers.h> - -/* Pad configuration in ramstage */ -/* Leave eSPI pins untouched from default settings */ -static const struct pad_config gpio_table[] = { - /* A0 thru A6 come configured out of reset, do not touch */ - /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ - /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ - /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ - /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ - /* A4 : ESPI_CS# ==> ESPI_CS_L */ - /* A5 : ESPI_CLK ==> ESPI_CLK */ - /* A6 : ESPI_RESET# ==> NC(TP764) */ - /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ - PAD_CFG_GPO(GPP_A7, 1, DEEP), - /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPO(GPP_A8, 1, DEEP), - /* A9 : I2S2_TXD ==> EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_A9, NONE, DEEP), - /* A10 : I2S2_RXD ==> EN_SPKR_PA */ - PAD_CFG_GPO(GPP_A10, 1, DEEP), - /* A11 : PMC_I2C_SDA ==> SSD_PERST_ODL */ - PAD_CFG_GPO(GPP_A11, 1, DEEP), - /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ - PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), - /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ - PAD_CFG_GPO(GPP_A13, 1, DEEP), - /* A14 : USB_OC1# ==> USB_A0_OC_ODL */ - PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), - /* A15 : USB_OC2# ==> USB_A1_OC_ODL */ - PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), - /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ - PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), - /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ - PAD_CFG_GPI(GPP_A17, NONE, DEEP), - /* A18 : DDSP_HPDB ==> HDMI_HPD */ - PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), - /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), - /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_A21, 1, DEEP), - /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ - PAD_CFG_GPO(GPP_A22, 1, DEEP), - /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ - PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), - - /* B0 : CORE_VID0 */ - PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), - /* B1 : CORE_VID1 */ - PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), - /* B2 : VRALERT# ==> VRALERT_L */ - PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), - /* B3 : CPU_GP2 ==> PEN_DET_ODL */ - PAD_CFG_GPI(GPP_B3, NONE, DEEP), - /* B4 : CPU_GP3 ==> NC */ - PAD_NC(GPP_B4, NONE), - /* B5 : ISH_I2C0_CVF_SDA */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), - /* B6 : ISH_I2C0_CVF_SCL */ - PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), - /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), - /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), - /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), - /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ - PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), - /* B11 : PMCALERT# ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), - /* B12 : SLP_S0# ==> SLP_S0_L */ - PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), - /* B13 : PLTRST# ==> PLT_RST_L */ - PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - /* B14 : SPKR ==> GPP_B14_STRAP */ - PAD_NC(GPP_B14, NONE), - /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ - PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), - /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ - PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), - /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ - PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), - /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ - PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), - /* B22 : GSPI1_MOSI ==> PCH_GSPI1_GPMCU_MOSI */ - PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), - /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */ - PAD_NC(GPP_B23, DN_20K), - - /* C0 : SMBCLK ==> EN_PP3300_WLAN */ - PAD_CFG_GPO(GPP_C0, 1, DEEP), - /* C1 : SMBDATA ==> EN_USB_CAM_PWR */ - PAD_CFG_GPO(GPP_C1, 1, DEEP), - /* C2 : SMBALERT# ==> GPP_C2_STRAP */ - PAD_NC(GPP_C2, DN_20K), - /* C3 : SML0CLK ==> USB4_SMB_SCL */ - PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), - /* C4 : SML0DATA ==> USB4_SMB_SDA */ - PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), - /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */ - PAD_NC(GPP_C5, DN_20K), - /* C6 : SML1CLK ==> EC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C6, NONE, PLTRST, LEVEL, INVERT), - /* C7 : SML1DATA ==> EN_USI_CHARGE */ - PAD_CFG_GPO(GPP_C7, 1, DEEP), - /* C8 : UART0_RXD ==> UART_PCH_RX_DEBUG_TX */ - PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), - /* C9 : UART0_TXD ==> UART_PCH_TX_DEBUG_RX */ - PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), - /* C10 : UART0_RTS# ==> USI_RST_L */ - PAD_CFG_GPO(GPP_C10, 1, DEEP), - /* C11 : UART0_CTS# ==> CVF_LPSS_INT_L */ - PAD_CFG_GPI(GPP_C11, NONE, DEEP), - /* C12 : UART1_RXD ==> MEM_STRAP_0 */ - PAD_CFG_GPI(GPP_C12, NONE, DEEP), - /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */ - PAD_CFG_GPO(GPP_C13, 1, DEEP), - /* C14 : UART1_RTS# ==> MEM_STRAP_2 */ - PAD_CFG_GPI(GPP_C14, NONE, DEEP), - /* C15 : UART1_CTS# ==> MEM_STRAP_1 */ - PAD_CFG_GPI(GPP_C15, NONE, DEEP), - /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ - PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), - /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ - PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - /* C20 : UART2_RXD ==> FPMCU_INT_L */ - PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), - /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ - PAD_CFG_GPO(GPP_C22, 0, DEEP), - /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_C23, 1, DEEP), - - /* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ - PAD_NC(GPP_D0, UP_20K), - /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ - PAD_CFG_GPI(GPP_D1, UP_20K, DEEP), - /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ - PAD_CFG_GPI(GPP_D2, UP_20K, DEEP), - /* D3 : ISH_GP3 ==> ISH_ALS_RGB_INT_L */ - PAD_CFG_GPI(GPP_D3, UP_20K, DEEP), - /* D4 : IMGCLKOUT0 ==> CAM_CVF_RST_L */ - PAD_CFG_GPO(GPP_D4, 0, PLTRST), - /* D5 : SRCCLKREQ0$ ==> SSD_CLKREQ_ODL */ - PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), - /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), - /* D7 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), - /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ - PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), - /* D9 : ISH_SPI_CS# ==> PCH_GSPI2_CVF_CS_L */ - PAD_CFG_NF(GPP_D9, NONE, DEEP, NF7), - /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ - PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7), - /* D11 : ISH_SPI_MISO ==> PCH_GSPI2_CVF_MISO */ - PAD_CFG_NF(GPP_D11, NONE, DEEP, NF7), - /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */ - PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), - /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ - PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), - /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ - PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), - /* D15 : ISH_UART0_RTS# ==> MEM_STRAP_3 */ - PAD_CFG_GPI(GPP_D15, NONE, DEEP), - /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ - PAD_CFG_GPO(GPP_D16, 1, DEEP), - /* D17 : ISH_GP4 ==> EN_CVF_PWR */ - PAD_CFG_GPO(GPP_D17, 1, DEEP), - /* D18 : ISH_GP5 ==> CVF_ACE_ISH_INT_L */ - PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1), - /* D19 : I2S_MCLK1 ==> I2S_MCLK1 */ - PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), - - /* E0 : SATAXPCIE0 ==> USB_A1_RT_RST_ODL */ - PAD_CFG_GPO(GPP_E0, 1, DEEP), - /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), - /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ - PAD_CFG_GPI(GPP_E2, NONE, DEEP), - /* E3 : CPU_GP0 ==> USI_REPORT_EN */ - PAD_CFG_GPO(GPP_E3, 1, DEEP), - /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ - PAD_NC(GPP_E4, NONE), - /* E5 : SATA_DEVSLP1 ==> M2_SSD_DEVSLP_OD */ - PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), - /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ - PAD_NC(GPP_E6, NONE), - /* E7 : CPU_GP1 ==> USI_INT */ - PAD_CFG_GPI(GPP_E7, NONE, DEEP), - /* E8 : SPI1_CS1# ==> SLP_S0IX */ - PAD_CFG_GPO(GPP_E8, 0, DEEP), - /* E9 : USB2_OC0# ==> USB_C1_OC_ODL */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - /* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */ - PAD_CFG_GPO(GPP_E10, 0, DEEP), - /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ - PAD_CFG_GPI(GPP_E11, NONE, DEEP), - /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_E12, 1, DEEP), - /* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */ - PAD_CFG_GPO(GPP_E13, 0, DEEP), - /* E14 : DDPC_HPDA ==> SOC_EDP_HPD */ - PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), - /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_E15, NONE, PLTRST, LEVEL, INVERT), - /* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */ - PAD_CFG_GPI(GPP_E16, NONE, DEEP), - /* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */ - PAD_CFG_TERM_GPO(GPP_E17, 1, DN_20K, DEEP), - /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */ - PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), - /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ - PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4), - /* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_SOC_TX */ - PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), - /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */ - PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), - /* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC: Retimer FW drives this pin */ - PAD_NC(GPP_E22, NONE), - /* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC: Retimer FW drives this pin */ - PAD_NC(GPP_E23, NONE), - - /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ - PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), - /* F1 : CNV_BRI_RSP ==> NCV_BRI_RSP */ - PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), - /* F2 : I2S2_TXD ==> CNV_RGI_DT_STRAP */ - PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), - /* F3 : I2S2_RXD ==> CNV_RGI_RSP */ - PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), - /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */ - PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), - /* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */ - PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), - /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */ - PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), - /* F7 : GPPF7_STRAP */ - PAD_NC(GPP_F7, DN_20K), - /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ - PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), - /* F9 : Reserved ==> NC */ - /* F10 : GPPF10_STRAP */ - PAD_NC(GPP_F10, DN_20K), - /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ - PAD_CFG_GPO(GPP_F11, 1, DEEP), - /* F12 : GSXDOUT ==> WWAN_RST_ODL */ - PAD_CFG_GPO(GPP_F12, 1, DEEP), - /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ - PAD_CFG_GPO(GPP_F13, 1, DEEP), - /* F14 : GSXDIN ==> SAR0_INT_L */ - PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE), - /* F15 : GSXSRESET# ==> SAR1_INT_L */ - PAD_CFG_GPI_SCI_LOW(GPP_F15, NONE, PLTRST, EDGE_SINGLE), - /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ - PAD_CFG_GPO(GPP_F16, 1, DEEP), - /* F17 : WWAN_RF_DISABLE_ODL */ - PAD_CFG_GPO(GPP_F17, 1, DEEP), - /* F18 : THC1_SPI2_INT# ==> WWAN_PCIE_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE), - /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ - PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), - /* F20 : EXT_PWR_GATE# ==> EXT_PWR_GATE_L */ - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - /* F21 : EXT_PWR_GATE2# ==> EXT_PWR_GATE2_L */ - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - /* F22 : VNN_CTRL */ - PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), - /* F23 : V1P05_CTRL */ - PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), - - /* H0 : GPPH0_BOOT_STRAP1 */ - PAD_NC(GPP_H0, DN_20K), - /* H1 : GPPH1_BOOT_STRAP2 */ - PAD_NC(GPP_H1, DN_20K), - /* H2 : GPPH2_BOOT_STRAP3 */ - PAD_NC(GPP_H2, DN_20K), - /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ - PAD_CFG_GPO(GPP_H3, 1, DEEP), - /* H4 : I2C2_SDA ==> PCH_I2C2_SAR0_WLAN_HDMI_SDA */ - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* H5 : I2C2_SCL ==> PCH_I2C2_SAR0_WLAN_HDMI_SCL */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* H6 : I2C3_SDA ==> PCH_I2C3_CAM_SAR1_SDA */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - /* H7 : I2C3_SCL ==> PCH_I2C3_CAM_SAR1_SCL */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), - /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ - PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), - /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ - PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), - /* H10 : SRCCLKREQ4# ==> USB_C1_RT_FORCE_PWR */ - PAD_CFG_GPO(GPP_H10, 1, DEEP), - /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ - PAD_CFG_GPO(GPP_H11, 1, DEEP), - /* H12 : M2_SKT2_CFG0 ==> WWAN_CONFIG0 */ - PAD_CFG_GPI(GPP_H12, NONE, DEEP), - /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */ - PAD_CFG_GPI(GPP_H13, NONE, DEEP), - /* H14 : M2_SKT2_CFG2 # ==> WWAN_CONFIG2 */ - PAD_CFG_GPI(GPP_H14, NONE, DEEP), - /* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */ - PAD_CFG_GPI(GPP_H15, NONE, DEEP), - /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ - PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), - /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ - PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), - /* H18 : CPU_C10_GATE# ==> CPU_C10_GATE_L */ - PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), - /* H19 : TIME_SYNC0 ==> PCH_CAM_VSYNC */ - PAD_CFG_GPI(GPP_H19, NONE, DEEP), - /* H20 : IMGCLKOUT1 ==> EN_MIPI_CAM_PWR */ - PAD_CFG_GPO(GPP_H20, 0, PLTRST), - /* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */ - PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), - /* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */ - PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), - /* H23 : IMGCLKOUT4 ==> WWAN_ESIM_SEL_ODL */ - PAD_CFG_GPO(GPP_H23, 1, DEEP), - - /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ - PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), - /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ - PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), - /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ - PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), - /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ - PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), - /* R4 : HDA_RST# ==> HDA_RST_L */ - PAD_CFG_NF(GPP_R4, DN_20K, DEEP, NF1), - /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ - PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), - /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), - /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), - - /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ - PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), - /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ - PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), - /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), - /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), - /* S4 : SNDW2_CLK ==> DMIC_CLK1 */ - PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), - /* S5 : SNDW2_DATA ==> DMIC_DATA1 */ - PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), - /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ - PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), - /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ - PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), - - /* GPD0: BATLOW# ==> BATLOW_L */ - PAD_CFG_NF(GPD0, NONE, DEEP, NF1), - /* GPD1: ACPRESENT ==> PCH_ACPRESENT */ - PAD_CFG_NF(GPD1, NONE, DEEP, NF1), - /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */ - PAD_CFG_NF(GPD2, NONE, DEEP, NF1), - /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */ - PAD_CFG_NF(GPD3, NONE, DEEP, NF1), - /* GPD4: SLP_S3# ==> SLP_S3_L */ - PAD_CFG_NF(GPD4, NONE, DEEP, NF1), - /* GPD5: SLP_S4# ==> SLP_S4_L */ - PAD_CFG_NF(GPD5, NONE, DEEP, NF1), - /* GPD6: SLP_A# ==> SLP_A_L */ - PAD_CFG_NF(GPD6, NONE, DEEP, NF1), - /* GPD7: GPD7_STRAP */ - PAD_CFG_GPI(GPD7, DN_20K, DEEP), - /* GPD8: SUSCLK ==> PCH_SUSCLK */ - PAD_CFG_NF(GPD8, NONE, DEEP, NF1), - /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ - PAD_CFG_NF(GPD9, NONE, DEEP, NF1), - /* GPD10: SLP_S5# ==> SLP_S5_L */ - PAD_CFG_NF(GPD10, NONE, DEEP, NF1), - /* GPD11: LANPHYC ==> NC */ -}; - -const struct pad_config *variant_base_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ - PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), - - /* B11 : PMCALERT# ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), - - /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - - /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - - /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - - /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ - PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), - - /* C0 : SMBCLK ==> EN_PP3300_WLAN */ - PAD_CFG_GPO(GPP_C0, 1, DEEP), - - /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - - /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ - PAD_CFG_GPO(GPP_C22, 0, DEEP), - - /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_E12, 1, DEEP), - - /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ - PAD_CFG_GPO(GPP_H11, 1, RSMRST), -}; - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), -}; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} diff --git a/src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl deleted file mode 100644 index 189cafe..0000000 --- a/src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/volteer/variants/ripto/include/variant/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/ripto/include/variant/acpi/mipi_camera.asl deleted file mode 100644 index 418f2e0..0000000 --- a/src/mainboard/google/volteer/variants/ripto/include/variant/acpi/mipi_camera.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/acpi/mipi_camera.asl> diff --git a/src/mainboard/google/volteer/variants/ripto/include/variant/ec.h b/src/mainboard/google/volteer/variants/ripto/include/variant/ec.h deleted file mode 100644 index 4a9a461..0000000 --- a/src/mainboard/google/volteer/variants/ripto/include/variant/ec.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __VARIANT_EC_H__ -#define __VARIANT_EC_H__ - -#include <baseboard/ec.h> - -#endif diff --git a/src/mainboard/google/volteer/variants/ripto/include/variant/gpio.h b/src/mainboard/google/volteer/variants/ripto/include/variant/gpio.h deleted file mode 100644 index 32dd17a..0000000 --- a/src/mainboard/google/volteer/variants/ripto/include/variant/gpio.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <baseboard/gpio.h> - -/* Memory configuration board straps */ -/* Copied from baseboard and may need to change for the new variant. */ -#define GPIO_MEM_CONFIG_0 GPP_C12 -#define GPIO_MEM_CONFIG_1 GPP_C15 -#define GPIO_MEM_CONFIG_2 GPP_C14 -#define GPIO_MEM_CONFIG_3 GPP_D15 - -#endif diff --git a/src/mainboard/google/volteer/variants/ripto/memory/Makefile.inc b/src/mainboard/google/volteer/variants/ripto/memory/Makefile.inc deleted file mode 100644 index 4c95819..0000000 --- a/src/mainboard/google/volteer/variants/ripto/memory/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later -## This is an auto-generated file. Do not edit!! - -SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL diff --git a/src/mainboard/google/volteer/variants/ripto/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/ripto/memory/dram_id.generated.txt deleted file mode 100644 index 9bf0bd9..0000000 --- a/src/mainboard/google/volteer/variants/ripto/memory/dram_id.generated.txt +++ /dev/null @@ -1,2 +0,0 @@ -DRAM Part Name ID to assign -K4U6E3S4AA-MGCL 0 (0000) diff --git a/src/mainboard/google/volteer/variants/ripto/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/ripto/memory/mem_list_variant.txt deleted file mode 100644 index a226d2f..0000000 --- a/src/mainboard/google/volteer/variants/ripto/memory/mem_list_variant.txt +++ /dev/null @@ -1 +0,0 @@ -K4U6E3S4AA-MGCL diff --git a/src/mainboard/google/volteer/variants/ripto/overridetree.cb b/src/mainboard/google/volteer/variants/ripto/overridetree.cb deleted file mode 100644 index f583cdd..0000000 --- a/src/mainboard/google/volteer/variants/ripto/overridetree.cb +++ /dev/null @@ -1,78 +0,0 @@ -chip soc/intel/tigerlake - - # NVMe warm reboot workaround - # Limit L1.1 (value:2) for RP9, RP11 - register "PcieRpL1Substates[8]" = "2" - register "PcieRpL1Substates[10]" = "2" - - device domain 0 on - device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Headset Codec"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_count" = "1" - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on - probe AUDIO MAX98357_ALC5682I_I2S - probe AUDIO MAX98373_ALC5682I_I2S - end - end - chip drivers/i2c/max98373 - register "vmon_slot_no" = "0" - register "imon_slot_no" = "1" - register "uid" = "0" - register "desc" = ""Right Speaker Amp"" - register "name" = ""MAXR"" - device i2c 31 on - probe AUDIO MAX98373_ALC5682I_I2S - end - end - chip drivers/i2c/max98373 - register "vmon_slot_no" = "2" - register "imon_slot_no" = "3" - register "uid" = "1" - register "desc" = ""Left Speaker Amp"" - register "name" = ""MAXL"" - device i2c 32 on - probe AUDIO MAX98373_ALC5682I_I2S - end - end - end - device pci 1f.3 on - chip drivers/generic/max98357a - register "hid" = ""MX98357A"" - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" - register "sdmode_delay" = "5" - device generic 0 on - probe AUDIO MAX98357_ALC5682I_I2S - end - end - chip drivers/intel/soundwire - device generic 0 on - probe AUDIO MAX98373_ALC5682_SNDW - chip drivers/soundwire/alc5682 - # SoundWire Link 0 ID 1 - register "desc" = ""Headset Codec"" - device generic 0.1 on end - end - chip drivers/soundwire/max98373 - # SoundWire Link 1 ID 3 - register "desc" = ""Left Speaker Amp"" - device generic 1.3 on end - end - chip drivers/soundwire/max98373 - # SoundWire Link 1 ID 7 - register "desc" = ""Right Speaker Amp"" - device generic 1.7 on end - end - end - end - end - end - -end -- To view, visit https://review.coreboot.org/c/coreboot/+/43227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic132256a192b8cb77662963bea844f193eb912d9 Gerrit-Change-Number: 43227 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: soc/amd/picasso: Add PCI driver for data fabric devices
by Furquan Shaikh (Code Review) 10 Jul '20

10 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43314 ) Change subject: soc/amd/picasso: Add PCI driver for data fabric devices ...................................................................... soc/amd/picasso: Add PCI driver for data fabric devices Data fabric devices are PCI devices which support PCI configuration space but do not require any MMIO/IO resources. This change adds a PCI driver for the data fabric devices which only provides device operations for adding node to SSDT and returning the ACPI name for the device. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I3da9287db5febf1a1d7eb1dfbed9f1348f80a588 --- M src/soc/amd/picasso/Makefile.inc R src/soc/amd/picasso/data_fabric.c 2 files changed, 54 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/43314/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index b6c0ddb..d19402f 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -52,7 +52,7 @@ ramstage-y += i2c.c ramstage-y += chip.c ramstage-y += cpu.c -ramstage-y += data_fabric_util.c +ramstage-y += data_fabric.c ramstage-y += root_complex.c ramstage-y += mca.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c diff --git a/src/soc/amd/picasso/data_fabric_util.c b/src/soc/amd/picasso/data_fabric.c similarity index 73% rename from src/soc/amd/picasso/data_fabric_util.c rename to src/soc/amd/picasso/data_fabric.c index a375b84..d044667 100644 --- a/src/soc/amd/picasso/data_fabric_util.c +++ b/src/soc/amd/picasso/data_fabric.c @@ -1,7 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_device.h> #include <console/console.h> #include <cpu/x86/lapic_def.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> #include <device/pci_ops.h> #include <soc/data_fabric.h> #include <soc/iomap.h> @@ -115,3 +119,52 @@ (IOMS0_FABRIC_ID << MMIO_DST_FABRIC_ID_SHIFT) | MMIO_NP | MMIO_WE | MMIO_RE); } + +static const char *data_fabric_acpi_name(const struct device *dev) +{ + switch (dev->device) { + case PCI_DEVICE_ID_AMD_FAM17H_DF0: + return "DFD0"; + case PCI_DEVICE_ID_AMD_FAM17H_DF1: + return "DFD1"; + case PCI_DEVICE_ID_AMD_FAM17H_DF2: + return "DFD2"; + case PCI_DEVICE_ID_AMD_FAM17H_DF3: + return "DFD3"; + case PCI_DEVICE_ID_AMD_FAM17H_DF4: + return "DFD4"; + case PCI_DEVICE_ID_AMD_FAM17H_DF5: + return "DFD5"; + case PCI_DEVICE_ID_AMD_FAM17H_DF6: + return "DFD6"; + default: + printk(BIOS_ERR, "%s: Unhandled device id 0x%x\n", __func__, + dev->device); + } + + return NULL; +} + +static struct device_operations data_fabric_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = data_fabric_acpi_name, + .acpi_fill_ssdt = acpi_device_write_pci_dev, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_AMD_FAM17H_DF0, + PCI_DEVICE_ID_AMD_FAM17H_DF1, + PCI_DEVICE_ID_AMD_FAM17H_DF2, + PCI_DEVICE_ID_AMD_FAM17H_DF3, + PCI_DEVICE_ID_AMD_FAM17H_DF4, + PCI_DEVICE_ID_AMD_FAM17H_DF5, + PCI_DEVICE_ID_AMD_FAM17H_DF6, + 0 +}; + +static const struct pci_driver data_fabric_driver __pci_driver = { + .ops = &data_fabric_ops, + .vendor = PCI_VENDOR_ID_AMD, + .devices = pci_device_ids, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/43314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3da9287db5febf1a1d7eb1dfbed9f1348f80a588 Gerrit-Change-Number: 43314 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: soc/amd/picasso: Add driver for handling PCIE GPP bridges
by Furquan Shaikh (Code Review) 10 Jul '20

10 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43312 ) Change subject: soc/amd/picasso: Add driver for handling PCIE GPP bridges ...................................................................... soc/amd/picasso: Add driver for handling PCIE GPP bridges This change adds a driver pcie_gpp.c which provides device_operations for external and internal PCIe GPP bridges. These device operations include standard PCI bridge operations as well as operations for generating ACPI node for the device and returning appropriate ACPI name for it. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I9f8809c2735bdc09435deda91a570c89e71e8062 --- M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/chip.c A src/soc/amd/picasso/pcie_gpp.c 3 files changed, 61 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/43312/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 593d17b..b6c0ddb 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -78,6 +78,7 @@ ramstage-y += config.c ramstage-y += update_microcode.c ramstage-y += graphics.c +ramstage-y += pcie_gpp.c smm-y += smihandler.c smm-y += smi_util.c diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 2e5fae5..7d56323 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -56,24 +56,6 @@ return "GNB"; case IOMMU_DEVFN: return "IOMM"; - case PCIE_GPP_0_DEVFN: - return "PBR0"; - case PCIE_GPP_1_DEVFN: - return "PBR1"; - case PCIE_GPP_2_DEVFN: - return "PBR2"; - case PCIE_GPP_3_DEVFN: - return "PBR3"; - case PCIE_GPP_4_DEVFN: - return "PBR4"; - case PCIE_GPP_5_DEVFN: - return "PBR5"; - case PCIE_GPP_6_DEVFN: - return "PBR6"; - case PCIE_GPP_A_DEVFN: - return "PBRA"; - case PCIE_GPP_B_DEVFN: - return "PBRB"; case LPC_DEVFN: return "LPCB"; case SMBUS_DEVFN: @@ -111,15 +93,6 @@ .acpi_name = soc_acpi_name, }; -static struct device_operations pci_ops_ops_bus_ab = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .acpi_fill_ssdt = acpi_device_write_pci_dev, -}; - static void set_mmio_dev_ops(struct device *dev) { switch (dev->path.mmio.addr) { @@ -144,15 +117,6 @@ dev->ops = &pci_domain_ops; } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; - } else if (dev->path.type == DEVICE_PATH_PCI) { - if (dev->bus->dev->path.type == DEVICE_PATH_DOMAIN) { - switch (dev->path.pci.devfn) { - case PCIE_GPP_A_DEVFN: - case PCIE_GPP_B_DEVFN: - dev->ops = &pci_ops_ops_bus_ab; - } - } - sb_enable(dev); } else if (dev->path.type == DEVICE_PATH_MMIO) { set_mmio_dev_ops(dev); } diff --git a/src/soc/amd/picasso/pcie_gpp.c b/src/soc/amd/picasso/pcie_gpp.c new file mode 100644 index 0000000..651855a --- /dev/null +++ b/src/soc/amd/picasso/pcie_gpp.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/pci_devs.h> +#include <stdio.h> + +static const char *pcie_gpp_acpi_name(const struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + case PCIE_GPP_0_DEVFN: + return "PBR0"; + case PCIE_GPP_1_DEVFN: + return "PBR1"; + case PCIE_GPP_2_DEVFN: + return "PBR2"; + case PCIE_GPP_3_DEVFN: + return "PBR3"; + case PCIE_GPP_4_DEVFN: + return "PBR4"; + case PCIE_GPP_5_DEVFN: + return "PBR5"; + case PCIE_GPP_6_DEVFN: + return "PBR6"; + case PCIE_GPP_A_DEVFN: + return "PBRA"; + case PCIE_GPP_B_DEVFN: + return "PBRB"; + } + + return NULL; +} + +static struct device_operations pcie_gpp_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .acpi_name = pcie_gpp_acpi_name, + .acpi_fill_ssdt = acpi_device_write_pci_dev, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP, + PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSA, + PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSB, + 0 +}; + +static const struct pci_driver sata0_driver __pci_driver = { + .ops = &pcie_gpp_ops, + .vendor = PCI_VENDOR_ID_AMD, + .devices = pci_device_ids, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/43312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f8809c2735bdc09435deda91a570c89e71e8062 Gerrit-Change-Number: 43312 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: mb/google/zork: enable i2c devices in verstage
by Martin Roth (Code Review) 10 Jul '20

10 Jul '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43334 ) Change subject: mb/google/zork: enable i2c devices in verstage ...................................................................... mb/google/zork: enable i2c devices in verstage Zork devices shut down the i2c controllers in S3 to save power. On resume, they need to be enabled in verstage before being accessed or the system hangs. BUG=b:160834101 TEST=Resume works with psp_verstage. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I7b8c7e12847876dab4ca74d67d3c41e63d7727cf --- M src/mainboard/google/zork/verstage.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/43334/1 diff --git a/src/mainboard/google/zork/verstage.c b/src/mainboard/google/zork/verstage.c index 8401196..bcbf396 100644 --- a/src/mainboard/google/zork/verstage.c +++ b/src/mainboard/google/zork/verstage.c @@ -31,5 +31,6 @@ void verstage_mainboard_init(void) { + enable_aoac_devices(); setup_i2c(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/43334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b8c7e12847876dab4ca74d67d3c41e63d7727cf Gerrit-Change-Number: 43334 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/amd/picasso: Map AOAC registers to enable i2c after S3
by Martin Roth (Code Review) 10 Jul '20

10 Jul '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43333 ) Change subject: soc/amd/picasso: Map AOAC registers to enable i2c after S3 ...................................................................... soc/amd/picasso: Map AOAC registers to enable i2c after S3 When entering S3, zork shuts down the i2c controllers to save power. On resume, we need to re-enable i2c before accessing them, so we need to map the AOAC registers in verstage. BUG=b:160834101 TEST=psp_verstage works after resume. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Ia8aa4923898a50f2202b6ca8434cee61a5918e91 --- M src/soc/amd/picasso/psp_verstage/fch.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43333/1 diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c index 9059c9e..e01a684 100644 --- a/src/soc/amd/picasso/psp_verstage/fch.c +++ b/src/soc/amd/picasso/psp_verstage/fch.c @@ -63,6 +63,11 @@ write8((void *)(io_bar + reg), value); } +static void aoac_set_bar(void *bar) +{ + acpimmio_aoac = bar; +} + static struct { const char *name; struct { @@ -79,6 +84,7 @@ {"eSPI", {FCH_IO_DEVICE_ESPI}, espi_set_bar}, {"I2C2", {FCH_IO_DEVICE_I2C, 2}, i2c2_set_bar}, {"I2C3", {FCH_IO_DEVICE_I2C, 3}, i2c3_set_bar}, + {"AOAC", {FCH_IO_DEVICE_AOAC}, aoac_set_bar}, }; uintptr_t *map_spi_rom(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/43333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8aa4923898a50f2202b6ca8434cee61a5918e91 Gerrit-Change-Number: 43333 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: Revert "mb/google/zork: Enable psp_verstage"
by Raul Rangel (Code Review) 10 Jul '20

10 Jul '20

Hello build bot (Jenkins), Martin Roth, Furquan Shaikh, Julius Werner, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43066 to review the following change. Change subject: Revert "mb/google/zork: Enable psp_verstage" ...................................................................... Revert "mb/google/zork: Enable psp_verstage" This reverts commit c35d4fa377fdf1a967ed426024d3886302d2081f. Reason for revert: Breaks S3 resume on trembyle. Change-Id: Ic086c60d8e6edc9c0dff65e2569999a314c7c4ba --- M src/mainboard/google/zork/Kconfig 1 file changed, 2 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/43066/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index a6c866d..19225d7 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -100,6 +100,8 @@ config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE config VBOOT_VBNV_OFFSET hex @@ -121,22 +123,6 @@ hex default 0x50 -config PICASSO_FW_A_POSITION - hex - default 0xFF031040 - depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK - help - Location of the AMD firmware in the RW_A region. This is the - start of the RW-A region + 64 bytes for the cbfs header. - -config PICASSO_FW_B_POSITION - hex - default 0xFF3CF040 - depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK - help - Location of the AMD firmware in the RW_B region. This is the - start of the RW-A region + 64 bytes for the cbfs header. - config VARIANT_HAS_FW_CONFIG bool help @@ -165,20 +151,4 @@ default 2 if BOARD_GOOGLE_VILBOZ default VARIANT_MIN_BOARD_ID_V3_SCHEMATICS -config VBOOT_STARTS_BEFORE_BOOTBLOCK - bool "PSP verstage" - default y if VBOOT - help - Firmware verification happens before the main processor is brought - online. - -config VBOOT_STARTS_IN_BOOTBLOCK - bool "X86 verstage (in bootblock)" - depends on VBOOT && ! VBOOT_STARTS_BEFORE_BOOTBLOCK - select VBOOT_SEPARATE_VERSTAGE - help - Firmware verification happens during the end of or right after the - bootblock. This implies that a static VBOOT2_WORK() buffer must be - allocated in memlayout. - endif # BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ -- To view, visit https://review.coreboot.org/c/coreboot/+/43066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic086c60d8e6edc9c0dff65e2569999a314c7c4ba Gerrit-Change-Number: 43066 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: nb/sandybridge: Remove unused <model_206ax.h>
by HAOUAS Elyes (Code Review) 10 Jul '20

10 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42351 ) Change subject: nb/sandybridge: Remove unused <model_206ax.h> ...................................................................... nb/sandybridge: Remove unused <model_206ax.h> Change-Id: I05a0a968f39e88aa8e05c8124f6390a943429840 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/sandybridge/sandybridge.h 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42351/1 diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 1652b09..43d460b 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -36,7 +36,6 @@ /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ -#include <cpu/intel/model_206ax/model_206ax.h> /* Chipset types */ enum platform_type { -- To view, visit https://review.coreboot.org/c/coreboot/+/42351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05a0a968f39e88aa8e05c8124f6390a943429840 Gerrit-Change-Number: 42351 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 4

Change in coreboot[master]: AMD mainboards: Drop commented-out include
by Angel Pons (Code Review) 10 Jul '20

10 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43271 ) Change subject: AMD mainboards: Drop commented-out include ...................................................................... AMD mainboards: Drop commented-out include This code is not even being build-tested. Drop it before it grows moss. Change-Id: I6f71419ea23b973b0bedb426e20cb3dc460ef68d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/amd/gardenia/dsdt.asl M src/mainboard/amd/inagua/dsdt.asl M src/mainboard/amd/mandolin/dsdt.asl M src/mainboard/amd/olivehill/dsdt.asl M src/mainboard/amd/padmelon/dsdt.asl M src/mainboard/amd/parmer/dsdt.asl M src/mainboard/amd/persimmon/dsdt.asl M src/mainboard/amd/south_station/dsdt.asl M src/mainboard/amd/thatcher/dsdt.asl M src/mainboard/amd/union_station/dsdt.asl M src/mainboard/asrock/e350m1/dsdt.asl M src/mainboard/asrock/imb-a180/dsdt.asl M src/mainboard/asus/am1i-a/dsdt.asl M src/mainboard/asus/f2a85-m/dsdt.asl M src/mainboard/bap/ode_e20XX/dsdt.asl M src/mainboard/biostar/a68n_5200/dsdt.asl M src/mainboard/biostar/am1ml/dsdt.asl M src/mainboard/elmex/pcm205400/dsdt.asl M src/mainboard/gizmosphere/gizmo/dsdt.asl M src/mainboard/gizmosphere/gizmo2/dsdt.asl M src/mainboard/google/kahlee/dsdt.asl M src/mainboard/google/zork/dsdt.asl M src/mainboard/hp/abm/dsdt.asl M src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl M src/mainboard/jetway/nf81-t56n-lf/dsdt.asl M src/mainboard/lenovo/g505s/dsdt.asl M src/mainboard/pcengines/apu1/dsdt.asl M src/mainboard/pcengines/apu2/dsdt.asl 28 files changed, 0 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/43271/1 diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl index 8e449b3..a2de635 100644 --- a/src/mainboard/amd/gardenia/dsdt.asl +++ b/src/mainboard/amd/gardenia/dsdt.asl @@ -13,7 +13,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* as needed */ /* global NVS and variables */ #include <globalnvs.asl> diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index a4214a4..a395d24 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/amd/mandolin/dsdt.asl b/src/mainboard/amd/mandolin/dsdt.asl index 4d5d743..244e02b 100644 --- a/src/mainboard/amd/mandolin/dsdt.asl +++ b/src/mainboard/amd/mandolin/dsdt.asl @@ -13,7 +13,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* as needed */ /* global NVS and variables */ #include <globalnvs.asl> diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl index ac06651..24b54c9 100644 --- a/src/mainboard/amd/olivehill/dsdt.asl +++ b/src/mainboard/amd/olivehill/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Globals for the platform */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl index ef97a22..716c791 100644 --- a/src/mainboard/amd/padmelon/dsdt.asl +++ b/src/mainboard/amd/padmelon/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* as needed */ /* global NVS and variables */ #include <globalnvs.asl> diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl index 16aef97..b04567a 100644 --- a/src/mainboard/amd/parmer/dsdt.asl +++ b/src/mainboard/amd/parmer/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Globals for the platform */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index a4214a4..a395d24 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index a4214a4..a395d24 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl index 16aef97..b04567a 100644 --- a/src/mainboard/amd/thatcher/dsdt.asl +++ b/src/mainboard/amd/thatcher/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Globals for the platform */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index a4214a4..a395d24 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index d1d730f..d1896ad 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/asrock/imb-a180/dsdt.asl b/src/mainboard/asrock/imb-a180/dsdt.asl index ac06651..24b54c9 100644 --- a/src/mainboard/asrock/imb-a180/dsdt.asl +++ b/src/mainboard/asrock/imb-a180/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Globals for the platform */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/asus/am1i-a/dsdt.asl b/src/mainboard/asus/am1i-a/dsdt.asl index 4000d61..13e97dc 100644 --- a/src/mainboard/asus/am1i-a/dsdt.asl +++ b/src/mainboard/asus/am1i-a/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Globals for the platform */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl index 6234a00..634a928 100644 --- a/src/mainboard/asus/f2a85-m/dsdt.asl +++ b/src/mainboard/asus/f2a85-m/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Globals for the platform */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/bap/ode_e20XX/dsdt.asl b/src/mainboard/bap/ode_e20XX/dsdt.asl index ac06651..24b54c9 100644 --- a/src/mainboard/bap/ode_e20XX/dsdt.asl +++ b/src/mainboard/bap/ode_e20XX/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Globals for the platform */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/biostar/a68n_5200/dsdt.asl b/src/mainboard/biostar/a68n_5200/dsdt.asl index ac06651..24b54c9 100644 --- a/src/mainboard/biostar/a68n_5200/dsdt.asl +++ b/src/mainboard/biostar/a68n_5200/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Globals for the platform */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/biostar/am1ml/dsdt.asl b/src/mainboard/biostar/am1ml/dsdt.asl index a6c850a..01502b2 100644 --- a/src/mainboard/biostar/am1ml/dsdt.asl +++ b/src/mainboard/biostar/am1ml/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Globals for the platform */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/elmex/pcm205400/dsdt.asl b/src/mainboard/elmex/pcm205400/dsdt.asl index a4214a4..a395d24 100644 --- a/src/mainboard/elmex/pcm205400/dsdt.asl +++ b/src/mainboard/elmex/pcm205400/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/gizmosphere/gizmo/dsdt.asl b/src/mainboard/gizmosphere/gizmo/dsdt.asl index 4fe88e3..ef08555 100644 --- a/src/mainboard/gizmosphere/gizmo/dsdt.asl +++ b/src/mainboard/gizmosphere/gizmo/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/gizmosphere/gizmo2/dsdt.asl b/src/mainboard/gizmosphere/gizmo2/dsdt.asl index ac06651..24b54c9 100644 --- a/src/mainboard/gizmosphere/gizmo2/dsdt.asl +++ b/src/mainboard/gizmosphere/gizmo2/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Globals for the platform */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl index 19d620e..ebee0f7 100644 --- a/src/mainboard/google/kahlee/dsdt.asl +++ b/src/mainboard/google/kahlee/dsdt.asl @@ -13,7 +13,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* as needed */ /* global NVS and variables */ #include <globalnvs.asl> diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl index 8b42102..d256f66 100644 --- a/src/mainboard/google/zork/dsdt.asl +++ b/src/mainboard/google/zork/dsdt.asl @@ -14,7 +14,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* as needed */ /* global NVS and variables */ #include <globalnvs.asl> diff --git a/src/mainboard/hp/abm/dsdt.asl b/src/mainboard/hp/abm/dsdt.asl index ac06651..24b54c9 100644 --- a/src/mainboard/hp/abm/dsdt.asl +++ b/src/mainboard/hp/abm/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Globals for the platform */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl index d365c00..4cd6a31 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl @@ -13,7 +13,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Globals for the platform */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl index f05c164..69553cb 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/lenovo/g505s/dsdt.asl b/src/mainboard/lenovo/g505s/dsdt.asl index fdb3e73..fde51d9 100644 --- a/src/mainboard/lenovo/g505s/dsdt.asl +++ b/src/mainboard/lenovo/g505s/dsdt.asl @@ -13,7 +13,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Globals for the platform */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/pcengines/apu1/dsdt.asl b/src/mainboard/pcengines/apu1/dsdt.asl index 6c62c65..592c6ba 100644 --- a/src/mainboard/pcengines/apu1/dsdt.asl +++ b/src/mainboard/pcengines/apu1/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl index e6543b9..7e106c2 100644 --- a/src/mainboard/pcengines/apu2/dsdt.asl +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Globals for the platform */ #include "acpi/mainboard.asl" -- To view, visit https://review.coreboot.org/c/coreboot/+/43271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f71419ea23b973b0bedb426e20cb3dc460ef68d Gerrit-Change-Number: 43271 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: src/cpu/intel/haswell/finalize.c: Drop dead code
by Angel Pons (Code Review) 10 Jul '20

10 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43207 ) Change subject: src/cpu/intel/haswell/finalize.c: Drop dead code ...................................................................... src/cpu/intel/haswell/finalize.c: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I3fc616eeb975aae7a5937f8b555ae554010d8dd3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/finalize.c 1 file changed, 0 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/43207/1 diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index a6d38ae..1f84b82 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -4,43 +4,6 @@ #include <cpu/x86/msr.h> #include "haswell.h" -/* MSR Documentation based on - * "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)" - * Document Number 504790 - * Revision 1.6.0, June 2012 */ - void intel_cpu_haswell_finalize_smm(void) { -#if 0 - /* Lock C-State MSR */ - msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15); - - /* Lock AES-NI only if supported */ - if (cpuid_ecx(1) & (1 << 25)) - msr_set_bit(MSR_FEATURE_CONFIG, 0); - -#ifdef LOCK_POWER_CONTROL_REGISTERS - /* - * Lock the power control registers. - * - * These registers can be left unlocked if modifying power - * limits from the OS is desirable. Modifying power limits - * from the OS can be especially useful for experimentation - * during early phases of system bringup while the thermal - * power envelope is being proven. - */ - - msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31); - msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31); - msr_set_bit(MSR_PKG_POWER_LIMIT, 63); - msr_set_bit(MSR_PP0_POWER_LIMIT, 31); - msr_set_bit(MSR_PP1_POWER_LIMIT, 31); -#endif - - /* Lock TM interrupts - route thermal events to all processors */ - msr_set_bit(MSR_MISC_PWR_MGMT, 22); - - /* Lock memory configuration to protect SMM */ - msr_set_bit(MSR_LT_LOCK_MEMORY, 0); -#endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/43207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fc616eeb975aae7a5937f8b555ae554010d8dd3 Gerrit-Change-Number: 43207 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mb/asrock/imb-a180: Drop dead code
by Angel Pons (Code Review) 10 Jul '20

10 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43238 ) Change subject: mb/asrock/imb-a180: Drop dead code ...................................................................... mb/asrock/imb-a180: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I00b3af64b6f842d298e91c20ab5f54f0ca3197ee Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/imb-a180/acpi/ide.asl M src/mainboard/asrock/imb-a180/acpi/sata.asl M src/mainboard/asrock/imb-a180/acpi/usb_oc.asl 3 files changed, 0 insertions(+), 462 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/43238/1 diff --git a/src/mainboard/asrock/imb-a180/acpi/ide.asl b/src/mainboard/asrock/imb-a180/acpi/ide.asl index a1db5e9..c8d7172 100644 --- a/src/mainboard/asrock/imb-a180/acpi/ide.asl +++ b/src/mainboard/asrock/imb-a180/acpi/ide.asl @@ -1,233 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* No IDE functionality */ - -#if 0 -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - /* save total time of primary PIO master timing to PIO spd0 */ - Store(GTTM(PPTM), PSD0) - /* save total time of primary PIO slave Timing to PIO spd1 */ - Store(GTTM(PPTS), PSD1) - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} -#endif diff --git a/src/mainboard/asrock/imb-a180/acpi/sata.asl b/src/mainboard/asrock/imb-a180/acpi/sata.asl index f22d3df..659a076 100644 --- a/src/mainboard/asrock/imb-a180/acpi/sata.asl +++ b/src/mainboard/asrock/imb-a180/acpi/sata.asl @@ -1,133 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* No SATA functionality */ - -#if 0 -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} -#endif diff --git a/src/mainboard/asrock/imb-a180/acpi/usb_oc.asl b/src/mainboard/asrock/imb-a180/acpi/usb_oc.asl index 473291d..a5846fe 100644 --- a/src/mainboard/asrock/imb-a180/acpi/usb_oc.asl +++ b/src/mainboard/asrock/imb-a180/acpi/usb_oc.asl @@ -1,15 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* simple name description */ -/* -#include <acpi/acpi.h> -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ - /* USB overcurrent mapping pins. */ Name(UOM0, 0) Name(UOM1, 2) @@ -21,95 +11,3 @@ Name(UOM7, 2) Name(UOM8, 6) Name(UOM9, 6) - -/* USB Overcurrent GPEs */ - -#if 0 /* TODO: Update for imba180 */ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - } - } -} -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/43238 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00b3af64b6f842d298e91c20ab5f54f0ca3197ee Gerrit-Change-Number: 43238 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 6

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2020