Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43333 )
Change subject: soc/amd/picasso: Map AOAC registers to enable i2c after S3 ......................................................................
soc/amd/picasso: Map AOAC registers to enable i2c after S3
When entering S3, zork shuts down the i2c controllers to save power. On resume, we need to re-enable i2c before accessing them, so we need to map the AOAC registers in verstage.
BUG=b:160834101 TEST=psp_verstage works after resume.
Signed-off-by: Martin Roth martinroth@chromium.org Change-Id: Ia8aa4923898a50f2202b6ca8434cee61a5918e91 --- M src/soc/amd/picasso/psp_verstage/fch.c 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43333/1
diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c index 9059c9e..e01a684 100644 --- a/src/soc/amd/picasso/psp_verstage/fch.c +++ b/src/soc/amd/picasso/psp_verstage/fch.c @@ -63,6 +63,11 @@ write8((void *)(io_bar + reg), value); }
+static void aoac_set_bar(void *bar) +{ + acpimmio_aoac = bar; +} + static struct { const char *name; struct { @@ -79,6 +84,7 @@ {"eSPI", {FCH_IO_DEVICE_ESPI}, espi_set_bar}, {"I2C2", {FCH_IO_DEVICE_I2C, 2}, i2c2_set_bar}, {"I2C3", {FCH_IO_DEVICE_I2C, 3}, i2c3_set_bar}, + {"AOAC", {FCH_IO_DEVICE_AOAC}, aoac_set_bar}, };
uintptr_t *map_spi_rom(void)
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43333 )
Change subject: soc/amd/picasso: Map AOAC registers to enable i2c after S3 ......................................................................
Patch Set 1: Code-Review+2
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43333 )
Change subject: soc/amd/picasso: Map AOAC registers to enable i2c after S3 ......................................................................
Patch Set 1: Code-Review+2
Aaron Durbin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43333 )
Change subject: soc/amd/picasso: Map AOAC registers to enable i2c after S3 ......................................................................
soc/amd/picasso: Map AOAC registers to enable i2c after S3
When entering S3, zork shuts down the i2c controllers to save power. On resume, we need to re-enable i2c before accessing them, so we need to map the AOAC registers in verstage.
BUG=b:160834101 TEST=psp_verstage works after resume.
Signed-off-by: Martin Roth martinroth@chromium.org Change-Id: Ia8aa4923898a50f2202b6ca8434cee61a5918e91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43333 Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Raul Rangel rrangel@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/picasso/psp_verstage/fch.c 1 file changed, 6 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c index 9059c9e..e01a684 100644 --- a/src/soc/amd/picasso/psp_verstage/fch.c +++ b/src/soc/amd/picasso/psp_verstage/fch.c @@ -63,6 +63,11 @@ write8((void *)(io_bar + reg), value); }
+static void aoac_set_bar(void *bar) +{ + acpimmio_aoac = bar; +} + static struct { const char *name; struct { @@ -79,6 +84,7 @@ {"eSPI", {FCH_IO_DEVICE_ESPI}, espi_set_bar}, {"I2C2", {FCH_IO_DEVICE_I2C, 2}, i2c2_set_bar}, {"I2C3", {FCH_IO_DEVICE_I2C, 3}, i2c3_set_bar}, + {"AOAC", {FCH_IO_DEVICE_AOAC}, aoac_set_bar}, };
uintptr_t *map_spi_rom(void)
-
Aaron Durbin (Code Review) -
Martin Roth (Code Review)
-
Raul Rangel (Code Review)