coreboot-gerrit July 2020

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Change in coreboot[master]: nb/intel/haswell: Add `mb_post_raminit_setup` function
by Angel Pons (Code Review) 11 Jul '20

11 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43094 ) Change subject: nb/intel/haswell: Add `mb_post_raminit_setup` function ...................................................................... nb/intel/haswell: Add `mb_post_raminit_setup` function This function is called at the end of `romstage_common`. Only one board makes use of it, the Lenovo ThinkPad T440p. To preserve behavior, call it after `romstage_common` has done nearly everything. Change-Id: I35742879e737be4f383a0e36aecc6682fc9df058 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/lenovo/t440p/romstage.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/romstage.c 3 files changed, 24 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/43094/1 diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index ea1193f..5ddbd03 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -26,8 +26,24 @@ RCBA_END_CONFIG, }; -void mainboard_config_superio(void) +void mb_post_raminit_setup(void) { + u8 enable_peg; + if (get_option(&enable_peg, "enable_dual_graphics") != CB_SUCCESS) + enable_peg = 0; + + bool power_en = pmh7_dgpu_power_state(); + + if (enable_peg != power_en) + pmh7_dgpu_power_enable(!power_en); + + if (!enable_peg) { + // Hide disabled dGPU device + u32 reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + reg32 &= ~DEVEN_D1F0EN; + + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); + } } void mainboard_romstage_entry(void) @@ -86,21 +102,4 @@ }; romstage_common(&romstage_params); - - u8 enable_peg; - if (get_option(&enable_peg, "enable_dual_graphics") != CB_SUCCESS) - enable_peg = 0; - - bool power_en = pmh7_dgpu_power_state(); - - if (enable_peg != power_en) - pmh7_dgpu_power_enable(!power_en); - - if (!enable_peg) { - // Hide disabled dGPU device - u32 reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~DEVEN_D1F0EN; - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); - } } diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index b98d880..0b35acb 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -198,6 +198,7 @@ void (*copy_spd)(struct pei_data *peid); }; void romstage_common(const struct romstage_params *params); +void mb_post_raminit_setup(void); /* optional */ void haswell_early_initialization(void); void haswell_late_initialization(void); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 579eca7..e5e29c1 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -13,6 +13,10 @@ #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/me.h> +void __weak mb_post_raminit_setup(void) +{ +} + void romstage_common(const struct romstage_params *params) { int wake_from_s3; @@ -77,5 +81,7 @@ romstage_handoff_init(wake_from_s3); + mb_post_raminit_setup(); + post_code(0x3f); } -- To view, visit https://review.coreboot.org/c/coreboot/+/43094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35742879e737be4f383a0e36aecc6682fc9df058 Gerrit-Change-Number: 43094 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 14

Change in coreboot[master]: payloads/tianocore: Don't recurse submodules
by Matt DeVillier (Code Review) 11 Jul '20

11 Jul '20

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43063 ) Change subject: payloads/tianocore: Don't recurse submodules ...................................................................... Patch Set 2: Code-Review+2 builds both CorebootPayloadpkg and UefiPayloadPkg without issue -- To view, visit https://review.coreboot.org/c/coreboot/+/43063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c5d6dd6e5070720870fc22b2476c6fe8dc7fd40 Gerrit-Change-Number: 43063 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 11 Jul 2020 18:56:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/supermicro/x11-lga1151: 5/5 Rewrite pad config using intelp2m
by Maxim Polyakov (Code Review) 11 Jul '20

11 Jul '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42919 ) Change subject: mb/supermicro/x11-lga1151: 5/5 Rewrite pad config using intelp2m ...................................................................... mb/supermicro/x11-lga1151: 5/5 Rewrite pad config using intelp2m Take into account the remapping of reset sources [1] for the Sunrice Point PCH, to fix Reset Config fields (bit 31:30) in the corresponding macros. The intelp2m utility does this remapping automatically, but these changes in a separate patch to pay attention to them. [1] src/soc/intel/skylake/gpio.c#n9 Change-Id: I388d39ca8314de60610588223d024e1bb1681264 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/42919/1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h index d005d8b..114095a 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h @@ -284,7 +284,7 @@ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* GPP_D22 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, PWROK, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, RSMRST, OFF, ACPI), /* GPP_D23 - GPIO */ PAD_NC(GPP_D23, NONE), @@ -398,7 +398,7 @@ PAD_NC(GPP_F22, NONE), /* GPP_F23 - GPIO */ - PAD_CFG_GPO(GPP_F23, 0, PWROK), + PAD_CFG_GPO(GPP_F23, 0, RSMRST), /* GPP_G0 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, ACPI), diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h index 4f16424..df13a21 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h @@ -298,7 +298,7 @@ PAD_CFG_GPO_GPIO_DRIVER(GPP_D21, 0, DEEP, NONE), /* GPP_D22 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, PWROK, OFF, DRIVER), + PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, RSMRST, OFF, DRIVER), /* GPP_D23 - GPIO */ PAD_NC(GPP_D23, NONE), @@ -416,7 +416,7 @@ PAD_NC(GPP_F22, NONE), /* GPP_F23 - GPIO */ - PAD_CFG_GPO_GPIO_DRIVER(GPP_F23, 0, PWROK, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F23, 0, RSMRST, NONE), /* GPIO Group GPP_G */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I388d39ca8314de60610588223d024e1bb1681264 Gerrit-Change-Number: 42919 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: arch/x86: Drop CBMEM_TOP_BACKUP
by Kyösti Mälkki (Code Review) 11 Jul '20

11 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43326 ) Change subject: arch/x86: Drop CBMEM_TOP_BACKUP ...................................................................... arch/x86: Drop CBMEM_TOP_BACKUP Code has evolved such that there seems to be little use for global definition of cbmem_top_chipset(). Even for AMD we had three different implementations. Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Makefile.inc D src/arch/x86/cbmem.c M src/cpu/amd/mtrr/amd_mtrr.c M src/drivers/amd/agesa/romstage.c M src/include/cbmem.h M src/northbridge/amd/agesa/Kconfig M src/northbridge/amd/agesa/family14/state_machine.c M src/northbridge/amd/agesa/family15tn/state_machine.c M src/northbridge/amd/agesa/family16kb/state_machine.c M src/northbridge/amd/pi/00730F01/state_machine.c M src/northbridge/amd/pi/Kconfig M src/soc/amd/common/block/acpimmio/biosram.c M src/soc/amd/common/block/include/amdblocks/biosram.h M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/stoneyridge/memmap.c 15 files changed, 23 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/43326/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index fa647b7..61e7edc 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -164,7 +164,6 @@ # gdt_init.S is included by entry32.inc when romstage is the first C # environment. romstage-y += gdt_init.S -romstage-y += cbmem.c romstage-y += cpu_common.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c deleted file mode 100644 index 353368a..0000000 --- a/src/arch/x86/cbmem.c +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cbmem.h> - -#if CONFIG(CBMEM_TOP_BACKUP) - -void *cbmem_top_chipset(void) -{ - /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ - return (void *)restore_top_of_low_cacheable(); -} - -#endif /* CBMEM_TOP_BACKUP */ diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 1234c82..fc3212f 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbmem.h> +#include <amdblocks/biosram.h> #include <console/console.h> #include <device/device.h> #include <arch/cpu.h> diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 617416a..29423ef 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -107,3 +107,9 @@ { romstage_main(); } + +void *cbmem_top_chipset(void) +{ + /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ + return (void *)restore_top_of_low_cacheable(); +} diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 4cc4045..b548cd9 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -139,17 +139,6 @@ static cbmem_init_hook_t init_fn_ ## _unused3_ = init_fn_; #endif /* ENV_RAMSTAGE */ - -/* Any new chipset and board must implement cbmem_top() for both - * romstage and ramstage to support early features like COLLECT_TIMESTAMPS - * and CBMEM_CONSOLE. Sometimes it is necessary to have cbmem_top() - * value stored in nvram to enable early recovery on S3 path. - */ -#if ENV_X86 -void backup_top_of_low_cacheable(uintptr_t ramtop); -uintptr_t restore_top_of_low_cacheable(void); -#endif - /* * Returns 0 for the stages where we know that cbmem does not come online. * Even if this function returns 1 for romstage, depending upon the point in diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 6711f87..6f6e3d6 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -3,7 +3,6 @@ config NORTHBRIDGE_AMD_AGESA bool default CPU_AMD_AGESA - select CBMEM_TOP_BACKUP if NORTHBRIDGE_AMD_AGESA diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index 202cdaa..36e5fd9 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -2,8 +2,8 @@ #include <Porting.h> #include <AGESA.h> +#include <amdblocks/biosram.h> #include <arch/io.h> -#include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> #include <device/device.h> diff --git a/src/northbridge/amd/agesa/family15tn/state_machine.c b/src/northbridge/amd/agesa/family15tn/state_machine.c index 8d450f9..29c1d87 100644 --- a/src/northbridge/amd/agesa/family15tn/state_machine.c +++ b/src/northbridge/amd/agesa/family15tn/state_machine.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/biosram.h> + #include <Porting.h> #include <AGESA.h> - -#include <cbmem.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c index 58bc345..cbf0313 100644 --- a/src/northbridge/amd/agesa/family16kb/state_machine.c +++ b/src/northbridge/amd/agesa/family16kb/state_machine.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/biosram.h> + #include <Porting.h> #include <AGESA.h> - -#include <cbmem.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c index f3c45a0..a97faeb 100644 --- a/src/northbridge/amd/pi/00730F01/state_machine.c +++ b/src/northbridge/amd/pi/00730F01/state_machine.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/biosram.h> + #include "Porting.h" #include "AGESA.h" -#include <cbmem.h> #include <device/device.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index e8c3530..833afae 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -4,7 +4,6 @@ bool default y if CPU_AMD_PI default n - select CBMEM_TOP_BACKUP if NORTHBRIDGE_AMD_PI diff --git a/src/soc/amd/common/block/acpimmio/biosram.c b/src/soc/amd/common/block/acpimmio/biosram.c index b01c196..06bbed9 100644 --- a/src/soc/amd/common/block/acpimmio/biosram.c +++ b/src/soc/amd/common/block/acpimmio/biosram.c @@ -2,7 +2,6 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/biosram.h> -#include <cbmem.h> #include <device/mmio.h> #include <stdint.h> diff --git a/src/soc/amd/common/block/include/amdblocks/biosram.h b/src/soc/amd/common/block/include/amdblocks/biosram.h index 39ce112..226fc17 100644 --- a/src/soc/amd/common/block/include/amdblocks/biosram.h +++ b/src/soc/amd/common/block/include/amdblocks/biosram.h @@ -5,6 +5,14 @@ #include <stdint.h> +/* Any new chipset and board must implement cbmem_top() for both + * romstage and ramstage to support early features like COLLECT_TIMESTAMPS + * and CBMEM_CONSOLE. With AMD it is necessary to have cbmem_top() + * value stored in nvram to enable early recovery on S3 path. + */ +void backup_top_of_low_cacheable(uintptr_t ramtop); +uintptr_t restore_top_of_low_cacheable(void); + /* Returns the bootblock C entry point for APs */ void *get_ap_entry_ptr(void); /* Used by BSP to store the bootblock entry point for APs */ diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index de9144c..ff52fbd 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <timestamp.h> #include <amdblocks/biosram.h> diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 9807905..67a4319 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -13,7 +13,7 @@ #include <arch/bert_storage.h> #include <soc/northbridge.h> #include <soc/iomap.h> -#include <amdblocks/acpimmio.h> +#include <amdblocks/biosram.h> #if CONFIG(ACPI_BERT) #if CONFIG_SMM_TSEG_SIZE == 0x0 -- To view, visit https://review.coreboot.org/c/coreboot/+/43326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b Gerrit-Change-Number: 43326 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: src/lib: Remove redundant code in imd.c
by Anna Karaś (Code Review) 11 Jul '20

11 Jul '20

Anna Karaś has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43339 ) Change subject: src/lib: Remove redundant code in imd.c ...................................................................... src/lib: Remove redundant code in imd.c Get rid of duplicated "if" statement in imdr_create_empty(). Signed-off-by: Anna Karas <aka(a)semihalf.com> Change-Id: I80c074d09f222086092478f8fd3ac665235ebb31 --- M src/lib/imd.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/43339/1 diff --git a/src/lib/imd.c b/src/lib/imd.c index c87037d..e19c03d 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -143,9 +143,6 @@ assert(IS_POWER_OF_2(root_size)); assert(IS_POWER_OF_2(entry_align)); - if (!imdr->limit) - return -1; - /* * root_size needs to be large enough to accommodate root pointer and * root book keeping structure. The caller needs to ensure there's -- To view, visit https://review.coreboot.org/c/coreboot/+/43339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80c074d09f222086092478f8fd3ac665235ebb31 Gerrit-Change-Number: 43339 Gerrit-PatchSet: 1 Gerrit-Owner: Anna Karaś <aka(a)semihalf.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: [NOTFORMERGE] soc/amd/common: Exclude some invalid PCI accessor
by Kyösti Mälkki (Code Review) 11 Jul '20

11 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43327 ) Change subject: [NOTFORMERGE] soc/amd/common: Exclude some invalid PCI accessor ...................................................................... [NOTFORMERGE] soc/amd/common: Exclude some invalid PCI accessor Change-Id: I58f25d30995f90104d60414f76fac59f79adafbe Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/lpc/espi_util.c M src/soc/amd/common/block/spi/fch_spi.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/43327/1 diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 3750a8b..7dfefea 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -24,7 +24,11 @@ if (espi_bar) return espi_bar; +#if ENV_X86 espi_spi_base = lpc_get_spibase(); +#else + espi_spi_base = 0; +#endif espi_update_static_bar(espi_spi_base + ESPI_OFFSET_FROM_BAR); return espi_bar; diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index bf64c3f..b762484 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -17,10 +17,14 @@ if (base) return base; +#if ENV_X86 lpc_set_spibase(SPI_BASE_ADDRESS); lpc_enable_spi_rom(SPI_ROM_ENABLE); return SPI_BASE_ADDRESS; +#else + return 0; +#endif } static void fch_spi_set_spi100(int norm, int fast, int alt, int tpm) @@ -77,7 +81,9 @@ void fch_spi_early_init(void) { +#if ENV_X86 lpc_set_spibase(SPI_BASE_ADDRESS); +#endif lpc_enable_spi_rom(SPI_ROM_ENABLE); lpc_enable_spi_prefetch(); fch_spi_disable_4dw_burst(); -- To view, visit https://review.coreboot.org/c/coreboot/+/43327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58f25d30995f90104d60414f76fac59f79adafbe Gerrit-Change-Number: 43327 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: nb/intel/i945: Drop dead code
by Angel Pons (Code Review) 11 Jul '20

11 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43230 ) Change subject: nb/intel/i945: Drop dead code ...................................................................... nb/intel/i945: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I5e33526a02872c14e9fa37a485d2f93dea8b088f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/raminit.c 2 files changed, 1 insertion(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/43230/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index f388330..a8c160a 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -364,7 +364,7 @@ printk(BIOS_DEBUG, "timeout!\n"); else printk(BIOS_DEBUG, "done..\n"); -#if 1 + /* Enable Active State Power Management (ASPM) L0 state */ reg32 = DMIBAR32(DMILCAP); @@ -387,7 +387,6 @@ if (activate_aspm) DMIBAR32(DMILCTL) |= (3 << 0); -#endif /* Last but not least, some additional steps */ reg32 = MCHBAR32(FSBSNPCTL); @@ -771,10 +770,6 @@ /* Initialize slot power limit for root ports */ pci_write_config32(PCI_DEV(0, 0x1c, 0), 0x54, 0x00000060); -#if 0 - pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0); - pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0); -#endif pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); } diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 1c7a1f0..cfe4d8f 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -194,19 +194,6 @@ return (!reg8); } -/* TODO check if we ever need this function */ -#if 0 -static int sdram_capabilities_MEM4G_disable(void) -{ - u8 reg8; - - reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */ - reg8 &= (1 << 0); - - return (reg8 != 0); -} -#endif - #define GFX_FREQUENCY_CAP_166MHZ 0x04 #define GFX_FREQUENCY_CAP_200MHZ 0x03 #define GFX_FREQUENCY_CAP_250MHZ 0x02 @@ -2198,11 +2185,7 @@ reg16 |= (4 << 11); MCHBAR16(CPCTL) = reg16; -#if 0 - if ((MCHBAR32(ECO) & (1 << 16)) != 0) { -#else if (i945_silicon_revision() != 0) { -#endif switch (sysinfo->fsb_frequency) { case 667: MCHBAR32(HGIPMC2) = 0x0d590d59; @@ -2253,13 +2236,6 @@ else MCHBAR32(ECO) |= (1 << 16); -#if 0 - - if (i945_silicon_revision() == 0) - MCHBAR32(FSBPMC3) &= ~(1 << 29); - else - MCHBAR32(FSBPMC3) |= (1 << 29); -#endif MCHBAR32(FSBPMC3) &= ~(1 << 29); MCHBAR32(FSBPMC3) |= (1 << 21); @@ -2288,19 +2264,6 @@ pci_or_config8(PCI_DEV(0, 0x2, 0), 0xc1, 1 << 2); -#ifdef C2_SELF_REFRESH_DISABLE - - if (integrated_graphics) { - printk(BIOS_DEBUG, "C2 self-refresh with IGD\n"); - MCHBAR16(MIPMC4) = 0x0468; - MCHBAR16(MIPMC5) = 0x046c; - MCHBAR16(MIPMC6) = 0x046c; - } else { - MCHBAR16(MIPMC4) = 0x6468; - MCHBAR16(MIPMC5) = 0x646c; - MCHBAR16(MIPMC6) = 0x646c; - } -#else if (integrated_graphics) { MCHBAR16(MIPMC4) = 0x04f8; MCHBAR16(MIPMC5) = 0x04fc; @@ -2311,8 +2274,6 @@ MCHBAR16(MIPMC6) = 0x64fc; } -#endif - reg32 = MCHBAR32(PMCFG); reg32 &= ~(3 << 17); reg32 |= (2 << 17); -- To view, visit https://review.coreboot.org/c/coreboot/+/43230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e33526a02872c14e9fa37a485d2f93dea8b088f Gerrit-Change-Number: 43230 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c/w83793: Drop dead code
by Angel Pons (Code Review) 11 Jul '20

11 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43268 ) Change subject: drivers/i2c/w83793: Drop dead code ...................................................................... drivers/i2c/w83793: Drop dead code Nothing selects this driver. Drop it before it grows moss. Change-Id: I4d0e678a8725c1fdf9263b9fae4e4fb6bb5ab4de Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- D src/drivers/i2c/w83793/Kconfig D src/drivers/i2c/w83793/Makefile.inc D src/drivers/i2c/w83793/chip.h D src/drivers/i2c/w83793/w83793.c D src/drivers/i2c/w83793/w83793.h 5 files changed, 0 insertions(+), 409 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/43268/1 diff --git a/src/drivers/i2c/w83793/Kconfig b/src/drivers/i2c/w83793/Kconfig deleted file mode 100644 index d7f8cd1..0000000 --- a/src/drivers/i2c/w83793/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config DRIVERS_I2C_W83793 - bool diff --git a/src/drivers/i2c/w83793/Makefile.inc b/src/drivers/i2c/w83793/Makefile.inc deleted file mode 100644 index f7843a5..0000000 --- a/src/drivers/i2c/w83793/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-$(CONFIG_DRIVERS_I2C_W83793) += w83793.c diff --git a/src/drivers/i2c/w83793/chip.h b/src/drivers/i2c/w83793/chip.h deleted file mode 100644 index ea992e4..0000000 --- a/src/drivers/i2c/w83793/chip.h +++ /dev/null @@ -1,93 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -struct drivers_i2c_w83793_config { - u8 mfc; - u8 fanin; - u8 fanin_sel; - u8 peci_agent_conf; - u8 tcase0; /* °C */ - u8 tcase1; /* °C */ - u8 tcase2; /* °C */ - u8 tcase3; /* °C */ - u8 tr_enable; - u8 td_mode_select; - u8 critical_temperature; /* °C */ - - u32 vcorea_high_limit_mv; /* mV */ - u32 vcorea_low_limit_mv; /* mV */ - u32 vcoreb_high_limit_mv; /* mV */ - u32 vcoreb_low_limit_mv; /* mV */ - u32 vtt_high_limit_mv; /* mV */ - u32 vtt_low_limit_mv; /* mV */ - u32 vsen1_high_limit_mv; /* mV */ - u32 vsen1_low_limit_mv; /* mV */ - u32 vsen2_high_limit_mv; /* mV */ - u32 vsen2_low_limit_mv; /* mV */ - u32 vsen3_high_limit_mv; /* mV */ - u32 vsen3_low_limit_mv; /* mV */ - u32 vsen4_high_limit_mv; /* mV */ - u32 vsen4_low_limit_mv; /* mV */ - u32 vdd_high_limit_mv; /* mV */ - u32 vdd_low_limit_mv; /* mV */ - u32 vsb_high_limit_mv; /* mV */ - u32 vsb_low_limit_mv; /* mV */ - u32 vbat_high_limit_mv; /* mV */ - u32 vbat_low_limit_mv; /* mV */ - - u8 td1_critical_temperature; /* °C */ - u8 td1_critical_hysteresis; /* °C */ - u8 td1_warning_temperature; /* °C */ - u8 td1_warning_hysteresis; /* °C */ - u8 td2_critical_temperature; /* °C */ - u8 td2_critical_hysteresis; /* °C */ - u8 td2_warning_temperature; /* °C */ - u8 td2_warning_hysteresis; /* °C */ - u8 td3_critical_temperature; /* °C */ - u8 td3_critical_hysteresis; /* °C */ - u8 td3_warning_temperature; /* °C */ - u8 td3_warning_hysteresis; /* °C */ - u8 td4_critical_temperature; /* °C */ - u8 td4_critical_hysteresis; /* °C */ - u8 td4_warning_temperature; /* °C */ - u8 td4_warning_hysteresis; /* °C */ - u8 tr1_critical_temperature; /* °C */ - u8 tr1_critical_hysteresis; /* °C */ - u8 tr1_warning_temperature; /* °C */ - u8 tr1_warning_hysteresis; /* °C */ - u8 tr2_critical_temperature; /* °C */ - u8 tr2_critical_hysteresis; /* °C */ - u8 tr2_warning_temperature; /* °C */ - u8 tr2_warning_hysteresis; /* °C */ - - u8 fanctrl1; - u8 fanctrl2; - u8 first_valid_fan_number; - - u8 td1_fan_select; - u8 td2_fan_select; - u8 td3_fan_select; - u8 td4_fan_select; - - u8 tr1_fan_select; - u8 tr2_fan_select; - - u8 fan1_nonstop; /* % of full speed (0-100) */ - u8 fan2_nonstop; /* % of full speed (0-100) */ - u8 fan3_nonstop; /* % of full speed (0-100) */ - u8 fan4_nonstop; /* % of full speed (0-100) */ - u8 fan5_nonstop; /* % of full speed (0-100) */ - u8 fan6_nonstop; /* % of full speed (0-100) */ - u8 fan7_nonstop; /* % of full speed (0-100) */ - u8 fan8_nonstop; /* % of full speed (0-100) */ - - u8 default_speed; /* % of full speed (0-100) */ - - u8 fan1_duty; /* % of full speed (0-100) */ - u8 fan2_duty; /* % of full speed (0-100) */ - u8 fan3_duty; /* % of full speed (0-100) */ - u8 fan4_duty; /* % of full speed (0-100) */ - u8 fan5_duty; /* % of full speed (0-100) */ - u8 fan6_duty; /* % of full speed (0-100) */ - u8 fan7_duty; /* % of full speed (0-100) */ - u8 fan8_duty; /* % of full speed (0-100) */ -}; diff --git a/src/drivers/i2c/w83793/w83793.c b/src/drivers/i2c/w83793/w83793.c deleted file mode 100644 index 1233f9f..0000000 --- a/src/drivers/i2c/w83793/w83793.c +++ /dev/null @@ -1,307 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <stdint.h> -#include <console/console.h> -#include <device/device.h> -#include "w83793.h" -#include <device/smbus.h> -#include "chip.h" - -static int w83793_fan_limit(struct device *dev, int fan, uint16_t limit) -{ - return smbus_write_byte(dev, 0x90 + fan * 2, limit >> 8) || - smbus_write_byte(dev, 0x91 + fan * 2, limit & 0xff); -} - -static int w83793_bank(struct device *dev, int bank) -{ - return smbus_write_byte(dev, 0, bank); -} - -static int w83793_td_level(struct device *dev, int fan, const char *level) -{ - fan *= 0x10; - - smbus_write_byte(dev, 0x30 + fan, level[0]); - smbus_write_byte(dev, 0x31 + fan, level[1]); - smbus_write_byte(dev, 0x32 + fan, level[2]); - smbus_write_byte(dev, 0x33 + fan, level[3]); - smbus_write_byte(dev, 0x34 + fan, level[4]); - smbus_write_byte(dev, 0x35 + fan, level[5]); - smbus_write_byte(dev, 0x36 + fan, level[6]); - return 0; -} - -static int w83793_tr_level(struct device *dev, int fan, const char *level) -{ - fan *= 0x10; - - smbus_write_byte(dev, 0x70 + fan, level[0]); - smbus_write_byte(dev, 0x71 + fan, level[1]); - smbus_write_byte(dev, 0x72 + fan, level[2]); - smbus_write_byte(dev, 0x73 + fan, level[3]); - smbus_write_byte(dev, 0x74 + fan, level[4]); - smbus_write_byte(dev, 0x75 + fan, level[5]); - smbus_write_byte(dev, 0x76 + fan, level[6]); - return 0; -} - - -static int w83793_td_fan_level(struct device *dev, int fan, const char *level) -{ - fan *= 0x10; - - smbus_write_byte(dev, 0x38 + fan, level[0]); - smbus_write_byte(dev, 0x39 + fan, level[1]); - smbus_write_byte(dev, 0x3a + fan, level[2]); - smbus_write_byte(dev, 0x3b + fan, level[3]); - smbus_write_byte(dev, 0x3c + fan, level[4]); - smbus_write_byte(dev, 0x3d + fan, level[5]); - smbus_write_byte(dev, 0x3e + fan, level[6]); - return 0; -} - -static int w83793_tr_fan_level(struct device *dev, int fan, const char *level) -{ - fan *= 0x10; - - smbus_write_byte(dev, 0x78 + fan, level[0]); - smbus_write_byte(dev, 0x79 + fan, level[1]); - smbus_write_byte(dev, 0x7a + fan, level[2]); - smbus_write_byte(dev, 0x7b + fan, level[3]); - smbus_write_byte(dev, 0x7c + fan, level[4]); - smbus_write_byte(dev, 0x7d + fan, level[5]); - smbus_write_byte(dev, 0x7e + fan, level[6]); - return 0; -} - -static uint8_t millivolts_to_limit_value_type1(int millivolts) -{ - /* Datasheet v1.4 page 64 (VCoreA, VCoreB, Vtt Limit) */ - return ((millivolts * 125) / 1000); -} - -static uint8_t millivolts_to_limit_value_type2(int millivolts) -{ - /* Datasheet v1.4 page 64 (VSEN1, VEN2, VSEN3) */ - return ((millivolts * 625) / 10000); -} - -static uint8_t millivolts_to_limit_value_type3(int millivolts) -{ - /* Datasheet v1.4 page 64 (5VDD, 5VSB) */ - return ((((millivolts * 10) + 1500) * 417) / 10000); -} - -static uint8_t fan_pct_to_cfg_val(uint8_t percent) -{ - uint8_t cfg = (((unsigned int)percent * 10000) / 15873); - if (cfg > 0x3f) - cfg = 0x3f; - return cfg; -} - -static void w83793_init(struct device *dev) -{ - struct drivers_i2c_w83793_config *config = dev->chip_info; - uint16_t id; - int i; - - if (w83793_bank(dev, 0)) - printk(BIOS_ERR, "%s: failed\n", __func__); - - if (!config) - return; - - id = smbus_read_byte(dev, 0x0d); - w83793_bank(dev, 0x80); - id |= smbus_read_byte(dev, 0x0d) << 8; - printk(BIOS_ERR, "ID: %04x\n", id); - - /* reset configuration */ - smbus_write_byte(dev, 0x40, 0x80); - smbus_write_byte(dev, 0x51, 0x06); - - /* Multi function control */ - smbus_write_byte(dev, 0x58, config->mfc); - - /* FANIN_Ctrl */ - smbus_write_byte(dev, 0x5c, config->fanin); - - /* FANIN_Sel */ - smbus_write_byte(dev, 0x5d, config->fanin_sel); - - /* Temperature source */ - smbus_write_byte(dev, 0x5e, config->td_mode_select); - /* TR monitor enable */ - smbus_write_byte(dev, 0x5f, config->tr_enable); - /* PECI Agent configuration */ - smbus_write_byte(dev, 0xd0, config->peci_agent_conf); - /* TCase */ - smbus_write_byte(dev, 0xd1, config->tcase0); - smbus_write_byte(dev, 0xd2, config->tcase1); - smbus_write_byte(dev, 0xd3, config->tcase2); - smbus_write_byte(dev, 0xd4, config->tcase3); - /* PECI Reportstyle */ - smbus_write_byte(dev, 0xd5, 0x00); - - /* Voltage high/low limits */ - smbus_write_byte(dev, 0x60, millivolts_to_limit_value_type1(config->vcorea_high_limit_mv)); - smbus_write_byte(dev, 0x61, millivolts_to_limit_value_type1(config->vcorea_low_limit_mv)); - smbus_write_byte(dev, 0x62, millivolts_to_limit_value_type1(config->vcoreb_high_limit_mv)); - smbus_write_byte(dev, 0x63, millivolts_to_limit_value_type1(config->vcoreb_low_limit_mv)); - smbus_write_byte(dev, 0x64, millivolts_to_limit_value_type1(config->vtt_high_limit_mv)); - smbus_write_byte(dev, 0x65, millivolts_to_limit_value_type1(config->vtt_low_limit_mv)); - smbus_write_byte(dev, 0x6a, millivolts_to_limit_value_type2(config->vsen1_high_limit_mv)); - smbus_write_byte(dev, 0x6b, millivolts_to_limit_value_type2(config->vsen1_low_limit_mv)); - smbus_write_byte(dev, 0x6c, millivolts_to_limit_value_type2(config->vsen2_high_limit_mv)); - smbus_write_byte(dev, 0x6d, millivolts_to_limit_value_type2(config->vsen2_low_limit_mv)); - smbus_write_byte(dev, 0x6e, millivolts_to_limit_value_type2(config->vsen3_high_limit_mv)); - smbus_write_byte(dev, 0x6f, millivolts_to_limit_value_type2(config->vsen3_low_limit_mv)); - smbus_write_byte(dev, 0x70, millivolts_to_limit_value_type1(config->vsen4_high_limit_mv)); - smbus_write_byte(dev, 0x71, millivolts_to_limit_value_type1(config->vsen4_low_limit_mv)); - smbus_write_byte(dev, 0x72, millivolts_to_limit_value_type3(config->vdd_high_limit_mv)); - smbus_write_byte(dev, 0x73, millivolts_to_limit_value_type3(config->vdd_low_limit_mv)); - smbus_write_byte(dev, 0x74, millivolts_to_limit_value_type3(config->vsb_high_limit_mv)); - smbus_write_byte(dev, 0x75, millivolts_to_limit_value_type3(config->vsb_low_limit_mv)); - smbus_write_byte(dev, 0x76, millivolts_to_limit_value_type2(config->vbat_high_limit_mv)); - smbus_write_byte(dev, 0x77, millivolts_to_limit_value_type2(config->vbat_low_limit_mv)); - - /* Temperature high/low limits */ - smbus_write_byte(dev, 0x78, config->td1_critical_temperature); - smbus_write_byte(dev, 0x79, config->td1_critical_hysteresis); - smbus_write_byte(dev, 0x7a, config->td1_warning_temperature); - smbus_write_byte(dev, 0x7b, config->td1_warning_hysteresis); - smbus_write_byte(dev, 0x7c, config->td2_critical_temperature); - smbus_write_byte(dev, 0x7d, config->td2_critical_hysteresis); - smbus_write_byte(dev, 0x7e, config->td2_warning_temperature); - smbus_write_byte(dev, 0x7f, config->td2_warning_hysteresis); - smbus_write_byte(dev, 0x80, config->td3_critical_temperature); - smbus_write_byte(dev, 0x81, config->td3_critical_hysteresis); - smbus_write_byte(dev, 0x82, config->td3_warning_temperature); - smbus_write_byte(dev, 0x83, config->td3_warning_hysteresis); - smbus_write_byte(dev, 0x84, config->td4_critical_temperature); - smbus_write_byte(dev, 0x85, config->td4_critical_hysteresis); - smbus_write_byte(dev, 0x86, config->td4_warning_temperature); - smbus_write_byte(dev, 0x87, config->td4_warning_hysteresis); - smbus_write_byte(dev, 0x88, config->tr1_critical_temperature); - smbus_write_byte(dev, 0x89, config->tr1_critical_hysteresis); - smbus_write_byte(dev, 0x8a, config->tr1_warning_temperature); - smbus_write_byte(dev, 0x8b, config->tr1_warning_hysteresis); - smbus_write_byte(dev, 0x8c, config->tr2_critical_temperature); - smbus_write_byte(dev, 0x8d, config->tr2_critical_hysteresis); - smbus_write_byte(dev, 0x8e, config->tr2_warning_temperature); - smbus_write_byte(dev, 0x8f, config->tr2_warning_hysteresis); - - /* Set minimum FAN speeds before alarms will be set */ - for (i = 0; i < config->first_valid_fan_number; i++) - w83793_fan_limit(dev, i, 0x0); - for (i = config->first_valid_fan_number; i < 12; i++) - w83793_fan_limit(dev, i, 0x768); - - /* Fan output style control */ - smbus_write_byte(dev, 0xb0, config->fanctrl1); - smbus_write_byte(dev, 0xb1, config->fanctrl2); - - /* FAN Uptime */ - smbus_write_byte(dev, 0xc3, 0x02); - - /* FAN downtime */ - smbus_write_byte(dev, 0xc4, 0x03); - - /* ALL FAN critical temperature */ - smbus_write_byte(dev, 0xc5, config->critical_temperature); - - /* Temperature offset */ - smbus_write_byte(dev, 0xa8, 0xf9); - smbus_write_byte(dev, 0xa9, 0xf9); - smbus_write_byte(dev, 0xaa, 0xf9); - smbus_write_byte(dev, 0xab, 0xf9); - - /* Default FAN speed */ - smbus_write_byte(dev, 0xb2, fan_pct_to_cfg_val(config->default_speed)); - - /* Manual FAN speeds */ - smbus_write_byte(dev, 0xb3, fan_pct_to_cfg_val(config->fan1_duty)); - smbus_write_byte(dev, 0xb4, fan_pct_to_cfg_val(config->fan2_duty)); - smbus_write_byte(dev, 0xb5, fan_pct_to_cfg_val(config->fan3_duty)); - smbus_write_byte(dev, 0xb6, fan_pct_to_cfg_val(config->fan4_duty)); - smbus_write_byte(dev, 0xb7, fan_pct_to_cfg_val(config->fan5_duty)); - smbus_write_byte(dev, 0xb8, fan_pct_to_cfg_val(config->fan6_duty)); - smbus_write_byte(dev, 0xb9, fan_pct_to_cfg_val(config->fan7_duty)); - smbus_write_byte(dev, 0xba, fan_pct_to_cfg_val(config->fan8_duty)); - - /* BANK 2 */ - smbus_write_byte(dev, 0x00, 0x02); - - /* TD FAN select */ - smbus_write_byte(dev, 0x01, config->td1_fan_select); - smbus_write_byte(dev, 0x02, config->td2_fan_select); - smbus_write_byte(dev, 0x03, config->td3_fan_select); - smbus_write_byte(dev, 0x04, config->td4_fan_select); - - smbus_write_byte(dev, 0x05, config->tr1_fan_select); - smbus_write_byte(dev, 0x06, config->tr2_fan_select); - - /* FAN control mode */ - smbus_write_byte(dev, 0x07, 0x00); - - /* hysteresis tolerance */ - smbus_write_byte(dev, 0x08, 0xaa); - smbus_write_byte(dev, 0x09, 0xaa); - - /* FanNonStop */ - smbus_write_byte(dev, 0x18, fan_pct_to_cfg_val(config->fan1_nonstop)); - smbus_write_byte(dev, 0x19, fan_pct_to_cfg_val(config->fan2_nonstop)); - smbus_write_byte(dev, 0x1a, fan_pct_to_cfg_val(config->fan3_nonstop)); - smbus_write_byte(dev, 0x1b, fan_pct_to_cfg_val(config->fan4_nonstop)); - smbus_write_byte(dev, 0x1c, fan_pct_to_cfg_val(config->fan5_nonstop)); - smbus_write_byte(dev, 0x1d, fan_pct_to_cfg_val(config->fan6_nonstop)); - smbus_write_byte(dev, 0x1e, fan_pct_to_cfg_val(config->fan7_nonstop)); - smbus_write_byte(dev, 0x1f, fan_pct_to_cfg_val(config->fan8_nonstop)); - - /* FanStart */ - smbus_write_byte(dev, 0x20, 0x08); - smbus_write_byte(dev, 0x21, 0x08); - smbus_write_byte(dev, 0x22, 0x08); - smbus_write_byte(dev, 0x23, 0x08); - smbus_write_byte(dev, 0x24, 0x08); - smbus_write_byte(dev, 0x25, 0x08); - smbus_write_byte(dev, 0x26, 0x08); - smbus_write_byte(dev, 0x27, 0x08); - - for (i = 0; i < 4; i++) - w83793_td_level(dev, i, (const char[]){ 0x32, 0x32, 0x32, 0x32, 0x37, 0x41, 0x4b }); - - for (i = 0; i < 2; i++) - w83793_tr_level(dev, i, (const char[]){ 0x1e, 0x23, 0x28, 0x2d, 0x32, 0x37, 0x3c }); - - for (i = 0; i < 4; i++) - w83793_td_fan_level(dev, i, (const char[]){ 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x26 }); - - for (i = 0; i < 2; i++) - w83793_tr_fan_level(dev, i, (const char[]){ 0x08, 0x0c, 0x10, 0x18, 0x20, 0x30, 0x38 }); - - - smbus_write_byte(dev, 0x00, 0x00); - - /* start monitoring operation */ - smbus_write_byte(dev, 0x40, 0x09); - -} - -static struct device_operations w83793_operations = { - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, - .init = w83793_init, -}; - -static void enable_dev(struct device *dev) -{ - dev->ops = &w83793_operations; -} - -struct chip_operations drivers_i2c_w83793_ops = { - CHIP_NAME("Nuvoton W83793 Hardware Monitor") - .enable_dev = enable_dev, -}; diff --git a/src/drivers/i2c/w83793/w83793.h b/src/drivers/i2c/w83793/w83793.h deleted file mode 100644 index 4ee33b0..0000000 --- a/src/drivers/i2c/w83793/w83793.h +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef W83793_H -#define W83793_H - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/43268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d0e678a8725c1fdf9263b9fae4e4fb6bb5ab4de Gerrit-Change-Number: 43268 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/amd/agesa/agesa_helper.h: Drop dead code
by Angel Pons (Code Review) 10 Jul '20

10 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43261 ) Change subject: nb/amd/agesa/agesa_helper.h: Drop dead code ...................................................................... nb/amd/agesa/agesa_helper.h: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: Icb98f3535f6c5f51081fc82262f6413f4b1a5733 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/amd/agesa/agesa_helper.h 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/43261/1 diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h index 8d229b1..120e74a 100644 --- a/src/northbridge/amd/agesa/agesa_helper.h +++ b/src/northbridge/amd/agesa/agesa_helper.h @@ -30,13 +30,8 @@ #define BSP_STACK_BASE_ADDR 0x30000 -#if 1 /* This covers node 0 only. */ #define HIGH_ROMSTAGE_STACK_SIZE (0x48000 - BSP_STACK_BASE_ADDR) -#else -/* This covers total of 8 nodes. */ -#define HIGH_ROMSTAGE_STACK_SIZE (0xA0000 - BSP_STACK_BASE_ADDR) -#endif #define HIGH_MEMORY_SCRATCH 0x30000 -- To view, visit https://review.coreboot.org/c/coreboot/+/43261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb98f3535f6c5f51081fc82262f6413f4b1a5733 Gerrit-Change-Number: 43261 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: sb/amd/cimx/sb800: Drop dead code
by Angel Pons (Code Review) 10 Jul '20

10 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43260 ) Change subject: sb/amd/cimx/sb800: Drop dead code ...................................................................... sb/amd/cimx/sb800: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I2a244436adb8f41e4246aad7e3bfaf0986f2d832 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/amd/cimx/sb800/Amd.h 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43260/1 diff --git a/src/southbridge/amd/cimx/sb800/Amd.h b/src/southbridge/amd/cimx/sb800/Amd.h index 1e57652..ac3c2e7 100644 --- a/src/southbridge/amd/cimx/sb800/Amd.h +++ b/src/southbridge/amd/cimx/sb800/Amd.h @@ -124,9 +124,6 @@ // 14:12 Function (3-bits) // 11:00 Offset (12-bits) -#if 0 -#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((unsigned int) (Seg)) << 28) | (((unsigned int) (Bus)) << 20) | \ - (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off))) #endif #define ILLEGAL_SBDFO 0xFFFFFFFF -- To view, visit https://review.coreboot.org/c/coreboot/+/43260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a244436adb8f41e4246aad7e3bfaf0986f2d832 Gerrit-Change-Number: 43260 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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