coreboot-gerrit July 2020

coreboot-gerrit@coreboot.org

1 participants
3166 discussions

Change in coreboot[master]: mb/asrock/h81m-hds: Factor out common MRC settings
by Angel Pons (Code Review) 12 Jul '20

12 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43110 ) Change subject: mb/asrock/h81m-hds: Factor out common MRC settings ...................................................................... mb/asrock/h81m-hds: Factor out common MRC settings There's no need to redefine common settings. Change-Id: Ie4ced6efc8119afca070ce86634a3c31c6580d0f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/h81m-hds/romstage.c 1 file changed, 42 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/43110/1 diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 14a68ec..8d360e5 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -22,52 +22,48 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data mainboard_pei_data = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 1, /* desktop/server */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, - .ec_present = 0, - .dimm_channel0_disabled = 2, /* Disable DIMM 1 on channel 0. */ - .dimm_channel1_disabled = 2, /* Disable DIMM 1 on channel 1. */ - .max_ddr3_freq = 1600, - .usb2_ports = { - /* Length, Enable, OCn#, Location */ - { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, - { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, - { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, - { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, - { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, - { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, - }, - .usb3_ports = { - /* Enable, OCn# */ - { 1, 0 }, - { 1, 0 }, - { 0, USB_OC_PIN_SKIP }, - { 0, USB_OC_PIN_SKIP }, - { 0, USB_OC_PIN_SKIP }, - { 0, USB_OC_PIN_SKIP }, - }, + pei_data->system_type = 1; /* Desktop/Server */ + pei_data->spd_addresses[0] = 0xa0; + pei_data->spd_addresses[2] = 0xa4; + pei_data->ec_present = 0; + /* + * 0 = leave channel enabled + * 1 = disable dimm 0 on channel + * 2 = disable dimm 1 on channel + * 3 = disable dimm 0+1 on channel + */ + pei_data->dimm_channel0_disabled = 2; + pei_data->dimm_channel1_disabled = 2; + pei_data->max_ddr3_freq = 1600; + + struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, }; - *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */ + struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + /* Enable, OCn# */ + { 1, 0 }, + { 1, 0 }, + { 0, USB_OC_PIN_SKIP }, + { 0, USB_OC_PIN_SKIP }, + { 0, USB_OC_PIN_SKIP }, + { 0, USB_OC_PIN_SKIP }, + }; + + memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); + memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/43110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4ced6efc8119afca070ce86634a3c31c6580d0f Gerrit-Change-Number: 43110 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/asrock/b85m_pro4: Factor out common MRC settings
by Angel Pons (Code Review) 12 Jul '20

12 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43109 ) Change subject: mb/asrock/b85m_pro4: Factor out common MRC settings ...................................................................... mb/asrock/b85m_pro4: Factor out common MRC settings These settings are the same on all boards. Since the other boards currently overwrite the struct contents, it doesn't make a difference. To ease review, the same settings will be dropped from other boards in separate commits, one board at a time. Change-Id: I500b7a1d7d97c6976e0c7c10ca491d3875cae22b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/romstage.c M src/northbridge/intel/haswell/romstage.c 2 files changed, 56 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/43109/1 diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index 576ba89..3bf1712 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -22,52 +22,50 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data mainboard_pei_data = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 1, /* desktop/server */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, - .ec_present = 0, - .gbe_enable = 1, - .dimm_channel0_disabled = 0, - .dimm_channel1_disabled = 0, - .max_ddr3_freq = 1600, - .usb2_ports = { - /* Length, Enable, OCn#, Location */ - { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, - { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, - { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, - }, - .usb3_ports = { - { 1, 0 }, - { 1, 0 }, - { 1, 1 }, - { 1, 1 }, - { 1, 2 }, - { 1, 2 }, - }, + pei_data->system_type = 1; /* Desktop/Server */ + pei_data->spd_addresses[0] = 0xa0; + pei_data->spd_addresses[1] = 0xa2; + pei_data->spd_addresses[2] = 0xa4; + pei_data->spd_addresses[3] = 0xa6; + pei_data->ec_present = 0; + pei_data->gbe_enable = 1; + /* + * 0 = leave channel enabled + * 1 = disable dimm 0 on channel + * 2 = disable dimm 1 on channel + * 3 = disable dimm 0+1 on channel + */ + pei_data->dimm_channel0_disabled = 0; + pei_data->dimm_channel1_disabled = 0; + pei_data->max_ddr3_freq = 1600; + + struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, }; - *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */ + struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, + }; + + memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); + memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); } diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index afcb3a5..6b37d42 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -29,6 +29,18 @@ int wake_from_s3; struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .tseg_size = CONFIG_SMM_TSEG_SIZE, }; mainboard_fill_pei_data(&pei_data); -- To view, visit https://review.coreboot.org/c/coreboot/+/43109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I500b7a1d7d97c6976e0c7c10ca491d3875cae22b Gerrit-Change-Number: 43109 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: haswell: Relocate `mainboard_romstage_entry` to northbridge
by Angel Pons (Code Review) 12 Jul '20

12 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43108 ) Change subject: haswell: Relocate `mainboard_romstage_entry` to northbridge ...................................................................... haswell: Relocate `mainboard_romstage_entry` to northbridge This is what sandybridge does, and if done properly allows factoring out common settings. Said refactoring will be handled in subsequent commits. Change-Id: I075eba1324a9e7cbd47e776b097eb940102ef4fe Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/romstage.c M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/google/beltino/romstage.c M src/mainboard/google/slippy/romstage.c M src/mainboard/intel/baskingridge/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/raminit.h M src/northbridge/intel/haswell/romstage.c 9 files changed, 35 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/43108/1 diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index c99bb6f..576ba89 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdint.h> -#include <arch/romstage.h> #include <cpu/intel/haswell/haswell.h> #include <device/pnp_ops.h> #include <northbridge/intel/haswell/haswell.h> @@ -21,9 +20,9 @@ RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); } -void mainboard_romstage_entry(void) +void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data = { + struct pei_data mainboard_pei_data = { .pei_version = PEI_VERSION, .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, @@ -70,5 +69,5 @@ }, }; - romstage_common(&pei_data); + *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */ } diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 5ce0145..14a68ec 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdint.h> -#include <arch/romstage.h> #include <cpu/intel/haswell/haswell.h> #include <device/pnp_ops.h> #include <northbridge/intel/haswell/haswell.h> @@ -21,9 +20,9 @@ RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); } -void mainboard_romstage_entry(void) +void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data = { + struct pei_data mainboard_pei_data = { .pei_version = PEI_VERSION, .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, @@ -70,5 +69,5 @@ }, }; - romstage_common(&pei_data); + *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */ } diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 4218393..5496092 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdint.h> -#include <arch/romstage.h> #include <cpu/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> @@ -43,9 +42,9 @@ RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ } -void mainboard_romstage_entry(void) +void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data = { + struct pei_data mainboard_pei_data = { .pei_version = PEI_VERSION, .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, @@ -100,6 +99,5 @@ }, }; - /* Call into the real romstage main with this board's attributes. */ - romstage_common(&pei_data); + *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */ } diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index a24f5c4..2231921 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/romstage.h> #include <cpu/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> @@ -43,9 +42,9 @@ RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ } -void mainboard_romstage_entry(void) +void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data = { + struct pei_data mainboard_pei_data = { .pei_version = PEI_VERSION, .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, @@ -73,8 +72,7 @@ .usb_xhci_on_resume = 1, }; - variant_romstage_entry(&pei_data); + *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */ - /* Call into the real romstage main with this board's attributes. */ - romstage_common(&pei_data); + variant_romstage_entry(pei_data); } diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index bdb334a..e126dc5 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -2,7 +2,6 @@ #include <stdint.h> #include <stddef.h> -#include <arch/romstage.h> #include <cpu/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> @@ -45,9 +44,9 @@ RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); } -void mainboard_romstage_entry(void) +void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data = { + struct pei_data mainboard_pei_data = { .pei_version = PEI_VERSION, .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, @@ -112,6 +111,5 @@ }, }; - /* Call into the real romstage main with this board's attributes. */ - romstage_common(&pei_data); + *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */ } diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 2e3f42e..8ef9040 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cpu/intel/haswell/haswell.h> -#include <arch/romstage.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/pei_data.h> #include <southbridge/intel/common/gpio.h> @@ -20,9 +19,9 @@ RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); } -void mainboard_romstage_entry(void) +void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data = { + struct pei_data mainboard_pei_data = { .pei_version = PEI_VERSION, .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, @@ -68,5 +67,5 @@ }, }; - romstage_common(&pei_data); + *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */ } diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index ca8c12c..23f00eb 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -189,8 +189,6 @@ void intel_northbridge_haswell_finalize_smm(void); -struct pei_data; -void romstage_common(struct pei_data *pei_data); void mb_post_raminit_setup(void); /* optional */ void haswell_early_initialization(void); diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index 920ee0f..140ea20 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -8,6 +8,9 @@ /* Optional function to copy SPD data for on-board memory */ void copy_spd(struct pei_data *peid); +/* Necessary function to initialize pei_data with mainboard-specific settings */ +void mainboard_fill_pei_data(struct pei_data *pei_data); + void sdram_initialize(struct pei_data *pei_data); void setup_sdram_meminfo(struct pei_data *pei_data); int fixup_haswell_errata(void); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 6c059da..afcb3a5 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/romstage.h> #include <console/console.h> #include <cf9_reset.h> #include <timestamp.h> @@ -22,10 +23,16 @@ { } -void romstage_common(struct pei_data *pei_data) +/* The romstage entry point for this platform is not mainboard-specific, hence the name */ +void mainboard_romstage_entry(void) { int wake_from_s3; + struct pei_data pei_data = { + }; + + mainboard_fill_pei_data(&pei_data); + enable_lapic(); wake_from_s3 = early_pch_init(); @@ -52,15 +59,15 @@ post_code(0x3a); /* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */ - pei_data->boot_mode = wake_from_s3 ? 2 : 0; + pei_data.boot_mode = wake_from_s3 ? 2 : 0; timestamp_add_now(TS_BEFORE_INITRAM); report_platform_info(); - copy_spd(pei_data); + copy_spd(&pei_data); - sdram_initialize(pei_data); + sdram_initialize(&pei_data); timestamp_add_now(TS_AFTER_INITRAM); @@ -71,7 +78,7 @@ if (!wake_from_s3) { cbmem_initialize_empty(); /* Save data returned from MRC on non-S3 resumes. */ - save_mrc_data(pei_data); + save_mrc_data(&pei_data); } else if (cbmem_initialize()) { #if CONFIG(HAVE_ACPI_RESUME) /* Failed S3 resume, reset to come up cleanly */ @@ -81,7 +88,7 @@ haswell_unhide_peg(); - setup_sdram_meminfo(pei_data); + setup_sdram_meminfo(&pei_data); romstage_handoff_init(wake_from_s3); -- To view, visit https://review.coreboot.org/c/coreboot/+/43108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I075eba1324a9e7cbd47e776b097eb940102ef4fe Gerrit-Change-Number: 43108 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: haswell boards: Fix writes to 16-bit DxxIR registers
by Angel Pons (Code Review) 12 Jul '20

12 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43107 ) Change subject: haswell boards: Fix writes to 16-bit DxxIR registers ...................................................................... haswell boards: Fix writes to 16-bit DxxIR registers The DxxIR (Device xx Interrupt Route) registers in RCBA are 16-bit wide, so do not use 32-bit operations to program them. Note that the DxxIP (Device xx Interrupt Pin) registers are 32-bit, so using 32-bit operations on them is correct. Change-Id: I9699b98d5fcd26b2c710bf018f16acc65dcb634e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/beltino/romstage.c M src/mainboard/google/slippy/romstage.c M src/mainboard/intel/baskingridge/romstage.c 3 files changed, 23 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/43107/1 diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index d410f55..4218393 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -33,14 +33,14 @@ RCBA32(D20IP) = (INTA << D20IP_XHCI); /* Device interrupt route registers */ - RCBA32(D31IR) = DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA); /* LPC */ - RCBA32(D29IR) = DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD); /* EHCI */ - RCBA32(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); /* PCIE */ - RCBA32(D27IR) = DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG); /* HDA */ - RCBA32(D22IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); /* ME */ - RCBA32(D21IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF); /* SIO */ - RCBA32(D20IR) = DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC); /* XHCI */ - RCBA32(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ + RCBA16(D31IR) = DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA); /* LPC */ + RCBA16(D29IR) = DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD); /* EHCI */ + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); /* PCIE */ + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG); /* HDA */ + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); /* ME */ + RCBA16(D21IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF); /* SIO */ + RCBA16(D20IR) = DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC); /* XHCI */ + RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ } void mainboard_romstage_entry(void) diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index c724049..a24f5c4 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -33,14 +33,14 @@ RCBA32(D20IP) = (INTA << D20IP_XHCI); /* Device interrupt route registers */ - RCBA32(D31IR) = DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA); /* LPC */ - RCBA32(D29IR) = DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD); /* EHCI */ - RCBA32(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); /* PCIE */ - RCBA32(D27IR) = DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG); /* HDA */ - RCBA32(D22IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); /* ME */ - RCBA32(D21IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF); /* SIO */ - RCBA32(D20IR) = DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC); /* XHCI */ - RCBA32(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ + RCBA16(D31IR) = DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA); /* LPC */ + RCBA16(D29IR) = DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD); /* EHCI */ + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); /* PCIE */ + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG); /* HDA */ + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); /* ME */ + RCBA16(D21IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF); /* SIO */ + RCBA16(D20IR) = DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC); /* XHCI */ + RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ } void mainboard_romstage_entry(void) diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 2ea74df..bdb334a 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -36,13 +36,13 @@ RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); /* Device interrupt route registers */ - RCBA32(D31IR) = DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA); - RCBA32(D29IR) = DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG); - RCBA32(D28IR) = DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE); - RCBA32(D27IR) = DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB); - RCBA32(D26IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); - RCBA32(D25IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); - RCBA32(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D31IR) = DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG); + RCBA16(D28IR) = DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB); + RCBA16(D26IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA16(D25IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); } void mainboard_romstage_entry(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/43107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9699b98d5fcd26b2c710bf018f16acc65dcb634e Gerrit-Change-Number: 43107 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: haswell: Drop `struct romstage_params` type
by Angel Pons (Code Review) 12 Jul '20

12 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43106 ) Change subject: haswell: Drop `struct romstage_params` type ...................................................................... haswell: Drop `struct romstage_params` type It only contains a pointer to another struct. Flatten it. Change-Id: Iab427592c332646e032a768719fc380c5794086b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/romstage.c M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/google/beltino/romstage.c M src/mainboard/google/slippy/romstage.c M src/mainboard/google/slippy/variant.h M src/mainboard/google/slippy/variants/falco/romstage.c M src/mainboard/google/slippy/variants/leon/romstage.c M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/intel/baskingridge/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/romstage.c 13 files changed, 28 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/43106/1 diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index a72418a..c99bb6f 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -70,9 +70,5 @@ }, }; - struct romstage_params romstage_params = { - .pei_data = &pei_data, - }; - - romstage_common(&romstage_params); + romstage_common(&pei_data); } diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 73c38e7..5ce0145 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -70,9 +70,5 @@ }, }; - struct romstage_params romstage_params = { - .pei_data = &pei_data, - }; - - romstage_common(&romstage_params); + romstage_common(&pei_data); } diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 6f95831..d410f55 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -100,10 +100,6 @@ }, }; - struct romstage_params romstage_params = { - .pei_data = &pei_data, - }; - /* Call into the real romstage main with this board's attributes. */ - romstage_common(&romstage_params); + romstage_common(&pei_data); } diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index 5261ddc..c724049 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -73,12 +73,8 @@ .usb_xhci_on_resume = 1, }; - struct romstage_params romstage_params = { - .pei_data = &pei_data, - }; - - variant_romstage_entry(&romstage_params); + variant_romstage_entry(&pei_data); /* Call into the real romstage main with this board's attributes. */ - romstage_common(&romstage_params); + romstage_common(&pei_data); } diff --git a/src/mainboard/google/slippy/variant.h b/src/mainboard/google/slippy/variant.h index 7eaac84..2263f9d 100644 --- a/src/mainboard/google/slippy/variant.h +++ b/src/mainboard/google/slippy/variant.h @@ -3,6 +3,6 @@ #ifndef VARIANT_H #define VARIANT_H -void variant_romstage_entry(struct romstage_params *rp); +void variant_romstage_entry(struct pei_data *pei_data); #endif diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 901c70e..11515cf 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -50,9 +50,9 @@ } } -void variant_romstage_entry(struct romstage_params *rp) +void variant_romstage_entry(struct pei_data *pei_data) { - rp->pei_data->ddr_refresh_2x = 1; /* Enable 2x refresh mode */ + pei_data->ddr_refresh_2x = 1; /* Enable 2x refresh mode */ struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ @@ -82,6 +82,6 @@ { 0, USB_OC_PIN_SKIP }, /* P4; */ }; - memcpy(rp->pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); - memcpy(rp->pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); + memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); + memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); } diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index 78c46dc..7a13b90 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -46,7 +46,7 @@ spd_file + (spd_index * spd_len), spd_len); } -void variant_romstage_entry(struct romstage_params *rp) +void variant_romstage_entry(struct pei_data *pei_data) { struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ @@ -76,6 +76,6 @@ { 0, USB_OC_PIN_SKIP }, /* P4; */ }; - memcpy(rp->pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); - memcpy(rp->pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); + memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); + memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); } diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index c962fe0..230595e 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -63,7 +63,7 @@ } } -void variant_romstage_entry(struct romstage_params *rp) +void variant_romstage_entry(struct pei_data *pei_data) { struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ @@ -93,6 +93,6 @@ { 0, USB_OC_PIN_SKIP }, /* P4; */ }; - memcpy(rp->pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); - memcpy(rp->pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); + memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); + memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); } diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index c3c01a3..4e02f73 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -50,7 +50,7 @@ } } -void variant_romstage_entry(struct romstage_params *rp) +void variant_romstage_entry(struct pei_data *pei_data) { struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ @@ -80,6 +80,6 @@ { 0, USB_OC_PIN_SKIP }, /* P4; */ }; - memcpy(rp->pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); - memcpy(rp->pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); + memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); + memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); } diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index f8760fd..2ea74df 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -112,10 +112,6 @@ }, }; - struct romstage_params romstage_params = { - .pei_data = &pei_data, - }; - /* Call into the real romstage main with this board's attributes. */ - romstage_common(&romstage_params); + romstage_common(&pei_data); } diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 8bcabd9..2e3f42e 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -68,9 +68,5 @@ }, }; - struct romstage_params romstage_params = { - .pei_data = &pei_data, - }; - - romstage_common(&romstage_params); + romstage_common(&pei_data); } diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index f322284..ca8c12c 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -190,10 +190,7 @@ void intel_northbridge_haswell_finalize_smm(void); struct pei_data; -struct romstage_params { - struct pei_data *pei_data; -}; -void romstage_common(const struct romstage_params *params); +void romstage_common(struct pei_data *pei_data); void mb_post_raminit_setup(void); /* optional */ void haswell_early_initialization(void); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index cb7b999..6c059da 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -22,7 +22,7 @@ { } -void romstage_common(const struct romstage_params *params) +void romstage_common(struct pei_data *pei_data) { int wake_from_s3; @@ -52,15 +52,15 @@ post_code(0x3a); /* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */ - params->pei_data->boot_mode = wake_from_s3 ? 2 : 0; + pei_data->boot_mode = wake_from_s3 ? 2 : 0; timestamp_add_now(TS_BEFORE_INITRAM); report_platform_info(); - copy_spd(params->pei_data); + copy_spd(pei_data); - sdram_initialize(params->pei_data); + sdram_initialize(pei_data); timestamp_add_now(TS_AFTER_INITRAM); @@ -71,7 +71,7 @@ if (!wake_from_s3) { cbmem_initialize_empty(); /* Save data returned from MRC on non-S3 resumes. */ - save_mrc_data(params->pei_data); + save_mrc_data(pei_data); } else if (cbmem_initialize()) { #if CONFIG(HAVE_ACPI_RESUME) /* Failed S3 resume, reset to come up cleanly */ @@ -81,7 +81,7 @@ haswell_unhide_peg(); - setup_sdram_meminfo(params->pei_data); + setup_sdram_meminfo(pei_data); romstage_handoff_init(wake_from_s3); -- To view, visit https://review.coreboot.org/c/coreboot/+/43106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab427592c332646e032a768719fc380c5794086b Gerrit-Change-Number: 43106 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: haswell: Make `copy_spd` a weak function
by Angel Pons (Code Review) 12 Jul '20

12 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43105 ) Change subject: haswell: Make `copy_spd` a weak function ...................................................................... haswell: Make `copy_spd` a weak function Instead of using function pointers, we can use weak functions. So, drop the pointer from `romstage_params`, leaving `pei_data` as the only remaining member. This will be cleaned up in a follow-up commit. Change-Id: I3b17d21ea7a650734119a5cab4892fcb158b589d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/slippy/variants/falco/romstage.c M src/mainboard/google/slippy/variants/leon/romstage.c M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/intel/baskingridge/romstage.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/raminit.h M src/northbridge/intel/haswell/romstage.c 8 files changed, 13 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/43105/1 diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 96fbbab..901c70e 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -13,7 +13,7 @@ #include "../../variant.h" /* Copy SPD data for on-board memory */ -static void copy_spd(struct pei_data *peid) +void copy_spd(struct pei_data *peid) { const int gpio_vector[] = {13, 9, 47, -1}; int spd_index = get_gpios(gpio_vector); @@ -84,6 +84,4 @@ memcpy(rp->pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); memcpy(rp->pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); - - rp->copy_spd = copy_spd; } diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index 35c5ef5..78c46dc 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -12,7 +12,7 @@ #include "../../variant.h" /* Copy SPD data for on-board memory */ -static void copy_spd(struct pei_data *peid) +void copy_spd(struct pei_data *peid) { const int gpio_vector[] = {13, 9, 47, -1}; int spd_index = get_gpios(gpio_vector); @@ -78,6 +78,4 @@ memcpy(rp->pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); memcpy(rp->pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); - - rp->copy_spd = copy_spd; } diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index b7daf89..c962fe0 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -14,7 +14,7 @@ #include "../../variant.h" /* Copy SPD data for on-board memory */ -static void copy_spd(struct pei_data *peid) +void copy_spd(struct pei_data *peid) { const int gpio_vector[] = {13, 9, 47, -1}; int spd_index = get_gpios(gpio_vector); @@ -95,6 +95,4 @@ memcpy(rp->pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); memcpy(rp->pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); - - rp->copy_spd = copy_spd; } diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index b35160f..c3c01a3 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -13,7 +13,7 @@ #include "../../variant.h" /* Copy SPD data for on-board memory */ -static void copy_spd(struct pei_data *peid) +void copy_spd(struct pei_data *peid) { const int gpio_vector[] = {13, 9, 47, -1}; int spd_index = get_gpios(gpio_vector); @@ -82,6 +82,4 @@ memcpy(rp->pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); memcpy(rp->pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); - - rp->copy_spd = copy_spd; } diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index b1f9854..f8760fd 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -114,7 +114,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .copy_spd = NULL, }; /* Call into the real romstage main with this board's attributes. */ diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index eab1ef6..f322284 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -192,7 +192,6 @@ struct pei_data; struct romstage_params { struct pei_data *pei_data; - void (*copy_spd)(struct pei_data *peid); }; void romstage_common(const struct romstage_params *params); void mb_post_raminit_setup(void); /* optional */ diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index 562c24d..920ee0f 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -5,6 +5,9 @@ #include "pei_data.h" +/* Optional function to copy SPD data for on-board memory */ +void copy_spd(struct pei_data *peid); + void sdram_initialize(struct pei_data *pei_data); void setup_sdram_meminfo(struct pei_data *pei_data); int fixup_haswell_errata(void); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 9c70743..cb7b999 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -13,6 +13,11 @@ #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/me.h> +/* Copy SPD data for on-board memory */ +void __weak copy_spd(struct pei_data *peid) +{ +} + void __weak mb_post_raminit_setup(void) { } @@ -53,8 +58,7 @@ report_platform_info(); - if (params->copy_spd != NULL) - params->copy_spd(params->pei_data); + copy_spd(params->pei_data); sdram_initialize(params->pei_data); -- To view, visit https://review.coreboot.org/c/coreboot/+/43105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b17d21ea7a650734119a5cab4892fcb158b589d Gerrit-Change-Number: 43105 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: sb/intel/i82801dx: Correct SMBUS_IO_BASE value
by Angel Pons (Code Review) 11 Jul '20

11 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43023 ) Change subject: sb/intel/i82801dx: Correct SMBUS_IO_BASE value ...................................................................... sb/intel/i82801dx: Correct SMBUS_IO_BASE value The current value of 0x1000 would overlap the first PCI bridge IO window. As we commonly reserve IO range 0x0 .. 0x1000 for LPC and integrated device use, change SMBUS_IO_BASE to 0x400. This is the prevalent value among Intel southbridges, too. Change-Id: I5c299f001f9012d6766b155a2f5def5cff6e88d1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801dx/i82801dx.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/43023/1 diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index d5f09aa..cf85274 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -94,7 +94,7 @@ #define RTC_FAILED (1 <<2) -#define SMBUS_IO_BASE 0x1000 +#define SMBUS_IO_BASE 0x400 #define PM1_STS 0x00 #define WAK_STS (1 << 15) -- To view, visit https://review.coreboot.org/c/coreboot/+/43023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c299f001f9012d6766b155a2f5def5cff6e88d1 Gerrit-Change-Number: 43023 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/google/beltino: Move Super I/O init to bootblock
by Angel Pons (Code Review) 11 Jul '20

11 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43104 ) Change subject: mb/google/beltino: Move Super I/O init to bootblock ...................................................................... mb/google/beltino: Move Super I/O init to bootblock Also remove an unneeded `pch_enable_lpc` function call. Change-Id: I83158a655670d4e6cd91f6bf3332d1b6f9f655d1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/beltino/Makefile.inc A src/mainboard/google/beltino/bootblock.c M src/mainboard/google/beltino/romstage.c 3 files changed, 22 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/43104/1 diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index ee8b8e5..8c5d6c5 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only +bootblock-y += bootblock.c + romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c @@ -8,7 +10,8 @@ smm-y += smihandler.c variants/$(VARIANT_DIR)/led.c romstage-y += variants/$(VARIANT_DIR)/gpio.c -romstage-y += variants/$(VARIANT_DIR)/led.c + +bootblock-y += variants/$(VARIANT_DIR)/led.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/google/beltino/bootblock.c b/src/mainboard/google/beltino/bootblock.c new file mode 100644 index 0000000..c52059b --- /dev/null +++ b/src/mainboard/google/beltino/bootblock.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8772f/it8772f.h> +#include "onboard.h" + +void mainboard_config_superio(void) +{ + /* Early SuperIO setup */ + ite_kill_watchdog(IT8772F_GPIO_DEV); + it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV); + ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Turn on Power LED */ + set_power_led(LED_ON); +} diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 5d9c37c..6f95831 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -7,9 +7,6 @@ #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8772f/it8772f.h> -#include "onboard.h" void mainboard_config_rcba(void) { @@ -107,15 +104,6 @@ .pei_data = &pei_data, }; - /* Early SuperIO setup */ - ite_kill_watchdog(IT8772F_GPIO_DEV); - it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV); - pch_enable_lpc(); - ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* Turn on Power LED */ - set_power_led(LED_ON); - /* Call into the real romstage main with this board's attributes. */ romstage_common(&romstage_params); } -- To view, visit https://review.coreboot.org/c/coreboot/+/43104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83158a655670d4e6cd91f6bf3332d1b6f9f655d1 Gerrit-Change-Number: 43104 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 12

Change in coreboot[master]: drivers/usb/ehci_debug.c: Drop preprocessor usage
by Angel Pons (Code Review) 11 Jul '20

11 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43295 ) Change subject: drivers/usb/ehci_debug.c: Drop preprocessor usage ...................................................................... drivers/usb/ehci_debug.c: Drop preprocessor usage There's no need to use ugly preprocessor here when regular C conditional statements will work just fine. Change-Id: I5abd445a335b43fb95e4df087d44e82c3f44349b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/usb/ehci_debug.c 1 file changed, 14 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/43295/1 diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 5af8e2e..e5841d7 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -584,23 +584,21 @@ //return ret; next_debug_port: -#if CONFIG_USBDEBUG_DEFAULT_PORT == 0 - port_map_tried |= (1 << (debug_port - 1)); - new_debug_port = ((debug_port-1 + 1) % n_ports) + 1; - if (port_map_tried != ((1 << n_ports) - 1)) { - ehci_debug_select_port(new_debug_port); - goto try_next_port; + if (CONFIG_USBDEBUG_DEFAULT_PORT == 0) { + port_map_tried |= (1 << (debug_port - 1)); + new_debug_port = ((debug_port-1 + 1) % n_ports) + 1; + if (port_map_tried != ((1 << n_ports) - 1)) { + ehci_debug_select_port(new_debug_port); + goto try_next_port; + } + if (--playtimes) { + ehci_debug_select_port(new_debug_port); + goto try_next_time; + } + } else { + if (--playtimes) + goto try_next_time; } - if (--playtimes) { - ehci_debug_select_port(new_debug_port); - goto try_next_time; - } -#else - if (0) - goto try_next_port; - if (--playtimes) - goto try_next_time; -#endif return -10; } -- To view, visit https://review.coreboot.org/c/coreboot/+/43295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5abd445a335b43fb95e4df087d44e82c3f44349b Gerrit-Change-Number: 43295 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mb/asrock/b85m_pro4: Reduce Super I/O ACPI code
by Angel Pons (Code Review) 11 Jul '20

11 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42430 ) Change subject: mb/asrock/b85m_pro4: Reduce Super I/O ACPI code ...................................................................... mb/asrock/b85m_pro4: Reduce Super I/O ACPI code We only need ACPI for the PS/2 devices. Change-Id: I4cfad012684264b21284674e8e3713a5d8bb37be Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/acpi/superio.asl 1 file changed, 1 insertion(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/42430/1 diff --git a/src/mainboard/asrock/b85m_pro4/acpi/superio.asl b/src/mainboard/asrock/b85m_pro4/acpi/superio.asl index 4bdb4b9..ee2eabe 100644 --- a/src/mainboard/asrock/b85m_pro4/acpi/superio.asl +++ b/src/mainboard/asrock/b85m_pro4/acpi/superio.asl @@ -1,12 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#define SUPERIO_DEV SIO0 -#define SUPERIO_PNP_BASE 0x2e -#define NCT6776_SHOW_PP -#define NCT6776_SHOW_SP1 -#define NCT6776_SHOW_KBC -#define NCT6776_SHOW_HWM - -#undef NCT6776_SHOW_GPIO - -#include <superio/nuvoton/nct6776/acpi/superio.asl> +#include <drivers/pc80/pc/ps2_controller.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/42430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cfad012684264b21284674e8e3713a5d8bb37be Gerrit-Change-Number: 42430 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 7

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2020