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Change in coreboot[master]: vc/amd/pi/00660F01: Drop dead code
by Angel Pons (Code Review) 11 Jul '20

11 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43259 ) Change subject: vc/amd/pi/00660F01: Drop dead code ...................................................................... vc/amd/pi/00660F01: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I14c575ac20cd94af1cfbb1204e2923149ef2920d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/vendorcode/amd/pi/00660F01/AMD.h 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/43259/1 diff --git a/src/vendorcode/amd/pi/00660F01/AMD.h b/src/vendorcode/amd/pi/00660F01/AMD.h index 990261b..39ee56a 100644 --- a/src/vendorcode/amd/pi/00660F01/AMD.h +++ b/src/vendorcode/amd/pi/00660F01/AMD.h @@ -145,10 +145,6 @@ AMD_INIT_RESUME = 0x00029000, ///< AmdInitResume entry point handle AMD_RELEASE_STRUCT = 0x0002A000, ///< AmdReleaseStruct handle AMD_S3LATE_RESTORE = 0x0002B000, ///< AmdS3LateRestore entry point handle -#if 0 - /* This was removed, shifting everything else up.*/ - AMD_S3_SAVE = 0x0002C000, -#endif AMD_GET_APIC_ID = 0x0002C000, ///< AmdGetApicId entry point handle AMD_GET_PCI_ADDRESS = 0x0002D000, ///< AmdGetPciAddress entry point handle AMD_IDENTIFY_CORE = 0x0002E000, ///< AmdIdentifyCore general service handle -- To view, visit https://review.coreboot.org/c/coreboot/+/43259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14c575ac20cd94af1cfbb1204e2923149ef2920d Gerrit-Change-Number: 43259 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/hp/abm: Drop dead code
by Angel Pons (Code Review) 11 Jul '20

11 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43241 ) Change subject: mb/hp/abm: Drop dead code ...................................................................... mb/hp/abm: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I2a97954a36e5af37dc3c379c39afa24030daceea Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/hp/abm/acpi/ide.asl M src/mainboard/hp/abm/acpi/sata.asl M src/mainboard/hp/abm/acpi/usb_oc.asl 3 files changed, 0 insertions(+), 462 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/43241/1 diff --git a/src/mainboard/hp/abm/acpi/ide.asl b/src/mainboard/hp/abm/acpi/ide.asl index a1db5e9..c8d7172 100644 --- a/src/mainboard/hp/abm/acpi/ide.asl +++ b/src/mainboard/hp/abm/acpi/ide.asl @@ -1,233 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* No IDE functionality */ - -#if 0 -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - /* save total time of primary PIO master timing to PIO spd0 */ - Store(GTTM(PPTM), PSD0) - /* save total time of primary PIO slave Timing to PIO spd1 */ - Store(GTTM(PPTS), PSD1) - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} -#endif diff --git a/src/mainboard/hp/abm/acpi/sata.asl b/src/mainboard/hp/abm/acpi/sata.asl index f22d3df..659a076 100644 --- a/src/mainboard/hp/abm/acpi/sata.asl +++ b/src/mainboard/hp/abm/acpi/sata.asl @@ -1,133 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* No SATA functionality */ - -#if 0 -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} -#endif diff --git a/src/mainboard/hp/abm/acpi/usb_oc.asl b/src/mainboard/hp/abm/acpi/usb_oc.asl index 168efff..a5846fe 100644 --- a/src/mainboard/hp/abm/acpi/usb_oc.asl +++ b/src/mainboard/hp/abm/acpi/usb_oc.asl @@ -1,15 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* simple name description */ -/* -#include <acpi/acpi.h> -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ - /* USB overcurrent mapping pins. */ Name(UOM0, 0) Name(UOM1, 2) @@ -21,95 +11,3 @@ Name(UOM7, 2) Name(UOM8, 6) Name(UOM9, 6) - -/* USB Overcurrent GPEs */ - -#if 0 /* TODO: Update */ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - } - } -} -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/43241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a97954a36e5af37dc3c379c39afa24030daceea Gerrit-Change-Number: 43241 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI
by Raul Rangel (Code Review) 11 Jul '20

11 Jul '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43332 ) Change subject: soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI ...................................................................... soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI This provides the functionality to provide the GPE to the pci_xhci driver. BUG=b:154756391 TEST=Made sure trembyle compiles Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ice7203831a1f65ed32f3a6392fe02c4b17d42617 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/include/soc/mainboard.h A src/soc/amd/picasso/mainboard.c A src/soc/amd/picasso/xhci.c 5 files changed, 85 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/43332/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4d07af6..1e7f3ef 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -18,6 +18,7 @@ select X86_AMD_INIT_SIPI select ACPI_AMD_HARDWARE_SLEEP_VALUES select DRIVERS_I2C_DESIGNWARE + select DRIVERS_USB_PCI_XHCI select GENERIC_GPIO_LIB select IDT_IN_EVERY_STAGE select IOAPIC diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 060f78d..45ded6d 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -77,6 +77,8 @@ ramstage-y += config.c ramstage-y += update_microcode.c ramstage-y += graphics.c +ramstage-y += mainboard.c +ramstage-y += xhci.c smm-y += smihandler.c smm-y += smi_util.c diff --git a/src/soc/amd/picasso/include/soc/mainboard.h b/src/soc/amd/picasso/include/soc/mainboard.h new file mode 100644 index 0000000..55154d8 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/mainboard.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PICASSO_MAINBOARD_H__ +#define __PICASSO_MAINBOARD_H__ + +#include <stddef.h> +#include <soc/smi.h> + +/* + * Returns the GPE table for non GPIO devices. + * i.e., GEVENTS above 23 + */ +const struct sci_source *mainboard_get_gpe_table(size_t *num); + +#endif /* __PICASSO_MAINBOARD_H__ */ diff --git a/src/soc/amd/picasso/mainboard.c b/src/soc/amd/picasso/mainboard.c new file mode 100644 index 0000000..717a579 --- /dev/null +++ b/src/soc/amd/picasso/mainboard.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/mainboard.h> + +__weak const struct sci_source *mainboard_get_gpe_table(size_t *num) +{ + return NULL; +} diff --git a/src/soc/amd/picasso/xhci.c b/src/soc/amd/picasso/xhci.c new file mode 100644 index 0000000..9f3ea9b --- /dev/null +++ b/src/soc/amd/picasso/xhci.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/device.h> +#include <drivers/usb/pci_xhci/pci_xhci.h> +#include <soc/mainboard.h> +#include <soc/pci_devs.h> + +static const struct sci_source *get_matching_sci_source(unsigned int sci_type) +{ + const struct sci_source *sci_sources, *sci_source; + size_t sci_count; + unsigned int i; + + sci_sources = mainboard_get_gpe_table(&sci_count); + + if (!sci_sources) + return NULL; + + for (i = 0; i < sci_count; ++i) { + sci_source = &sci_sources[i]; + if (sci_source->scimap == sci_type) + return sci_source; + } + + return NULL; +} + +enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) +{ + const struct sci_source *sci_source; + unsigned int sci_type; + + if (dev->bus->dev->path.type != DEVICE_PATH_PCI) + return CB_ERR_ARG; + + if (dev->bus->dev->path.pci.devfn != PCIE_GPP_A_DEVFN) + return CB_ERR_ARG; + + if (dev->path.type != DEVICE_PATH_PCI) + return CB_ERR_ARG; + + if (dev->path.pci.devfn == XHCI0_DEVFN) + sci_type = SMITYPE_XHC0_PME; + else if (dev->path.pci.devfn == XHCI1_DEVFN) + sci_type = SMITYPE_XHC1_PME; + else + return CB_ERR_ARG; + + sci_source = get_matching_sci_source(sci_type); + + if (!sci_source) { + *gpe = -1; + return CB_SUCCESS; + } + + *gpe = sci_source->gpe; + return CB_SUCCESS; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/43332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice7203831a1f65ed32f3a6392fe02c4b17d42617 Gerrit-Change-Number: 43332 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: drivers/usb/pci_xhci: Add Picasso xHCI controllers
by Raul Rangel (Code Review) 11 Jul '20

11 Jul '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43331 ) Change subject: drivers/usb/pci_xhci: Add Picasso xHCI controllers ...................................................................... drivers/usb/pci_xhci: Add Picasso xHCI controllers BUG=b:154756391 TEST=Dump ACPI table and see xHCI nodes being created. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I1541dc8ebf314a204708a7767f30f4db72990907 --- M src/drivers/usb/pci_xhci/pci_xhci.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/43331/1 diff --git a/src/drivers/usb/pci_xhci/pci_xhci.c b/src/drivers/usb/pci_xhci/pci_xhci.c index 659b009..6dcc588 100644 --- a/src/drivers/usb/pci_xhci/pci_xhci.c +++ b/src/drivers/usb/pci_xhci/pci_xhci.c @@ -174,6 +174,9 @@ }; static const unsigned short amd_pci_device_ids[] = { + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI1, + PCI_DEVICE_ID_AMD_FAM17H_MODEL20H_XHCI0, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/43331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1541dc8ebf314a204708a7767f30f4db72990907 Gerrit-Change-Number: 43331 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/amd/picasso: Switch to using xhci common block
by Raul Rangel (Code Review) 11 Jul '20

11 Jul '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41901 ) Change subject: soc/amd/picasso: Switch to using xhci common block ...................................................................... soc/amd/picasso: Switch to using xhci common block BUG=b:154756391 TEST=Boot trembyle and look at ACPI table Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I3e9973dd416ccd51971f4d9410bed991eb7c3c41 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/acpi/sb_pci0_fch.asl D src/soc/amd/picasso/acpi/usb.asl D src/soc/amd/picasso/usb.c 5 files changed, 1 insertion(+), 102 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/41901/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index ddbc6c3..0b17c25 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -40,6 +40,7 @@ select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_PSP_GEN2 + select SOC_AMD_COMMON_BLOCK_XHCI select PROVIDES_ROM_SHARING select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index d0046ea..d1ff319 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -56,7 +56,6 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-$(CONFIG_PICASSO_UART) += uart.c -ramstage-y += usb.c ramstage-y += tsc_freq.c ramstage-y += finalize.c ramstage-y += soc_util.c diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 751c178..c7c424f 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -27,8 +27,6 @@ Name(_ADR, 0x00140000) } /* end SBUS */ -#include "usb.asl" - /* 0:14.2 - I2S Audio */ /* 0:14.3 - LPC */ diff --git a/src/soc/amd/picasso/acpi/usb.asl b/src/soc/amd/picasso/acpi/usb.asl deleted file mode 100644 index f902100..0000000 --- a/src/soc/amd/picasso/acpi/usb.asl +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* 0:12.0 - EHCI */ -Device(EHC0) { - Name(_ADR, 0x00120000) - Name(_PRW, Package() { 0xb, 3 }) - Device (RHUB) { - Name (_ADR, Zero) - Device (HS01) { Name (_ADR, 1) } - Device (HS02) { Name (_ADR, 2) } - Device (HS03) { Name (_ADR, 3) } - Device (HS04) { Name (_ADR, 4) } - Device (HS05) { Name (_ADR, 5) } - Device (HS06) { Name (_ADR, 6) } - Device (HS07) { Name (_ADR, 7) } - Device (HS08) { Name (_ADR, 8) } - } - - Method(_S0W,0) { - Return(0) - } - - Method(_S3W,0) { - Return(4) - } - - Method(_S4W,0) { - Return(4) - } -} /* end EHC0 */ - - -/* 0:10.0 - XHCI 0*/ -Device(XHC0) { - Name(_ADR, 0x00100000) - Name(_PRW, Package() { 0xb, 3 }) - Device (SS01) { Name (_ADR, 1) } - Device (SS02) { Name (_ADR, 2) } - Device (SS03) { Name (_ADR, 3) } - - Method(_S0W,0) { - Return(0) - } - - Method(_S3W,0) { - Return(4) - } - - Method(_S4W,0) { - Return(4) - } - -} /* end XHC0 */ diff --git a/src/soc/amd/picasso/usb.c b/src/soc/amd/picasso/usb.c deleted file mode 100644 index a507956..0000000 --- a/src/soc/amd/picasso/usb.c +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <device/pci_ehci.h> -#include <soc/acpi.h> -#include <soc/pci_devs.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> - -static void picasso_usb_init(struct device *dev) -{ - /* USB overcurrent configuration is programmed inside the FSP */ - - printk(BIOS_DEBUG, "%s\n", __func__); -} - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations usb_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = picasso_usb_init, - .scan_bus = scan_static_bus, - .acpi_name = soc_acpi_name, - .ops_pci = &lops_pci, -}; - -static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0, - PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI1, - PCI_DEVICE_ID_AMD_FAM17H_MODEL20H_XHCI0, - 0 -}; - -static const struct pci_driver usb_0_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_AMD, - .devices = pci_device_ids, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/41901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e9973dd416ccd51971f4d9410bed991eb7c3c41 Gerrit-Change-Number: 41901 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: soc/amd/common/blocks/xhci: Add an AMD block to generate xHCI ACPI nodes
by Raul Rangel (Code Review) 11 Jul '20

11 Jul '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41900 ) Change subject: soc/amd/common/blocks/xhci: Add an AMD block to generate xHCI ACPI nodes ...................................................................... soc/amd/common/blocks/xhci: Add an AMD block to generate xHCI ACPI nodes We can use xhci_for_each_ext_cap to inspect the xHC so we generate the correct number of device nodes. BUG=b:154756391 TEST=Boot trembyle and look at ACPI table. See all xHCI nodes. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I44ebaef342e45923bc181ceebef882358d33f0d1 --- A src/soc/amd/common/block/xhci/Kconfig A src/soc/amd/common/block/xhci/Makefile.inc A src/soc/amd/common/block/xhci/xhci.c 3 files changed, 128 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/41900/1 diff --git a/src/soc/amd/common/block/xhci/Kconfig b/src/soc/amd/common/block/xhci/Kconfig new file mode 100644 index 0000000..5751907 --- /dev/null +++ b/src/soc/amd/common/block/xhci/Kconfig @@ -0,0 +1,5 @@ +config SOC_AMD_COMMON_BLOCK_XHCI + bool + default n + help + Select this option to use AMD common xhci driver support. diff --git a/src/soc/amd/common/block/xhci/Makefile.inc b/src/soc/amd/common/block/xhci/Makefile.inc new file mode 100644 index 0000000..2387450 --- /dev/null +++ b/src/soc/amd/common/block/xhci/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_XHCI) += xhci.c diff --git a/src/soc/amd/common/block/xhci/xhci.c b/src/soc/amd/common/block/xhci/xhci.c new file mode 100644 index 0000000..72bb9bb --- /dev/null +++ b/src/soc/amd/common/block/xhci/xhci.c @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <amdblocks/gpio_banks.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <device/pci_ehci.h> +#include <soc/acpi.h> +#include <soc/pci_devs.h> +#include <soc/smi.h> +#include <soc/southbridge.h> +#include <amdblocks/acpimmio.h> +#include <device/xhci.h> + +#define XHCI_GEVENT GEVENT_31 + +struct port_counts { + unsigned int high_speed; + unsigned int super_speed; +}; + +static void handle_xhci_ext_cap(void *context, const struct xhci_ext_cap *cap) +{ + const struct xhci_supported_protocol *data; + const char *format; + char buf[16]; + struct port_counts *counts = context; + unsigned int *dev_num; + + if (cap->cap_id != XHCI_ECP_CAP_ID_SUPP) + return; + + data = &cap->supported_protocol; + + if (memcmp(data->name, "USB ", 4)) { + printk(BIOS_INFO, "%s: Unknown Protocol: %.*s\n", __func__, + (int)sizeof(data->name), data->name); + return; + } + + if (data->major_rev == 3) { + format = "SS%02d"; + dev_num = &counts->super_speed; + } else if (data->major_rev == 2) { + format = "HS%02d"; + dev_num = &counts->high_speed; + } else { + printk(BIOS_INFO, "%s: Unknown USB Version: %#x\n", __func__, data->major_rev); + return; + } + + for (unsigned int i = 0; i < data->port_count; ++i) { + snprintf(buf, sizeof(buf), format, ++(*dev_num)); + acpigen_write_device(buf); + acpigen_write_name_byte("_ADR", data->port_offset + i); + acpigen_pop_len(); + } +} + +static void xhci_add_devices(const struct device *device) +{ + struct port_counts counts = {0, 0}; + + acpigen_write_device("RHUB"); + acpigen_write_name_integer("_ADR", 0x00000000); + + xhci_for_each_ext_cap(device, &counts, handle_xhci_ext_cap); + + /* Exit RHUB device */ + acpigen_pop_len(); +} + +static void xhci_fill_ssdt_generator(const struct device *device) +{ + printk(BIOS_INFO, "xHCI SSDT generation\n"); + + /* Write SSDT entry for xHCI controller */ + acpigen_write_scope(acpi_device_scope(device)); + acpigen_write_device(acpi_device_name(device)); + acpigen_write_ADR_pci_device(device); + acpigen_write_STA(acpi_device_status(device)); + acpigen_write_PRW(XHCI_GEVENT, 3); + + xhci_add_devices(device); + + acpigen_write_name_integer("_S0W", 0); + acpigen_write_name_integer("_S3W", 4); + acpigen_write_name_integer("_S4W", 4); + + acpigen_pop_len(); // xHCI device + + acpigen_pop_len(); // Bridge scope +} + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .scan_bus = scan_static_bus, + .ops_pci = &lops_pci, + .acpi_fill_ssdt = xhci_fill_ssdt_generator, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI1, + PCI_DEVICE_ID_AMD_FAM17H_MODEL20H_XHCI0, + 0 +}; + +static const struct pci_driver usb_0_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_AMD, + .devices = pci_device_ids, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/41900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44ebaef342e45923bc181ceebef882358d33f0d1 Gerrit-Change-Number: 41900 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 27

Change in coreboot[master]: soc/amd/picasso: Add missing include to smi.h
by Raul Rangel (Code Review) 11 Jul '20

11 Jul '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43330 ) Change subject: soc/amd/picasso: Add missing include to smi.h ...................................................................... soc/amd/picasso: Add missing include to smi.h BUG=b:154756391 TEST=Don't see build failure. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I36b81643c29ec1e7978d521206fbc366060ab286 --- M src/soc/amd/picasso/include/soc/smi.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/43330/1 diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index 02a23f5..d66f093 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -3,6 +3,7 @@ #ifndef __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ #define __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ +#include <stdint.h> #define SMI_GEVENTS 24 #define SCIMAPS 58 -- To view, visit https://review.coreboot.org/c/coreboot/+/43330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36b81643c29ec1e7978d521206fbc366060ab286 Gerrit-Change-Number: 43330 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

6 13

Change in coreboot[master]: mb/google/zork: Enable xHCI Gevents
by Raul Rangel (Code Review) 11 Jul '20

11 Jul '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41973 ) Change subject: mb/google/zork: Enable xHCI Gevents ...................................................................... mb/google/zork: Enable xHCI Gevents This allows the xHCI to wake the system from S3. BUG=b:154756391 TEST=Boot trembyle and inspect the smi registers. S3 doesn't currently work upstream, so I can't fully test. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I6ba1fc5756c17da4dc1727425af17c4582c01a18 --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 2 files changed, 30 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/41973/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index b5b2847..d7a2db8 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -3,6 +3,7 @@ #include <baseboard/variants.h> #include <soc/gpio.h> #include <soc/smi.h> +#include <soc/xhci.h> #include <stdlib.h> #include <boardid.h> #include <variant/gpio.h> @@ -225,6 +226,15 @@ return gpio_set_stage_ram; } +static const struct sci_source gpe_table[] = { + { + .scimap = SMITYPE_XHC0_PME, + .gpe = XHCI_GEVENT, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + } +}; + /* * This function is still needed for boards that sets gevents above 23 * that will generate SCI or SMI. Normally this function @@ -234,5 +244,6 @@ */ const __weak struct sci_source *get_gpe_table(size_t *num) { - return NULL; + *num = ARRAY_SIZE(gpe_table); + return gpe_table; } diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 6101330..456ac40 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -3,6 +3,7 @@ #include <baseboard/variants.h> #include <soc/gpio.h> #include <soc/smi.h> +#include <soc/xhci.h> #include <stdlib.h> #include <boardid.h> #include <variant/gpio.h> @@ -234,6 +235,21 @@ return gpio_set_stage_ram; } +static const struct sci_source gpe_table[] = { + { + .scimap = SMITYPE_XHC0_PME, + .gpe = XHCI_GEVENT, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + }, + { + .scimap = SMITYPE_XHC1_PME, + .gpe = XHCI_GEVENT, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + } +}; + /* * This function is still needed for boards that sets gevents above 23 * that will generate SCI or SMI. Normally this function @@ -243,5 +259,6 @@ */ const __weak struct sci_source *get_gpe_table(size_t *num) { - return NULL; + *num = ARRAY_SIZE(gpe_table); + return gpe_table; } -- To view, visit https://review.coreboot.org/c/coreboot/+/41973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ba1fc5756c17da4dc1727425af17c4582c01a18 Gerrit-Change-Number: 41973 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

7 23

Change in coreboot[master]: include/acpi/acpi.h: Add ACPI_NAME_BUFFER_SIZE
by Raul Rangel (Code Review) 11 Jul '20

11 Jul '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43329 ) Change subject: include/acpi/acpi.h: Add ACPI_NAME_BUFFER_SIZE ...................................................................... include/acpi/acpi.h: Add ACPI_NAME_BUFFER_SIZE ACPI names can only be 4 characters long. Define a constant that defines the size of the name + the NULL terminator. BUG=b:154756391 TEST=none Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Iad230c029f324005620ddad66c433ada26be78cc --- M src/include/acpi/acpi.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/43329/1 diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index cd99899..dabbb2b 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -52,6 +52,8 @@ #define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ #define ASLC "CORE" /* Must be exactly 4 bytes long! */ +#define ACPI_NAME_BUFFER_SIZE 5 /* 4 chars + 1 NULL */ + /* * The assigned ACPI ID for the coreboot project is 'BOOT' * http://www.uefi.org/acpi_id_list -- To view, visit https://review.coreboot.org/c/coreboot/+/43329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad230c029f324005620ddad66c433ada26be78cc Gerrit-Change-Number: 43329 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: lib: Add ASan support to ramstage on x86 arch
by Harshit Sharma (Code Review) 11 Jul '20

11 Jul '20

Harshit Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42496 ) Change subject: lib: Add ASan support to ramstage on x86 arch ...................................................................... Patch Set 19: > Patch Set 18: Code-Review+1 > > I rebased the series on master to be able to build it on ppc64le, rebuilt crossgcc, built an image for the ASRock E350M1 with KASAN enable, and it booted without errors. (I would have expected problems with AGESA, but maybe Coverity and the other static analyzers found all the bug already.) > > Great job! > > It’d be great if you rebased your series on origin/master. Thanks for testing it on your hardware. I've rebased it now. -- To view, visit https://review.coreboot.org/c/coreboot/+/42496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica06bd2be78fcfc79fa888721ed920d4e8248f3b Gerrit-Change-Number: 42496 Gerrit-PatchSet: 19 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 10 Jul 2020 22:21:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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