Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43326 )
Change subject: arch/x86: Drop CBMEM_TOP_BACKUP ......................................................................
arch/x86: Drop CBMEM_TOP_BACKUP
Code has evolved such that there seems to be little use for global definition of cbmem_top_chipset(). Even for AMD we had three different implementations.
Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/Makefile.inc D src/arch/x86/cbmem.c M src/cpu/amd/mtrr/amd_mtrr.c M src/drivers/amd/agesa/romstage.c M src/include/cbmem.h M src/northbridge/amd/agesa/Kconfig M src/northbridge/amd/agesa/family14/state_machine.c M src/northbridge/amd/agesa/family15tn/state_machine.c M src/northbridge/amd/agesa/family16kb/state_machine.c M src/northbridge/amd/pi/00730F01/state_machine.c M src/northbridge/amd/pi/Kconfig M src/soc/amd/common/block/acpimmio/biosram.c M src/soc/amd/common/block/include/amdblocks/biosram.h M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/stoneyridge/memmap.c 15 files changed, 23 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/43326/1
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index fa647b7..61e7edc 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -164,7 +164,6 @@ # gdt_init.S is included by entry32.inc when romstage is the first C # environment. romstage-y += gdt_init.S -romstage-y += cbmem.c romstage-y += cpu_common.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c deleted file mode 100644 index 353368a..0000000 --- a/src/arch/x86/cbmem.c +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cbmem.h> - -#if CONFIG(CBMEM_TOP_BACKUP) - -void *cbmem_top_chipset(void) -{ - /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ - return (void *)restore_top_of_low_cacheable(); -} - -#endif /* CBMEM_TOP_BACKUP */ diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 1234c82..fc3212f 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <cbmem.h> +#include <amdblocks/biosram.h> #include <console/console.h> #include <device/device.h> #include <arch/cpu.h> diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 617416a..29423ef 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -107,3 +107,9 @@ { romstage_main(); } + +void *cbmem_top_chipset(void) +{ + /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ + return (void *)restore_top_of_low_cacheable(); +} diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 4cc4045..b548cd9 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -139,17 +139,6 @@ static cbmem_init_hook_t init_fn_ ## _unused3_ = init_fn_; #endif /* ENV_RAMSTAGE */
- -/* Any new chipset and board must implement cbmem_top() for both - * romstage and ramstage to support early features like COLLECT_TIMESTAMPS - * and CBMEM_CONSOLE. Sometimes it is necessary to have cbmem_top() - * value stored in nvram to enable early recovery on S3 path. - */ -#if ENV_X86 -void backup_top_of_low_cacheable(uintptr_t ramtop); -uintptr_t restore_top_of_low_cacheable(void); -#endif - /* * Returns 0 for the stages where we know that cbmem does not come online. * Even if this function returns 1 for romstage, depending upon the point in diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 6711f87..6f6e3d6 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -3,7 +3,6 @@ config NORTHBRIDGE_AMD_AGESA bool default CPU_AMD_AGESA - select CBMEM_TOP_BACKUP
if NORTHBRIDGE_AMD_AGESA
diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index 202cdaa..36e5fd9 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -2,8 +2,8 @@
#include <Porting.h> #include <AGESA.h> +#include <amdblocks/biosram.h> #include <arch/io.h> -#include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> #include <device/device.h> diff --git a/src/northbridge/amd/agesa/family15tn/state_machine.c b/src/northbridge/amd/agesa/family15tn/state_machine.c index 8d450f9..29c1d87 100644 --- a/src/northbridge/amd/agesa/family15tn/state_machine.c +++ b/src/northbridge/amd/agesa/family15tn/state_machine.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <amdblocks/biosram.h> + #include <Porting.h> #include <AGESA.h> - -#include <cbmem.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h>
diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c index 58bc345..cbf0313 100644 --- a/src/northbridge/amd/agesa/family16kb/state_machine.c +++ b/src/northbridge/amd/agesa/family16kb/state_machine.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <amdblocks/biosram.h> + #include <Porting.h> #include <AGESA.h> - -#include <cbmem.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h>
diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c index f3c45a0..a97faeb 100644 --- a/src/northbridge/amd/pi/00730F01/state_machine.c +++ b/src/northbridge/amd/pi/00730F01/state_machine.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <amdblocks/biosram.h> + #include "Porting.h" #include "AGESA.h"
-#include <cbmem.h> #include <device/device.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index e8c3530..833afae 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -4,7 +4,6 @@ bool default y if CPU_AMD_PI default n - select CBMEM_TOP_BACKUP
if NORTHBRIDGE_AMD_PI
diff --git a/src/soc/amd/common/block/acpimmio/biosram.c b/src/soc/amd/common/block/acpimmio/biosram.c index b01c196..06bbed9 100644 --- a/src/soc/amd/common/block/acpimmio/biosram.c +++ b/src/soc/amd/common/block/acpimmio/biosram.c @@ -2,7 +2,6 @@
#include <amdblocks/acpimmio.h> #include <amdblocks/biosram.h> -#include <cbmem.h> #include <device/mmio.h> #include <stdint.h>
diff --git a/src/soc/amd/common/block/include/amdblocks/biosram.h b/src/soc/amd/common/block/include/amdblocks/biosram.h index 39ce112..226fc17 100644 --- a/src/soc/amd/common/block/include/amdblocks/biosram.h +++ b/src/soc/amd/common/block/include/amdblocks/biosram.h @@ -5,6 +5,14 @@
#include <stdint.h>
+/* Any new chipset and board must implement cbmem_top() for both + * romstage and ramstage to support early features like COLLECT_TIMESTAMPS + * and CBMEM_CONSOLE. With AMD it is necessary to have cbmem_top() + * value stored in nvram to enable early recovery on S3 path. + */ +void backup_top_of_low_cacheable(uintptr_t ramtop); +uintptr_t restore_top_of_low_cacheable(void); + /* Returns the bootblock C entry point for APs */ void *get_ap_entry_ptr(void); /* Used by BSP to store the bootblock entry point for APs */ diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index de9144c..ff52fbd 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <timestamp.h> #include <amdblocks/biosram.h> diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 9807905..67a4319 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -13,7 +13,7 @@ #include <arch/bert_storage.h> #include <soc/northbridge.h> #include <soc/iomap.h> -#include <amdblocks/acpimmio.h> +#include <amdblocks/biosram.h>
#if CONFIG(ACPI_BERT) #if CONFIG_SMM_TSEG_SIZE == 0x0
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43326 )
Change subject: arch/x86: Drop CBMEM_TOP_BACKUP ......................................................................
Patch Set 1: Code-Review+2
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43326 )
Change subject: arch/x86: Drop CBMEM_TOP_BACKUP ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43326 )
Change subject: arch/x86: Drop CBMEM_TOP_BACKUP ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43326/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43326/1//COMMIT_MSG@7 PS1, Line 7: CBMEM_TOP_BACKUP Also drop it from src/arch/x86/Kconfig please.
Hello build bot (Jenkins), Raul Rangel, Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43326
to look at the new patch set (#2).
Change subject: arch/x86: Drop CBMEM_TOP_BACKUP ......................................................................
arch/x86: Drop CBMEM_TOP_BACKUP
Code has evolved such that there seems to be little use for global definition of cbmem_top_chipset(). Even for AMD we had three different implementations.
Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/Kconfig M src/arch/x86/Makefile.inc D src/arch/x86/cbmem.c M src/cpu/amd/mtrr/amd_mtrr.c M src/drivers/amd/agesa/romstage.c M src/include/cbmem.h M src/northbridge/amd/agesa/Kconfig M src/northbridge/amd/agesa/family14/state_machine.c M src/northbridge/amd/agesa/family15tn/state_machine.c M src/northbridge/amd/agesa/family16kb/state_machine.c M src/northbridge/amd/pi/00730F01/state_machine.c M src/northbridge/amd/pi/Kconfig M src/soc/amd/common/block/acpimmio/biosram.c M src/soc/amd/common/block/include/amdblocks/biosram.h M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/stoneyridge/memmap.c 16 files changed, 23 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/43326/2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43326 )
Change subject: arch/x86: Drop CBMEM_TOP_BACKUP ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43326/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43326/1//COMMIT_MSG@7 PS1, Line 7: CBMEM_TOP_BACKUP
Also drop it from src/arch/x86/Kconfig please.
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43326 )
Change subject: arch/x86: Drop CBMEM_TOP_BACKUP ......................................................................
Patch Set 2: Code-Review+2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43326 )
Change subject: arch/x86: Drop CBMEM_TOP_BACKUP ......................................................................
Patch Set 2: Code-Review+2
Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43326 )
Change subject: arch/x86: Drop CBMEM_TOP_BACKUP ......................................................................
arch/x86: Drop CBMEM_TOP_BACKUP
Code has evolved such that there seems to be little use for global definition of cbmem_top_chipset(). Even for AMD we had three different implementations.
Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/arch/x86/Kconfig M src/arch/x86/Makefile.inc D src/arch/x86/cbmem.c M src/cpu/amd/mtrr/amd_mtrr.c M src/drivers/amd/agesa/romstage.c M src/include/cbmem.h M src/northbridge/amd/agesa/Kconfig M src/northbridge/amd/agesa/family14/state_machine.c M src/northbridge/amd/agesa/family15tn/state_machine.c M src/northbridge/amd/agesa/family16kb/state_machine.c M src/northbridge/amd/pi/00730F01/state_machine.c M src/northbridge/amd/pi/Kconfig M src/soc/amd/common/block/acpimmio/biosram.c M src/soc/amd/common/block/include/amdblocks/biosram.h M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/stoneyridge/memmap.c 16 files changed, 23 insertions(+), 43 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 968d784..660ff2d 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -133,12 +133,6 @@ int default 2
-config CBMEM_TOP_BACKUP - def_bool n - help - Platform implements non-volatile storage to cache cbmem_top() - over stage transitions and optionally also over S3 suspend. - config PRERAM_CBMEM_CONSOLE_SIZE hex default 0xc00 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index fa647b7..61e7edc 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -164,7 +164,6 @@ # gdt_init.S is included by entry32.inc when romstage is the first C # environment. romstage-y += gdt_init.S -romstage-y += cbmem.c romstage-y += cpu_common.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c deleted file mode 100644 index 353368a..0000000 --- a/src/arch/x86/cbmem.c +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cbmem.h> - -#if CONFIG(CBMEM_TOP_BACKUP) - -void *cbmem_top_chipset(void) -{ - /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ - return (void *)restore_top_of_low_cacheable(); -} - -#endif /* CBMEM_TOP_BACKUP */ diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 1234c82..fc3212f 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <cbmem.h> +#include <amdblocks/biosram.h> #include <console/console.h> #include <device/device.h> #include <arch/cpu.h> diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 617416a..29423ef 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -107,3 +107,9 @@ { romstage_main(); } + +void *cbmem_top_chipset(void) +{ + /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ + return (void *)restore_top_of_low_cacheable(); +} diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 4cc4045..b548cd9 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -139,17 +139,6 @@ static cbmem_init_hook_t init_fn_ ## _unused3_ = init_fn_; #endif /* ENV_RAMSTAGE */
- -/* Any new chipset and board must implement cbmem_top() for both - * romstage and ramstage to support early features like COLLECT_TIMESTAMPS - * and CBMEM_CONSOLE. Sometimes it is necessary to have cbmem_top() - * value stored in nvram to enable early recovery on S3 path. - */ -#if ENV_X86 -void backup_top_of_low_cacheable(uintptr_t ramtop); -uintptr_t restore_top_of_low_cacheable(void); -#endif - /* * Returns 0 for the stages where we know that cbmem does not come online. * Even if this function returns 1 for romstage, depending upon the point in diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 6711f87..6f6e3d6 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -3,7 +3,6 @@ config NORTHBRIDGE_AMD_AGESA bool default CPU_AMD_AGESA - select CBMEM_TOP_BACKUP
if NORTHBRIDGE_AMD_AGESA
diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index 202cdaa..36e5fd9 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -2,8 +2,8 @@
#include <Porting.h> #include <AGESA.h> +#include <amdblocks/biosram.h> #include <arch/io.h> -#include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> #include <device/device.h> diff --git a/src/northbridge/amd/agesa/family15tn/state_machine.c b/src/northbridge/amd/agesa/family15tn/state_machine.c index 8d450f9..29c1d87 100644 --- a/src/northbridge/amd/agesa/family15tn/state_machine.c +++ b/src/northbridge/amd/agesa/family15tn/state_machine.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <amdblocks/biosram.h> + #include <Porting.h> #include <AGESA.h> - -#include <cbmem.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h>
diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c index 58bc345..cbf0313 100644 --- a/src/northbridge/amd/agesa/family16kb/state_machine.c +++ b/src/northbridge/amd/agesa/family16kb/state_machine.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <amdblocks/biosram.h> + #include <Porting.h> #include <AGESA.h> - -#include <cbmem.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h>
diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c index f3c45a0..a97faeb 100644 --- a/src/northbridge/amd/pi/00730F01/state_machine.c +++ b/src/northbridge/amd/pi/00730F01/state_machine.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <amdblocks/biosram.h> + #include "Porting.h" #include "AGESA.h"
-#include <cbmem.h> #include <device/device.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index e8c3530..833afae 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -4,7 +4,6 @@ bool default y if CPU_AMD_PI default n - select CBMEM_TOP_BACKUP
if NORTHBRIDGE_AMD_PI
diff --git a/src/soc/amd/common/block/acpimmio/biosram.c b/src/soc/amd/common/block/acpimmio/biosram.c index b01c196..06bbed9 100644 --- a/src/soc/amd/common/block/acpimmio/biosram.c +++ b/src/soc/amd/common/block/acpimmio/biosram.c @@ -2,7 +2,6 @@
#include <amdblocks/acpimmio.h> #include <amdblocks/biosram.h> -#include <cbmem.h> #include <device/mmio.h> #include <stdint.h>
diff --git a/src/soc/amd/common/block/include/amdblocks/biosram.h b/src/soc/amd/common/block/include/amdblocks/biosram.h index 39ce112..226fc17 100644 --- a/src/soc/amd/common/block/include/amdblocks/biosram.h +++ b/src/soc/amd/common/block/include/amdblocks/biosram.h @@ -5,6 +5,14 @@
#include <stdint.h>
+/* Any new chipset and board must implement cbmem_top() for both + * romstage and ramstage to support early features like COLLECT_TIMESTAMPS + * and CBMEM_CONSOLE. With AMD it is necessary to have cbmem_top() + * value stored in nvram to enable early recovery on S3 path. + */ +void backup_top_of_low_cacheable(uintptr_t ramtop); +uintptr_t restore_top_of_low_cacheable(void); + /* Returns the bootblock C entry point for APs */ void *get_ap_entry_ptr(void); /* Used by BSP to store the bootblock entry point for APs */ diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index de9144c..ff52fbd 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <timestamp.h> #include <amdblocks/biosram.h> diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 9807905..67a4319 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -13,7 +13,7 @@ #include <arch/bert_storage.h> #include <soc/northbridge.h> #include <soc/iomap.h> -#include <amdblocks/acpimmio.h> +#include <amdblocks/biosram.h>
#if CONFIG(ACPI_BERT) #if CONFIG_SMM_TSEG_SIZE == 0x0
-
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Kyösti Mälkki (Code Review)
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