coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

1 participants
2826 discussions

Change in coreboot[master]: soc/intel/tigerlake: update elog to include CSME reset causes
by Derek Huang (Code Review) 03 Jun '20

03 Jun '20

Derek Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41026 ) Change subject: soc/intel/tigerlake: update elog to include CSME reset causes ...................................................................... soc/intel/tigerlake: update elog to include CSME reset causes Call out the CSME-initiated bits from HPR_CAUSE0 register and update the elog to include reset causes Change-Id: I32ffb55ff2ad26ec4e7609c41fc65e021a327a14 Signed-off-by: derek.huang <derek.huang(a)intel.corp-partner.google.com> --- M src/soc/intel/tigerlake/elog.c 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/41026/1 diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index 2aceea0..5b6c9db 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -62,6 +62,18 @@ if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) elog_add_event(ELOG_TYPE_THERM_TRIP); + /* CSME-Initiated Host Reset with power down */ + if (ps->hpr_cause0 & HPR_CAUSE0_MI_HRPD) + elog_add_event(ELOG_TYPE_MI_HRPD); + + /* CSME-Initiated Host Reset with power cycle */ + if (ps->hpr_cause0 & HPR_CAUSE0_MI_HRPC) + elog_add_event(ELOG_TYPE_MI_HRPC); + + /* CSME-Initiated Host Reset without power cycle */ + if (ps->hpr_cause0 & HPR_CAUSE0_MI_HR) + elog_add_event(ELOG_TYPE_MI_HR); + /* PWR_FLR Power Failure */ if (ps->gen_pmcon_a & PWR_FLR) elog_add_event(ELOG_TYPE_POWER_FAIL); -- To view, visit https://review.coreboot.org/c/coreboot/+/41026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32ffb55ff2ad26ec4e7609c41fc65e021a327a14 Gerrit-Change-Number: 41026 Gerrit-PatchSet: 1 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: drivers/intel/mipi_camera: camera SSDT generation
by Tim Wawrzynczak (Code Review) 03 Jun '20

03 Jun '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41607 ) Change subject: drivers/intel/mipi_camera: camera SSDT generation ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/41607/6/src/drivers/intel/mipi_cam… File src/drivers/intel/mipi_camera/camera.c: https://review.coreboot.org/c/coreboot/+/41607/6/src/drivers/intel/mipi_cam… PS6, Line 188: /* Method (_DSM, 4, NotSerialized) */ : acpigen_write_method("_DSM", 0x4); : : /* ToBuffer (Arg0, Local0) */ : acpigen_write_to_buffer(ARG0_OP, LOCAL0_OP); : : /* If (LEqual (Local0, ToUUID(uuid))) */ : acpigen_write_if(); : acpigen_emit_byte(LEQUAL_OP); : acpigen_emit_byte(LOCAL0_OP); : acpigen_write_uuid("822ace8f-2814-4174-a56b-5f029fe079ee"); : acpigen_write_return_string(config->sensor_name ? config->sensor_name : "UNKNOWN"); : acpigen_pop_len(); /* If */ : : /* If (LEqual (Local0, ToUUID(uuid))) */ : acpigen_write_if(); : acpigen_emit_byte(LEQUAL_OP); : acpigen_emit_byte(LOCAL0_OP); : acpigen_write_uuid("26257549-9271-4ca4-bb43-c4899d5a4881"); : /* ToInteger (Arg2, Local1) */ : acpigen_write_to_integer(ARG2_OP, LOCAL1_OP); : : /* If (LEqual (Local1, 1)) */ : acpigen_write_if_lequal_op_int(LOCAL1_OP, 1); : acpigen_write_return_integer((config->ssdb.vcm_type ? 1 : 0) + : (config->ssdb.rom_type ? 1 : 0) + 1); : acpigen_pop_len(); /* If Arg2=1 */ : : /* If (LEqual (Local1, 2)) */ : acpigen_write_if_lequal_op_int(LOCAL1_OP, 2); : acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 | : ((uint32_t)i2c_addr) << 8 | 0x0); /* type 0 for sensor */ : acpigen_pop_len(); /* If Arg2=2 */ : : if (config->ssdb.vcm_type) { : /* If (LEqual (Local1, 3)) */ : acpigen_write_if_lequal_op_int(LOCAL1_OP, 3); : acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 | /* type 1 for vcm */ : ((uint32_t)config->vcm_address) << 8 | 0x01); : acpigen_pop_len(); /* If Arg2=3 */ : } : if (config->ssdb.rom_type) { : /* If (LEqual (Local1, 3 or 4)) */ : acpigen_write_if_lequal_op_int(LOCAL1_OP, 3 + (config->ssdb.vcm_type ? 1 : 0)); : acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 | /* type 2 for rom */ : ((uint32_t)config->rom_address) << 8 | 0x02); : acpigen_pop_len(); /* If Arg2=3 or 4 */ : } : : acpigen_pop_len(); /* If uuid */ : : /* Return (Buffer (One) { 0x0 }) */ : acpigen_write_return_singleton_buffer(0x0); : : acpigen_pop_len(); /* Method _DSM */ > acpigen_write_dsm_uuid_arr() could be used for "26257549-9271-4ca4-bb43-c4899d5a4881", though "822ac […] They should be checking Arg2 as well; _DSM is a weird Method: "[Arg2] represents a specific function whose meaning is specific to the UUID and Revision ID." So you should be checking which Function is requested before returning anything. -- To view, visit https://review.coreboot.org/c/coreboot/+/41607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15979f345fb823df2560db269e902a1ea650b69e Gerrit-Change-Number: 41607 Gerrit-PatchSet: 10 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 03 Jun 2020 01:40:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt Delco <delco(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/xeon_sp/cpx: fix MADT ACPI table
by Jonathan Zhang (Code Review) 03 Jun '20

03 Jun '20

Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Johnny Lin, Jingle Hsu, Morgan Jang, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40383 to look at the new patch set (#19). Change subject: soc/intel/xeon_sp/cpx: fix MADT ACPI table ...................................................................... soc/intel/xeon_sp/cpx: fix MADT ACPI table Fix MADT table generation to keep IIO stack design in consideration. Add cpu devices to DSDT. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com> Change-Id: If1bf6e39db545e227e9867aa8d24f7db1d820216 --- M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/include/soc/acpi.h M src/soc/intel/xeon_sp/cpx/include/soc/nvs.h M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h 5 files changed, 144 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/40383/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/40383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1bf6e39db545e227e9867aa8d24f7db1d820216 Gerrit-Change-Number: 40383 Gerrit-PatchSet: 19 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/xeon_sp/cpx: set up cpus
by Jonathan Zhang (Code Review) 03 Jun '20

03 Jun '20

Hello Philipp Deppenwiese, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth, Johnny Lin, Jingle Hsu, Morgan Jang, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40112 to look at the new patch set (#19). Change subject: soc/intel/xeon_sp/cpx: set up cpus ...................................................................... soc/intel/xeon_sp/cpx: set up cpus Set up cpus: * setup apic IDs. * setup MSR to enable fast string, speed step, etc. * Enable turbo Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com> Change-Id: I5765e98151f6ceebaabccc06db63d5911caf7ce8 --- M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h A src/soc/intel/xeon_sp/cpx/include/soc/msr.h M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/cpx/soc_util.c 6 files changed, 336 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/40112/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/40112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5765e98151f6ceebaabccc06db63d5911caf7ce8 Gerrit-Change-Number: 40112 Gerrit-PatchSet: 19 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/xeon_sp/cpx: add chip operation and PCIe enumeration
by Jonathan Zhang (Code Review) 03 Jun '20

03 Jun '20

Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth, Johnny Lin, Jingle Hsu, Subrata Banik, Furquan Shaikh, Aaron Durbin, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40110 to look at the new patch set (#19). Change subject: soc/intel/xeon_sp/cpx: add chip operation and PCIe enumeration ...................................................................... soc/intel/xeon_sp/cpx: add chip operation and PCIe enumeration Add PCIe enumeration and resource assignment/allocation. Xeon-SP processor family has split IIO design, where PCIe domain 0 is split into multiple stacks. Each stack has its own resource ranges (eg. IO resource, mem32 resource, mem64 resource). The stack itself is not PCIe device, it does not have config space to be probed/programmed. The stack is programmed by FSP. coreboot needs to take into account of stack when doing PCIe enumeration and resource allocation. Current coreboot PCIe resource allocator does not support the concept of split IIO stack, thus entire support is done locally in this patch. In near future, improvements will be done, first generalize for xeon-sp, then generalize for coreboot PCIe device code. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com> Change-Id: If461b1dc1f313d98b676dc9e91d08a1dbb9cb388 --- M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/chip.h M src/soc/intel/xeon_sp/cpx/include/soc/irq.h A src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h A src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/include/soc/util.h 7 files changed, 642 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/40110/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/40110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If461b1dc1f313d98b676dc9e91d08a1dbb9cb388 Gerrit-Change-Number: 40110 Gerrit-PatchSet: 19 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Morgan Jang Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/xeon_sp/cpx: enable cpu power/performance management
by Jonathan Zhang (Code Review) 03 Jun '20

03 Jun '20

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40112 ) Change subject: soc/intel/xeon_sp/cpx: enable cpu power/performance management ...................................................................... Patch Set 18: (1 comment) Thanks for the review! https://review.coreboot.org/c/coreboot/+/40112/9//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40112/9//COMMIT_MSG@11 PS9, Line 11: > I can split this change into two, one focus on NUMA tables, another on turbo enablement. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/40112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5765e98151f6ceebaabccc06db63d5911caf7ce8 Gerrit-Change-Number: 40112 Gerrit-PatchSet: 18 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jun 2020 23:35:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/xeon_sp/cpx: add chip operation and PCIe enumeration
by Jonathan Zhang (Code Review) 03 Jun '20

03 Jun '20

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40110 ) Change subject: soc/intel/xeon_sp/cpx: add chip operation and PCIe enumeration ...................................................................... Patch Set 18: (3 comments) Thanks for the review. We are planning for the next phase of work on this aspect. Some further requirement/design discussions are on-going; a RFC will be sent to the community once the ideas are more concrete, then we will work on implementation. https://review.coreboot.org/c/coreboot/+/40110/15/src/soc/intel/xeon_sp/cpx… File src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h: https://review.coreboot.org/c/coreboot/+/40110/15/src/soc/intel/xeon_sp/cpx… PS15, Line 19: MAX_SOCKET * MAX_LOGIC_IIO_STAC > They are provided at src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds. […] Done https://review.coreboot.org/c/coreboot/+/40110/15/src/soc/intel/xeon_sp/cpx… PS15, Line 22: uint8_t > yes, this is the same case for console.h as well. Done https://review.coreboot.org/c/coreboot/+/40110/15/src/soc/intel/xeon_sp/cpx… File src/soc/intel/xeon_sp/cpx/soc_util.c: https://review.coreboot.org/c/coreboot/+/40110/15/src/soc/intel/xeon_sp/cpx… PS15, Line 34: MAX_IIO_STACK > MAX_IIO_STACK is the maximum number of IIO stacks per socket. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/40110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If461b1dc1f313d98b676dc9e91d08a1dbb9cb388 Gerrit-Change-Number: 40110 Gerrit-PatchSet: 18 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Morgan Jang Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jun 2020 23:27:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: src/mainboard: drop now undefined option `wait_for_bmc` from devicetrees
by Michael Niewöhner (Code Review) 03 Jun '20

03 Jun '20

Michael Niewöhner has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/42021 ) Change subject: src/mainboard: drop now undefined option `wait_for_bmc` from devicetrees ...................................................................... Abandoned needed to be squashed due to build test failure -- To view, visit https://review.coreboot.org/c/coreboot/+/42021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb76d6c8abaa506358cd847bea0c776eb61db312 Gerrit-Change-Number: 42021 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Kollasch <jakllsch(a)kollasch.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: drivers/ipmi: drop redundant option `wait_for_bmc`
by Michael Niewöhner (Code Review) 03 Jun '20

03 Jun '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42020 ) Change subject: drivers/ipmi: drop redundant option `wait_for_bmc` ...................................................................... Uploaded patch set 2. -- To view, visit https://review.coreboot.org/c/coreboot/+/42020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id26f85e82a13f53a3731ab88035f2ae4bbffac00 Gerrit-Change-Number: 42020 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Kollasch <jakllsch(a)kollasch.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Jun 2020 22:48:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/ipmi: drop redundant option `wait_for_bmc`
by Michael Niewöhner (Code Review) 03 Jun '20

03 Jun '20

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Jonathan Kollasch, Paul Menzel, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42020 to look at the new patch set (#2). Change subject: drivers/ipmi: drop redundant option `wait_for_bmc` ...................................................................... drivers/ipmi: drop redundant option `wait_for_bmc` The boolean value of `bmc_boot_timeout` already reflects the corresponding value of `wait_for_bmc`. Drop the redundant option `wait_for_bmc` from the driver and the devicetrees. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: Id26f85e82a13f53a3731ab88035f2ae4bbffac00 --- M src/drivers/ipmi/chip.h M src/drivers/ipmi/ipmi_kcs_ops.c M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb M src/mainboard/supermicro/x9scl/devicetree.cb 5 files changed, 3 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/42020/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id26f85e82a13f53a3731ab88035f2ae4bbffac00 Gerrit-Change-Number: 42020 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Kollasch <jakllsch(a)kollasch.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2020