coreboot-gerrit June 2020

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Change in coreboot[master]: mb/google/hatch: Modify the puff fmd files to support CSE Lite SKU
by 9elements QA (Code Review) 03 Jun '20

03 Jun '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41198 ) Change subject: mb/google/hatch: Modify the puff fmd files to support CSE Lite SKU ...................................................................... Patch Set 11: Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4742 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4741 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4740 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4739 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/41198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d39a1bdeabf48fc740da67539f48a9ff72c442c Gerrit-Change-Number: 41198 Gerrit-PatchSet: 11 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sam McNally <sammc(a)google.com> Gerrit-Comment-Date: Wed, 03 Jun 2020 07:43:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch: Enable the CSE Lite SKU for Puff variants
by Furquan Shaikh (Code Review) 03 Jun '20

03 Jun '20

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41199 ) Change subject: mb/google/hatch: Enable the CSE Lite SKU for Puff variants ...................................................................... mb/google/hatch: Enable the CSE Lite SKU for Puff variants This patch enables enables the CSE Lite SKU for all the puff variant boards. BUG=b:143229683 TEST=Build and boot puff with CSE Lite SKU. Cq-Depend: chrome-internal:3046770 Change-Id: I0de6bca162b01870ca554ae97bc4a41cf66fef18 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41199 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/hatch/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Sridhar Siricilla: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index ed478f8..46aa4d1 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -12,6 +12,7 @@ select RT8168_SET_LED_MODE select ROMSTAGE_SPD_SMBUS select SPD_READ_BY_WORD + select SOC_INTEL_CSE_LITE_SKU config BOARD_GOOGLE_HATCH_COMMON def_bool n -- To view, visit https://review.coreboot.org/c/coreboot/+/41199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0de6bca162b01870ca554ae97bc4a41cf66fef18 Gerrit-Change-Number: 41199 Gerrit-PatchSet: 9 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/hatch: Modify the puff fmd files to support CSE Lite SKU
by Furquan Shaikh (Code Review) 03 Jun '20

03 Jun '20

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41198 ) Change subject: mb/google/hatch: Modify the puff fmd files to support CSE Lite SKU ...................................................................... mb/google/hatch: Modify the puff fmd files to support CSE Lite SKU This patch modified the puff fmd files to support CSE Lite SKU. * Reduce the SI_ALL size to 3MiB since ME binary size is less than 2.5MiB. * Increase the FW_MAIN_A/B size to accommodate the ME_RW update binary with CSE Lite SKU. BUG=b:154561163 TEST=Build and boot puff with CSE Lite SKU. Cq-Depend: chrome-internal:3046770 Change-Id: I4d39a1bdeabf48fc740da67539f48a9ff72c442c Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41198 Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/hatch/chromeos-puff-16MiB.fmd M src/mainboard/google/hatch/chromeos-puff-32MiB.fmd 2 files changed, 23 insertions(+), 23 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Sridhar Siricilla: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/hatch/chromeos-puff-16MiB.fmd b/src/mainboard/google/hatch/chromeos-puff-16MiB.fmd index 9f09819..61a0b0f 100644 --- a/src/mainboard/google/hatch/chromeos-puff-16MiB.fmd +++ b/src/mainboard/google/hatch/chromeos-puff-16MiB.fmd @@ -1,20 +1,20 @@ FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x400000 { + SI_ALL@0x0 0x300000 { SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x3ff000 + SI_ME@0x1000 0x2ff000 } - SI_BIOS@0x400000 0xc00000 { - RW_SECTION_A@0x0 0x368000 { + SI_BIOS@0x300000 0xd00000 { + RW_SECTION_A@0x0 0x3e8000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x357fc0 - RW_FWID_A@0x367fc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x3d7fc0 + RW_FWID_A@0x3e7fc0 0x40 } - RW_SECTION_B@0x368000 0x368000 { + RW_SECTION_B@0x3e8000 0x3e8000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x357fc0 - RW_FWID_B@0x367fc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x3d7fc0 + RW_FWID_B@0x3e7fc0 0x40 } - RW_MISC@0x6D0000 0x30000 { + RW_MISC@0x7d0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 @@ -29,8 +29,8 @@ RW_SPD_CACHE(PRESERVE)@0x2f000 0x1000 } # RW_LEGACY needs to be minimum of 1MB - RW_LEGACY(CBFS)@0x700000 0x100000 - WP_RO@0x800000 0x400000 { + RW_LEGACY(CBFS)@0x800000 0x100000 + WP_RO@0x900000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x3fc000 { FMAP@0x0 0x800 diff --git a/src/mainboard/google/hatch/chromeos-puff-32MiB.fmd b/src/mainboard/google/hatch/chromeos-puff-32MiB.fmd index 37bc1bd..81840b1 100644 --- a/src/mainboard/google/hatch/chromeos-puff-32MiB.fmd +++ b/src/mainboard/google/hatch/chromeos-puff-32MiB.fmd @@ -1,24 +1,24 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x400000 { + SI_ALL@0x0 0x300000 { SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x3ff000 + SI_ME@0x1000 0x2ff000 } - SI_BIOS@0x400000 0x1c00000 { + SI_BIOS@0x300000 0x1d00000 { # Place RW_LEGACY at the start of BIOS region such that the rest # of BIOS regions start at 16MiB boundary. Since this is a 32MiB # SPI flash only the top 16MiB actually gets memory mapped. RW_LEGACY(CBFS)@0x0 0x1000000 - RW_SECTION_A@0x1000000 0x3e0000 { + RW_SECTION_A@0x1000000 0x460000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3cffc0 - RW_FWID_A@0x3dffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x44ffc0 + RW_FWID_A@0x45ffc0 0x40 } - RW_SECTION_B@0x13e0000 0x3e0000 { + RW_SECTION_B@0x1460000 0x460000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3cffc0 - RW_FWID_B@0x3dffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x44ffc0 + RW_FWID_B@0x45ffc0 0x40 } - RW_MISC@0x17c0000 0x40000 { + RW_MISC@0x18c0000 0x40000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x20000 @@ -34,7 +34,7 @@ } # Make WP_RO region align with SPI vendor # memory protected range specification. - WP_RO@0x1800000 0x400000 { + WP_RO@0x1900000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x3fc000 { FMAP@0x0 0x800 -- To view, visit https://review.coreboot.org/c/coreboot/+/41198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d39a1bdeabf48fc740da67539f48a9ff72c442c Gerrit-Change-Number: 41198 Gerrit-PatchSet: 11 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sam McNally <sammc(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/hatch: Enable the CSE Lite SKU for Puff variants
by Furquan Shaikh (Code Review) 03 Jun '20

03 Jun '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41199 ) Change subject: mb/google/hatch: Enable the CSE Lite SKU for Puff variants ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/41199/7//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/41199/7//COMMIT_MSG@14 PS7, Line 14: 3046770 > Just a few comments on 3046770 that need to be addressed. But this change looks good to me. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/41199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0de6bca162b01870ca554ae97bc4a41cf66fef18 Gerrit-Change-Number: 41199 Gerrit-PatchSet: 8 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 03 Jun 2020 07:07:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Enable CSE Firmware Lite SKU for JSLRVP
by Sridhar Siricilla (Code Review) 03 Jun '20

03 Jun '20

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40571 ) Change subject: mb/intel/jasperlake_rvp: Enable CSE Firmware Lite SKU for JSLRVP ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/40571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60039ffb1f24cf98f55e83d8c8649745598aa43a Gerrit-Change-Number: 40571 Gerrit-PatchSet: 3 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Comment-Date: Wed, 03 Jun 2020 06:56:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: acpigen: Add some new helper functions
by Duncan Laurie (Code Review) 03 Jun '20

03 Jun '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41985 ) Change subject: acpigen: Add some new helper functions ...................................................................... acpigen: Add some new helper functions These build on existing functions but use different object types in order to provide functions for upcoming changes: acpigen_write_return_op(): Return an operator. acpigen_write_if_lequal_op_op(): Check of 2 operands are equal. acpigen_get_package_op_element(): Read an element from a package into an operator. This one just provides the missing helper, the other 3 already exist: acpigen_get_tx_gpio: Read TX gpio state. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I1141fd132d6f09cf482f74e95308947cba2c5846 --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/41985/1 diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 793841c..d734dad 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -339,6 +339,18 @@ acpigen_emit_namestring(name); } +void acpigen_get_package_op_element(uint8_t package_op, unsigned int element, uint8_t dest_op) +{ + /* <dest_op> = DeRefOf (<package_op>[<element]) */ + acpigen_write_store(); + acpigen_emit_byte(DEREF_OP); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_byte(package_op); + acpigen_write_integer(element); + acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */ + acpigen_emit_byte(dest_op); +} + void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) { /* @@ -1269,6 +1281,20 @@ } /* + * Generates ACPI code for checking if operand1 and operand2 are equal. + * Both operand1 and operand2 are ACPI ops. + * + * If (Lequal (op, op)) + */ +void acpigen_write_if_lequal_op_op(uint8_t op, uint8_t val) +{ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(op); + acpigen_emit_byte(val); +} + +/* * Generates ACPI code for checking if operand1 and operand2 are equal, where, * operand1 is ACPI op and operand2 is an integer. * @@ -1341,6 +1367,12 @@ acpigen_write_return_byte_buffer(&arg, 1); } +void acpigen_write_return_op(uint8_t arg) +{ + acpigen_emit_byte(RETURN_OP); + acpigen_emit_byte(arg); +} + void acpigen_write_return_byte(uint8_t arg) { acpigen_emit_byte(RETURN_OP); @@ -1790,6 +1822,14 @@ acpigen_write_xor(LOCAL0_OP, 1, LOCAL0_OP); } +void acpigen_get_tx_gpio(struct acpi_gpio *gpio) +{ + acpigen_soc_get_tx_gpio(gpio->pins[0]); + + if (gpio->polarity == ACPI_GPIO_ACTIVE_LOW) + acpigen_write_xor(LOCAL0_OP, 1, LOCAL0_OP); +} + /* refer to ACPI 6.4.3.5.3 Word Address Space Descriptor section for details */ void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran, u16 range_min, u16 range_max, u16 translation, u16 length) diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index a99489d..1dc2c02 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -360,6 +360,7 @@ void acpigen_write_debug_op(uint8_t op); void acpigen_write_if(void); void acpigen_write_if_and(uint8_t arg1, uint8_t arg2); +void acpigen_write_if_lequal_op_op(uint8_t op, uint8_t val); void acpigen_write_if_lequal_op_int(uint8_t op, uint64_t val); void acpigen_write_if_lequal_namestr_int(const char *namestr, uint64_t val); void acpigen_write_else(void); @@ -368,6 +369,7 @@ void acpigen_write_byte_buffer(uint8_t *arr, size_t size); void acpigen_write_return_byte_buffer(uint8_t *arr, size_t size); void acpigen_write_return_singleton_buffer(uint8_t arg); +void acpigen_write_return_op(uint8_t arg); void acpigen_write_return_byte(uint8_t arg); void acpigen_write_upc(enum acpi_upc_type type); void acpigen_write_pld(const struct acpi_pld *pld); @@ -439,6 +441,16 @@ int get_cst_entries(acpi_cstate_t **); /* + * Get element from package into specified desination op: + * <dest_op> = DeRefOf (<package_op>[<element]) + * + * Example: + * acpigen_get_package_op_element(ARG0_OP, 0, LOCAL0_OP) + * Local0 = DeRefOf (Arg0[0]) + */ +void acpigen_get_package_op_element(uint8_t package_op, unsigned int element, uint8_t dest_op); + +/* * Soc-implemented functions for generating ACPI AML code for GPIO handling. All * these functions are expected to use only Local5, Local6 and Local7 * variables. If the functions call into another ACPI method, then there is no @@ -478,6 +490,14 @@ */ void acpigen_get_rx_gpio(struct acpi_gpio *gpio); +/* + * Helper function for getting a TX GPIO value based on the GPIO polarity. + * The return value is stored in Local0 variable. + * This function ends up calling acpigen_soc_get_rx_gpio to make callbacks + * into SoC acpigen code + */ +void acpigen_get_tx_gpio(struct acpi_gpio *gpio); + /* refer to ACPI 6.4.3.5.3 Word Address Space Descriptor section for details */ void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran, u16 range_min, u16 range_max, u16 translation, u16 length); -- To view, visit https://review.coreboot.org/c/coreboot/+/41985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1141fd132d6f09cf482f74e95308947cba2c5846 Gerrit-Change-Number: 41985 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3197
by Srinidhi N Kaushik (Code Review) 03 Jun '20

03 Jun '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41974 ) Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3197 ...................................................................... vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3197 Update FSP headers for Tiger Lake platform generated based FSP version 3197, which includes below additional UPDs: FSPM: CmdMirror RMTBIT FSPS: SataPortsEnableDitoConfig BUG=157725468 BRANCH=none TEST=build and boot volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I23d6baacc3d963b473280c7fdb1e5df950cd7ca8 --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 2 files changed, 41 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/41974/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index ac56ad5..a709858 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -801,7 +801,17 @@ /** Offset 0x05C1 - Reserved **/ - UINT8 Reserved30[109]; + UINT8 Reserved30[102]; + +/** Offset 0x0627 - Rank Margin Tool Per Bit + Enable/Disable Rank Margin Tool Per Bit + $EN_DIS +**/ + UINT8 RMTBIT; + +/** Offset 0x0628 - Reserved +**/ + UINT8 Reserved31[6]; /** Offset 0x062E - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to @@ -811,7 +821,7 @@ /** Offset 0x0630 - Reserved **/ - UINT8 Reserved31[62]; + UINT8 Reserved32[62]; /** Offset 0x066E - PcdSerialDebugLevel Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, @@ -824,7 +834,7 @@ /** Offset 0x066F - Reserved **/ - UINT8 Reserved32[2]; + UINT8 Reserved33[2]; /** Offset 0x0671 - Safe Mode Support This option configures the varous items in the IO and MC to be more conservative.(def=Disable) @@ -834,7 +844,7 @@ /** Offset 0x0672 - Reserved **/ - UINT8 Reserved33[2]; + UINT8 Reserved34[2]; /** Offset 0x0674 - TCSS USB Port Enable Bitmap for per port enabling @@ -843,7 +853,17 @@ /** Offset 0x0675 - Reserved **/ - UINT8 Reserved34[80]; + UINT8 Reserved35[71]; + +/** Offset 0x06BC - Command Pins Mirrored + BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller + 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror. +**/ + UINT32 CmdMirror[1]; + +/** Offset 0x06C0 - Reserved +**/ + UINT8 Reserved36[5]; /** Offset 0x06C5 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -854,7 +874,7 @@ /** Offset 0x06C6 - Reserved **/ - UINT8 Reserved35[2]; + UINT8 Reserved37[2]; /** Offset 0x06C8 - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 @@ -864,7 +884,7 @@ /** Offset 0x06C9 - Reserved **/ - UINT8 Reserved36[122]; + UINT8 Reserved38[122]; /** Offset 0x0743 - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. @@ -874,7 +894,7 @@ /** Offset 0x0744 - Reserved **/ - UINT8 Reserved37[3]; + UINT8 Reserved39[3]; /** Offset 0x0747 - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. @@ -883,7 +903,7 @@ /** Offset 0x0749 - Reserved **/ - UINT8 Reserved38[3]; + UINT8 Reserved40[3]; /** Offset 0x074C - DMIC<N> ClkA Pin Muxing (N - DMIC number) Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* @@ -903,7 +923,7 @@ /** Offset 0x075D - Reserved **/ - UINT8 Reserved39[3]; + UINT8 Reserved41[3]; /** Offset 0x0760 - DMIC<N> Data Pin Muxing Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* @@ -940,7 +960,7 @@ /** Offset 0x0775 - Reserved **/ - UINT8 Reserved40[297]; + UINT8 Reserved42[297]; /** Offset 0x089E - Serial Io Uart Debug Mode Select SerialIo Uart Controller mode @@ -951,7 +971,7 @@ /** Offset 0x089F - Reserved **/ - UINT8 Reserved41[121]; + UINT8 Reserved43[121]; } FSP_M_CONFIG; /** Fsp M UPD Configuration diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 34f3689..a68ba17 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -727,7 +727,12 @@ /** Offset 0x085B - Reserved **/ - UINT8 Reserved40[50]; + UINT8 Reserved40[42]; + +/** Offset 0x0885 - Enable SATA Port Enable Dito Config + Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). +**/ + UINT8 SataPortsEnableDitoConfig[8]; /** Offset 0x088D - Enable SATA Port DmVal DITO multiplier. Default is 15. @@ -879,7 +884,7 @@ /** Offset 0x0DB0 - Reserved **/ - UINT8 Reserved52[224]; + UINT8 Reserved52[232]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -894,11 +899,11 @@ **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0E90 +/** Offset 0x0E98 **/ UINT8 UnusedUpdSpace36[6]; -/** Offset 0x0E96 +/** Offset 0x0E9E **/ UINT16 UpdTerminator; } FSPS_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/41974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23d6baacc3d963b473280c7fdb1e5df950cd7ca8 Gerrit-Change-Number: 41974 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Update SMBIOS type 0 firmware version by VPD variable
by Johnny Lin (Code Review) 03 Jun '20

03 Jun '20

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41720 ) Change subject: mb/ocp/deltalake: Update SMBIOS type 0 firmware version by VPD variable ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/41720/11/src/mainboard/ocp/deltala… File src/mainboard/ocp/deltalake/ramstage.c: https://review.coreboot.org/c/coreboot/+/41720/11/src/mainboard/ocp/deltala… PS11, Line 79: const char *smbios_mainboard_bios_version(void) > this feature would be useful beyond just DeltaLake. […] I added the implementation to drivers/vpd in CB:42029. -- To view, visit https://review.coreboot.org/c/coreboot/+/41720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98a8fe1135728f31ec154d6340d19be8d8f980ba Gerrit-Change-Number: 41720 Gerrit-PatchSet: 11 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: insomniac <insomniac(a)slackware.it> Gerrit-Comment-Date: Wed, 03 Jun 2020 04:06:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: insomniac <insomniac(a)slackware.it> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/deltaur: Change H1 I2C speed to FAST
by EricR Lai (Code Review) 03 Jun '20

03 Jun '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41964 ) Change subject: mb/google/deltaur: Change H1 I2C speed to FAST ...................................................................... mb/google/deltaur: Change H1 I2C speed to FAST H1 is stable after HW rework. Connect +3.3V_ALW_PCH with +3.3V_PRIM. Therefore change I2C speed back to FAST. BUG=b:154885320 TEST=Check H1 I2C speed is 375kHz by scope. And no error message in cbmem and kernel log. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: If58721039d90514a17f024e6b432f3a5226440e7 --- M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/41964/1 diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 14516a0..1af8325 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -89,7 +89,7 @@ .speed = I2C_SPEED_FAST, }, .i2c[3] = { - .speed = I2C_SPEED_STANDARD, + .speed = I2C_SPEED_FAST, .early_init = 1, }, .i2c[5] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/41964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If58721039d90514a17f024e6b432f3a5226440e7 Gerrit-Change-Number: 41964 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/intel/apollolake: Reinstate APL_SKIP_SET_POWER_LIMITS
by Tim Wawrzynczak (Code Review) 03 Jun '20

03 Jun '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41786 ) Change subject: soc/intel/apollolake: Reinstate APL_SKIP_SET_POWER_LIMITS ...................................................................... soc/intel/apollolake: Reinstate APL_SKIP_SET_POWER_LIMITS The config option APL_SKIP_SET_POWER_LIMITS was accidentally left out during the set_power_limits refactor (SHA 2adb50d32e8). This patch reinstates the config option which will cause APL boards to not set any power limits. TEST=util/abuild/abuild -p none -t siemens/mc_apl1 -a Change-Id: Iec9f9f340d50a1212b6ef20c2c0e1b66385ae1b2 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/apollolake/chip.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/41786/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index cc190ba..1bd7332 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -322,6 +322,11 @@ /* Allocate ACPI NVS in CBMEM */ cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs_t)); + if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { + printk(BIOS_INFO, "Skip the RAPL settings.\n"); + return; + } + config = config_of_soc(); /* Set RAPL MSR for Package power limits */ soc_config = &config->power_limits_config; -- To view, visit https://review.coreboot.org/c/coreboot/+/41786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec9f9f340d50a1212b6ef20c2c0e1b66385ae1b2 Gerrit-Change-Number: 41786 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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