coreboot-gerrit June 2020

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Change in coreboot[master]: drivers/generic/max98357a: Don't write device if HID is missing
by Raul Rangel (Code Review) 03 Jun '20

03 Jun '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42014 ) Change subject: drivers/generic/max98357a: Don't write device if HID is missing ...................................................................... drivers/generic/max98357a: Don't write device if HID is missing If the device is missing the HID, the code would previously leave an open scope and device on the stack. BUG=b:154756391 TEST=Verify stack ACPI stack does not exceed limit on Trembyle. Fixes: a1c82c5ebee ("drivers/generic/max98357a: Allow custom _HID from config") Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I798ed08ef0a0575def12937a66a7ce99f743e60d --- M src/drivers/generic/max98357a/max98357a.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/42014/1 diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index bd45296..575548b 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -26,15 +26,15 @@ if (!scope || !name) return; - /* Device */ - acpigen_write_scope(scope); - acpigen_write_device(name); - if (!config->hid) { printk(BIOS_ERR, "%s: ERROR: _HID required\n", dev_path(dev)); return; } + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(name); + acpigen_write_name_string("_HID", config->hid); acpigen_write_name_integer("_UID", 0); acpigen_write_name_string("_DDN", dev->chip_ops->name); -- To view, visit https://review.coreboot.org/c/coreboot/+/42014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I798ed08ef0a0575def12937a66a7ce99f743e60d Gerrit-Change-Number: 42014 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: soc/amd: Use mp_cpu_bus_init()
by Kyösti Mälkki (Code Review) 03 Jun '20

03 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41952 ) Change subject: soc/amd: Use mp_cpu_bus_init() ...................................................................... soc/amd: Use mp_cpu_bus_init() Change-Id: Ia4508a9a087e3996ef7667280f8e2788421e5700 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/cpu.c M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/cpu.c M src/soc/amd/stoneyridge/include/soc/cpu.h 6 files changed, 6 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/41952/1 diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index f593664..af67e07 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -22,7 +22,7 @@ struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, - .init = picasso_init_cpus, + .init = mp_cpu_bus_init, .acpi_fill_ssdt = generate_cpu_entries, }; diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 55f9014..3512c94 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -92,10 +92,10 @@ .post_mp_init = enable_smi_generation, }; -void picasso_init_cpus(struct device *dev) +void mp_init_cpus(struct bus *cpu_bus) { /* Clear for take-off */ - if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) + if (mp_init_with_smm(cpu_bus, &mp_ops) < 0) printk(BIOS_ERR, "MP initialization failure.\n"); /* The flash is now no longer cacheable. Reset to WP for performance. */ diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index d413c72..99b31c3 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -3,11 +3,8 @@ #ifndef __PICASSO_CPU_H__ #define __PICASSO_CPU_H__ -#include <device/device.h> - #define CSTATE_BASE_REG 0xc0010073 -void picasso_init_cpus(struct device *dev); int get_cpu_count(void); void check_mca(void); diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 41fcafb..909b847 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -25,7 +25,7 @@ struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, - .init = stoney_init_cpus, + .init = mp_cpu_bus_init, .acpi_fill_ssdt = generate_cpu_entries, }; diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 36583a5..9189cfb 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -93,10 +93,10 @@ .post_mp_init = enable_smi_generation, }; -void stoney_init_cpus(struct device *dev) +void mp_init_cpus(struct bus *cpu_bus) { /* Clear for take-off */ - if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) + if (mp_init_with_smm(cpu_bus, &mp_ops) < 0) printk(BIOS_ERR, "MP initialization failure.\n"); /* The flash is now no longer cacheable. Reset to WP for performance. */ diff --git a/src/soc/amd/stoneyridge/include/soc/cpu.h b/src/soc/amd/stoneyridge/include/soc/cpu.h index ea51f76..8d25fb6 100644 --- a/src/soc/amd/stoneyridge/include/soc/cpu.h +++ b/src/soc/amd/stoneyridge/include/soc/cpu.h @@ -3,8 +3,6 @@ #ifndef __STONEYRIDGE_CPU_H__ #define __STONEYRIDGE_CPU_H__ -#include <device/device.h> - /* * Set a variable MTRR in bootblock and/or romstage. AGESA will use the lowest * numbered registers. Any values defined below are subtracted from the @@ -16,7 +14,6 @@ #define SOC_EARLY_VMTRR_CAR_HEAP 2 #define SOC_EARLY_VMTRR_TEMPRAM 3 -void stoney_init_cpus(struct device *dev); void check_mca(void); #endif /* __STONEYRIDGE_CPU_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4508a9a087e3996ef7667280f8e2788421e5700 Gerrit-Change-Number: 41952 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: mb/google/dedede: config spk_en gpio to low by default
by Tim Wawrzynczak (Code Review) 03 Jun '20

03 Jun '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41853 ) Change subject: mb/google/dedede: config spk_en gpio to low by default ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/41853/2/src/mainboard/google/deded… File src/mainboard/google/dedede/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/41853/2/src/mainboard/google/deded… PS2, Line 178: GPP_D17 > This is the baseboard GPIO file, so it should apply to all variants. I think Furquan was referring to register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" in waddledoo's devicetree. -- To view, visit https://review.coreboot.org/c/coreboot/+/41853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I070679457b06cb82633c1197b893a5d89c8b2cf0 Gerrit-Change-Number: 41853 Gerrit-PatchSet: 3 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 03 Jun 2020 16:27:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Usha P <usha.p(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/xeon_sp/cpx: add chip operation and PCIe enumeration
by Aaron Durbin (Code Review) 03 Jun '20

03 Jun '20

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40110 ) Change subject: soc/intel/xeon_sp/cpx: add chip operation and PCIe enumeration ...................................................................... Patch Set 19: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/40110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If461b1dc1f313d98b676dc9e91d08a1dbb9cb388 Gerrit-Change-Number: 40110 Gerrit-PatchSet: 19 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Morgan Jang Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 03 Jun 2020 16:01:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc,southbridge/amd: Remove some explicit zero-initializers
by Kyösti Mälkki (Code Review) 03 Jun '20

03 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41908 ) Change subject: soc,southbridge/amd: Remove some explicit zero-initializers ...................................................................... soc,southbridge/amd: Remove some explicit zero-initializers Change-Id: I263c159fe4b7757dd5abfc0d6248e45b749df980 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/southbridge/amd/agesa/hudson/fadt.c M src/southbridge/amd/cimx/sb800/fadt.c M src/southbridge/amd/pi/hudson/fadt.c 5 files changed, 6 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/41908/1 diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 2eea6f9..d5a890b 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -111,16 +111,6 @@ fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0; /* Not supported */ - fadt->pstate_cnt = 0; /* Not supported */ - fadt->cst_cnt = 0; /* Not supported */ - } else { - fadt->smi_cmd = 0; /* disable system management mode */ - fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ - fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */ - fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ - fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ - fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index c98a1b4..47d12bf 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -83,16 +83,6 @@ fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0; /* Not supported */ - fadt->pstate_cnt = 0; /* Not supported */ - fadt->cst_cnt = 0; /* Not supported */ - } else { - fadt->smi_cmd = 0; /* disable system management mode */ - fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ - fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */ - fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ - fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ - fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index 0476057..660598a 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -61,16 +61,6 @@ fadt->smi_cmd = ACPI_SMI_CTL_PORT; fadt->acpi_enable = ACPI_SMI_CMD_ENABLE; fadt->acpi_disable = ACPI_SMI_CMD_DISABLE; - fadt->s4bios_req = 0; /* Not supported */ - fadt->pstate_cnt = 0; /* Not supported */ - fadt->cst_cnt = 0; /* Not supported */ - } else { - fadt->smi_cmd = 0; /* disable system management mode */ - fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ - fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */ - fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ - fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ - fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 1939bac..e836cfb 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -61,11 +61,12 @@ fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON 1 - IRQ 09 - ACPI SCI */ - fadt->smi_cmd = 0; /* disable system management mode */ - fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ - fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */ - fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ - fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = ACPI_SMI_CTL_PORT; + fadt->acpi_enable = ACPI_SMI_CMD_ENABLE; + fadt->acpi_disable = ACPI_SMI_CMD_DISABLE; + } val = PM1_EVT_BLK_ADDRESS; WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val); @@ -109,7 +110,6 @@ fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index d45be9a..100cfb6 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -53,16 +53,6 @@ fadt->smi_cmd = ACPI_SMI_CTL_PORT; fadt->acpi_enable = ACPI_SMI_CMD_ENABLE; fadt->acpi_disable = ACPI_SMI_CMD_DISABLE; - fadt->s4bios_req = 0; /* Not supported */ - fadt->pstate_cnt = 0; /* Not supported */ - fadt->cst_cnt = 0; /* Not supported */ - } else { - fadt->smi_cmd = 0; /* disable system management mode */ - fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ - fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */ - fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ - fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ - fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; -- To view, visit https://review.coreboot.org/c/coreboot/+/41908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I263c159fe4b7757dd5abfc0d6248e45b749df980 Gerrit-Change-Number: 41908 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/quark/memmap: Add missing 'include <cpu/x86/mtrr.h>'
by HAOUAS Elyes (Code Review) 03 Jun '20

03 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41787 ) Change subject: soc/intel/quark/memmap: Add missing 'include <cpu/x86/mtrr.h>' ...................................................................... soc/intel/quark/memmap: Add missing 'include <cpu/x86/mtrr.h>' Change-Id: I6a066659758aeb0251d9b37f525ad987b90832db Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/quark/memmap.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/41787/1 diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index c2a2b5d..97a9fd8 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -2,6 +2,7 @@ #include <arch/romstage.h> #include <cbmem.h> +#include <cpu/x86/mtrr.h> #include <soc/reg_access.h> void fill_postcar_frame(struct postcar_frame *pcf) -- To view, visit https://review.coreboot.org/c/coreboot/+/41787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a066659758aeb0251d9b37f525ad987b90832db Gerrit-Change-Number: 41787 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/gigabyte/ga-g41m-es2l: Remove MEI PCI devices from devicetree
by Arthur Heymans (Code Review) 03 Jun '20

03 Jun '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41866 ) Change subject: mb/gigabyte/ga-g41m-es2l: Remove MEI PCI devices from devicetree ...................................................................... mb/gigabyte/ga-g41m-es2l: Remove MEI PCI devices from devicetree These devices never show on the PCI domain. Change-Id: I2d4d99c1e96c15dacb950aeb85b3e9a5d127c791 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/41866/1 diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 2b23ca1..6328bc6 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -21,8 +21,6 @@ device pci 2.1 on # Integrated graphics controller 2 subsystemid 0x1458 0xd001 end - device pci 3.0 off end # ME - device pci 3.1 off end # ME chip southbridge/intel/i82801gx # Southbridge register "pirqa_routing" = "0x0b" register "pirqb_routing" = "0x0b" -- To view, visit https://review.coreboot.org/c/coreboot/+/41866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d4d99c1e96c15dacb950aeb85b3e9a5d127c791 Gerrit-Change-Number: 41866 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/gigabyte/ga-g41m-es2l: Add PEG to devicetree
by Arthur Heymans (Code Review) 03 Jun '20

03 Jun '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41865 ) Change subject: mb/gigabyte/ga-g41m-es2l: Add PEG to devicetree ...................................................................... mb/gigabyte/ga-g41m-es2l: Add PEG to devicetree Change-Id: Icebf0eea4e1fee6d15ba3f1a080cbc40b42fd733 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/41865/1 diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index dade0b4..2b23ca1 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -14,6 +14,7 @@ device pci 0.0 on # Host Bridge subsystemid 0x1458 0x5000 end + device pci 1.0 on end # PEG device pci 2.0 on # Integrated graphics controller subsystemid 0x1458 0xd000 end -- To view, visit https://review.coreboot.org/c/coreboot/+/41865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icebf0eea4e1fee6d15ba3f1a080cbc40b42fd733 Gerrit-Change-Number: 41865 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: northbridge/intel/sandybridge: Mask lower 20 bits of TOLUD and TOLM i...
by Furquan Shaikh (Code Review) 03 Jun '20

03 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41979 ) Change subject: northbridge/intel/sandybridge: Mask lower 20 bits of TOLUD and TOLM in hostbridge.asl ...................................................................... northbridge/intel/sandybridge: Mask lower 20 bits of TOLUD and TOLM in hostbridge.asl Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and 1 lock bit. If lock bit is set, then systemagent.asl would end up reporting the base address of low MMIO incorrectly i.e. off by 1. This change masks the lower 20 bits of TOLUD and TOM registers when exposing it in the ACPI tables to ensure that the base address of low MMIO region is reported correctly. Change-Id: Ib0ffd9a332fa9590de63f8828d30daa710fe50db Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/northbridge/intel/sandybridge/acpi/hostbridge.asl 1 file changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/41979/1 diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index c8efc98..0f70f8c 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -342,13 +342,17 @@ // Fix up PCI memory region // Start with Top of Lower Usable DRAM - Local0 = ^MCHC.TLUD + // Lower 20 bits of TOLUD register need to be masked since they contain lock and + // reserved bits. + Local0 = ^MCHC.TLUD & (0xfff << 20) Local1 = ^MCHC.MEBA // Check if ME base is equal If (Local0 == Local1) { // Use Top Of Memory instead - Local0 = ^MCHC.TOM + // Lower 20 bits of TOM register need to be masked since they contain lock and + // reserved bits. + Local0 = ^MCHC.TOM & (0x7ffff << 20) } PMIN = Local0 -- To view, visit https://review.coreboot.org/c/coreboot/+/41979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0ffd9a332fa9590de63f8828d30daa710fe50db Gerrit-Change-Number: 41979 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: northbridge/intel/haswell: Mask lower 20 bits of TOLUD and TOLM in ho...
by Furquan Shaikh (Code Review) 03 Jun '20

03 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41977 ) Change subject: northbridge/intel/haswell: Mask lower 20 bits of TOLUD and TOLM in hostbridge.asl ...................................................................... northbridge/intel/haswell: Mask lower 20 bits of TOLUD and TOLM in hostbridge.asl Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and 1 lock bit. If lock bit is set, then systemagent.asl would end up reporting the base address of low MMIO incorrectly i.e. off by 1. This change masks the lower 20 bits of TOLUD and TOM registers when exposing it in the ACPI tables to ensure that the base address of low MMIO region is reported correctly. Change-Id: I1fb52a42e84130d973e0970024e263f443aa0b89 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/northbridge/intel/haswell/acpi/hostbridge.asl 1 file changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/41977/1 diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 8fbfabf..dd4b79a 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -425,13 +425,17 @@ // Fix up PCI memory region // Start with Top of Lower Usable DRAM - Local0 = ^MCHC.TLUD + // Lower 20 bits of TOLUD register need to be masked since they contain lock and + // reserved bits. + Local0 = ^MCHC.TLUD & (0xfff << 20) Local1 = ^MCHC.MEBA // Check if ME base is equal If (Local0 == Local1) { // Use Top Of Memory instead - Local0 = ^MCHC.TOM + // Lower 20 bits of TOM register need to be masked since they contain lock and + // reserved bits. + Local0 = ^MCHC.TOM & (0x7ffff << 20) } PMIN = Local0 -- To view, visit https://review.coreboot.org/c/coreboot/+/41977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fb52a42e84130d973e0970024e263f443aa0b89 Gerrit-Change-Number: 41977 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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