Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Maulik V Vaghela, Duncan Laurie, Sridhar Siricilla, Aamir Bohra, Srinidhi N Kaushik, Andrey Petrov, Aaron Durbin, Patrick Rudolph, Nathaniel L Desimone,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41728
to look at the new patch set (#9).
Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support
......................................................................
drivers/intel/fsp2_0: Add FSP 2.2 specific support
• Based on FSP EAS v2.1 – Backward compatibility is retained.
• Added multi-phase silicon initialization to increase the modularity of the
FspSiliconInit() API.
• Added FspMultiPhaseSiInit() API
• FSP_INFO_HEADER changes
o Added FspMultiPhaseSiInitEntryOffset
• Added FSPS_ARCH_UPD
o Added EnableMultiPhaseSiliconInit, bootloaders designed for
FSP 2.0/2.1 can disable the FspMultiPhaseSiInit() API and
continue to use FspSiliconInit() without change.
FSP 2.2 Specification:
https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-…
Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/commonlib/include/commonlib/timestamp_serialized.h
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/include/fsp/api.h
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/intel/fsp2_0/include/fsp/upd.h
M src/drivers/intel/fsp2_0/include/fsp/util.h
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/util.c
M src/include/console/post_codes.h
9 files changed, 177 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/41728/9
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Gerrit-MessageType: newpatchset
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Maulik V Vaghela, Duncan Laurie, Sridhar Siricilla, Aamir Bohra, Srinidhi N Kaushik, Andrey Petrov, Aaron Durbin, Patrick Rudolph, Nathaniel L Desimone,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41728
to look at the new patch set (#8).
Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support
......................................................................
drivers/intel/fsp2_0: Add FSP 2.2 specific support
• Based on FSP EAS v2.1 – Backward compatibility is retained.
• Added multi-phase silicon initialization to increase the modularity of the
FspSiliconInit() API.
• Added FspMultiPhaseSiInit() API
• FSP_INFO_HEADER changes
o Added FspMultiPhaseSiInitEntryOffset
• Added FSPS_ARCH_UPD
o Added EnableMultiPhaseSiliconInit, bootloaders designed for
FSP 2.0/2.1 can disable the FspMultiPhaseSiInit() API and
continue to use FspSiliconInit() without change.
FSP 2.2 Specification:
https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-…
Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/commonlib/include/commonlib/timestamp_serialized.h
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/include/fsp/api.h
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/intel/fsp2_0/include/fsp/upd.h
M src/drivers/intel/fsp2_0/include/fsp/util.h
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/util.c
M src/include/console/post_codes.h
9 files changed, 176 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/41728/8
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41728 )
Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support
......................................................................
Patch Set 7:
(3 comments)
https://review.coreboot.org/c/coreboot/+/41728/7/src/drivers/intel/fsp2_0/s…
File src/drivers/intel/fsp2_0/silicon_init.c:
https://review.coreboot.org/c/coreboot/+/41728/7/src/drivers/intel/fsp2_0/s…
PS7, Line 28: return 1;
code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/41728/7/src/drivers/intel/fsp2_0/s…
PS7, Line 28: return 1;
please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/41728/7/src/drivers/intel/fsp2_0/s…
PS7, Line 87: FSPS_ARCH_UPD *arch_upd;
need consistent spacing around '*' (ctx:WxV)
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Gerrit-Comment-Date: Thu, 04 Jun 2020 04:36:26 +0000
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Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Maulik V Vaghela, Duncan Laurie, Sridhar Siricilla, Aamir Bohra, Srinidhi N Kaushik, Andrey Petrov, Aaron Durbin, Patrick Rudolph, Nathaniel L Desimone,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41728
to look at the new patch set (#7).
Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support
......................................................................
drivers/intel/fsp2_0: Add FSP 2.2 specific support
• Based on FSP EAS v2.1 – Backward compatibility is retained.
• Added multi-phase silicon initialization to increase the modularity of the
FspSiliconInit() API.
• Added FspMultiPhaseSiInit() API
• FSP_INFO_HEADER changes
o Added FspMultiPhaseSiInitEntryOffset
• Added FSPS_ARCH_UPD
o Added EnableMultiPhaseSiliconInit, bootloaders designed for
FSP 2.0/2.1 can disable the FspMultiPhaseSiInit() API and
continue to use FspSiliconInit() without change.
FSP 2.2 Specification:
https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-…
Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/commonlib/include/commonlib/timestamp_serialized.h
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/include/fsp/api.h
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/intel/fsp2_0/include/fsp/upd.h
M src/drivers/intel/fsp2_0/include/fsp/util.h
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/util.c
M src/include/console/post_codes.h
9 files changed, 206 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/41728/7
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41728 )
Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support
......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41728/3/src/drivers/intel/fsp2_0/K…
File src/drivers/intel/fsp2_0/Kconfig:
https://review.coreboot.org/c/coreboot/+/41728/3/src/drivers/intel/fsp2_0/K…
PS3, Line 44: config FSPS_ARCH_UPD
: bool
: depends on HAVE_FSPS_ARCH_UPD
: default y
: help
: Select this option to use Intel FSP-S Architecture UPDs from FspsUpd.h.
> I don't see this used anywhere. […]
Ack
https://review.coreboot.org/c/coreboot/+/41728/3/src/drivers/intel/fsp2_0/s…
File src/drivers/intel/fsp2_0/silicon_init.c:
https://review.coreboot.org/c/coreboot/+/41728/3/src/drivers/intel/fsp2_0/s…
PS3, Line 136: multi_phase_si_init
> It is optional for the FSP to implement multi_phase_si_init() per FSP 2.2 spec. […]
Ack
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Gerrit-MessageType: comment
Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Johnny Lin, Jingle Hsu, Morgan Jang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40385
to look at the new patch set (#21).
Change subject: soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters
......................................................................
soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters
Configure FSP-M UPD parameters.
These parameters are proved to work on OCP DeltaLake server.
Discussion is on-going with Intel FSP engineering team on what
those parameters mean, and why those value settings are necessary.
Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com>
Change-Id: I2d0762a742d8803c7396034e3244120c1e8ece67
---
M src/soc/intel/xeon_sp/cpx/romstage.c
1 file changed, 45 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/40385/21
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Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Johnny Lin, Jingle Hsu, Morgan Jang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40383
to look at the new patch set (#20).
Change subject: soc/intel/xeon_sp/cpx: fix MADT ACPI table
......................................................................
soc/intel/xeon_sp/cpx: fix MADT ACPI table
Fix MADT table generation to keep IIO stack design in consideration.
Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com>
Change-Id: If1bf6e39db545e227e9867aa8d24f7db1d820216
---
M src/soc/intel/xeon_sp/cpx/acpi.c
M src/soc/intel/xeon_sp/cpx/include/soc/acpi.h
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
3 files changed, 99 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/40383/20
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Nathaniel L Desimone has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41728 )
Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support
......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41728/3/src/drivers/intel/fsp2_0/K…
File src/drivers/intel/fsp2_0/Kconfig:
https://review.coreboot.org/c/coreboot/+/41728/3/src/drivers/intel/fsp2_0/K…
PS3, Line 44: config FSPS_ARCH_UPD
: bool
: depends on HAVE_FSPS_ARCH_UPD
: default y
: help
: Select this option to use Intel FSP-S Architecture UPDs from FspsUpd.h.
I don't see this used anywhere. Do we really need it? Seems a little redundant with HAVE_FSPS_ARCH_UPD.
https://review.coreboot.org/c/coreboot/+/41728/3/src/drivers/intel/fsp2_0/s…
File src/drivers/intel/fsp2_0/silicon_init.c:
https://review.coreboot.org/c/coreboot/+/41728/3/src/drivers/intel/fsp2_0/s…
PS3, Line 136: multi_phase_si_init
It is optional for the FSP to implement multi_phase_si_init() per FSP 2.2 spec. You need to check if this is == NULL and if it is only use silicon_init().
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