coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/foster: Remove EC_GOOGLE_CHROMEEC stubs
by Kyösti Mälkki (Code Review) 03 Jun '20

03 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41983 ) Change subject: mb/google/foster: Remove EC_GOOGLE_CHROMEEC stubs ...................................................................... mb/google/foster: Remove EC_GOOGLE_CHROMEEC stubs Board does not have ChromeEC. Change-Id: Id6ab2495d6e082fdcb71ec5162efde877d97ce22 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/foster/chromeos.c D src/mainboard/google/foster/ec_dummy.c 2 files changed, 0 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/41983/1 diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 6f7f09c..8dc236e 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -1,10 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <boot/coreboot_tables.h> -#include <ec/google/chromeec/ec.h> -#include <ec/google/chromeec/ec_commands.h> #include <gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -21,15 +18,7 @@ int get_recovery_mode_switch(void) { -#if CONFIG(EC_GOOGLE_CHROMEEC) - uint64_t ec_events; - - ec_events = google_chromeec_get_events_b(); - return !!(ec_events & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); -#else return 0; -#endif } int get_write_protect_state(void) diff --git a/src/mainboard/google/foster/ec_dummy.c b/src/mainboard/google/foster/ec_dummy.c deleted file mode 100644 index d96a258..0000000 --- a/src/mainboard/google/foster/ec_dummy.c +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Dummy CHROMEEC file to provide stub functions for vboot compilation */ - -#include <stdint.h> - -int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len); -int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len) -{ - return 0; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/41983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6ab2495d6e082fdcb71ec5162efde877d97ce22 Gerrit-Change-Number: 41983 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: soc/amd/picasso/acpi: Add missing eMMC device
by Raul Rangel (Code Review) 03 Jun '20

03 Jun '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41836 ) Change subject: soc/amd/picasso/acpi: Add missing eMMC device ...................................................................... soc/amd/picasso/acpi: Add missing eMMC device BUG=b:154756391 TEST=Boot trembyle and see that /dev/mmcblk1 now exists Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ica83b78a7ab081d9eac9f5e267b2904dcde0b283 --- M src/soc/amd/picasso/acpi/pcie.asl M src/soc/amd/picasso/acpi/sb_fch.asl 2 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/41836/1 diff --git a/src/soc/amd/picasso/acpi/pcie.asl b/src/soc/amd/picasso/acpi/pcie.asl index 561a3f8..954c5365 100644 --- a/src/soc/amd/picasso/acpi/pcie.asl +++ b/src/soc/amd/picasso/acpi/pcie.asl @@ -16,6 +16,9 @@ PIRG, 0x00000008, /* Index 6: INTG */ PIRH, 0x00000008, /* Index 7: INTH */ + Offset (0x43), + PMMC, 0x00000008, /* Index 0x43: eMMC */ + Offset (0x62), PGPI, 0x00000008, /* Index 0x62: GPIO */ @@ -42,6 +45,9 @@ IORG, 0x00000008, /* Index 0x86: INTG */ IORH, 0x00000008, /* Index 0x87: INTH */ + Offset (0xC3), + IMMC, 0x00000008, /* Index 0xC3: eMMC */ + Offset (0xE2), IGPI, 0x00000008, /* Index 0xE2: GPIO */ diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 197da3a..98f716b 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -57,6 +57,41 @@ } } +Device (MMC0) +{ + Name (_HID, "AMDI0040") + Name (_UID, 0x0) + Method(_CRS, 0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Level, + ActiveLow, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_EMMC_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If (PMOD) { + IRQN=IMMC + } Else { + IRQN=PMMC + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_EMMC_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + Device (FUR0) { Name (_HID, "AMD0020") -- To view, visit https://review.coreboot.org/c/coreboot/+/41836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica83b78a7ab081d9eac9f5e267b2904dcde0b283 Gerrit-Change-Number: 41836 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: acpi: Drop typoed __ROMC__
by Kyösti Mälkki (Code Review) 03 Jun '20

03 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41967 ) Change subject: acpi: Drop typoed __ROMC__ ...................................................................... acpi: Drop typoed __ROMC__ Change-Id: I4fcec5bbc038a31565882631052ab07e38946e65 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/acpi/acpi.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/41967/1 diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index ea80e3b..2b001ac 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1046,6 +1046,6 @@ * coreboot default ACPI spec version supported. */ int get_acpi_table_revision(enum acpi_tables table); -#endif // !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMC__) +#endif // !defined(__ASSEMBLER__) && !defined(__ACPI__) #endif /* __ACPI_ACPI_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fcec5bbc038a31565882631052ab07e38946e65 Gerrit-Change-Number: 41967 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/google/zork: Delete sb_fch.asl
by Raul Rangel (Code Review) 03 Jun '20

03 Jun '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41837 ) Change subject: mb/google/zork: Delete sb_fch.asl ...................................................................... mb/google/zork: Delete sb_fch.asl This file is not used. BUG=b:154756391 TEST=Build trembyle and check that peripherals still work Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I721e295546aa75c9745a4836425b6e3e0067afaf --- D src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sb_fch.asl 1 file changed, 0 insertions(+), 246 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/41837/1 diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sb_fch.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sb_fch.asl deleted file mode 100644 index 21c31a3..0000000 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sb_fch.asl +++ /dev/null @@ -1,246 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <soc/gpio.h> -#include <soc/iomap.h> - -Device (AAHB) -{ - Name (_HID, "AAHB0000") - Name (_UID, 0x0) - Name (_CRS, ResourceTemplate() - { - Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000) - }) - - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } -} - -Device (GPIO) -{ - Name (_HID, GPIO_DEVICE_NAME) - Name (_CID, GPIO_DEVICE_NAME) - Name (_UID, 0) - Name (_DDN, GPIO_DEVICE_DESC) - - Method(_CRS ,0) { - local0=ResourceTemplate(){ - Interrupt ( - ResourceConsumer, - Level, - ActiveLow, - Exclusive, , , IRQR) - { 0 } - Memory32Fixed (ReadWrite, 0xFED81500, 0x300) - } - CreateDWordField(local0, IRQR._INT, IRQN) - If(PMOD) { - IRQN=IGPI - } Else { - IRQN=PGPI - } - If (IRQN == 0x1f) { - Return(ResourceTemplate(){ - Memory32Fixed (ReadWrite, 0xFED81500, 0x300) - }) - } Else { - Return(local0) - } - } - - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } -} - -Device (MMC0) -{ - Name (_HID, "AMDI0040") - Name (_UID, 0x0) - Method(_CRS ,0) { - local0=ResourceTemplate(){ - Interrupt ( - ResourceConsumer, - Level, - ActiveLow, - Exclusive, , , IRQR) - { 0 } - Memory32Fixed (ReadWrite, APU_EMMC_BASE, 0x1000) - } - CreateDWordField(local0, IRQR._INT, IRQN) - If(PMOD) { - IRQN=IMMC - } Else { - IRQN=PMMC - } - If (IRQN == 0x1f) { - Return(ResourceTemplate(){ - Memory32Fixed (ReadWrite, APU_EMMC_BASE, 0x1000) - }) - } Else { - Return(local0) - } - } - - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } -} - -Device (FUR0) -{ - Name (_HID, "AMD0020") - Name (_UID, 0x0) - Method(_CRS ,0) { - local0=ResourceTemplate(){ - Interrupt ( - ResourceConsumer, - Edge, - ActiveHigh, - Exclusive, , , IRQR) - { 0 } - Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) - Memory32Fixed (ReadWrite, APU_DMAC0_BASE, 0x1000) - } - CreateDWordField(local0, IRQR._INT, IRQN) - If(PMOD) { - IRQN=IUA0 - } Else { - IRQN=PUA0 - } - If (IRQN == 0x1f) { - Return(ResourceTemplate(){ - Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) - Memory32Fixed (ReadWrite, APU_DMAC0_BASE, 0x1000) - }) - } Else { - Return(local0) - } - } - - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } -} - -Device (FUR1) { - Name (_HID, "AMD0020") - Name (_UID, 0x1) - Method(_CRS ,0) { - local0=ResourceTemplate(){ - Interrupt ( - ResourceConsumer, - Edge, - ActiveHigh, - Exclusive, , , IRQR) - { 0 } - Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) - Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000) - } - CreateDWordField(local0, IRQR._INT, IRQN) - If(PMOD) { - IRQN=IUA1 - } Else { - IRQN=PUA1 - } - If (IRQN == 0x1f) { - Return(ResourceTemplate(){ - Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) - Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000) - }) - } Else { - Return(local0) - } - } - - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } -} - -Device (I2C2) { - Name (_HID, "AMD0010") - Name (_UID, 0x2) - Method(_CRS ,0) { - local0=ResourceTemplate(){ - Interrupt ( - ResourceConsumer, - Edge, - ActiveHigh, - Exclusive, , , IRQR) - { 0 } - Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) - } - CreateDWordField(local0, IRQR._INT, IRQN) - If(PMOD) { - IRQN=II22 - } Else { - IRQN=PI22 - } - If (IRQN == 0x1f) { - Return(ResourceTemplate(){ - Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) - }) - } Else { - Return(local0) - } - } - - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } -} - -Device (I2C3) -{ - Name (_HID, "AMD0010") - Name (_UID, 0x3) - Method(_CRS ,0) { - local0=ResourceTemplate(){ - Interrupt ( - ResourceConsumer, - Edge, - ActiveHigh, - Exclusive, , , IRQR) - { 0 } - Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000) - } - CreateDWordField(local0, IRQR._INT, IRQN) - If(PMOD) { - IRQN=II23 - } Else { - IRQN=PI23 - } - If (IRQN == 0x1f) { - Return(ResourceTemplate(){ - Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000) - }) - } Else { - Return(local0) - } - } - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } -} - -Device (MISC) -{ - Name (_HID, "AMD0040") - Name (_UID, 0x3) - Name (_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100) - }) - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/41837 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I721e295546aa75c9745a4836425b6e3e0067afaf Gerrit-Change-Number: 41837 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbers
by Raul Rangel (Code Review) 03 Jun '20

03 Jun '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41835 ) Change subject: soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbers ...................................................................... soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbers Modify the FCH ACPI devices to query the PCI IRQ mapping registers for their current IRQ numbers. BUG=b:139429446, b:154756391 TEST=Boot trembyle and see that I2C and UART devices are finally functional. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I8f2035f74240ead4089ff4d503dfbeb447cf8de4 --- M src/soc/amd/picasso/acpi/pcie.asl M src/soc/amd/picasso/acpi/sb_fch.asl 2 files changed, 239 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41835/1 diff --git a/src/soc/amd/picasso/acpi/pcie.asl b/src/soc/amd/picasso/acpi/pcie.asl index 2bbfec56..561a3f8 100644 --- a/src/soc/amd/picasso/acpi/pcie.asl +++ b/src/soc/amd/picasso/acpi/pcie.asl @@ -16,6 +16,21 @@ PIRG, 0x00000008, /* Index 6: INTG */ PIRH, 0x00000008, /* Index 7: INTH */ + Offset (0x62), + PGPI, 0x00000008, /* Index 0x62: GPIO */ + + Offset (0x70), + PI20, 0x00000008, /* Index 0x70: I2C0 */ + PI21, 0x00000008, /* Index 0x71: I2C1 */ + PI22, 0x00000008, /* Index 0x72: I2C2 */ + PI23, 0x00000008, /* Index 0x73: I2C3 */ + PUA0, 0x00000008, /* Index 0x74: UART0 */ + PUA1, 0x00000008, /* Index 0x75: UART1 */ + PI24, 0x00000008, /* Index 0x76: I2C4 */ + PI25, 0x00000008, /* Index 0x77: I2C5 */ + PUA2, 0x00000008, /* Index 0x78: UART2 */ + PUA3, 0x00000008, /* Index 0x79: UART3 */ + /* IO-APIC IRQs */ Offset (0x80), IORA, 0x00000008, /* Index 0x80: INTA */ @@ -26,6 +41,21 @@ IORF, 0x00000008, /* Index 0x85: INTF */ IORG, 0x00000008, /* Index 0x86: INTG */ IORH, 0x00000008, /* Index 0x87: INTH */ + + Offset (0xE2), + IGPI, 0x00000008, /* Index 0xE2: GPIO */ + + Offset (0xF0), + II20, 0x00000008, /* Index 0xF0: I2C0 */ + II21, 0x00000008, /* Index 0xF1: I2C1 */ + II22, 0x00000008, /* Index 0xF2: I2C2 */ + II23, 0x00000008, /* Index 0xF3: I2C3 */ + IUA0, 0x00000008, /* Index 0xF4: UART0 */ + IUA1, 0x00000008, /* Index 0xF5: UART1 */ + II24, 0x00000008, /* Index 0xF6: I2C4 */ + II25, 0x00000008, /* Index 0xF7: I2C5 */ + IUA2, 0x00000008, /* Index 0xF8: UART2 */ + IUA3, 0x00000008, /* Index 0xF9: UART3 */ } /* PCI Error control register */ diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index f8df3c0..197da3a 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -26,12 +26,30 @@ Name (_UID, 0) Name (_DDN, GPIO_DEVICE_DESC) - Name (_CRS, ResourceTemplate() - { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) - { 7 } - Memory32Fixed (ReadWrite, 0xFED81500, 0x300) - }) + Method(_CRS, 0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Level, + ActiveLow, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, 0xFED81500, 0x300) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If (PMOD) { + IRQN=IGPI + } Else { + IRQN=PGPI + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, 0xFED81500, 0x300) + }) + } Else { + Return(local0) + } + } Method (_STA, 0x0, NotSerialized) { @@ -43,12 +61,33 @@ { Name (_HID, "AMD0020") Name (_UID, 0x0) - Name (_CRS, ResourceTemplate() - { - IRQ (Edge, ActiveHigh, Exclusive) { 10 } - Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) - Memory32Fixed (ReadWrite, APU_DMAC0_BASE, 0x1000) - }) + Method(_CRS, 0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC0_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If (PMOD) { + IRQN=IUA0 + } Else { + IRQN=PUA0 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC0_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } + Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -58,28 +97,69 @@ Device (FUR1) { Name (_HID, "AMD0020") Name (_UID, 0x1) - Name (_CRS, ResourceTemplate() - { - IRQ (Edge, ActiveHigh, Exclusive) { 11 } - Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) - Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000) - }) + Method(_CRS, 0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If (PMOD) { + IRQN=IUA1 + } Else { + IRQN=PUA1 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } + Method (_STA, 0x0, NotSerialized) { Return (0x0F) } } -Device (FUR2) -{ +Device (FUR2) { Name (_HID, "AMD0020") - Name (_UID, 0x0) - Name (_CRS, ResourceTemplate() - { - IRQ (Edge, ActiveHigh, Exclusive) { 15 } - Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000) - Memory32Fixed (ReadWrite, APU_DMAC2_BASE, 0x1000) - }) + Name (_UID, 0x2) + Method(_CRS, 0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC2_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If (PMOD) { + IRQN=IUA2 + } Else { + IRQN=PUA2 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } + Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -88,13 +168,34 @@ Device (FUR3) { Name (_HID, "AMD0020") - Name (_UID, 0x1) - Name (_CRS, ResourceTemplate() - { - IRQ (Edge, ActiveHigh, Exclusive) { 5 } - Memory32Fixed (ReadWrite, APU_UART3_BASE, 0x1000) - Memory32Fixed (ReadWrite, APU_DMAC3_BASE, 0x1000) - }) + Name (_UID, 0x3) + Method(_CRS, 0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If (PMOD) { + IRQN=IUA3 + } Else { + IRQN=PUA3 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_UART3_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC3_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } + Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -104,11 +205,30 @@ Device (I2C2) { Name (_HID, "AMD0010") Name (_UID, 0x2) - Name (_CRS, ResourceTemplate() - { - IRQ (Edge, ActiveHigh, Exclusive) { 4 } - Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) - }) + Method(_CRS, 0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If (PMOD) { + IRQN=II22 + } Else { + IRQN=PI22 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } Method (_STA, 0x0, NotSerialized) { @@ -120,24 +240,64 @@ { Name (_HID, "AMD0010") Name (_UID, 0x3) - Name (_CRS, ResourceTemplate() { - IRQ (Edge, ActiveHigh, Exclusive) { 6 } - Memory32Fixed(ReadWrite, APU_I2C3_BASE, 0x1000) - }) + Method(_CRS, 0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If (PMOD) { + IRQN=II23 + } Else { + IRQN=PI23 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } Method (_STA, 0x0, NotSerialized) { Return (0x0F) } } -Device (I2C4) -{ +Device (I2C4) { Name (_HID, "AMD0010") Name (_UID, 0x4) - Name (_CRS, ResourceTemplate() { - IRQ (Edge, ActiveHigh, Exclusive) { 14 } - Memory32Fixed(ReadWrite, APU_I2C4_BASE, 0x1000) - }) + Method(_CRS, 0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C4_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If (PMOD) { + IRQN=II24 + } Else { + IRQN=PI24 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_I2C4_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } + Method (_STA, 0x0, NotSerialized) { Return (0x0F) -- To view, visit https://review.coreboot.org/c/coreboot/+/41835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f2035f74240ead4089ff4d503dfbeb447cf8de4 Gerrit-Change-Number: 41835 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: soc/intel/jasperlake: Update C-States info
by Patrick Georgi (Code Review) 03 Jun '20

03 Jun '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40902 ) Change subject: soc/intel/jasperlake: Update C-States info ...................................................................... soc/intel/jasperlake: Update C-States info - Update C-States max latency values - Remove MSR programming for C-States latency BRANCH=None TEST=Boot to OS and check CState Latenecy >cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency} POLL C1_ACPI C2_ACPI C3_ACPI 0 1 253 1048 Change-Id: I05c0b5b31d1883f72ca94171aa1b536621e97449 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40902 Reviewed-by: Aamir Bohra <aamir.bohra(a)intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/jasperlake/acpi.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/jasperlake/include/soc/cpu.h 3 files changed, 20 insertions(+), 56 deletions(-) Approvals: build bot (Jenkins): Verified Aamir Bohra: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 373f95c..88ec5fe 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -52,70 +52,70 @@ static const acpi_cstate_t cstate_map[NUM_C_STATES] = { [C_STATE_C0] = {}, [C_STATE_C1] = { - .latency = 0, + .latency = C1_LATENCY, .power = C1_POWER, .resource = MWAIT_RES(0, 0), }, [C_STATE_C1E] = { - .latency = 0, + .latency = C1_LATENCY, .power = C1_POWER, .resource = MWAIT_RES(0, 1), }, [C_STATE_C6_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C6_LATENCY, .power = C6_POWER, .resource = MWAIT_RES(2, 0), }, [C_STATE_C6_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C6_LATENCY, .power = C6_POWER, .resource = MWAIT_RES(2, 1), }, [C_STATE_C7_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C7_LATENCY, .power = C7_POWER, .resource = MWAIT_RES(3, 0), }, [C_STATE_C7_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C7_LATENCY, .power = C7_POWER, .resource = MWAIT_RES(3, 1), }, [C_STATE_C7S_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C7_LATENCY, .power = C7_POWER, .resource = MWAIT_RES(3, 2), }, [C_STATE_C7S_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C7_LATENCY, .power = C7_POWER, .resource = MWAIT_RES(3, 3), }, [C_STATE_C8] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C8_LATENCY, .power = C8_POWER, .resource = MWAIT_RES(4, 0), }, [C_STATE_C9] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C9_LATENCY, .power = C9_POWER, .resource = MWAIT_RES(5, 0), }, [C_STATE_C10] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C10_LATENCY, .power = C10_POWER, .resource = MWAIT_RES(6, 0), }, }; static int cstate_set_non_s0ix[] = { - C_STATE_C1E, + C_STATE_C1, C_STATE_C6_LONG_LAT, C_STATE_C7S_LONG_LAT }; static int cstate_set_s0ix[] = { - C_STATE_C1E, + C_STATE_C1, C_STATE_C7S_LONG_LAT, C_STATE_C10 }; diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 2533fe0..0c84468 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -137,39 +137,6 @@ wrmsr(IA32_ENERGY_PERF_BIAS, msr); } -static void configure_c_states(void) -{ - msr_t msr; - - /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr); - - /* C-state Interrupt Response Latency Control 2 - package C6/C7 long */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); - - /* C-state Interrupt Response Latency Control 3 - package C8 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_32768_NS | - C_STATE_LATENCY_CONTROL_3_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); - - /* C-state Interrupt Response Latency Control 4 - package C9 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_32768_NS | - C_STATE_LATENCY_CONTROL_4_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); - - /* C-state Interrupt Response Latency Control 5 - package C10 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_32768_NS | - C_STATE_LATENCY_CONTROL_5_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -183,9 +150,6 @@ enable_lapic_tpr(); setup_lapic(); - /* Configure c-state interrupt response time */ - configure_c_states(); - /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/soc/intel/jasperlake/include/soc/cpu.h b/src/soc/intel/jasperlake/include/soc/cpu.h index 1e5332d..c61f2ee 100644 --- a/src/soc/intel/jasperlake/include/soc/cpu.h +++ b/src/soc/intel/jasperlake/include/soc/cpu.h @@ -5,13 +5,13 @@ #include <intelblocks/msr.h> -/* Latency times in units of 32768ns */ -#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x9d -#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x9d -#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x9d -#define C_STATE_LATENCY_CONTROL_3_LIMIT 0x9d -#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x9d -#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x9d +/* Latency times in us */ +#define C1_LATENCY 1 +#define C6_LATENCY 127 +#define C7_LATENCY 253 +#define C8_LATENCY 260 +#define C9_LATENCY 487 +#define C10_LATENCY 1048 /* Power in units of mW */ #define C1_POWER 0x3e8 -- To view, visit https://review.coreboot.org/c/coreboot/+/40902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05c0b5b31d1883f72ca94171aa1b536621e97449 Gerrit-Change-Number: 40902 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: drivers/ipmi: drop redundant option `wait_for_bmc`
by Paul Menzel (Code Review) 03 Jun '20

03 Jun '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42020 ) Change subject: drivers/ipmi: drop redundant option `wait_for_bmc` ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/42020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id26f85e82a13f53a3731ab88035f2ae4bbffac00 Gerrit-Change-Number: 42020 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Kollasch <jakllsch(a)kollasch.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 03 Jun 2020 10:50:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede: config spk_en gpio to low by default
by Usha P (Code Review) 03 Jun '20

03 Jun '20

Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41853 ) Change subject: mb/google/dedede: config spk_en gpio to low by default ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/41853/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/41853/3//COMMIT_MSG@10 PS3, Line 10: based on use, so configure it low to save power. > Did you measure the power saving? Yes, we are seeing a power saving of ~10mW. -- To view, visit https://review.coreboot.org/c/coreboot/+/41853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I070679457b06cb82633c1197b893a5d89c8b2cf0 Gerrit-Change-Number: 41853 Gerrit-PatchSet: 3 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 03 Jun 2020 10:47:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede: config spk_en gpio to low by default
by Paul Menzel (Code Review) 03 Jun '20

03 Jun '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41853 ) Change subject: mb/google/dedede: config spk_en gpio to low by default ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/41853/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/41853/3//COMMIT_MSG@10 PS3, Line 10: based on use, so configure it low to save power. Did you measure the power saving? -- To view, visit https://review.coreboot.org/c/coreboot/+/41853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I070679457b06cb82633c1197b893a5d89c8b2cf0 Gerrit-Change-Number: 41853 Gerrit-PatchSet: 3 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 03 Jun 2020 10:00:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/hatch: Enable the CSE Lite SKU for Puff variants
by 9elements QA (Code Review) 03 Jun '20

03 Jun '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41199 ) Change subject: mb/google/hatch: Enable the CSE Lite SKU for Puff variants ...................................................................... Patch Set 9: Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4746 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4745 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4744 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4743 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/41199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0de6bca162b01870ca554ae97bc4a41cf66fef18 Gerrit-Change-Number: 41199 Gerrit-PatchSet: 9 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 03 Jun 2020 07:52:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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