coreboot-gerrit June 2020

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Change in coreboot[master]: northbridge/intel/sandybridge: Update hostbridge.asl to ASL2.0 syntax
by Furquan Shaikh (Code Review) 03 Jun '20

03 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41978 ) Change subject: northbridge/intel/sandybridge: Update hostbridge.asl to ASL2.0 syntax ...................................................................... northbridge/intel/sandybridge: Update hostbridge.asl to ASL2.0 syntax This change updates hostbridge.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for google/link. Change-Id: I5345ee22df7da92ee48c718f5bd748d7ea6155f2 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/northbridge/intel/sandybridge/acpi/hostbridge.asl 1 file changed, 26 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/41978/1 diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index c3561f8..c8efc98 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -130,17 +130,16 @@ External (\_SB.CP00._PSS) Method (PSSS, 1, NotSerialized) { - Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_SB.CP00._PSS), Local1) + Local0 = 1 /* Start at P1 */ + Local1 = SizeOf (\_SB.CP00._PSS) - While (LLess (Local0, Local1)) { + While (Local0 < Local1) { /* Store _PSS entry Control value to Local2 */ - ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_SB.CP00._PSS, Local0)), 4)), 8, Local2) - If (LEqual (Local2, Arg0)) { - Return (Subtract (Local0, 1)) + Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8 + If (Local2 == Arg0) { + Return (Local0 - 1) } - Increment (Local0) + Local0++ } Return (0) @@ -160,23 +159,23 @@ Store ("Set TDP Down", Debug) /* Set CTC */ - Store (CTCD, CTCS) + CTCS = CTCD /* Set TAR */ - Store (TARD, TARS) + TARS = TARD /* Set PPC limit and notify OS */ - Store (PSSS (TARD), PPCM) + PPCM = PSSS (TARD) PPCN () /* Set PL2 to 1.25 * PL1 */ - Divide (Multiply (CTDD, 125), 100, , PL2V) + PL2V = (CTDD * 125) / 100 /* Set PL1 */ - Store (CTDD, PL1V) + PL1V = CTDD /* Store the new TDP Down setting */ - Store (CTCD, CTCC) + CTCC = CTCD Release (CTCM) Return (1) @@ -196,23 +195,23 @@ Store ("Set TDP Nominal", Debug) /* Set PL1 */ - Store (CTDN, PL1V) + PL1V = CTDN /* Set PL2 to 1.25 * PL1 */ - Divide (Multiply (CTDN, 125), 100, , PL2V) + PL2V = (CTDN * 125) / 100 /* Set PPC limit and notify OS */ - Store (PSSS (TARN), PPCM) + PPCM = PSSS (TARN) PPCN () /* Set TAR */ - Store (TARN, TARS) + TARS = TARN /* Set CTC */ - Store (CTCN, CTCS) + CTCS = CTCN /* Store the new TDP Nominal setting */ - Store (CTCN, CTCC) + CTCC = CTCN Release (CTCM) Return (1) @@ -343,18 +342,18 @@ // Fix up PCI memory region // Start with Top of Lower Usable DRAM - Store (^MCHC.TLUD, Local0) - Store (^MCHC.MEBA, Local1) + Local0 = ^MCHC.TLUD + Local1 = ^MCHC.MEBA // Check if ME base is equal - If (LEqual (Local0, Local1)) { + If (Local0 == Local1) { // Use Top Of Memory instead - Store (^MCHC.TOM, Local0) + Local0 = ^MCHC.TOM } - Store (Local0, PMIN) - Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) - Add(Subtract(PMAX, PMIN), 1, PLEN) + PMIN = Local0 + PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1 + PLEN = PMAX - PMIN + 1 Return (MCRS) } -- To view, visit https://review.coreboot.org/c/coreboot/+/41978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5345ee22df7da92ee48c718f5bd748d7ea6155f2 Gerrit-Change-Number: 41978 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Update C-States info
by 9elements QA (Code Review) 03 Jun '20

03 Jun '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40902 ) Change subject: soc/intel/jasperlake: Update C-States info ...................................................................... Patch Set 7: Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4799 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4798 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4797 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4796 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/40902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05c0b5b31d1883f72ca94171aa1b536621e97449 Gerrit-Change-Number: 40902 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 03 Jun 2020 14:25:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: northbridge/intel/haswell: Update hostbridge.asl to ASL2.0
by Furquan Shaikh (Code Review) 03 Jun '20

03 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41976 ) Change subject: northbridge/intel/haswell: Update hostbridge.asl to ASL2.0 ...................................................................... northbridge/intel/haswell: Update hostbridge.asl to ASL2.0 This change updates hostbridge.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for google/beltino. Change-Id: I0ba2da441c7b398cc7f84a7ef7a5d233b0365cbe Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/northbridge/intel/haswell/acpi/hostbridge.asl 1 file changed, 40 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/41976/1 diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index d8e35d3..8fbfabf 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -141,17 +141,16 @@ External (\_SB.CP00._PSS) Method (PSSS, 1, NotSerialized) { - Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_SB.CP00._PSS), Local1) + Local0 = One /* Start at P1 */ + Local1 = SizeOf (\_SB.CP00._PSS) - While (LLess (Local0, Local1)) { + While (Local0 < Local1) { /* Store _PSS entry Control value to Local2 */ - ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_SB.CP00._PSS, Local0)), 4)), 8, Local2) - If (LEqual (Local2, Arg0)) { - Return (Subtract (Local0, 1)) + Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8 + If (Local2 == Arg0) { + Return (Local0 - 1) } - Increment (Local0) + Local0++ } Return (0) @@ -162,10 +161,10 @@ { If (\ISLP ()) { /* Haswell ULT PL2 = 25W */ - Return (Multiply (25, 8)) + Return (25 * 8) } Else { /* Haswell Mobile PL2 = 1.25 * PL1 */ - Return (Divide (Multiply (Arg0, 125), 100)) + Return ((Arg0 * 125) / 100) } } @@ -183,23 +182,23 @@ Store ("Set TDP Down", Debug) /* Set CTC */ - Store (CTCD, CTCS) + CTCS = CTCD /* Set TAR */ - Store (TARD, TARS) + TARS = TARD /* Set PPC limit and notify OS */ - Store (PSSS (TARD), PPCM) + PPCM = PSSS (TARD) PPCN () /* Set PL2 */ - Store (CPL2 (CTDD), PL2V) + PL2V = CPL2 (CTDD) /* Set PL1 */ - Store (CTDD, PL1V) + PL1V = CTDD /* Store the new TDP Down setting */ - Store (CTCD, CTCC) + CTCC = CTCD Release (CTCM) Return (1) @@ -211,7 +210,7 @@ If (Acquire (CTCM, 100)) { Return (0) } - If (LEqual (CTCN, CTCC)) { + If (CTCN == CTCC) { Release (CTCM) Return (0) } @@ -219,23 +218,23 @@ Store ("Set TDP Nominal", Debug) /* Set PL1 */ - Store (CTDN, PL1V) + PL1V = CTDN /* Set PL2 */ - Store (CPL2 (CTDN), PL2V) + PL2V = CPL2 (CTDN) /* Set PPC limit and notify OS */ - Store (PSSS (TARN), PPCM) + PPCM = PSSS (TARN) PPCN () /* Set TAR */ - Store (TARN, TARS) + TARS = TARN /* Set CTC */ - Store (CTCN, CTCS) + CTCS = CTCN /* Store the new TDP Nominal setting */ - Store (CTCN, CTCC) + CTCC = CTCN Release (CTCM) Return (1) @@ -244,7 +243,7 @@ /* Calculate PL1 value based on requested TDP */ Method (TDPP, 1, NotSerialized) { - Return (Multiply (ShiftLeft (Subtract (PUNI, 1), 2), Arg0)) + Return (((PUNI - 1) << 2) * Arg0) } /* Enable Controllable TDP to limit PL1 to requested value */ @@ -257,19 +256,19 @@ Store ("Enable PL1 Limit", Debug) /* Set _PPC to LFM */ - Store (PSSS (LFM_), Local0) - Add (Local0, 1, PPCM) + Local0 = PSSS (LFM_) + PPCM = Local0 + 1 \PPCN () /* Set TAR to LFM-1 */ - Subtract (LFM_, 1, TARS) + TARS = LFM_ - 1 /* Set PL1 to desired value */ - Store (PL1V, SPL1) - Store (TDPP (Arg0), PL1V) + SPL1 = PL1V + PL1V = TDPP (Arg0) /* Set PL1 CLAMP bit */ - Store (One, PL1C) + PL1C = 1 Release (CTCM) Return (1) @@ -285,16 +284,16 @@ Store ("Disable PL1 Limit", Debug) /* Clear PL1 CLAMP bit */ - Store (Zero, PL1C) + PL1C = 0 /* Set PL1 to normal value */ - Store (SPL1, PL1V) + PL1V = SPL1 /* Set TAR to 0 */ - Store (Zero, TARS) + TARS = 0 /* Set _PPC to 0 */ - Store (Zero, PPCM) + PPCM = 0 \PPCN () Release (CTCM) @@ -426,18 +425,18 @@ // Fix up PCI memory region // Start with Top of Lower Usable DRAM - Store (^MCHC.TLUD, Local0) - Store (^MCHC.MEBA, Local1) + Local0 = ^MCHC.TLUD + Local1 = ^MCHC.MEBA // Check if ME base is equal - If (LEqual (Local0, Local1)) { + If (Local0 == Local1) { // Use Top Of Memory instead - Store (^MCHC.TOM, Local0) + Local0 = ^MCHC.TOM } - Store (Local0, PMIN) - Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) - Add(Subtract(PMAX, PMIN), 1, PLEN) + PMIN = Local0 + PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1 + PLEN = PMAX - PMIN + 1 Return (MCRS) } -- To view, visit https://review.coreboot.org/c/coreboot/+/41976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ba2da441c7b398cc7f84a7ef7a5d233b0365cbe Gerrit-Change-Number: 41976 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register
by HAOUAS Elyes (Code Review) 03 Jun '20

03 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40841 ) Change subject: soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register ...................................................................... soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register Change-Id: Ibe9752a3f09e8944f7fbcf385b83faae95a7cd9b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/graphics.c 2 files changed, 8 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/40841/1 diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index c240f3b..2af4cc4 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -42,22 +42,21 @@ static void soc_config_pwrmbase(void) { uint32_t reg32; + uint16_t reg16; /* * Assign Resources to PWRMBASE * Clear BIT 1-2 Command Register */ - reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MEMORY); - pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); + reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MEMORY); + pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); /* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); /* Enable Bus Master and MMIO Space */ - reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); - reg32 |= PCI_COMMAND_MEMORY; - pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); /* Enable PWRM in PMC */ reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c index b8192c9..a1ec5bb 100644 --- a/src/soc/intel/icelake/graphics.c +++ b/src/soc/intel/icelake/graphics.c @@ -43,9 +43,9 @@ return; /* IGD needs to Bus Master */ - uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); + uint16_t reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config16(dev, PCI_COMMAND, reg16); /* Initialize PCI device, load/execute BIOS Option ROM */ pci_dev_init(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/40841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe9752a3f09e8944f7fbcf385b83faae95a7cd9b Gerrit-Change-Number: 40841 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/tigerlake: Fix 16-bit read/write PCI_COMMAND register
by HAOUAS Elyes (Code Review) 03 Jun '20

03 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40838 ) Change subject: soc/tigerlake: Fix 16-bit read/write PCI_COMMAND register ...................................................................... soc/tigerlake: Fix 16-bit read/write PCI_COMMAND register Change-Id: I1731313798a4aadcbc17808bfe02b50bf8bd41db Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/tigerlake/bootblock/pch.c M src/soc/intel/tigerlake/graphics.c 2 files changed, 8 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/40838/1 diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index a3f38c2..eaac177 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -51,22 +51,21 @@ static void soc_config_pwrmbase(void) { uint32_t reg32; + uint16_t reg16; /* * Assign Resources to PWRMBASE * Clear BIT 1-2 Command Register */ - reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MEMORY); - pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); + reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MEMORY); + pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); /* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); /* Enable Bus Master and MMIO Space */ - reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); - reg32 |= PCI_COMMAND_MEMORY; - pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); /* Enable PWRM in PMC */ reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c index eaa07c3..96b1ca8 100644 --- a/src/soc/intel/tigerlake/graphics.c +++ b/src/soc/intel/tigerlake/graphics.c @@ -49,9 +49,9 @@ return; /* IGD needs to Bus Master */ - uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); + uint16_t reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config16(dev, PCI_COMMAND, reg16); /* Initialize PCI device, load/execute BIOS Option ROM */ pci_dev_init(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/40838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1731313798a4aadcbc17808bfe02b50bf8bd41db Gerrit-Change-Number: 40838 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: Makefile: Drop HAVE_SMI_HANDLER test for smm-class
by Kyösti Mälkki (Code Review) 03 Jun '20

03 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41984 ) Change subject: Makefile: Drop HAVE_SMI_HANDLER test for smm-class ...................................................................... Makefile: Drop HAVE_SMI_HANDLER test for smm-class Change-Id: Id0bb5266246dbd959c6497d7c411f908cc49318c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/dedede/Makefile.inc M src/mainboard/intel/jasperlake_rvp/Makefile.inc 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/41984/1 diff --git a/src/mainboard/google/dedede/Makefile.inc b/src/mainboard/google/dedede/Makefile.inc index 9af93dd..76b1af1 100644 --- a/src/mainboard/google/dedede/Makefile.inc +++ b/src/mainboard/google/dedede/Makefile.inc @@ -10,7 +10,7 @@ ramstage-y += ec.c ramstage-y += board_info.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/baseboard subdirs-y += spd diff --git a/src/mainboard/intel/jasperlake_rvp/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/Makefile.inc index c1fde49..a1cd12c 100644 --- a/src/mainboard/intel/jasperlake_rvp/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/Makefile.inc @@ -15,7 +15,7 @@ ramstage-y += mainboard.c ramstage-y += board_id.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += ../common subdirs-y += variants/baseboard -- To view, visit https://review.coreboot.org/c/coreboot/+/41984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0bb5266246dbd959c6497d7c411f908cc49318c Gerrit-Change-Number: 41984 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Fix 16-bit read/write PCI_COMMAND register
by HAOUAS Elyes (Code Review) 03 Jun '20

03 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40840 ) Change subject: soc/intel/jasperlake: Fix 16-bit read/write PCI_COMMAND register ...................................................................... soc/intel/jasperlake: Fix 16-bit read/write PCI_COMMAND register Change-Id: I78f091e0d3d17fcfc60cd54721b34d143cbe2d86 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/jasperlake/bootblock/pch.c M src/soc/intel/jasperlake/graphics.c 2 files changed, 8 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/40840/1 diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c index 9c517fe..3897d0d 100644 --- a/src/soc/intel/jasperlake/bootblock/pch.c +++ b/src/soc/intel/jasperlake/bootblock/pch.c @@ -46,22 +46,21 @@ static void soc_config_pwrmbase(void) { uint32_t reg32; + uint16_t reg16; /* * Assign Resources to PWRMBASE * Clear BIT 1-2 Command Register */ - reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MEMORY); - pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); + reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MEMORY); + pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); /* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); /* Enable Bus Master and MMIO Space */ - reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); - reg32 |= PCI_COMMAND_MEMORY; - pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); /* Enable PWRM in PMC */ reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c index b8192c9..a1ec5bb 100644 --- a/src/soc/intel/jasperlake/graphics.c +++ b/src/soc/intel/jasperlake/graphics.c @@ -43,9 +43,9 @@ return; /* IGD needs to Bus Master */ - uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); + uint16_t reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config16(dev, PCI_COMMAND, reg16); /* Initialize PCI device, load/execute BIOS Option ROM */ pci_dev_init(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/40840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78f091e0d3d17fcfc60cd54721b34d143cbe2d86 Gerrit-Change-Number: 40840 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/aopen/dxplplusu: Control SMI related FADT entries
by Kyösti Mälkki (Code Review) 03 Jun '20

03 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41904 ) Change subject: mb/aopen/dxplplusu: Control SMI related FADT entries ...................................................................... mb/aopen/dxplplusu: Control SMI related FADT entries When no SMI is installed, FADT should not advertise a trigger mechanism that does respond. Board does not support ACPI S4 or C-states or P-states. Change-Id: If83efb72e076d404468259e312a5afac625f04af Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/aopen/dxplplusu/fadt.c 1 file changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/41904/1 diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/mainboard/aopen/dxplplusu/fadt.c index 36465eb..339c243 100644 --- a/src/mainboard/aopen/dxplplusu/fadt.c +++ b/src/mainboard/aopen/dxplplusu/fadt.c @@ -37,11 +37,13 @@ fadt->preferred_pm_profile = 0; /* PM_MOBILE; */ fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = ACPI_ENABLE; - fadt->acpi_disable = ACPI_DISABLE; - fadt->s4bios_req = S4_BIOS; - fadt->pstate_cnt = PST_CONTROL; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = ACPI_ENABLE; + fadt->acpi_disable = ACPI_DISABLE; + fadt->pstate_cnt = PST_CONTROL; + } fadt->pm1a_evt_blk = pmbase; fadt->pm1b_evt_blk = 0x0; @@ -60,7 +62,6 @@ fadt->gpe0_blk_len = 8; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; /* CST_CONTROL; */ fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 85; fadt->flush_size = 1024; -- To view, visit https://review.coreboot.org/c/coreboot/+/41904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If83efb72e076d404468259e312a5afac625f04af Gerrit-Change-Number: 41904 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by Paul Menzel (Code Review) 03 Jun '20

03 Jun '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35403 ) Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... Patch Set 89: (1 comment) https://review.coreboot.org/c/coreboot/+/35403/89//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35403/89//COMMIT_MSG@10 PS89, Line 10: Please make this a list/enumeration. -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 89 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 03 Jun 2020 13:37:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cyan,intel/strago: Remove EC_GOOGLE_CHROMEEC tests
by Kyösti Mälkki (Code Review) 03 Jun '20

03 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41982 ) Change subject: mb/google/cyan,intel/strago: Remove EC_GOOGLE_CHROMEEC tests ...................................................................... mb/google/cyan,intel/strago: Remove EC_GOOGLE_CHROMEEC tests Boards have unconditional select EC_GOOGLE_CHROMEEC. Change-Id: Id444c83fc40f908d2257e8ec2606f149722a9bde Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/cyan/ec.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/intel/strago/ec.c M src/mainboard/intel/strago/smihandler.c 4 files changed, 2 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/41982/1 diff --git a/src/mainboard/google/cyan/ec.c b/src/mainboard/google/cyan/ec.c index f69d4c4..912ae56 100644 --- a/src/mainboard/google/cyan/ec.c +++ b/src/mainboard/google/cyan/ec.c @@ -19,8 +19,7 @@ printk(BIOS_DEBUG, "mainboard_ec_init\n"); post_code(0xf0); - if (CONFIG(EC_GOOGLE_CHROMEEC)) - google_chromeec_events_init(&info, acpi_is_wakeup_s3()); + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); post_code(0xf1); } diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 160b14b..693a72d 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -41,7 +41,6 @@ return 1; } -#if CONFIG(EC_GOOGLE_CHROMEEC) static uint8_t mainboard_smi_ec(void) { uint8_t cmd = google_chromeec_get_event(); @@ -65,7 +64,6 @@ return cmd; } -#endif /* * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that @@ -73,13 +71,11 @@ */ void mainboard_smi_gpi(uint32_t alt_gpio_smi) { -#if CONFIG(EC_GOOGLE_CHROMEEC) if (alt_gpio_smi & (1 << EC_SMI_GPI)) { /* Process all pending events */ while (mainboard_smi_ec() != 0) ; } -#endif } void mainboard_smi_sleep(uint8_t slp_typ) @@ -90,7 +86,6 @@ /* Disable USB charging if required */ switch (slp_typ) { case ACPI_S3: -#if CONFIG(EC_GOOGLE_CHROMEEC) if (smm_get_gnvs()->s3u0 == 0) google_chromeec_set_usb_charge_mode( 0, USB_CHARGE_MODE_DISABLED); @@ -100,12 +95,10 @@ /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); -#endif /* Enable wake pin in GPE block. */ enable_gpe(WAKE_GPIO_EN); break; case ACPI_S5: -#if CONFIG(EC_GOOGLE_CHROMEEC) if (smm_get_gnvs()->s5u0 == 0) google_chromeec_set_usb_charge_mode( 0, USB_CHARGE_MODE_DISABLED); @@ -115,7 +108,6 @@ /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); -#endif /* Disabling wake from SUS_GPIO1 (TOUCH INT) and * SUS_GPIO7 (TRACKPAD INT) in North bank as they are not @@ -129,7 +121,6 @@ break; } -#if CONFIG(EC_GOOGLE_CHROMEEC) /* Disable SCI and SMI events */ google_chromeec_set_smi_mask(0); google_chromeec_set_sci_mask(0); @@ -142,29 +133,24 @@ if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5)) { lpc_set_low_power(); } -#endif } int mainboard_smi_apmc(uint8_t apmc) { switch (apmc) { case APM_CNT_ACPI_ENABLE: -#if CONFIG(EC_GOOGLE_CHROMEEC) google_chromeec_set_smi_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0) ; google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); -#endif break; case APM_CNT_ACPI_DISABLE: -#if CONFIG(EC_GOOGLE_CHROMEEC) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0) ; google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); -#endif break; } return 0; diff --git a/src/mainboard/intel/strago/ec.c b/src/mainboard/intel/strago/ec.c index f69d4c4..912ae56 100644 --- a/src/mainboard/intel/strago/ec.c +++ b/src/mainboard/intel/strago/ec.c @@ -19,8 +19,7 @@ printk(BIOS_DEBUG, "mainboard_ec_init\n"); post_code(0xf0); - if (CONFIG(EC_GOOGLE_CHROMEEC)) - google_chromeec_events_init(&info, acpi_is_wakeup_s3()); + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); post_code(0xf1); } diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index e770057..4116ed4 100644 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -40,7 +40,6 @@ return 1; } -#if CONFIG(EC_GOOGLE_CHROMEEC) static uint8_t mainboard_smi_ec(void) { uint8_t cmd = google_chromeec_get_event(); @@ -64,7 +63,6 @@ return cmd; } -#endif /* * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that @@ -72,13 +70,11 @@ */ void mainboard_smi_gpi(uint32_t alt_gpio_smi) { -#if CONFIG(EC_GOOGLE_CHROMEEC) if (alt_gpio_smi & (1 << EC_SMI_GPI)) { /* Process all pending events */ while (mainboard_smi_ec() != 0) ; } -#endif } void mainboard_smi_sleep(uint8_t slp_typ) @@ -86,7 +82,6 @@ /* Disable USB charging if required */ switch (slp_typ) { case ACPI_S3: -#if CONFIG(EC_GOOGLE_CHROMEEC) if (smm_get_gnvs()->s3u0 == 0) google_chromeec_set_usb_charge_mode( 0, USB_CHARGE_MODE_DISABLED); @@ -96,12 +91,10 @@ /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); -#endif /* Enable wake pin in GPE block. */ enable_gpe(WAKE_GPIO_EN); break; case ACPI_S5: -#if CONFIG(EC_GOOGLE_CHROMEEC) if (smm_get_gnvs()->s5u0 == 0) google_chromeec_set_usb_charge_mode( 0, USB_CHARGE_MODE_DISABLED); @@ -111,11 +104,9 @@ /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); -#endif break; } -#if CONFIG(EC_GOOGLE_CHROMEEC) /* Disable SCI and SMI events */ google_chromeec_set_smi_mask(0); google_chromeec_set_sci_mask(0); @@ -127,29 +118,24 @@ /* Set LPC lines to low power in S3/S5. */ if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5)) lpc_set_low_power(); -#endif } int mainboard_smi_apmc(uint8_t apmc) { switch (apmc) { case APM_CNT_ACPI_ENABLE: -#if CONFIG(EC_GOOGLE_CHROMEEC) google_chromeec_set_smi_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0) ; google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); -#endif break; case APM_CNT_ACPI_DISABLE: -#if CONFIG(EC_GOOGLE_CHROMEEC) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0) ; google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); -#endif break; } return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/41982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id444c83fc40f908d2257e8ec2606f149722a9bde Gerrit-Change-Number: 41982 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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