coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: drivers/intel/fsp2_0: Add FSP 2.2 specific support
by Nathaniel L Desimone (Code Review) 04 Jun '20

04 Jun '20

Nathaniel L Desimone has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41728 ) Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support ...................................................................... Patch Set 9: (2 comments) https://review.coreboot.org/c/coreboot/+/41728/3/src/drivers/intel/fsp2_0/K… File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/41728/3/src/drivers/intel/fsp2_0/K… PS3, Line 44: config FSPS_ARCH_UPD : bool : depends on HAVE_FSPS_ARCH_UPD : default y : help : Select this option to use Intel FSP-S Architecture UPDs from FspsUpd.h. > Ack Done https://review.coreboot.org/c/coreboot/+/41728/3/src/drivers/intel/fsp2_0/s… File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/c/coreboot/+/41728/3/src/drivers/intel/fsp2_0/s… PS3, Line 136: multi_phase_si_init > Ack Done -- To view, visit https://review.coreboot.org/c/coreboot/+/41728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Gerrit-Change-Number: 41728 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 04 Jun 2020 17:44:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/spi: Add support for common SPI configuration
by Furquan Shaikh (Code Review) 04 Jun '20

04 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41248 ) Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ...................................................................... soc/amd/common/block/spi: Add support for common SPI configuration This change adds support for following SPI configuration functions to common block SPI driver and exposes them to be used by SoC: 1. fch_spi_early_init(): Sets up SPI ROM base, enables SPI ROM, enables prefetching, disables 4dw burst mode and sets SPI speed and mode. 2. fch_spi_config_modes(): This allows SoC to configure SPI speed and mode. It uses SPI settings from soc_amd_common_config to configure the speed and mode. These functions expect SoC to include soc_amd_common_config in SoC chip config and mainboard to configure these settings in device tree. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: Ia4f231bab69e8450005dd6abe7a8e014d5eb7261 --- M src/soc/amd/common/block/include/amdblocks/chip.h A src/soc/amd/common/block/include/amdblocks/spi.h M src/soc/amd/common/block/spi/Makefile.inc A src/soc/amd/common/block/spi/fch_spi.c M src/soc/amd/common/block/spi/fch_spi_ctrl.c 5 files changed, 202 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/41248/1 diff --git a/src/soc/amd/common/block/include/amdblocks/chip.h b/src/soc/amd/common/block/include/amdblocks/chip.h index 26ad26a..9281bd8 100644 --- a/src/soc/amd/common/block/include/amdblocks/chip.h +++ b/src/soc/amd/common/block/include/amdblocks/chip.h @@ -4,7 +4,19 @@ #ifndef __AMDBLOCKS_CHIP_H__ #define __AMDBLOCKS_CHIP_H__ +#include <amdblocks/spi.h> + struct soc_amd_common_config { + /* + * SPI configuration + * Default values if not overriden by mainboard: + * Read mode - Normal 33MHz + * Normal speed - 66MHz + * Fast speed - 66MHz + * Alt speed - 66MHz + * TPM speed - 66MHz + */ + struct spi_config spi_config; }; /* diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h new file mode 100644 index 0000000..077681d --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __AMDBLOCKS_SPI_H__ +#define __AMDBLOCKS_SPI_H__ + +#define SPI_CNTRL0 0x00 +#define SPI_BUSY BIT(31) + +enum spi_read_mode { + SPI_READ_MODE_NORMAL33M = 0, + /* 1 is reserved. */ + SPI_READ_MODE_DUAL112 = 2, + SPI_READ_MODE_QUAD114 = 3, + SPI_READ_MODE_DUAL122 = 4, + SPI_READ_MODE_QUAD144 = 5, + SPI_READ_MODE_NORMAL66M = 6, + SPI_READ_MODE_FAST_READ = 7, +}; +/* + * SPI read mode is split into bits 18, 29, 30 such that [30:29:18] correspond to bits [2:0] for + * SpiReadMode. + */ +#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) +#define SPI_READ_MODE_UPPER_BITS(x) ((((x) >> 1) & 0x3) << 29) +#define SPI_READ_MODE_LOWER_BITS(x) (((x) & 0x1) << 18) +#define SPI_READ_MODE(x) (SPI_READ_MODE_UPPER_BITS(x) | \ + SPI_READ_MODE_LOWER_BITS(x)) +#define SPI_ACCESS_MAC_ROM_EN BIT(22) + +#define SPI100_ENABLE 0x20 +#define SPI_USE_SPI100 BIT(0) + +/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */ +#define SPI100_SPEED_CONFIG 0x22 +enum spi100_speed { + SPI_SPEED_66M = 0, + SPI_SPEED_33M = 1, + SPI_SPEED_22M = 2, + SPI_SPEED_16M = 3, + SPI_SPEED_100M = 4, + SPI_SPEED_800K = 5, +}; + +#define SPI_SPEED_MASK 0xf +#define SPI_SPEED_MODE(x, shift) (((x) & SPI_SPEED_MASK) << shift) +#define SPI_NORM_SPEED(x) SPI_SPEED_MODE(x, 12) +#define SPI_FAST_SPEED(x) SPI_SPEED_MODE(x, 8) +#define SPI_ALT_SPEED(x) SPI_SPEED_MODE(x, 4) +#define SPI_TPM_SPEED(x) SPI_SPEED_MODE(x, 0) + +#define SPI_SPEED_CFG(n, f, a, t) (SPI_NORM_SPEED(n) | SPI_FAST_SPEED(f) | \ + SPI_ALT_SPEED(a) | SPI_TPM_SPEED(t)) + +#define SPI100_HOST_PREF_CONFIG 0x2c +#define SPI_RD4DW_EN_HOST BIT(15) + +#define SPI_FIFO 0x80 +#define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO) + +struct spi_config { + /* + * Default values if not overriden by mainboard: + * Read mode - Normal 33MHz + * Normal speed - 66MHz + * Fast speed - 66MHz + * Alt speed - 66MHz + * TPM speed - 66MHz + */ + enum spi_read_mode read_mode; + enum spi100_speed normal_speed; + enum spi100_speed fast_speed; + enum spi100_speed altio_speed; + enum spi100_speed tpm_speed; +}; + +/* + * Perform early SPI initialization: + * 1. Sets SPI ROM base and enables SPI ROM + * 2. Enables SPI ROM prefetching + * 3. Disables 4dw burst + * 4. Configures SPI speed and read mode. + * + * This function expects SoC to include soc_amd_common_config in chip SoC config and uses + * settings from mainboard devicetree to configure speed and read mode. + */ +void fch_spi_early_init(void); + +/* + * Configure SPI speed and read mode. + * + * This function expects SoC to include soc_amd_common_config in chip SoC config and uses + * settings from mainboard devicetree to configure speed and read mode. + */ +void fch_spi_config_modes(void); + +#endif /* __AMDBLOCKS_SPI_H__ */ diff --git a/src/soc/amd/common/block/spi/Makefile.inc b/src/soc/amd/common/block/spi/Makefile.inc index 0e706ef..3d541b7 100644 --- a/src/soc/amd/common/block/spi/Makefile.inc +++ b/src/soc/amd/common/block/spi/Makefile.inc @@ -9,4 +9,13 @@ smm-y += fch_spi_ctrl.c endif +bootblock-y += fch_spi.c +romstage-y += fch_spi.c +postcar-y += fch_spi.c +ramstage-y += fch_spi.c +verstage-y += fch_spi.c +ifeq ($(CONFIG_SPI_FLASH_SMM),y) +smm-y += fch_spi.c +endif + endif diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c new file mode 100644 index 0000000..68af70e --- /dev/null +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <amdblocks/chip.h> +#include <amdblocks/lpc.h> +#include <amdblocks/spi.h> +#include <arch/mmio.h> +#include <console/console.h> +#include <soc/iomap.h> +#include <stdint.h> + +static uintptr_t fch_spi_base(void) +{ + uintptr_t base; + + base = lpc_get_spibase(); + + if (base) + return base; + + lpc_initialize_spi_bar(SPI_BASE_ADDRESS, SPI_ROM_ENABLE); + return SPI_BASE_ADDRESS; +} + +static void fch_spi_set_spi100(int norm, int fast, int alt, int tpm) +{ + uintptr_t base = fch_spi_base(); + + write16((void *)(base + SPI100_SPEED_CONFIG), SPI_SPEED_CFG(norm, fast, alt, tpm)); + write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); +} + +static void fch_spi_disable_4dw_burst(void) +{ + uintptr_t base = fch_spi_base(); + uint16_t val = read16((void *)(base + SPI100_HOST_PREF_CONFIG)); + + write16((void *)(base + SPI100_HOST_PREF_CONFIG), val & ~SPI_RD4DW_EN_HOST); +} + +static void fch_spi_set_read_mode(u32 mode) +{ + uintptr_t base = fch_spi_base(); + uint32_t val = read32((void *)(base + SPI_CNTRL0)) & ~SPI_READ_MODE_MASK; + + write32((void *)(base + SPI_CNTRL0), val | SPI_READ_MODE(mode)); +} + +static void fch_spi_config_mb_modes(void) +{ + const struct soc_amd_common_config *cfg = soc_get_common_config(); + + if (!cfg) + die("Common config structure is NULL!\n"); + + const struct spi_config *spi_cfg = &cfg->spi_config; + + fch_spi_set_read_mode(spi_cfg->read_mode); + fch_spi_set_spi100(spi_cfg->normal_speed, spi_cfg->fast_speed, + spi_cfg->altio_speed, spi_cfg->tpm_speed); +} + +static void fch_spi_config_em100_modes(void) +{ + fch_spi_set_read_mode(SPI_READ_MODE_NORMAL33M); + fch_spi_set_spi100(SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M); +} + +void fch_spi_config_modes(void) +{ + if (CONFIG(EM100)) + fch_spi_config_em100_modes(); + else + fch_spi_config_mb_modes(); +} + +void fch_spi_early_init(void) +{ + lpc_initialize_spi_bar(SPI_BASE_ADDRESS, SPI_ROM_ENABLE); + lpc_enable_spi_prefetch(); + fch_spi_disable_4dw_burst(); + fch_spi_config_modes(); +} diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index c0751a3..b048f1c 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -2,9 +2,9 @@ #include <console/console.h> #include <spi_flash.h> -#include <soc/southbridge.h> #include <soc/pci_devs.h> #include <amdblocks/lpc.h> +#include <amdblocks/spi.h> #include <device/pci_ops.h> #include <lib.h> #include <timer.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/41248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4f231bab69e8450005dd6abe7a8e014d5eb7261 Gerrit-Change-Number: 41248 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Select PLATFORM_USES_FSP2_2
by Nathaniel L Desimone (Code Review) 04 Jun '20

04 Jun '20

Nathaniel L Desimone has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41729 ) Change subject: soc/intel/tigerlake: Select PLATFORM_USES_FSP2_2 ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/41729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15252d2db3f8e75d430b84e86cc5141225a3f981 Gerrit-Change-Number: 41729 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 04 Jun 2020 17:42:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Add FSP 2.2 specific support
by Nathaniel L Desimone (Code Review) 04 Jun '20

04 Jun '20

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Change in coreboot[master]: [WIP] cpu/x86/smm: Enable SMM support for Xeon-SP
by Rocky Phagura (Code Review) 04 Jun '20

04 Jun '20

Rocky Phagura has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41829 ) Change subject: [WIP] cpu/x86/smm: Enable SMM support for Xeon-SP ...................................................................... Patch Set 3: (18 comments) > Patch Set 2: > > > Patch Set 2: > > > > (3 comments) > > > > This change is ready for review. > > Fat finger - needs changes first. Eugene, Thank you for the review. I've uploaded patch set 3 with your feedback. I also updated the SMRAM layout map (described on top of smm_load_module). STM stays as is. Moved stacks to the start of SMRAM since stacks grow downward and they can't corrupt any SMM code. SMM GDT (global descriptor table) is set for flat code and flat data, so there are no protections. By having stacks on top, in theory they could grow downward enough to corrupt code and data, though we have a canary in place, it could still cause problems. That is my reasoning for moving stacks to the bottom for better protection (unless we change the descriptor for stack segment and make it bound, then it can be anywhere in SMRAM). https://review.coreboot.org/c/coreboot/+/41829/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/41829/1//COMMIT_MSG@44 PS1, Line 44: exiting SMM properly.i > Trailing i. Done https://review.coreboot.org/c/coreboot/+/41829/1/src/cpu/x86/mp_init.c File src/cpu/x86/mp_init.c: https://review.coreboot.org/c/coreboot/+/41829/1/src/cpu/x86/mp_init.c@546 PS1, Line 546: mdelay(1000); > I guess, that is one of the reasons this is marked as WIP. […] Correct. I would like others to comment if possible. https://review.coreboot.org/c/coreboot/+/41829/1/src/cpu/x86/mp_init.c@776 PS1, Line 776: Thereforefore > Therefore Done https://review.coreboot.org/c/coreboot/+/41829/1/src/cpu/x86/smm/smm_module… File src/cpu/x86/smm/smm_module_loader.c: https://review.coreboot.org/c/coreboot/+/41829/1/src/cpu/x86/smm/smm_module… PS1, Line 59: /** > It’s common to start with exactly `/*` in this file. Done https://review.coreboot.org/c/coreboot/+/41829/1/src/cpu/x86/smm/smm_module… PS1, Line 97: * be created from 0 to num_cpus. > Please re-flow for 96 character line length. Done https://review.coreboot.org/c/coreboot/+/41829/1/src/cpu/x86/smm/smm_module… PS1, Line 218: */ > Please move that on the line above. […] Done https://review.coreboot.org/c/coreboot/+/41829/1/src/cpu/x86/smm/smm_module… PS1, Line 220: int size; > Please use unsigned types were possible. Done https://review.coreboot.org/c/coreboot/+/41829/1/src/cpu/x86/smm/smm_module… PS1, Line 225: */ > https://doc.coreboot.org/coding_style. […] Done https://review.coreboot.org/c/coreboot/+/41829/1/src/cpu/x86/smm/smm_module… PS1, Line 227: - > Please add spaces around the operators. Done https://review.coreboot.org/c/coreboot/+/41829/1/src/cpu/x86/smm/smm_module… PS1, Line 553: if (size > SMM_CODE_SEGMENT_SIZE*2) { > 'size' needs to be reduced here to account for the MSEG and the BIOS RESOURCE LIST when the STM is […] Done https://review.coreboot.org/c/coreboot/+/41829/1/src/cpu/x86/smm/smm_module… PS1, Line 554: base = (char *)(params->smram_end - SMM_CODE_SEGMENT_SIZE); > base gets used outside of this block. Done https://review.coreboot.org/c/coreboot/+/41829/1/src/cpu/x86/smm/smm_module… PS1, Line 567: /* Stacks start at the base of SMRAM. */ > Important issue is the location of the BIOS Resource List. […] Done https://review.coreboot.org/c/coreboot/+/41829/1/src/soc/intel/xeon_sp/Make… File src/soc/intel/xeon_sp/Makefile.inc: https://review.coreboot.org/c/coreboot/+/41829/1/src/soc/intel/xeon_sp/Make… PS1, Line 11: +=smmrelocate.c > Missing space. Done https://review.coreboot.org/c/coreboot/+/41829/1/src/soc/intel/xeon_sp/smmr… File src/soc/intel/xeon_sp/smmrelocate.c: https://review.coreboot.org/c/coreboot/+/41829/1/src/soc/intel/xeon_sp/smmr… PS1, Line 13: */ > Please use the current file header. Done https://review.coreboot.org/c/coreboot/+/41829/1/src/soc/intel/xeon_sp/smmr… PS1, Line 15: #include <types.h> : #include <string.h> : #include <device/device.h> : #include <device/pci.h> : #include <device/pci_ops.h> : #include <cpu/x86/cache.h> : #include <cpu/x86/lapic.h> : #include <cpu/x86/mp.h> : #include <cpu/x86/msr.h> : #include <cpu/x86/mtrr.h> : #include <cpu/x86/smm.h> : #include <cpu/intel/em64t101_save_state.h> : #include <cpu/intel/smm_reloc.h> : #include <console/console.h> : #include <smp/node.h> : #include <soc/cpu.h> : #include <soc/msr.h> : #include <soc/pci_devs.h> : #include "chip.h" > Please include only what you use. Done https://review.coreboot.org/c/coreboot/+/41829/1/src/southbridge/intel/comm… File src/southbridge/intel/common/pmbase.c: https://review.coreboot.org/c/coreboot/+/41829/1/src/southbridge/intel/comm… PS1, Line 87: #if CONFIG(ACPI_INTEL_HARDWARE_SLEEP_VALUES) > Please use C if statement, so all code gets build tested. […] I'm retracting my changes. I have enabled ACPI_INTEL_HARDWARE_SLEEP_VALUES in my board config for now to make this work. Though we should not have ACPI code in a common file that provides access routines of read/write pmbase. https://review.coreboot.org/c/coreboot/+/41829/1/src/southbridge/intel/comm… File src/southbridge/intel/common/smihandler.c: https://review.coreboot.org/c/coreboot/+/41829/1/src/southbridge/intel/comm… PS1, Line 56: static void busmaster_disable_on_bus(int bus) > Use the unused annotation instead? I'm retracting my changes. I have enabled ACPI_INTEL_HARDWARE_SLEEP_VALUES to make this work for now. https://review.coreboot.org/c/coreboot/+/41829/1/src/southbridge/intel/comm… PS1, Line 113: static void southbridge_smi_sleep(void) > Use the unused annotation? I'm retracting my changes. I have enabled ACPI_INTEL_HARDWARE_SLEEP_VALUES to make this work for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/41829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78bd74c11ca42fb430f63711b5ec87d4bfe6ca2a Gerrit-Change-Number: 41829 Gerrit-PatchSet: 3 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Eugene Myers <cedarhouse(a)comcast.net> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki.2011(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ron Minnich <rminnich(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 04 Jun 2020 16:52:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eugene Myers <cedarhouse1(a)comcast.net> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso/Makefile: Allow absolute path for picasso firmware
by Raul Rangel (Code Review) 04 Jun '20

04 Jun '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40910 ) Change subject: soc/amd/picasso/Makefile: Allow absolute path for picasso firmware ...................................................................... soc/amd/picasso/Makefile: Allow absolute path for picasso firmware If AMD_PUBKEY_FILE contains an absolute path the resulting path is incorrect since it contains $(top). BUG=b:147042464 TEST=Build trembyle with absolute and relative path. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ib46b1799fad5588a18411f8c32541192d699cdd4 --- M src/soc/amd/picasso/Makefile.inc 1 file changed, 37 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/40910/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 4790ecb..fdbb49b 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -94,26 +94,26 @@ # # type = 0x0 -FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) +FIRMWARE_LOCATE=$(realpath $(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)))) # type = 0x1 ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_WL_RV.sbin +PSPBTLDR_FILE=$(FIRMWARE_LOCATE)/PspBootLoader_WL_RV.sbin else -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_RV.sbin +PSPBTLDR_FILE=$(FIRMWARE_LOCATE)/PspBootLoader_prod_RV.sbin endif # types = 0x8 and 0x12 -PSP_SMUFW1_SUB1_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmwareRV2.csbin -PSP_SMUFW1_SUB2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmwarePCO.csbin -PSP_SMUFW2_SUB1_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2RV2.csbin -PSP_SMUFW2_SUB2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2PCO.csbin +PSP_SMUFW1_SUB1_FILE=$(FIRMWARE_LOCATE)/SmuFirmwareRV2.csbin +PSP_SMUFW1_SUB2_FILE=$(FIRMWARE_LOCATE)/SmuFirmwarePCO.csbin +PSP_SMUFW2_SUB1_FILE=$(FIRMWARE_LOCATE)/SmuFirmware2RV2.csbin +PSP_SMUFW2_SUB2_FILE=$(FIRMWARE_LOCATE)/SmuFirmware2PCO.csbin ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) # type = 0x9 -PSP_SEC_DBG_KEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RavenSecureDebug_PublicKey.bin +PSP_SEC_DBG_KEY_FILE=$(FIRMWARE_LOCATE)/RavenSecureDebug_PublicKey.bin # type = 0x13 -PSP_SEC_DEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/secure_unlock_prod_RV.sbin +PSP_SEC_DEBUG_FILE=$(FIRMWARE_LOCATE)/secure_unlock_prod_RV.sbin # Enable secure debug unlock PSP_SOFTFUSE_BITS += 0 PSP_TOKEN_UNLOCK="--token-unlock" @@ -121,43 +121,43 @@ ifeq ($(CONFIG_USE_PSPSCUREOS),y) # types = 0x2 -PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/psp_os_combined_prod_RV.sbin +PSPSCUREOS_FILE=$(FIRMWARE_LOCATE)/psp_os_combined_prod_RV.sbin endif # type = 0x21 -PSP_IKEK_FILE=$(top)/$(FIRMWARE_LOCATE)/PspIkekRV.bin +PSP_IKEK_FILE=$(FIRMWARE_LOCATE)/PspIkekRV.bin # type = 0x24 -PSP_SECG1_FILE=$(top)/$(FIRMWARE_LOCATE)/security_policy_RV2_FP5_AM4.sbin -PSP_SECG2_FILE=$(top)/$(FIRMWARE_LOCATE)/security_policy_PCO_FP5_AM4.sbin +PSP_SECG1_FILE=$(FIRMWARE_LOCATE)/security_policy_RV2_FP5_AM4.sbin +PSP_SECG2_FILE=$(FIRMWARE_LOCATE)/security_policy_PCO_FP5_AM4.sbin ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) # type = 0x25 -PSP_MP2FW1_FILE=$(top)/$(FIRMWARE_LOCATE)/MP2I2CFWRV2.sbin -PSP_MP2FW2_FILE=$(top)/$(FIRMWARE_LOCATE)/MP2I2CFWPCO.sbin +PSP_MP2FW1_FILE=$(FIRMWARE_LOCATE)/MP2I2CFWRV2.sbin +PSP_MP2FW2_FILE=$(FIRMWARE_LOCATE)/MP2I2CFWPCO.sbin # BIOS type = 0x6a -PSP_MP2CFG_FILE=$(top)/$(FIRMWARE_LOCATE)/MP2FWConfig.sbin +PSP_MP2CFG_FILE=$(FIRMWARE_LOCATE)/MP2FWConfig.sbin else # Disable MP2 firmware loading PSP_SOFTFUSE_BITS += 29 endif # type = 0x28 -PSP_DRIVERS_FILE=$(top)/$(FIRMWARE_LOCATE)/drv_sys_prod_RV.sbin +PSP_DRIVERS_FILE=$(FIRMWARE_LOCATE)/drv_sys_prod_RV.sbin ifeq ($(CONFIG_PSP_LOAD_S0I3_FW),y) -PSP_S0I3_FILE=$(top)/$(FIRMWARE_LOCATE)/dr_agesa_prod_RV.sbin +PSP_S0I3_FILE=$(FIRMWARE_LOCATE)/dr_agesa_prod_RV.sbin endif # types = 0x30 - 0x37 -PSP_ABL0_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader0_prod_RV.csbin -PSP_ABL1_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader1_prod_RV.csbin -PSP_ABL2_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader2_prod_RV.csbin -PSP_ABL3_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader3_prod_RV.csbin -PSP_ABL4_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader4_prod_RV.csbin -PSP_ABL5_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader5_prod_RV.csbin -PSP_ABL6_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader6_prod_RV.csbin -PSP_ABL7_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader7_prod_RV.csbin +PSP_ABL0_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader0_prod_RV.csbin +PSP_ABL1_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader1_prod_RV.csbin +PSP_ABL2_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader2_prod_RV.csbin +PSP_ABL3_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader3_prod_RV.csbin +PSP_ABL4_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader4_prod_RV.csbin +PSP_ABL5_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader5_prod_RV.csbin +PSP_ABL6_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader6_prod_RV.csbin +PSP_ABL7_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader7_prod_RV.csbin # type = 0x3a ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) @@ -194,19 +194,19 @@ endif # type2 = 0x64, 0x65 -PSP_PMUI_FILE1=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Imem.csbin -PSP_PMUI_FILE2=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_2D_Ddr4_Imem.csbin -PSP_PMUI_FILE3=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv2_1D_ddr4_Udimm_Imem.csbin -PSP_PMUI_FILE4=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv2_2D_ddr4_Udimm_Imem.csbin -PSP_PMUD_FILE1=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin -PSP_PMUD_FILE2=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_2D_Ddr4_Dmem.csbin -PSP_PMUD_FILE3=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin -PSP_PMUD_FILE4=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin +PSP_PMUI_FILE1=$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE2=$(FIRMWARE_LOCATE)/Appb_Rv_2D_Ddr4_Imem.csbin +PSP_PMUI_FILE3=$(FIRMWARE_LOCATE)/Appb_Rv2_1D_ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE4=$(FIRMWARE_LOCATE)/Appb_Rv2_2D_ddr4_Udimm_Imem.csbin +PSP_PMUD_FILE1=$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE2=$(FIRMWARE_LOCATE)/Appb_Rv_2D_Ddr4_Dmem.csbin +PSP_PMUD_FILE3=$(FIRMWARE_LOCATE)/Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE4=$(FIRMWARE_LOCATE)/Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin # type = 0x66 -PSP_UCODE_FILE1=$(top)/$(FIRMWARE_LOCATE)/UcodePatch_PCO_B1.bin -PSP_UCODE_FILE2=$(top)/$(FIRMWARE_LOCATE)/UcodePatch_PCO_B0.bin -PSP_UCODE_FILE3=$(top)/$(FIRMWARE_LOCATE)/UcodePatch_RV2_A0.bin +PSP_UCODE_FILE1=$(FIRMWARE_LOCATE)/UcodePatch_PCO_B1.bin +PSP_UCODE_FILE2=$(FIRMWARE_LOCATE)/UcodePatch_PCO_B0.bin +PSP_UCODE_FILE3=$(FIRMWARE_LOCATE)/UcodePatch_RV2_A0.bin # type = 0xb - See #55758 (NDA) for bit definitions. PSP_SOFTFUSE_BITS += 28 -- To view, visit https://review.coreboot.org/c/coreboot/+/40910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib46b1799fad5588a18411f8c32541192d699cdd4 Gerrit-Change-Number: 40910 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: util/mb/google: add templates for puff boards
by Paul Fagerburg (Code Review) 04 Jun '20

04 Jun '20

Paul Fagerburg has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42026 ) Change subject: util/mb/google: add templates for puff boards ...................................................................... util/mb/google: add templates for puff boards Add template directory for the Puff reference board. BUG=b:157701044 BRANCH=None TEST=N/A Signed-off-by: Paul Fagerburg <pfagerburg(a)chromium.org> Change-Id: Ic81c663b92eeb1d39c2b425d331eb16812f58b7d --- A util/mainboard/google/puff/template/Makefile.inc A util/mainboard/google/puff/template/include/variant/acpi/dptf.asl A util/mainboard/google/puff/template/include/variant/ec.h A util/mainboard/google/puff/template/include/variant/gpio.h A util/mainboard/google/puff/template/overridetree.cb 5 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/42026/1 diff --git a/util/mainboard/google/puff/template/Makefile.inc b/util/mainboard/google/puff/template/Makefile.inc new file mode 100644 index 0000000..61b23ed --- /dev/null +++ b/util/mainboard/google/puff/template/Makefile.inc @@ -0,0 +1,4 @@ +## +## SPDX-License-Identifier: GPL-2.0-only + +SPD_SOURCES = diff --git a/util/mainboard/google/puff/template/include/variant/acpi/dptf.asl b/util/mainboard/google/puff/template/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..fd3b5cf --- /dev/null +++ b/util/mainboard/google/puff/template/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/acpi/dptf.asl> diff --git a/util/mainboard/google/puff/template/include/variant/ec.h b/util/mainboard/google/puff/template/include/variant/ec.h new file mode 100644 index 0000000..ce6fbfe --- /dev/null +++ b/util/mainboard/google/puff/template/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/util/mainboard/google/puff/template/include/variant/gpio.h b/util/mainboard/google/puff/template/include/variant/gpio.h new file mode 100644 index 0000000..79a1410 --- /dev/null +++ b/util/mainboard/google/puff/template/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/util/mainboard/google/puff/template/overridetree.cb b/util/mainboard/google/puff/template/overridetree.cb new file mode 100644 index 0000000..abbcaaa --- /dev/null +++ b/util/mainboard/google/puff/template/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/cannonlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/42026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic81c663b92eeb1d39c2b425d331eb16812f58b7d Gerrit-Change-Number: 42026 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/intel/xeon_sp/cpx: add chip operation and PCIe enumeration
by 9elements QA (Code Review) 04 Jun '20

04 Jun '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40110 ) Change subject: soc/intel/xeon_sp/cpx: add chip operation and PCIe enumeration ...................................................................... Patch Set 20: Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4853 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4852 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4851 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4850 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/40110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If461b1dc1f313d98b676dc9e91d08a1dbb9cb388 Gerrit-Change-Number: 40110 Gerrit-PatchSet: 20 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Morgan Jang Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 04 Jun 2020 15:58:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters
by Philipp Deppenwiese (Code Review) 04 Jun '20

04 Jun '20

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40385 ) Change subject: soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters ...................................................................... Patch Set 21: (1 comment) https://review.coreboot.org/c/coreboot/+/40385/21/src/soc/intel/xeon_sp/cpx… File src/soc/intel/xeon_sp/cpx/romstage.c: https://review.coreboot.org/c/coreboot/+/40385/21/src/soc/intel/xeon_sp/cpx… PS21, Line 24: arch_upd->StackBase = (void *) 0xfe930000; Can we do this as part of the device tree and not hardcode the configuration? -- To view, visit https://review.coreboot.org/c/coreboot/+/40385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d0762a742d8803c7396034e3244120c1e8ece67 Gerrit-Change-Number: 40385 Gerrit-PatchSet: 21 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 04 Jun 2020 15:56:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/xeon_sp/cpx: fix MADT ACPI table
by Philipp Deppenwiese (Code Review) 04 Jun '20

04 Jun '20

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40383 ) Change subject: soc/intel/xeon_sp/cpx: fix MADT ACPI table ...................................................................... Patch Set 20: (2 comments) https://review.coreboot.org/c/coreboot/+/40383/20/src/soc/intel/xeon_sp/cpx… File src/soc/intel/xeon_sp/cpx/acpi.c: https://review.coreboot.org/c/coreboot/+/40383/20/src/soc/intel/xeon_sp/cpx… PS20, Line 191: int gsi_bases[] = { 0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60 }; define? https://review.coreboot.org/c/coreboot/+/40383/20/src/soc/intel/xeon_sp/cpx… File src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h: https://review.coreboot.org/c/coreboot/+/40383/20/src/soc/intel/xeon_sp/cpx… PS20, Line 75: #define VTD_DEV 5 one tab too much -- To view, visit https://review.coreboot.org/c/coreboot/+/40383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1bf6e39db545e227e9867aa8d24f7db1d820216 Gerrit-Change-Number: 40383 Gerrit-PatchSet: 20 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 04 Jun 2020 15:54:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit June 2020