Change in coreboot[master]: soc/amd/common/block/spi: Add support for common SPI configuration
Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41248 )
Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ......................................................................
soc/amd/common/block/spi: Add support for common SPI configuration
This change adds support for following SPI configuration functions to common block SPI driver and exposes them to be used by SoC: 1. fch_spi_early_init(): Sets up SPI ROM base, enables SPI ROM, enables prefetching, disables 4dw burst mode and sets SPI speed and mode. 2. fch_spi_config_modes(): This allows SoC to configure SPI speed and mode. It uses SPI settings from soc_amd_common_config to configure the speed and mode.
These functions expect SoC to include soc_amd_common_config in SoC chip config and mainboard to configure these settings in device tree.
Signed-off-by: Furquan Shaikh furquan@google.com Change-Id: Ia4f231bab69e8450005dd6abe7a8e014d5eb7261 --- M src/soc/amd/common/block/include/amdblocks/chip.h A src/soc/amd/common/block/include/amdblocks/spi.h M src/soc/amd/common/block/spi/Makefile.inc A src/soc/amd/common/block/spi/fch_spi.c M src/soc/amd/common/block/spi/fch_spi_ctrl.c 5 files changed, 202 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/41248/1
diff --git a/src/soc/amd/common/block/include/amdblocks/chip.h b/src/soc/amd/common/block/include/amdblocks/chip.h index 26ad26a..9281bd8 100644 --- a/src/soc/amd/common/block/include/amdblocks/chip.h +++ b/src/soc/amd/common/block/include/amdblocks/chip.h @@ -4,7 +4,19 @@ #ifndef __AMDBLOCKS_CHIP_H__ #define __AMDBLOCKS_CHIP_H__
+#include <amdblocks/spi.h> + struct soc_amd_common_config { + /* + * SPI configuration + * Default values if not overriden by mainboard: + * Read mode - Normal 33MHz + * Normal speed - 66MHz + * Fast speed - 66MHz + * Alt speed - 66MHz + * TPM speed - 66MHz + */ + struct spi_config spi_config; };
/* diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h new file mode 100644 index 0000000..077681d --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __AMDBLOCKS_SPI_H__ +#define __AMDBLOCKS_SPI_H__ + +#define SPI_CNTRL0 0x00 +#define SPI_BUSY BIT(31) + +enum spi_read_mode { + SPI_READ_MODE_NORMAL33M = 0, + /* 1 is reserved. */ + SPI_READ_MODE_DUAL112 = 2, + SPI_READ_MODE_QUAD114 = 3, + SPI_READ_MODE_DUAL122 = 4, + SPI_READ_MODE_QUAD144 = 5, + SPI_READ_MODE_NORMAL66M = 6, + SPI_READ_MODE_FAST_READ = 7, +}; +/* + * SPI read mode is split into bits 18, 29, 30 such that [30:29:18] correspond to bits [2:0] for + * SpiReadMode. + */ +#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) +#define SPI_READ_MODE_UPPER_BITS(x) ((((x) >> 1) & 0x3) << 29) +#define SPI_READ_MODE_LOWER_BITS(x) (((x) & 0x1) << 18) +#define SPI_READ_MODE(x) (SPI_READ_MODE_UPPER_BITS(x) | \ + SPI_READ_MODE_LOWER_BITS(x)) +#define SPI_ACCESS_MAC_ROM_EN BIT(22) + +#define SPI100_ENABLE 0x20 +#define SPI_USE_SPI100 BIT(0) + +/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */ +#define SPI100_SPEED_CONFIG 0x22 +enum spi100_speed { + SPI_SPEED_66M = 0, + SPI_SPEED_33M = 1, + SPI_SPEED_22M = 2, + SPI_SPEED_16M = 3, + SPI_SPEED_100M = 4, + SPI_SPEED_800K = 5, +}; + +#define SPI_SPEED_MASK 0xf +#define SPI_SPEED_MODE(x, shift) (((x) & SPI_SPEED_MASK) << shift) +#define SPI_NORM_SPEED(x) SPI_SPEED_MODE(x, 12) +#define SPI_FAST_SPEED(x) SPI_SPEED_MODE(x, 8) +#define SPI_ALT_SPEED(x) SPI_SPEED_MODE(x, 4) +#define SPI_TPM_SPEED(x) SPI_SPEED_MODE(x, 0) + +#define SPI_SPEED_CFG(n, f, a, t) (SPI_NORM_SPEED(n) | SPI_FAST_SPEED(f) | \ + SPI_ALT_SPEED(a) | SPI_TPM_SPEED(t)) + +#define SPI100_HOST_PREF_CONFIG 0x2c +#define SPI_RD4DW_EN_HOST BIT(15) + +#define SPI_FIFO 0x80 +#define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO) + +struct spi_config { + /* + * Default values if not overriden by mainboard: + * Read mode - Normal 33MHz + * Normal speed - 66MHz + * Fast speed - 66MHz + * Alt speed - 66MHz + * TPM speed - 66MHz + */ + enum spi_read_mode read_mode; + enum spi100_speed normal_speed; + enum spi100_speed fast_speed; + enum spi100_speed altio_speed; + enum spi100_speed tpm_speed; +}; + +/* + * Perform early SPI initialization: + * 1. Sets SPI ROM base and enables SPI ROM + * 2. Enables SPI ROM prefetching + * 3. Disables 4dw burst + * 4. Configures SPI speed and read mode. + * + * This function expects SoC to include soc_amd_common_config in chip SoC config and uses + * settings from mainboard devicetree to configure speed and read mode. + */ +void fch_spi_early_init(void); + +/* + * Configure SPI speed and read mode. + * + * This function expects SoC to include soc_amd_common_config in chip SoC config and uses + * settings from mainboard devicetree to configure speed and read mode. + */ +void fch_spi_config_modes(void); + +#endif /* __AMDBLOCKS_SPI_H__ */ diff --git a/src/soc/amd/common/block/spi/Makefile.inc b/src/soc/amd/common/block/spi/Makefile.inc index 0e706ef..3d541b7 100644 --- a/src/soc/amd/common/block/spi/Makefile.inc +++ b/src/soc/amd/common/block/spi/Makefile.inc @@ -9,4 +9,13 @@ smm-y += fch_spi_ctrl.c endif
+bootblock-y += fch_spi.c +romstage-y += fch_spi.c +postcar-y += fch_spi.c +ramstage-y += fch_spi.c +verstage-y += fch_spi.c +ifeq ($(CONFIG_SPI_FLASH_SMM),y) +smm-y += fch_spi.c +endif + endif diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c new file mode 100644 index 0000000..68af70e --- /dev/null +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <amdblocks/chip.h> +#include <amdblocks/lpc.h> +#include <amdblocks/spi.h> +#include <arch/mmio.h> +#include <console/console.h> +#include <soc/iomap.h> +#include <stdint.h> + +static uintptr_t fch_spi_base(void) +{ + uintptr_t base; + + base = lpc_get_spibase(); + + if (base) + return base; + + lpc_initialize_spi_bar(SPI_BASE_ADDRESS, SPI_ROM_ENABLE); + return SPI_BASE_ADDRESS; +} + +static void fch_spi_set_spi100(int norm, int fast, int alt, int tpm) +{ + uintptr_t base = fch_spi_base(); + + write16((void *)(base + SPI100_SPEED_CONFIG), SPI_SPEED_CFG(norm, fast, alt, tpm)); + write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); +} + +static void fch_spi_disable_4dw_burst(void) +{ + uintptr_t base = fch_spi_base(); + uint16_t val = read16((void *)(base + SPI100_HOST_PREF_CONFIG)); + + write16((void *)(base + SPI100_HOST_PREF_CONFIG), val & ~SPI_RD4DW_EN_HOST); +} + +static void fch_spi_set_read_mode(u32 mode) +{ + uintptr_t base = fch_spi_base(); + uint32_t val = read32((void *)(base + SPI_CNTRL0)) & ~SPI_READ_MODE_MASK; + + write32((void *)(base + SPI_CNTRL0), val | SPI_READ_MODE(mode)); +} + +static void fch_spi_config_mb_modes(void) +{ + const struct soc_amd_common_config *cfg = soc_get_common_config(); + + if (!cfg) + die("Common config structure is NULL!\n"); + + const struct spi_config *spi_cfg = &cfg->spi_config; + + fch_spi_set_read_mode(spi_cfg->read_mode); + fch_spi_set_spi100(spi_cfg->normal_speed, spi_cfg->fast_speed, + spi_cfg->altio_speed, spi_cfg->tpm_speed); +} + +static void fch_spi_config_em100_modes(void) +{ + fch_spi_set_read_mode(SPI_READ_MODE_NORMAL33M); + fch_spi_set_spi100(SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M); +} + +void fch_spi_config_modes(void) +{ + if (CONFIG(EM100)) + fch_spi_config_em100_modes(); + else + fch_spi_config_mb_modes(); +} + +void fch_spi_early_init(void) +{ + lpc_initialize_spi_bar(SPI_BASE_ADDRESS, SPI_ROM_ENABLE); + lpc_enable_spi_prefetch(); + fch_spi_disable_4dw_burst(); + fch_spi_config_modes(); +} diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index c0751a3..b048f1c 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -2,9 +2,9 @@
#include <console/console.h> #include <spi_flash.h> -#include <soc/southbridge.h> #include <soc/pci_devs.h> #include <amdblocks/lpc.h> +#include <amdblocks/spi.h> #include <device/pci_ops.h> #include <lib.h> #include <timer.h>
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41248 )
Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41248/1/src/soc/amd/common/block/in... File src/soc/amd/common/block/include/amdblocks/chip.h:
https://review.coreboot.org/c/coreboot/+/41248/1/src/soc/amd/common/block/in... PS1, Line 12: * Default values if not overriden by mainboard: 'overriden' may be misspelled - perhaps 'overridden'?
https://review.coreboot.org/c/coreboot/+/41248/1/src/soc/amd/common/block/in... File src/soc/amd/common/block/include/amdblocks/spi.h:
https://review.coreboot.org/c/coreboot/+/41248/1/src/soc/amd/common/block/in... PS1, Line 63: * Default values if not overriden by mainboard: 'overriden' may be misspelled - perhaps 'overridden'?
Hello Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41248
to look at the new patch set (#2).
Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ......................................................................
soc/amd/common/block/spi: Add support for common SPI configuration
This change adds support for following SPI configuration functions to common block SPI driver and exposes them to be used by SoC: 1. fch_spi_early_init(): Sets up SPI ROM base, enables SPI ROM, enables prefetching, disables 4dw burst mode and sets SPI speed and mode. 2. fch_spi_config_modes(): This allows SoC to configure SPI speed and mode. It uses SPI settings from soc_amd_common_config to configure the speed and mode.
These functions expect SoC to include soc_amd_common_config in SoC chip config and mainboard to configure these settings in device tree.
Signed-off-by: Furquan Shaikh furquan@google.com Change-Id: Ia4f231bab69e8450005dd6abe7a8e014d5eb7261 --- M src/soc/amd/common/block/include/amdblocks/chip.h A src/soc/amd/common/block/include/amdblocks/spi.h M src/soc/amd/common/block/spi/Makefile.inc A src/soc/amd/common/block/spi/fch_spi.c M src/soc/amd/common/block/spi/fch_spi_ctrl.c 5 files changed, 202 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/41248/2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41248 )
Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41248/1/src/soc/amd/common/block/in... File src/soc/amd/common/block/include/amdblocks/chip.h:
https://review.coreboot.org/c/coreboot/+/41248/1/src/soc/amd/common/block/in... PS1, Line 12: * Default values if not overriden by mainboard:
'overriden' may be misspelled - perhaps 'overridden'?
Done
https://review.coreboot.org/c/coreboot/+/41248/1/src/soc/amd/common/block/in... File src/soc/amd/common/block/include/amdblocks/spi.h:
https://review.coreboot.org/c/coreboot/+/41248/1/src/soc/amd/common/block/in... PS1, Line 63: * Default values if not overriden by mainboard:
'overriden' may be misspelled - perhaps 'overridden'?
Done
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41248 )
Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41248/4/src/soc/amd/common/block/sp... File src/soc/amd/common/block/spi/fch_spi.c:
https://review.coreboot.org/c/coreboot/+/41248/4/src/soc/amd/common/block/sp... PS4, Line 69: fch_spi_config_modes Does all this logic belong in fch_spi_ctrl.c?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41248 )
Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41248/4/src/soc/amd/common/block/sp... File src/soc/amd/common/block/spi/fch_spi.c:
https://review.coreboot.org/c/coreboot/+/41248/4/src/soc/amd/common/block/sp... PS4, Line 69: fch_spi_config_modes
Does all this logic belong in fch_spi_ctrl. […]
fch_spi_ctrl.c is basically exposing a SPI flash controller for use by coreboot and implementing the generic functions expected from the flash controller to talk to the SPI flash - spi_init, spi_xfer, etc. This file is meant for any SPI configuration. I modeled it mostly around how other x86 SoC drivers are currently written.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41248 )
Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ......................................................................
Patch Set 4: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/41248/4/src/soc/amd/common/block/sp... File src/soc/amd/common/block/spi/fch_spi.c:
https://review.coreboot.org/c/coreboot/+/41248/4/src/soc/amd/common/block/sp... PS4, Line 69: fch_spi_config_modes
fch_spi_ctrl. […]
Ack
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41248 )
Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ......................................................................
Patch Set 4: Code-Review+2
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41248 )
Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41248/5/src/soc/amd/common/block/sp... File src/soc/amd/common/block/spi/fch_spi.c:
https://review.coreboot.org/c/coreboot/+/41248/5/src/soc/amd/common/block/sp... PS5, Line 21: lpc_initialize_spi_bar(SPI_BASE_ADDRESS, SPI_ROM_ENABLE); This declaration is unknown?
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41248 )
Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41248/5/src/soc/amd/common/block/sp... File src/soc/amd/common/block/spi/fch_spi.c:
https://review.coreboot.org/c/coreboot/+/41248/5/src/soc/amd/common/block/sp... PS5, Line 21: lpc_initialize_spi_bar(SPI_BASE_ADDRESS, SPI_ROM_ENABLE);
This declaration is unknown?
Looks like we need to do the split here?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41248 )
Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41248/5/src/soc/amd/common/block/sp... File src/soc/amd/common/block/spi/fch_spi.c:
https://review.coreboot.org/c/coreboot/+/41248/5/src/soc/amd/common/block/sp... PS5, Line 21: lpc_initialize_spi_bar(SPI_BASE_ADDRESS, SPI_ROM_ENABLE);
Looks like we need to do the split here?
Yeah, I put the split into the next CL. Need to fix that.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41248 )
Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41248/5/src/soc/amd/common/block/sp... File src/soc/amd/common/block/spi/fch_spi.c:
https://review.coreboot.org/c/coreboot/+/41248/5/src/soc/amd/common/block/sp... PS5, Line 21: lpc_initialize_spi_bar(SPI_BASE_ADDRESS, SPI_ROM_ENABLE);
Yeah, I put the split into the next CL. Need to fix that.
Done. Pushing a new patchset.
Hello build bot (Jenkins), Raul Rangel, Patrick Georgi, Martin Roth, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41248
to look at the new patch set (#6).
Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ......................................................................
soc/amd/common/block/spi: Add support for common SPI configuration
This change adds support for following SPI configuration functions to common block SPI driver and exposes them to be used by SoC: 1. fch_spi_early_init(): Sets up SPI ROM base, enables SPI ROM, enables prefetching, disables 4dw burst mode and sets SPI speed and mode. 2. fch_spi_config_modes(): This allows SoC to configure SPI speed and mode. It uses SPI settings from soc_amd_common_config to configure the speed and mode.
These functions expect SoC to include soc_amd_common_config in SoC chip config and mainboard to configure these settings in device tree.
Signed-off-by: Furquan Shaikh furquan@google.com Change-Id: Ia4f231bab69e8450005dd6abe7a8e014d5eb7261 --- M src/soc/amd/common/block/include/amdblocks/chip.h A src/soc/amd/common/block/include/amdblocks/spi.h M src/soc/amd/common/block/spi/Makefile.inc A src/soc/amd/common/block/spi/fch_spi.c M src/soc/amd/common/block/spi/fch_spi_ctrl.c 5 files changed, 205 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/41248/6
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41248 )
Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ......................................................................
Patch Set 6: Code-Review+2
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41248 )
Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ......................................................................
Patch Set 6: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/41248/6/src/soc/amd/common/block/sp... File src/soc/amd/common/block/spi/fch_spi.c:
https://review.coreboot.org/c/coreboot/+/41248/6/src/soc/amd/common/block/sp... PS6, Line 22: lpc_enable_spi_rom(SPI_ROM_ENABLE); As a cleanup, we should move this out of this function. It's up to the MB to decide if it uses SPI_ROM_ENABLE or SPI_ROM_ALT_ENABLE.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41248 )
Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41248/6/src/soc/amd/common/block/sp... File src/soc/amd/common/block/spi/fch_spi.c:
https://review.coreboot.org/c/coreboot/+/41248/6/src/soc/amd/common/block/sp... PS6, Line 22: lpc_enable_spi_rom(SPI_ROM_ENABLE);
As a cleanup, we should move this out of this function. […]
Agreed. Probably a devicetree config option here would be helpful.
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41248 )
Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ......................................................................
soc/amd/common/block/spi: Add support for common SPI configuration
This change adds support for following SPI configuration functions to common block SPI driver and exposes them to be used by SoC: 1. fch_spi_early_init(): Sets up SPI ROM base, enables SPI ROM, enables prefetching, disables 4dw burst mode and sets SPI speed and mode. 2. fch_spi_config_modes(): This allows SoC to configure SPI speed and mode. It uses SPI settings from soc_amd_common_config to configure the speed and mode.
These functions expect SoC to include soc_amd_common_config in SoC chip config and mainboard to configure these settings in device tree.
Signed-off-by: Furquan Shaikh furquan@google.com Change-Id: Ia4f231bab69e8450005dd6abe7a8e014d5eb7261 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41248 Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Raul Rangel rrangel@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/common/block/include/amdblocks/chip.h A src/soc/amd/common/block/include/amdblocks/spi.h M src/soc/amd/common/block/spi/Makefile.inc A src/soc/amd/common/block/spi/fch_spi.c M src/soc/amd/common/block/spi/fch_spi_ctrl.c 5 files changed, 205 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/common/block/include/amdblocks/chip.h b/src/soc/amd/common/block/include/amdblocks/chip.h index 26ad26a..6e3c973 100644 --- a/src/soc/amd/common/block/include/amdblocks/chip.h +++ b/src/soc/amd/common/block/include/amdblocks/chip.h @@ -4,7 +4,19 @@ #ifndef __AMDBLOCKS_CHIP_H__ #define __AMDBLOCKS_CHIP_H__
+#include <amdblocks/spi.h> + struct soc_amd_common_config { + /* + * SPI configuration + * Default values if not overridden by mainboard: + * Read mode - Normal 33MHz + * Normal speed - 66MHz + * Fast speed - 66MHz + * Alt speed - 66MHz + * TPM speed - 66MHz + */ + struct spi_config spi_config; };
/* diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h new file mode 100644 index 0000000..d901f7e --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __AMDBLOCKS_SPI_H__ +#define __AMDBLOCKS_SPI_H__ + +#define SPI_CNTRL0 0x00 +#define SPI_BUSY BIT(31) + +enum spi_read_mode { + SPI_READ_MODE_NORMAL33M = 0, + /* 1 is reserved. */ + SPI_READ_MODE_DUAL112 = 2, + SPI_READ_MODE_QUAD114 = 3, + SPI_READ_MODE_DUAL122 = 4, + SPI_READ_MODE_QUAD144 = 5, + SPI_READ_MODE_NORMAL66M = 6, + SPI_READ_MODE_FAST_READ = 7, +}; +/* + * SPI read mode is split into bits 18, 29, 30 such that [30:29:18] correspond to bits [2:0] for + * SpiReadMode. + */ +#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) +#define SPI_READ_MODE_UPPER_BITS(x) ((((x) >> 1) & 0x3) << 29) +#define SPI_READ_MODE_LOWER_BITS(x) (((x) & 0x1) << 18) +#define SPI_READ_MODE(x) (SPI_READ_MODE_UPPER_BITS(x) | \ + SPI_READ_MODE_LOWER_BITS(x)) +#define SPI_ACCESS_MAC_ROM_EN BIT(22) + +#define SPI100_ENABLE 0x20 +#define SPI_USE_SPI100 BIT(0) + +/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */ +#define SPI100_SPEED_CONFIG 0x22 +enum spi100_speed { + SPI_SPEED_66M = 0, + SPI_SPEED_33M = 1, + SPI_SPEED_22M = 2, + SPI_SPEED_16M = 3, + SPI_SPEED_100M = 4, + SPI_SPEED_800K = 5, +}; + +#define SPI_SPEED_MASK 0xf +#define SPI_SPEED_MODE(x, shift) (((x) & SPI_SPEED_MASK) << shift) +#define SPI_NORM_SPEED(x) SPI_SPEED_MODE(x, 12) +#define SPI_FAST_SPEED(x) SPI_SPEED_MODE(x, 8) +#define SPI_ALT_SPEED(x) SPI_SPEED_MODE(x, 4) +#define SPI_TPM_SPEED(x) SPI_SPEED_MODE(x, 0) + +#define SPI_SPEED_CFG(n, f, a, t) (SPI_NORM_SPEED(n) | SPI_FAST_SPEED(f) | \ + SPI_ALT_SPEED(a) | SPI_TPM_SPEED(t)) + +#define SPI100_HOST_PREF_CONFIG 0x2c +#define SPI_RD4DW_EN_HOST BIT(15) + +#define SPI_FIFO 0x80 +#define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO) + +struct spi_config { + /* + * Default values if not overridden by mainboard: + * Read mode - Normal 33MHz + * Normal speed - 66MHz + * Fast speed - 66MHz + * Alt speed - 66MHz + * TPM speed - 66MHz + */ + enum spi_read_mode read_mode; + enum spi100_speed normal_speed; + enum spi100_speed fast_speed; + enum spi100_speed altio_speed; + enum spi100_speed tpm_speed; +}; + +/* + * Perform early SPI initialization: + * 1. Sets SPI ROM base and enables SPI ROM + * 2. Enables SPI ROM prefetching + * 3. Disables 4dw burst + * 4. Configures SPI speed and read mode. + * + * This function expects SoC to include soc_amd_common_config in chip SoC config and uses + * settings from mainboard devicetree to configure speed and read mode. + */ +void fch_spi_early_init(void); + +/* + * Configure SPI speed and read mode. + * + * This function expects SoC to include soc_amd_common_config in chip SoC config and uses + * settings from mainboard devicetree to configure speed and read mode. + */ +void fch_spi_config_modes(void); + +#endif /* __AMDBLOCKS_SPI_H__ */ diff --git a/src/soc/amd/common/block/spi/Makefile.inc b/src/soc/amd/common/block/spi/Makefile.inc index 0e706ef..3d541b7 100644 --- a/src/soc/amd/common/block/spi/Makefile.inc +++ b/src/soc/amd/common/block/spi/Makefile.inc @@ -9,4 +9,13 @@ smm-y += fch_spi_ctrl.c endif
+bootblock-y += fch_spi.c +romstage-y += fch_spi.c +postcar-y += fch_spi.c +ramstage-y += fch_spi.c +verstage-y += fch_spi.c +ifeq ($(CONFIG_SPI_FLASH_SMM),y) +smm-y += fch_spi.c +endif + endif diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c new file mode 100644 index 0000000..950eee2 --- /dev/null +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <amdblocks/chip.h> +#include <amdblocks/lpc.h> +#include <amdblocks/spi.h> +#include <arch/mmio.h> +#include <console/console.h> +#include <soc/iomap.h> +#include <stdint.h> + +static uintptr_t fch_spi_base(void) +{ + uintptr_t base; + + base = lpc_get_spibase(); + + if (base) + return base; + + lpc_set_spibase(SPI_BASE_ADDRESS); + lpc_enable_spi_rom(SPI_ROM_ENABLE); + + return SPI_BASE_ADDRESS; +} + +static void fch_spi_set_spi100(int norm, int fast, int alt, int tpm) +{ + uintptr_t base = fch_spi_base(); + + write16((void *)(base + SPI100_SPEED_CONFIG), SPI_SPEED_CFG(norm, fast, alt, tpm)); + write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); +} + +static void fch_spi_disable_4dw_burst(void) +{ + uintptr_t base = fch_spi_base(); + uint16_t val = read16((void *)(base + SPI100_HOST_PREF_CONFIG)); + + write16((void *)(base + SPI100_HOST_PREF_CONFIG), val & ~SPI_RD4DW_EN_HOST); +} + +static void fch_spi_set_read_mode(u32 mode) +{ + uintptr_t base = fch_spi_base(); + uint32_t val = read32((void *)(base + SPI_CNTRL0)) & ~SPI_READ_MODE_MASK; + + write32((void *)(base + SPI_CNTRL0), val | SPI_READ_MODE(mode)); +} + +static void fch_spi_config_mb_modes(void) +{ + const struct soc_amd_common_config *cfg = soc_get_common_config(); + + if (!cfg) + die("Common config structure is NULL!\n"); + + const struct spi_config *spi_cfg = &cfg->spi_config; + + fch_spi_set_read_mode(spi_cfg->read_mode); + fch_spi_set_spi100(spi_cfg->normal_speed, spi_cfg->fast_speed, + spi_cfg->altio_speed, spi_cfg->tpm_speed); +} + +static void fch_spi_config_em100_modes(void) +{ + fch_spi_set_read_mode(SPI_READ_MODE_NORMAL33M); + fch_spi_set_spi100(SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M); +} + +void fch_spi_config_modes(void) +{ + if (CONFIG(EM100)) + fch_spi_config_em100_modes(); + else + fch_spi_config_mb_modes(); +} + +void fch_spi_early_init(void) +{ + lpc_set_spibase(SPI_BASE_ADDRESS); + lpc_enable_spi_rom(SPI_ROM_ENABLE); + lpc_enable_spi_prefetch(); + fch_spi_disable_4dw_burst(); + fch_spi_config_modes(); +} diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index c0751a3..b048f1c 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -2,9 +2,9 @@
#include <console/console.h> #include <spi_flash.h> -#include <soc/southbridge.h> #include <soc/pci_devs.h> #include <amdblocks/lpc.h> +#include <amdblocks/spi.h> #include <device/pci_ops.h> #include <lib.h> #include <timer.h>
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41248 )
Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41248/6/src/soc/amd/common/block/in... File src/soc/amd/common/block/include/amdblocks/spi.h:
https://review.coreboot.org/c/coreboot/+/41248/6/src/soc/amd/common/block/in... PS6, Line 59: #define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO) this one seems very odd to me
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41248 )
Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ......................................................................
Patch Set 7:
oh, already merged. SPI_FIFO_DEPTH is copy-pasted, but seems to be at least semantically wrong
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41248 )
Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41248/6/src/soc/amd/common/block/in... File src/soc/amd/common/block/include/amdblocks/spi.h:
https://review.coreboot.org/c/coreboot/+/41248/6/src/soc/amd/common/block/in... PS6, Line 59: #define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO)
this one seems very odd to me
This is just a straight copy of what was present in the SoC header files. I agree it does look odd. Can you please push a follow-up patch to fix this?
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41248 )
Change subject: soc/amd/common/block/spi: Add support for common SPI configuration ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41248/6/src/soc/amd/common/block/in... File src/soc/amd/common/block/include/amdblocks/spi.h:
https://review.coreboot.org/c/coreboot/+/41248/6/src/soc/amd/common/block/in... PS6, Line 59: #define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO)
This is just a straight copy of what was present in the SoC header files. I agree it does look odd. […]
Addressed in 42076. Turned out to be correct, but said change improves the readability
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Aaron Durbin (Code Review) -
build bot (Jenkins) (Code Review)
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Felix Held (Code Review)
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Furquan Shaikh (Code Review)
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Raul Rangel (Code Review)