coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: drivers/intel/mipi_camera: camera SSDT generation
by Sugnan Prabhu S (Code Review) 04 Jun '20

04 Jun '20

Sugnan Prabhu S has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41607 ) Change subject: drivers/intel/mipi_camera: camera SSDT generation ...................................................................... Patch Set 11: (6 comments) https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… File src/drivers/intel/mipi_camera/camera.c: https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… PS11, Line 40: = 0; > no need to initialize. will update this in next patch. https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… PS11, Line 42: struct acpi_dp *ep_table = NULL; : struct acpi_dp *port_table = NULL; : struct acpi_dp *remote = NULL; > Initializing these as NULL only makes sense if you do a NULL check after acpi_dp_new_table() which d […] acpi_dp_new_table is internally calling malloc which calls die incase if it unable to allocated any memory. Memory allocation is unlikely to fail in coreboot. Initial version of this patch had these checks and error handling. But after discussing with @Matt it was removed. https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… PS11, Line 48: strdup > check for NULL? As mentioned above strdup is calling malloc https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… PS11, Line 50: acpi_dp_add_integer > It seems uncommon to do but do you want to check the return value? acpi_dp_add_integer is calling acpi_dp_new which calls malloc https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… PS11, Line 91: *config > check for NULL. camera_fill_ssdt is be called only if required configs are enabled in devicetree. So dev->chip_info will always be initialized? May be we can check in camera_fill_ssdt so that we will not enter any of these function if chip_info is not set. https://review.coreboot.org/c/coreboot/+/41607/11/src/drivers/intel/mipi_ca… PS11, Line 216: config > check for NULL. As mentioned above. -- To view, visit https://review.coreboot.org/c/coreboot/+/41607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15979f345fb823df2560db269e902a1ea650b69e Gerrit-Change-Number: 41607 Gerrit-PatchSet: 11 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 05 Jun 2020 02:49:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "soc/intel/xeon_sp/cpx: Finalize PCU configuration"
by Jonathan Zhang (Code Review) 04 Jun '20

04 Jun '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41451 ) Change subject: Revert "soc/intel/xeon_sp/cpx: Finalize PCU configuration" ...................................................................... Revert "soc/intel/xeon_sp/cpx: Finalize PCU configuration" This reverts commit 73f73655e7e7bbaed170b56e0b1bb8e9bba3cb69. This is needed to work around bug introduced by newer FSP releases, such as WW20 release. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I9f2c0e02f5f53d07f4224f6e5565f8a5a3476e01 --- M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/cpx/soc_util.c 4 files changed, 0 insertions(+), 163 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/41451/1 diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index f0eb7b1..ab0233c 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -581,8 +581,6 @@ static void chip_final(void *data) { p2sb_hide(); - - set_bios_init_completion(); } static void chip_init(void *data) diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 730f2f7..41054697b 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -24,32 +24,6 @@ #define SAD_ALL_PAM0123_CSR 0x40 #define SAD_ALL_PAM456_CSR 0x44 -#define PCU_IIO_STACK 1 -#define PCU_DEV 30 -#define PCU_CR1_FUN 1 - -#define PCU_CR1_BIOS_MB_DATA_REG 0x8c - -#define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 -#define BIOS_MB_RUN_BUSY_MASK ((uint32_t)1 << 31) -#define BIOS_MB_CMD_MASK ((uint32_t)0xff) -#define BIOS_CMD_READ_PCU_MISC_CFG 0x5 -#define BIOS_CMD_WRITE_PCU_MISC_CFG 0x6 -#define BIOS_ERR_INVALID_CMD 0x01 - -#define PCU_CR1_BIOS_RESET_CPL_REG 0x94 -#define RST_CPL1_MASK ((uint32_t)1 << 1) -#define RST_CPL2_MASK ((uint32_t)1 << 2) -#define RST_CPL3_MASK ((uint32_t)1 << 3) -#define RST_CPL4_MASK ((uint32_t)1 << 4) -#define PCODE_INIT_DONE1_MASK ((uint32_t)1 << 9) -#define PCODE_INIT_DONE2_MASK ((uint32_t)1 << 10) -#define PCODE_INIT_DONE3_MASK ((uint32_t)1 << 11) -#define PCODE_INIT_DONE4_MASK ((uint32_t)1 << 12) - -#define PCU_CR1_DESIRED_CORES_CFG2_REG 0xa0 -#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK ((uint32_t)1 << 31) - #define UBOX_DECS_BUS 0 #define UBOX_DECS_DEV 8 #define UBOX_DECS_FUNC 2 diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index 0bbc509..f195ce3 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -39,6 +39,4 @@ int xeon_sp_get_cpu_count(void); -void set_bios_init_completion(void); - #endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 99b2b1b..8b6b5f2 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -15,16 +15,12 @@ #include <assert.h> #include <commonlib/sort.h> -#include <delay.h> #include <device/device.h> -#include <device/pci.h> #include <intelblocks/cpulib.h> #include <soc/cpu.h> -#include <soc/pci_devs.h> #include <soc/soc_util.h> #include <stdlib.h> #include <string.h> -#include <timer.h> int get_threads_per_package(void) { @@ -195,133 +191,4 @@ return hob->PlatformData.Pci64BitResourceAllocation; } -/* return 1 if command timed out else 0 */ -static uint32_t wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t mask, - uint32_t target) -{ - uint32_t max_delay = 5000; /* 5 seconds max */ - uint32_t step_delay = 50; /* 50 us */ - struct stopwatch sw; - - stopwatch_init_msecs_expire(&sw, max_delay); - while ((pci_mmio_read_config32(dev, reg) & mask) != target) { - udelay(step_delay); - if (stopwatch_expired(&sw)) { - printk(BIOS_ERR, "%s timed out for dev: 0x%x, reg: 0x%x, " - "mask: 0x%x, target: 0x%x\n", __func__, dev, reg, mask, target); - return 1; /* timedout */ - } - } - return 0; /* successful */ -} - -/* return 1 if command timed out else 0 */ -static uint32_t write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32_t data) -{ - /* verify bios is not in busy state */ - if (wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, BIOS_MB_RUN_BUSY_MASK, 0)) - return 1; /* timed out */ - - /* write data to data register */ - printk(BIOS_SPEW, "%s - pci_mmio_write_config32 reg: 0x%x, data: 0x%x\n", __func__, - PCU_CR1_BIOS_MB_DATA_REG, data); - pci_mmio_write_config32(dev, PCU_CR1_BIOS_MB_DATA_REG, data); - - /* write the command */ - printk(BIOS_SPEW, "%s - pci_mmio_write_config32 reg: 0x%x, data: 0x%x\n", __func__, - PCU_CR1_BIOS_MB_INTERFACE_REG, - (uint32_t) (command | BIOS_MB_RUN_BUSY_MASK)); - pci_mmio_write_config32(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, - (uint32_t) (command | BIOS_MB_RUN_BUSY_MASK)); - - /* wait for completion or time out*/ - return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, - BIOS_MB_RUN_BUSY_MASK, 0); -} - -static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) -{ - const IIO_UDS *hob = get_iio_uds(); - - assert(socket < hob->SystemStatus.numCpus && stack < MAX_LOGIC_IIO_STACK); - - return hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; -} - -/* return 1 if command timed out else 0 */ -static int set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask, - uint32_t pcode_init_mask, uint32_t val) -{ - uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); - pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); - - uint32_t reg = pci_mmio_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG); - reg &= (uint32_t) ~rst_cpl_mask; - reg |= rst_cpl_mask; - reg |= val; - - /* update BIOS RESET completion bit */ - pci_mmio_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg); - - /* wait for PCU ack */ - return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask, - pcode_init_mask); -} - -static void set_bios_init_completion_for_package(uint32_t socket) -{ - uint32_t data; - uint32_t timedout; - uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); - pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); - - /* read pcu config */ - timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0); - if (timedout) { - /* 2nd try */ - timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0); - if (timedout) - die("BIOS PCU Misc Config Read timed out.\n"); - - data = pci_mmio_read_config32(dev, PCU_CR1_BIOS_MB_DATA_REG); - printk(BIOS_SPEW, "%s - pci_mmio_read_config32 reg: 0x%x, data: 0x%x\n", - __func__, PCU_CR1_BIOS_MB_DATA_REG, data); - - /* write PCU config */ - timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_WRITE_PCU_MISC_CFG, data); - if (timedout) - die("BIOS PCU Misc Config Write timed out.\n"); - } - - /* update RST_CPL3, PCODE_INIT_DONE3 */ - timedout = set_bios_reset_cpl_for_package(socket, RST_CPL3_MASK, - PCODE_INIT_DONE3_MASK, RST_CPL3_MASK); - if (timedout) - die("BIOS RESET CPL3 timed out.\n"); - - /* update RST_CPL4, PCODE_INIT_DONE4 */ - timedout = set_bios_reset_cpl_for_package(socket, RST_CPL4_MASK, - PCODE_INIT_DONE4_MASK, RST_CPL4_MASK); - if (timedout) - die("BIOS RESET CPL4 timed out.\n"); - /* set CSR_DESIRED_CORES_CFG2 lock bit */ - data = pci_mmio_read_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG); - data |= PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK; - printk(BIOS_SPEW, "%s - pci_mmio_write_config32 PCU_CR1_DESIRED_CORES_CFG2_REG 0x%x, data: 0x%x\n", - __func__, PCU_CR1_DESIRED_CORES_CFG2_REG, data); - pci_mmio_write_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG, data); -} - -void set_bios_init_completion(void) -{ - uint32_t sbsp_socket_id = 0; /* TODO - this needs to be configurable */ - - for (uint32_t socket = 0; socket < xeon_sp_get_cpu_count(); ++socket) { - if (socket == sbsp_socket_id) - continue; - set_bios_init_completion_for_package(socket); - } - set_bios_init_completion_for_package(sbsp_socket_id); -} - #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/41451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f2c0e02f5f53d07f4224f6e5565f8a5a3476e01 Gerrit-Change-Number: 41451 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters
by Jonathan Zhang (Code Review) 04 Jun '20

04 Jun '20

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40385 ) Change subject: soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters ...................................................................... Patch Set 22: (1 comment) https://review.coreboot.org/c/coreboot/+/40385/21/src/soc/intel/xeon_sp/cpx… File src/soc/intel/xeon_sp/cpx/romstage.c: https://review.coreboot.org/c/coreboot/+/40385/21/src/soc/intel/xeon_sp/cpx… PS21, Line 24: arch_upd->StackBase = (void *) 0xfe930000; > Can we do this as part of the device tree and not hardcode the configuration? We have an IPS ticket with Intel. Intel agreed that this is a violation of FSP spec, and thus it will be fixed in near future (once we clear the critical issues). At that time, this part of code (hardcoding StackBase and StackSize) will be reverted, to use FSP_USES_CB_STACK instead. -- To view, visit https://review.coreboot.org/c/coreboot/+/40385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d0762a742d8803c7396034e3244120c1e8ece67 Gerrit-Change-Number: 40385 Gerrit-PatchSet: 22 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 05 Jun 2020 00:56:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: fix MADT ACPI table
by Jonathan Zhang (Code Review) 04 Jun '20

04 Jun '20

Hello Philipp Deppenwiese, build bot (Jenkins), Anjaneya "Reddy" Chagam, Johnny Lin, Jingle Hsu, Morgan Jang, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40383 to look at the new patch set (#21). Change subject: soc/intel/xeon_sp/cpx: fix MADT ACPI table ...................................................................... soc/intel/xeon_sp/cpx: fix MADT ACPI table Fix MADT table generation to keep IIO stack design in consideration. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com> Change-Id: If1bf6e39db545e227e9867aa8d24f7db1d820216 --- M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/cpx/include/soc/acpi.h M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h 3 files changed, 106 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/40383/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/40383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1bf6e39db545e227e9867aa8d24f7db1d820216 Gerrit-Change-Number: 40383 Gerrit-PatchSet: 21 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp2_0: Add FSP 2.2 specific support
by Nathaniel L Desimone (Code Review) 04 Jun '20

04 Jun '20

Nathaniel L Desimone has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41728 ) Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support ...................................................................... Patch Set 9: -Code-Review (1 comment) https://review.coreboot.org/c/coreboot/+/41728/9/src/drivers/intel/fsp2_0/s… File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/c/coreboot/+/41728/9/src/drivers/intel/fsp2_0/s… PS9, Line 46: != > if you made this == and returned here the indent could be removed and strings wouldn't need to be aw […] This isn't the correct way to test for success anyway. It should be if(!EFI_ERROR(status)). It is possible to have "successful" error codes other than EFI_SUCCESS. The MSB indicates error. -- To view, visit https://review.coreboot.org/c/coreboot/+/41728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Gerrit-Change-Number: 41728 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 04 Jun 2020 22:03:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: drivers/usb: add a USB pre-poll hook
by Caveh Jalali (Code Review) 04 Jun '20

04 Jun '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42072 ) Change subject: libpayload: drivers/usb: add a USB pre-poll hook ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/42072/2/payloads/libpayload/includ… File payloads/libpayload/include/usb/usb.h: https://review.coreboot.org/c/coreboot/+/42072/2/payloads/libpayload/includ… PS2, Line 352: void __attribute__((weak)) usb_poll_prepare (void); > space prohibited between function name and open parenthesis '(' Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/42072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c23756f64b891b3c5683cd650c605b8630b0fb Gerrit-Change-Number: 42072 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 04 Jun 2020 21:50:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: drivers/usb: add a USB pre-poll hook
by Julius Werner (Code Review) 04 Jun '20

04 Jun '20

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42072 ) Change subject: libpayload: drivers/usb: add a USB pre-poll hook ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c23756f64b891b3c5683cd650c605b8630b0fb Gerrit-Change-Number: 42072 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 04 Jun 2020 21:46:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: drivers/usb: add a USB pre-poll hook
by build bot (Jenkins) (Code Review) 04 Jun '20

04 Jun '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42072 ) Change subject: libpayload: drivers/usb: add a USB pre-poll hook ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/42072/2/payloads/libpayload/includ… File payloads/libpayload/include/usb/usb.h: https://review.coreboot.org/c/coreboot/+/42072/2/payloads/libpayload/includ… PS2, Line 352: void __attribute__((weak)) usb_poll_prepare (void); space prohibited between function name and open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/42072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c23756f64b891b3c5683cd650c605b8630b0fb Gerrit-Change-Number: 42072 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 04 Jun 2020 21:38:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: drivers/usb: add a USB pre-poll hook
by Caveh Jalali (Code Review) 04 Jun '20

04 Jun '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42072 ) Change subject: libpayload: drivers/usb: add a USB pre-poll hook ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/c/coreboot/+/42072/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42072/1//COMMIT_MSG@7 PS1, Line 7: drivers/usb: add a USB pre-poll hook > libpayload should be in the prefix. Maybe: […] Done https://review.coreboot.org/c/coreboot/+/42072/1//COMMIT_MSG@14 PS1, Line 14: hookink > hooking? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/42072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c23756f64b891b3c5683cd650c605b8630b0fb Gerrit-Change-Number: 42072 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 04 Jun 2020 21:37:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: drivers/usb: add a USB pre-poll hook
by Caveh Jalali (Code Review) 04 Jun '20

04 Jun '20

Hello build bot (Jenkins), Nico Huber, Tim Wawrzynczak, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42072 to look at the new patch set (#2). Change subject: libpayload: drivers/usb: add a USB pre-poll hook ...................................................................... libpayload: drivers/usb: add a USB pre-poll hook This adds a hook so that a payload can optionally perform USB service functions in conjunction with regular USB port status polling. In particular, this allows depthcharge to control the state of an external USB mux. Some SoCs like Tiger Lake have a USB mux for Type-C ports that must be kept in sync with the state of the port as reported by the TCPC. This can be achieved by hooking into the poll routine to refresh the state of the USB mux. BUG=b:149883933 TEST=booted into recovery from Type-C flash drive on volteer Change-Id: Ic6c23756f64b891b3c5683cd650c605b8630b0fb Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M payloads/libpayload/drivers/usb/usb.c M payloads/libpayload/include/usb/usb.h 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/42072/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c23756f64b891b3c5683cd650c605b8630b0fb Gerrit-Change-Number: 42072 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit June 2020