coreboot-gerrit June 2020

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Change in coreboot[master]: src/soc/rockchip: Remove direct 'include <soc/gpio.h>'
by HAOUAS Elyes (Code Review) 05 Jun '20

05 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41332 ) Change subject: src/soc/rockchip: Remove direct 'include <soc/gpio.h>' ...................................................................... src/soc/rockchip: Remove direct 'include <soc/gpio.h>' Don't directly include <soc/gpio.h>. All code using GPIO features should always and only include <gpio.h>, which should indirectly include the SoC-specific <soc/gpio.h>. Change-Id: Ib7e71007cd111083eb6c7deda9def5d223c01f1f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/rockchip/common/gpio.c M src/soc/rockchip/rk3288/display.c M src/soc/rockchip/rk3288/gpio.c M src/soc/rockchip/rk3399/display.c M src/soc/rockchip/rk3399/gpio.c 5 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/41332/1 diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c index 73ddfd7..5629e6b 100644 --- a/src/soc/rockchip/common/gpio.c +++ b/src/soc/rockchip/common/gpio.c @@ -3,7 +3,6 @@ #include <device/mmio.h> #include <assert.h> #include <gpio.h> -#include <soc/gpio.h> #include <soc/grf.h> #include <soc/soc.h> #include <types.h> diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index fd86b95..f5f5d7c 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -13,7 +13,6 @@ #include <soc/display.h> #include <soc/edp.h> #include <soc/hdmi.h> -#include <soc/gpio.h> #include <soc/grf.h> #include <soc/soc.h> #include <soc/vop.h> diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c index 885b419..ad1972b 100644 --- a/src/soc/rockchip/rk3288/gpio.c +++ b/src/soc/rockchip/rk3288/gpio.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <gpio.h> -#include <soc/gpio.h> #include <soc/grf.h> #include <soc/pmu.h> #include <soc/soc.h> diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index b47fabc..eca0588 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -12,7 +12,6 @@ #include <soc/clock.h> #include <soc/display.h> #include <soc/edp.h> -#include <soc/gpio.h> #include <soc/grf.h> #include <soc/mmu_operations.h> #include <soc/mipi.h> diff --git a/src/soc/rockchip/rk3399/gpio.c b/src/soc/rockchip/rk3399/gpio.c index 6c022d8..8c66987 100644 --- a/src/soc/rockchip/rk3399/gpio.c +++ b/src/soc/rockchip/rk3399/gpio.c @@ -2,7 +2,6 @@ #include <gpio.h> #include <soc/addressmap.h> -#include <soc/gpio.h> #include <soc/grf.h> #include <soc/soc.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/41332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7e71007cd111083eb6c7deda9def5d223c01f1f Gerrit-Change-Number: 41332 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/qualcomm: Remove direct 'include <soc/gpio.h>'
by HAOUAS Elyes (Code Review) 05 Jun '20

05 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41331 ) Change subject: src/soc/qualcomm: Remove direct 'include <soc/gpio.h>' ...................................................................... src/soc/qualcomm: Remove direct 'include <soc/gpio.h>' Don't directly include <soc/gpio.h>. All code using GPIO features should always and only include <gpio.h>, which should indirectly include the SoC-specific <soc/gpio.h>. Change-Id: I4b34bde72d9464963d7829a7f97bf807b2925923 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/qualcomm/ipq40xx/i2c.c M src/soc/qualcomm/qcs405/blsp.c M src/soc/qualcomm/qcs405/i2c.c M src/soc/qualcomm/qcs405/qup.c M src/soc/qualcomm/sc7180/qspi.c M src/soc/qualcomm/sc7180/qupv3_spi.c M src/soc/qualcomm/sdm845/qspi.c 7 files changed, 7 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/41331/1 diff --git a/src/soc/qualcomm/ipq40xx/i2c.c b/src/soc/qualcomm/ipq40xx/i2c.c index e2cda11..2d92497 100644 --- a/src/soc/qualcomm/ipq40xx/i2c.c +++ b/src/soc/qualcomm/ipq40xx/i2c.c @@ -5,7 +5,7 @@ #include <string.h> #include <soc/blsp.h> #include <soc/qup.h> -#include <soc/gpio.h> +#include <gpio.h> static qup_config_t blsp1_qup0_config = { QUP_MINICORE_I2C_MASTER, diff --git a/src/soc/qualcomm/qcs405/blsp.c b/src/soc/qualcomm/qcs405/blsp.c index 7fb4954..e1b94e95 100644 --- a/src/soc/qualcomm/qcs405/blsp.c +++ b/src/soc/qualcomm/qcs405/blsp.c @@ -2,7 +2,7 @@ #include <device/mmio.h> #include <soc/blsp.h> -#include <soc/gpio.h> +#include <gpio.h> #include <soc/iomap.h> #include <soc/clock.h> diff --git a/src/soc/qualcomm/qcs405/i2c.c b/src/soc/qualcomm/qcs405/i2c.c index 85af6e4..6c558cc 100644 --- a/src/soc/qualcomm/qcs405/i2c.c +++ b/src/soc/qualcomm/qcs405/i2c.c @@ -6,7 +6,7 @@ #include <string.h> #include <soc/blsp.h> #include <soc/qup.h> -#include <soc/gpio.h> +#include <gpio.h> static qup_config_t blsp1_qup0_config = { QUP_MINICORE_I2C_MASTER, diff --git a/src/soc/qualcomm/qcs405/qup.c b/src/soc/qualcomm/qcs405/qup.c index 3ba4ba6..894bf42 100644 --- a/src/soc/qualcomm/qcs405/qup.c +++ b/src/soc/qualcomm/qcs405/qup.c @@ -3,7 +3,7 @@ #include <device/mmio.h> #include <console/console.h> #include <delay.h> -#include <soc/gpio.h> +#include <gpio.h> #include <soc/iomap.h> #include <soc/qup.h> diff --git a/src/soc/qualcomm/sc7180/qspi.c b/src/soc/qualcomm/sc7180/qspi.c index 10038e4..b776f7d 100644 --- a/src/soc/qualcomm/sc7180/qspi.c +++ b/src/soc/qualcomm/sc7180/qspi.c @@ -6,11 +6,10 @@ #include <device/mmio.h> #include <soc/addressmap.h> #include <soc/qspi.h> -#include <soc/gpio.h> +#include <gpio.h> #include <soc/clock.h> #include <symbols.h> #include <assert.h> -#include <gpio.h> #include <string.h> #define CACHE_LINE_SIZE 64 diff --git a/src/soc/qualcomm/sc7180/qupv3_spi.c b/src/soc/qualcomm/sc7180/qupv3_spi.c index c3827ef..47fbaf7 100644 --- a/src/soc/qualcomm/sc7180/qupv3_spi.c +++ b/src/soc/qualcomm/sc7180/qupv3_spi.c @@ -4,7 +4,7 @@ #include <delay.h> #include <lib.h> #include <soc/clock.h> -#include <soc/gpio.h> +#include <gpio.h> #include <soc/qcom_qup_se.h> #include <soc/qupv3_config.h> #include <soc/qupv3_spi.h> diff --git a/src/soc/qualcomm/sdm845/qspi.c b/src/soc/qualcomm/sdm845/qspi.c index 8c98316..772f7a2 100644 --- a/src/soc/qualcomm/sdm845/qspi.c +++ b/src/soc/qualcomm/sdm845/qspi.c @@ -6,11 +6,10 @@ #include <device/mmio.h> #include <soc/addressmap.h> #include <soc/qspi.h> -#include <soc/gpio.h> +#include <gpio.h> #include <soc/clock.h> #include <symbols.h> #include <assert.h> -#include <gpio.h> #include <string.h> #define CACHE_LINE_SIZE 64 -- To view, visit https://review.coreboot.org/c/coreboot/+/41331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b34bde72d9464963d7829a7f97bf807b2925923 Gerrit-Change-Number: 41331 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/mediatek: Remove direct 'include <soc/gpio.h>'
by HAOUAS Elyes (Code Review) 05 Jun '20

05 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41329 ) Change subject: src/soc/mediatek: Remove direct 'include <soc/gpio.h>' ...................................................................... src/soc/mediatek: Remove direct 'include <soc/gpio.h>' Don't directly include <soc/gpio.h>. All code using GPIO features should always and only include <gpio.h>, which should indirectly include the SoC-specific <soc/gpio.h>. Change-Id: I099c579dcc8f53159410034334b092c7a79cba23 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/mediatek/mt8173/gpio_init.c M src/soc/mediatek/mt8173/spi.c M src/soc/mediatek/mt8183/i2c.c M src/soc/mediatek/mt8183/mt8183.c M src/soc/mediatek/mt8183/spi.c 5 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/41329/1 diff --git a/src/soc/mediatek/mt8173/gpio_init.c b/src/soc/mediatek/mt8173/gpio_init.c index 80652d8..b03de9f 100644 --- a/src/soc/mediatek/mt8173/gpio_init.c +++ b/src/soc/mediatek/mt8173/gpio_init.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/mmio.h> -#include <soc/gpio.h> +#include <gpio.h> #include <soc/mipi.h> /* diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index dd5c2ae..02ba28e 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -5,7 +5,7 @@ #include <spi_flash.h> #include <soc/addressmap.h> #include <soc/flash_controller.h> -#include <soc/gpio.h> +#include <gpio.h> #include <soc/spi.h> struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = { diff --git a/src/soc/mediatek/mt8183/i2c.c b/src/soc/mediatek/mt8183/i2c.c index ec9b797..a8d97e4 100644 --- a/src/soc/mediatek/mt8183/i2c.c +++ b/src/soc/mediatek/mt8183/i2c.c @@ -4,7 +4,7 @@ #include <device/mmio.h> #include <soc/pll.h> #include <soc/i2c.h> -#include <soc/gpio.h> +#include <gpio.h> #define I2C_CLK_HZ (UNIVPLL_HZ / 20) diff --git a/src/soc/mediatek/mt8183/mt8183.c b/src/soc/mediatek/mt8183/mt8183.c index 1c34246..4668b7e 100644 --- a/src/soc/mediatek/mt8183/mt8183.c +++ b/src/soc/mediatek/mt8183/mt8183.c @@ -2,7 +2,7 @@ #include <soc/mt8183.h> #include <soc/wdt.h> -#include <soc/gpio.h> +#include <gpio.h> void mt8183_early_init(void) { diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c index 87362dc..dd6a5a4 100644 --- a/src/soc/mediatek/mt8183/spi.c +++ b/src/soc/mediatek/mt8183/spi.c @@ -5,7 +5,7 @@ #include <spi_flash.h> #include <soc/addressmap.h> #include <soc/flash_controller.h> -#include <soc/gpio.h> +#include <gpio.h> #include <soc/spi.h> struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/41329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I099c579dcc8f53159410034334b092c7a79cba23 Gerrit-Change-Number: 41329 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/amd: Remove direct 'include <soc/gpio.h>'
by HAOUAS Elyes (Code Review) 05 Jun '20

05 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41327 ) Change subject: src/soc/amd: Remove direct 'include <soc/gpio.h>' ...................................................................... src/soc/amd: Remove direct 'include <soc/gpio.h>' Don't directly include <soc/gpio.h>. All code using GPIO features should always and only include <gpio.h>, which should indirectly include the SoC-specific <soc/gpio.h>. Change-Id: Ibe93386c1e48a8fe4083563eac5e7c62b64f4eab Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/common/block/gpio_banks/gpio.c M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/gpio.c M src/soc/amd/picasso/uart.c M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/gpio.c 6 files changed, 5 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/41327/1 diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 2d4558f..d895c4a 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -6,7 +6,6 @@ #include <gpio.h> #include <amdblocks/acpimmio.h> #include <amdblocks/acpimmio_map.h> -#include <soc/gpio.h> #include <soc/smi.h> #include <assert.h> diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index a02d8f3..c0c11de 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -22,7 +22,7 @@ #include <soc/southbridge.h> #include <soc/northbridge.h> #include <soc/nvs.h> -#include <soc/gpio.h> +#include <gpio.h> #include <version.h> unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/soc/amd/picasso/gpio.c b/src/soc/amd/picasso/gpio.c index c402fb5..f6e6cca 100644 --- a/src/soc/amd/picasso/gpio.c +++ b/src/soc/amd/picasso/gpio.c @@ -3,7 +3,7 @@ #include <stdint.h> #include <amdblocks/gpio_banks.h> #include <amdblocks/acpimmio.h> -#include <soc/gpio.h> +#include <gpio.h> #include <soc/smi.h> static const struct soc_amd_event gpio_event_table[] = { diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index 6ae79b95..334b567 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -6,7 +6,7 @@ #include <amdblocks/gpio_banks.h> #include <amdblocks/acpimmio.h> #include <soc/southbridge.h> -#include <soc/gpio.h> +#include <gpio.h> static const struct _uart_info { uintptr_t base; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index c98a1b4..a1600b5 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -21,7 +21,7 @@ #include <soc/southbridge.h> #include <soc/northbridge.h> #include <soc/nvs.h> -#include <soc/gpio.h> +#include <gpio.h> #include <version.h> unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index a595014..106b762 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -3,7 +3,7 @@ #include <stdint.h> #include <amdblocks/gpio_banks.h> #include <amdblocks/acpimmio.h> -#include <soc/gpio.h> +#include <gpio.h> #include <soc/smi.h> static const struct soc_amd_event gpio_event_table[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/41327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe93386c1e48a8fe4083563eac5e7c62b64f4eab Gerrit-Change-Number: 41327 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11-lga1151-series: Remove direct 'include <soc/gpio.h>'
by HAOUAS Elyes (Code Review) 05 Jun '20

05 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41326 ) Change subject: mb/supermicro/x11-lga1151-series: Remove direct 'include <soc/gpio.h>' ...................................................................... mb/supermicro/x11-lga1151-series: Remove direct 'include <soc/gpio.h>' Don't directly include <soc/gpio.h>. All code using GPIO features should always and only include <gpio.h>, which should indirectly include the SoC-specific <soc/gpio.h>. Change-Id: Ie2b5374b2ef1f2bfea865bb69a94b94a99de4e13 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/supermicro/x11-lga1151-series/bootblock.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/41326/1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c index 94eeee7..f96a401 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c +++ b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <soc/gpio.h> +#include <gpio.h> #include <variant/gpio.h> #include <superio/aspeed/common/aspeed.h> #include <superio/aspeed/ast2400/ast2400.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/41326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2b5374b2ef1f2bfea865bb69a94b94a99de4e13 Gerrit-Change-Number: 41326 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Add FSP 2.2 specific support
by Subrata Banik (Code Review) 05 Jun '20

05 Jun '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41728 ) Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/41728/10/src/drivers/intel/fsp2_0/… File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/c/coreboot/+/41728/10/src/drivers/intel/fsp2_0/… PS10, Line 151: printk(BIOS_SPEW, "Executing Phase %d of FspMultiPhaseSiInit \n", i); > unnecessary whitespace before a quoted newline Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/41728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Gerrit-Change-Number: 41728 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 05 Jun 2020 09:01:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Add FSP 2.2 specific support
by Subrata Banik (Code Review) 05 Jun '20

05 Jun '20

Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Maulik V Vaghela, Duncan Laurie, Sridhar Siricilla, Aamir Bohra, Srinidhi N Kaushik, Andrey Petrov, Aaron Durbin, Patrick Rudolph, Nathaniel L Desimone, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41728 to look at the new patch set (#11). Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support ...................................................................... drivers/intel/fsp2_0: Add FSP 2.2 specific support • Based on FSP EAS v2.1 – Backward compatibility is retained. • Added multi-phase silicon initialization to increase the modularity of the FspSiliconInit() API. • Added FspMultiPhaseSiInit() API • FSP_INFO_HEADER changes o Added FspMultiPhaseSiInitEntryOffset • Added FSPS_ARCH_UPD o Added EnableMultiPhaseSiliconInit, bootloaders designed for FSP 2.0/2.1 can disable the FspMultiPhaseSiInit() API and continue to use FspSiliconInit() without change. FSP 2.2 Specification: https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-… Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/commonlib/include/commonlib/timestamp_serialized.h M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/intel/fsp2_0/include/fsp/upd.h M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/fsp2_0/util.c M src/include/console/post_codes.h 9 files changed, 172 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/41728/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/41728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Gerrit-Change-Number: 41728 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp2_0: Add FSP 2.2 specific support
by build bot (Jenkins) (Code Review) 05 Jun '20

05 Jun '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41728 ) Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/41728/10/src/drivers/intel/fsp2_0/… File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/c/coreboot/+/41728/10/src/drivers/intel/fsp2_0/… PS10, Line 151: printk(BIOS_SPEW, "Executing Phase %d of FspMultiPhaseSiInit \n", i); unnecessary whitespace before a quoted newline -- To view, visit https://review.coreboot.org/c/coreboot/+/41728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Gerrit-Change-Number: 41728 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 05 Jun 2020 08:57:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Add FSP 2.2 specific support
by Subrata Banik (Code Review) 05 Jun '20

05 Jun '20

Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Maulik V Vaghela, Duncan Laurie, Sridhar Siricilla, Aamir Bohra, Srinidhi N Kaushik, Andrey Petrov, Aaron Durbin, Patrick Rudolph, Nathaniel L Desimone, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41728 to look at the new patch set (#10). Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support ...................................................................... drivers/intel/fsp2_0: Add FSP 2.2 specific support • Based on FSP EAS v2.1 – Backward compatibility is retained. • Added multi-phase silicon initialization to increase the modularity of the FspSiliconInit() API. • Added FspMultiPhaseSiInit() API • FSP_INFO_HEADER changes o Added FspMultiPhaseSiInitEntryOffset • Added FSPS_ARCH_UPD o Added EnableMultiPhaseSiliconInit, bootloaders designed for FSP 2.0/2.1 can disable the FspMultiPhaseSiInit() API and continue to use FspSiliconInit() without change. FSP 2.2 Specification: https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-… Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/commonlib/include/commonlib/timestamp_serialized.h M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/intel/fsp2_0/include/fsp/upd.h M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/fsp2_0/util.c M src/include/console/post_codes.h 9 files changed, 172 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/41728/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/41728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Gerrit-Change-Number: 41728 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp2_0: Add FSP 2.2 specific support
by Subrata Banik (Code Review) 05 Jun '20

05 Jun '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41728 ) Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support ...................................................................... Patch Set 9: (3 comments) https://review.coreboot.org/c/coreboot/+/41728/9/src/drivers/intel/fsp2_0/s… File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/c/coreboot/+/41728/9/src/drivers/intel/fsp2_0/s… PS9, Line 46: != > > This isn't the correct way to test for success anyway. It should be if(!EFI_ERROR(status)). […] Ack https://review.coreboot.org/c/coreboot/+/41728/9/src/drivers/intel/fsp2_0/s… PS9, Line 59: FSP_MULTI_PHASE_SI_INIT_GET_NUMBER_OF_PHASES_API > Should we attempt to continue to boot without multiphase in this case rather than treat this as fata […] Ack https://review.coreboot.org/c/coreboot/+/41728/9/src/drivers/intel/fsp2_0/s… PS9, Line 66: " > prefix with "FspMultiPhaseSiInit ExecutePhase" (for consistency with other output) Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/41728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Gerrit-Change-Number: 41728 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 05 Jun 2020 08:06:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Duncan Laurie <dlaurie(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-MessageType: comment

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