coreboot-gerrit June 2020

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Change in coreboot[master]: drivers/intel/fsp2_0: Add FSP 2.2 specific support
by Subrata Banik (Code Review) 05 Jun '20

05 Jun '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41728 ) Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support ...................................................................... Patch Set 9: (6 comments) https://review.coreboot.org/c/coreboot/+/41728/9/src/drivers/intel/fsp2_0/i… File src/drivers/intel/fsp2_0/include/fsp/info_header.h: https://review.coreboot.org/c/coreboot/+/41728/9/src/drivers/intel/fsp2_0/i… PS9, Line 33: #if CONFIG(PLATFORM_USES_FSP2_2) > this doesn't seem to be used as a packed structure (each field read separately in fsp_identify) so d […] Ack https://review.coreboot.org/c/coreboot/+/41728/9/src/drivers/intel/fsp2_0/i… File src/drivers/intel/fsp2_0/include/fsp/util.h: https://review.coreboot.org/c/coreboot/+/41728/9/src/drivers/intel/fsp2_0/i… PS9, Line 24: enum fsp_multi_phase_action { : GET_NUMBER_OF_PHASES, : EXECUTE_PHASE : }; > This is part of an ABI, it would be good to explicitly call out the integer value of each enum. Ack https://review.coreboot.org/c/coreboot/+/41728/9/src/drivers/intel/fsp2_0/s… File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/c/coreboot/+/41728/9/src/drivers/intel/fsp2_0/s… PS9, Line 45: erros > errors Ack https://review.coreboot.org/c/coreboot/+/41728/9/src/drivers/intel/fsp2_0/s… PS9, Line 46: != > This isn't the correct way to test for success anyway. It should be if(!EFI_ERROR(status)). We don't use those EFI_ERROR handling case in coreboot. > It is possible to have "successful" error codes other than EFI_SUCCESS. The MSB indicates error. Right now its mostly 5 return types as per spec EFI_SUCCESS FSP execution environment was initialized successfully. EFI_INVALID_PARAMETER Input parameters are invalid. EFI_UNSUPPORTED The FSP calling conditions were not met. EFI_DEVICE_ERROR FSP silicon initialization failed. FSP_STATUS_RESET_REQUIRED_* A reset is required. These status codes will not be returned during S3. https://review.coreboot.org/c/coreboot/+/41728/9/src/drivers/intel/fsp2_0/s… handles FSP_STATUS_RESET_REQUIRED_* return type case EFI_SUCCESS been checked here Rest everything is error code which results into die in coreboot code https://review.coreboot.org/c/coreboot/+/41728/9/src/drivers/intel/fsp2_0/s… PS9, Line 146: (void *) > I don't think you need to cast here Ack https://review.coreboot.org/c/coreboot/+/41728/9/src/drivers/intel/fsp2_0/u… File src/drivers/intel/fsp2_0/util.c: https://review.coreboot.org/c/coreboot/+/41728/9/src/drivers/intel/fsp2_0/u… PS9, Line 52: #if CONFIG(PLATFORM_USES_FSP2_2) > if the header didn't use #if to guard this field the code could just be "if (CONFIG(PLATFORM_USES_FS […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/41728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Gerrit-Change-Number: 41728 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 05 Jun 2020 08:04:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Duncan Laurie <dlaurie(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: device/pci: Add early PCI dump
by Paul Menzel (Code Review) 05 Jun '20

05 Jun '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36606 ) Change subject: device/pci: Add early PCI dump ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Sorry, I think I removed the WIP status in February due to the confusing Gerrit user interface. I can set it back if you want. https://review.coreboot.org/c/coreboot/+/36606/3/src/device/pci_dump.c File src/device/pci_dump.c: https://review.coreboot.org/c/coreboot/+/36606/3/src/device/pci_dump.c@12 PS3, Line 12: */ The new SPDX headers should be used. -- To view, visit https://review.coreboot.org/c/coreboot/+/36606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic095213ab51a3c29af462782fdb75cfcd409714f Gerrit-Change-Number: 36606 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Dmitry Ponamorev Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Comment-Date: Fri, 05 Jun 2020 07:18:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Revert "mb/google/zork: Increase RO section to 5MB"
by Raul Rangel (Code Review) 05 Jun '20

05 Jun '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42049 ) Change subject: Revert "mb/google/zork: Increase RO section to 5MB" ...................................................................... Revert "mb/google/zork: Increase RO section to 5MB" This reverts commit fddd101904188193197be10c8eae04e76386299b. Reason for revert: With FSP compression and non serial FSP we now have enough space in RO. Original change's description: > mb/google/zork: Increase RO section to 5MB > > The current size is too small to fit all the depthcharge assets. > Increasing it to 5MB gives us 648k of free space. > > $ cbfstool /build/zork/firmware/image-trembyle.serial.bin print -r COREBOOT > FMAP REGION: COREBOOT > Name Offset Type Size Comp > cbfs master header 0x0 cbfs header 32 none > fallback/romstage 0x80 stage 524316 none > fallback/ramstage 0x80100 stage 96592 none > config 0x97ac0 raw 843 none > revision 0x97e80 raw 680 none > spd.bin 0x98180 spd 8192 none > etc/sdcard0 0x9a1c0 raw 8 none > locales 0x9a200 raw 141 LZMA (166 decompressed) > (empty) 0x9a300 null 3224 none > fspm.bin 0x9afc0 fsp 720896 none > (empty) 0x14b000 null 3992 none > fsps.bin 0x14bfc0 fsp 327680 none > pci1002,15d8,c1.rom 0x19c000 optionrom 54272 none > pci1002,15d8,c4.rom 0x1a9480 optionrom 54272 none > fallback/dsdt.aml 0x1b6900 raw 12727 none > locale_hi.bin 0x1b9b00 raw 10441 LZMA (239928 decompressed) > ... > locale_ko.bin 0x254f80 raw 11282 LZMA (231168 decompressed) > fallback/payload 0x257c00 simple elf 95169 none > (empty) 0x26f000 null 245656 none > apu/amdfw 0x2aafc0 raw 1277440 none > (empty) 0x3e2e00 null 688472 none > bootblock 0x48af80 bootblock 64 none > > BUG=b:130028876 > BRANCH=none > TEST=Built image with depthcharge and booted. > > Change-Id: I9cd2902404ef68cdbd4a9484d5cb1ee9cba3efd1 > Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… > Reviewed-by: Martin Roth <martinroth(a)google.com> BUG=b:130028876, b:150746858 BRANCH=none TEST=emerge-zork coreboot-zork chromeos-bootimage and boot trembyle localhost ~ # flashrom -p host -r /tmp/main.bin flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64) flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64) Calibrating delay loop... OK. coreboot table found at 0xcbe54000. Reading flash... SUCCESS localhost ~ # futility dump_fmap /tmp/main.bin | grep WP_RO -B 3 area: 22 area_offset: 0x00c00000 area_size: 0x00400000 (4194304) area_name: WP_RO localhost ~ # flashrom -p host --wp-range 0xc00000 0x400000 --wp-enable flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64) flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64) coreboot table found at 0xcbe54000. SUCCESS localhost ~ # flashrom -p host --wp-status flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64) flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64) coreboot table found at 0xcbe54000. WP: status: 0x0094 WP: status.srp0: 1 WP: status.srp1: 0 WP: write protect is enabled. WP: write protect range: start=0x00c00000, len=0x00400000 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I5df10ee8e855adfaaf4b2fac4c2c47037ec093b4 --- M src/mainboard/google/zork/chromeos.fmd 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/42049/1 diff --git a/src/mainboard/google/zork/chromeos.fmd b/src/mainboard/google/zork/chromeos.fmd index 963d1ee..90cd2d7 100644 --- a/src/mainboard/google/zork/chromeos.fmd +++ b/src/mainboard/google/zork/chromeos.fmd @@ -23,15 +23,15 @@ RW_NVRAM(PRESERVE)@0x767000 0x5000 RW_UNUSED@0x76C000 0x14000 SMMSTORE(PRESERVE)@0x780000 0x20000 - RW_LEGACY(CBFS)@0x7A0000 0x360000 - WP_RO@0xB00000 0x500000 { + RW_LEGACY(CBFS)@0x7A0000 0x460000 + WP_RO@0xC00000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x4FC000 { + RO_SECTION@0x4000 0x3FC000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7C0 GBB@0x1000 0x70000 - COREBOOT(CBFS)@0x71000 0x48B000 + COREBOOT(CBFS)@0x71000 0x38B000 } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/42049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5df10ee8e855adfaaf4b2fac4c2c47037ec093b4 Gerrit-Change-Number: 42049 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi: Accomodate non-standard UUIDs in device properties
by Duncan Laurie (Code Review) 05 Jun '20

05 Jun '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42047 ) Change subject: acpi: Accomodate non-standard UUIDs in device properties ...................................................................... acpi: Accomodate non-standard UUIDs in device properties There have been changes to the way device properties are supported in Linux[1] and Windows[2] which add flexibilty: - non-standard UUIDs can be used instead of only ACPI_DP_UUID - support for multiple different packages within the _DSD that associate different properties with unique UUIDs. To handle this I extracted the part that does the write of UUID and properties to a separate function and defined a new PACKAGE type which has the custom UUID as a name and can be used the same way that child properties are today. For example a PCIe root port for a USB4 port has a standard property indicating the USB4 reference, and then two custom properties which are defined for different attributes. Example code: /* Create property table */ acpi_dp *dsd = acpi_dp_new_table("_DSD"); acpi_dp_add_reference(dsd, "usb4-port", usb4_path); /* Add package for hotplug */ acpi_dp *pkg = acpi_dp_new_table("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"); acpi_dp_add_integer(pkg, "HotPlugSupportInD3", 1); acpi_dp_add_package(dsd, pkg); /* Add package for external port info */ pkg = acpi_dp_new_table("efcc06cc-73ac-4bc3-bff0-76143807c389"); acpi_dp_add_integer(pkg, "ExternalFacingPort", 1); acpi_dp_add_package(dsd, pkg); /* Write all properties */ acpi_dp_write(dsd); Resulting ACPI: Scope (\_SB.PCI0.TRP0) { Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") Package () { Package (0x02) { "usb4-port", \_SB.PCI0.TDM0.RHUB.PRTA } }, ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"), Package () { Package () { "HotPlugSupportInD3", One } }, ToUUID ("efcc06cc-73ac-4bc3-bff0-76143807c389"), Package () { Package () { "ExternalFacingPort", One }, } }) } [1] https://patchwork.kernel.org/patch/10599675/ [2] https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-… Change-Id: I75f47825bf4ffc5e9e92af2c45790d1b5945576e Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/acpi/device.c M src/include/acpi/acpi_device.h 2 files changed, 77 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/42047/1 diff --git a/src/acpi/device.c b/src/acpi/device.c index 8b03bfd..9e8efa4 100644 --- a/src/acpi/device.c +++ b/src/acpi/device.c @@ -53,7 +53,7 @@ return NULL; /* Check for device specific handler */ - if (dev->ops->acpi_name) + if (dev->ops && dev->ops->acpi_name) return dev->ops->acpi_name(dev); /* Walk up the tree to find if any parent can identify this device */ @@ -658,10 +658,48 @@ } } +static bool acpi_dp_write_properties(struct acpi_dp *prop, const char *uuid) +{ + struct acpi_dp *dp; + char *prop_count = NULL; + + /* Print base properties */ + for (dp = prop; dp; dp = dp->next) { + if (dp->type == ACPI_DP_TYPE_TABLE || + dp->type == ACPI_DP_TYPE_CHILD || + dp->type == ACPI_DP_TYPE_PACKAGE) + continue; + + /* + * The UUID and package is only added when + * we come across the first property. This + * is to avoid creating a zero-length package + * in situations where there are only children. + */ + if (!prop_count) { + /* ToUUID (dp->uuid) */ + acpigen_write_uuid(uuid); + /* + * Package (PROP), element count determined as + * it is populated + */ + prop_count = acpigen_write_package(0); + } + (*prop_count)++; + acpi_dp_write_property(dp); + } + if (prop_count) { + /* Package (PROP) length, if a package was written */ + acpigen_pop_len(); + return true; + } + return false; +} + void acpi_dp_write(struct acpi_dp *table) { struct acpi_dp *dp, *prop; - char *dp_count, *prop_count = NULL; + char *dp_count; int child_count = 0; if (!table || table->type != ACPI_DP_TYPE_TABLE || !table->next) @@ -677,37 +715,17 @@ dp_count = acpigen_write_package(0); /* Print base properties */ - for (dp = prop; dp; dp = dp->next) { - if (dp->type == ACPI_DP_TYPE_CHILD) { - child_count++; - } else { - /* - * The UUID and package is only added when - * we come across the first property. This - * is to avoid creating a zero-length package - * in situations where there are only children. - */ - if (!prop_count) { - *dp_count += 2; - /* ToUUID (ACPI_DP_UUID) */ - acpigen_write_uuid(ACPI_DP_UUID); - /* - * Package (PROP), element count determined as - * it is populated - */ - prop_count = acpigen_write_package(0); - } - (*prop_count)++; - acpi_dp_write_property(dp); - } - } - if (prop_count) { - /* Package (PROP) length, if a package was written */ - acpigen_pop_len(); - } + if (acpi_dp_write_properties(prop, table->uuid)) + *dp_count += 2; + /* Count child properties */ + for (dp = prop; dp; dp = dp->next) + if (dp->type == ACPI_DP_TYPE_CHILD) + child_count++; + + /* Add child properties to the base table */ if (child_count) { - /* Update DP package count to 2 or 4 */ + /* Update DP package count */ *dp_count += 2; /* ToUUID (ACPI_DP_CHILD_UUID) */ acpigen_write_uuid(ACPI_DP_CHILD_UUID); @@ -722,6 +740,12 @@ acpigen_pop_len(); } + /* Write packages of properties with unique UUID */ + for (dp = prop; dp; dp = dp->next) + if (dp->type == ACPI_DP_TYPE_PACKAGE) + if (acpi_dp_write_properties(dp->child, dp->uuid)) + *dp_count += 2; + /* Package (DP) length */ acpigen_pop_len(); @@ -746,6 +770,7 @@ memset(new, 0, sizeof(*new)); new->type = type; new->name = name; + new->uuid = ACPI_DP_UUID; if (dp) { /* Add to end of property list */ @@ -863,6 +888,22 @@ return new; } +struct acpi_dp *acpi_dp_add_package(struct acpi_dp *dp, struct acpi_dp *package) +{ + struct acpi_dp *new; + + if (!dp || !package || package->type != ACPI_DP_TYPE_TABLE) + return NULL; + + new = acpi_dp_new(dp, ACPI_DP_TYPE_PACKAGE, NULL); + if (new) { + new->uuid = package->name; + new->child = package; + } + + return new; +} + struct acpi_dp *acpi_dp_add_array(struct acpi_dp *dp, struct acpi_dp *array) { struct acpi_dp *new; diff --git a/src/include/acpi/acpi_device.h b/src/include/acpi/acpi_device.h index 20dd8a4..2c2c67a 100644 --- a/src/include/acpi/acpi_device.h +++ b/src/include/acpi/acpi_device.h @@ -15,11 +15,13 @@ ACPI_DP_TYPE_TABLE, ACPI_DP_TYPE_ARRAY, ACPI_DP_TYPE_CHILD, + ACPI_DP_TYPE_PACKAGE, }; struct acpi_dp { enum acpi_dp_type type; const char *name; + const char *uuid; struct acpi_dp *next; union { struct acpi_dp *child; @@ -464,6 +466,9 @@ /* Start a new Device Property table with provided ACPI reference */ struct acpi_dp *acpi_dp_new_table(const char *ref); +/* Add package of device properties with a unique UUID */ +struct acpi_dp *acpi_dp_add_package(struct acpi_dp *dp, struct acpi_dp *package); + /* Add integer Device Property */ struct acpi_dp *acpi_dp_add_integer(struct acpi_dp *dp, const char *name, uint64_t value); -- To view, visit https://review.coreboot.org/c/coreboot/+/42047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75f47825bf4ffc5e9e92af2c45790d1b5945576e Gerrit-Change-Number: 42047 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi: Add support for writing UART device descriptors
by Duncan Laurie (Code Review) 05 Jun '20

05 Jun '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41792 ) Change subject: acpi: Add support for writing UART device descriptors ...................................................................... acpi: Add support for writing UART device descriptors This change adds support for generating the device descriptor that corresponds to the UARTSerialBusV2() ACPI macro. The resulting ACPI code for ACPI_UART_RAW_DEVICE(115200, 64) is: UartSerialBusV2 (0x0001C200, DataBitsEight, StopBitsOne, 0x00, LittleEndian, ParityTypeNone, FlowControlNone, 0x0040, 0x0040, "\\_SB.PCI0.UAR2", 0x00, ResourceConsumer, , Exclusive) Change-Id: I671ce2a499d74717d8677528c46ab3fbc1d7faf5 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/acpi/device.c M src/include/acpi/acpi_device.h 2 files changed, 163 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/41792/1 diff --git a/src/acpi/device.c b/src/acpi/device.c index 8b03bfd..030c940 100644 --- a/src/acpi/device.c +++ b/src/acpi/device.c @@ -523,6 +523,80 @@ acpi_device_fill_len(desc_length); } +/* UART Serial Bus - UARTSerialBusV2() */ +void acpi_device_write_uart(const struct acpi_uart *uart) +{ + void *desc_length, *type_length; + uint16_t flags; + + /* Byte 0: Descriptor Type */ + acpigen_emit_byte(ACPI_DESCRIPTOR_SERIAL_BUS); + + /* Byte 1+2: Length (filled in later) */ + desc_length = acpi_device_write_zero_len(); + + /* Byte 3: Revision ID */ + acpigen_emit_byte(ACPI_UART_SERIAL_BUS_REVISION_ID); + + /* Byte 4: Resource Source Index is Reserved */ + acpigen_emit_byte(0); + + /* Byte 5: Serial Bus Type is UART */ + acpigen_emit_byte(ACPI_SERIAL_BUS_TYPE_UART); + + /* + * Byte 6: Flags + * [7:2]: 0 => Reserved + * [1]: 1 => ResourceConsumer + * [0]: 0 => ControllerInitiated + */ + acpigen_emit_byte(BIT(1)); + + /* + * Byte 7-8: Type Specific Flags + * [15:8]: 0 => Reserved + * [7]: 0 => Little Endian, 1 => Big Endian + * [6:4]: Data bits + * [3:2]: Stop bits + * [1:0]: Flow control + */ + flags = uart->flow_control & 3; + flags |= (uart->stop_bits & 3) << 2; + flags |= (uart->data_bits & 7) << 4; + flags |= (uart->endian & 1) << 7; + acpigen_emit_word(flags); + + /* Byte 9: Type Specific Revision ID */ + acpigen_emit_byte(ACPI_UART_TYPE_SPECIFIC_REVISION_ID); + + /* Byte 10-11: Type Data Length */ + type_length = acpi_device_write_zero_len(); + + /* Byte 12-15: Initial Baud Rate */ + acpigen_emit_dword(uart->initial_baud_rate); + + /* Byte 16-17: RX FIFO size */ + acpigen_emit_word(uart->rx_fifo_bytes); + + /* Byte 18-19: TX FIFO size */ + acpigen_emit_word(uart->tx_fifo_bytes); + + /* Byte 20: Parity */ + acpigen_emit_byte(uart->parity); + + /* Byte 21: Lines Enabled */ + acpigen_emit_byte(uart->lines_in_use); + + /* Fill in Type Data Length */ + acpi_device_fill_len(type_length); + + /* Byte 22+: ResourceSource */ + acpigen_emit_string(uart->resource); + + /* Fill in Descriptor Length */ + acpi_device_fill_len(desc_length); +} + /* PowerResource() with Enable and/or Reset control */ void acpi_device_add_power_res(const struct acpi_power_res_params *params) { diff --git a/src/include/acpi/acpi_device.h b/src/include/acpi/acpi_device.h index 20dd8a4..f3f329f 100644 --- a/src/include/acpi/acpi_device.h +++ b/src/include/acpi/acpi_device.h @@ -321,10 +321,14 @@ #define ACPI_SERIAL_BUS_TYPE_I2C 1 #define ACPI_SERIAL_BUS_TYPE_SPI 2 +#define ACPI_SERIAL_BUS_TYPE_UART 3 + #define ACPI_I2C_SERIAL_BUS_REVISION_ID 1 /* TODO: upgrade to 2 */ #define ACPI_I2C_TYPE_SPECIFIC_REVISION_ID 1 #define ACPI_SPI_SERIAL_BUS_REVISION_ID 1 #define ACPI_SPI_TYPE_SPECIFIC_REVISION_ID 1 +#define ACPI_UART_SERIAL_BUS_REVISION_ID 1 +#define ACPI_UART_TYPE_SPECIFIC_REVISION_ID 1 /* * ACPI I2C Bus @@ -370,6 +374,91 @@ /* Write SPI Bus descriptor to SSDT AML output */ void acpi_device_write_spi(const struct acpi_spi *spi); +/* + * ACPI UART Bus + */ + +enum acpi_uart_data_bits { + ACPI_UART_DATA_BITS_5, + ACPI_UART_DATA_BITS_6, + ACPI_UART_DATA_BITS_7, + ACPI_UART_DATA_BITS_8, + ACPI_UART_DATA_BITS_9 +}; + +enum acpi_uart_stop_bits { + ACPI_UART_STOP_BITS_0, + ACPI_UART_STOP_BITS_1, + ACPI_UART_STOP_BITS_1_5, + ACPI_UART_STOP_BITS_2 +}; + +enum acpi_uart_lines { + ACPI_UART_LINE_DTD = BIT(2), /* Data Carrier Detect */ + ACPI_UART_LINE_RI = BIT(3), /* Ring Indicator */ + ACPI_UART_LINE_DSR = BIT(4), /* Data Set Ready */ + ACPI_UART_LINE_DTR = BIT(5), /* Data Terminal Ready */ + ACPI_UART_LINE_CTS = BIT(6), /* Clear to Send */ + ACPI_UART_LINE_RTS = BIT(7) /* Request to Send */ +}; + +enum acpi_uart_endian { + ACPI_UART_ENDIAN_LITTLE, + ACPI_UART_ENDIAN_BIG +}; + +enum acpi_uart_parity { + ACPI_UART_PARITY_NONE, + ACPI_UART_PARITY_EVEN, + ACPI_UART_PARITY_ODD, + ACPI_UART_PARITY_MARK, + ACPI_UART_PARITY_SPACE +}; + +enum acpi_uart_flow_control { + ACPI_UART_FLOW_NONE, + ACPI_UART_FLOW_HARDWARE, + ACPI_UART_FLOW_SOFTWARE +}; + +struct acpi_uart { + /* Initial Baud Rate in bytes per second. */ + uint32_t initial_baud_rate; + /* Number of bits of data in a packet between 5-9. */ + enum acpi_uart_data_bits data_bits; + /* Number of bits to signal end of packet. */ + enum acpi_uart_stop_bits stop_bits; + /* Bitmask indicating presence or absence of particular line. */ + unsigned int lines_in_use; + /* Specify if the device expects big or little endian format. */ + enum acpi_uart_endian endian; + /* Specify the type of parity bits included after the data in a packet. */ + enum acpi_uart_parity parity; + /* Specify the flow control method. */ + enum acpi_uart_flow_control flow_control; + /* Upper limit in bytes of the buffer sizes for this device. */ + uint16_t rx_fifo_bytes; + uint16_t tx_fifo_bytes; + /* Set to indicate that UART is shared. */ + bool shared; + /* Reference to UART controller. */ + const char *resource; +}; + +#define ACPI_UART_RAW_DEVICE(baud_rate, fifo_bytes) { \ + .initial_baud_rate = (baud_rate), \ + .data_bits = ACPI_UART_DATA_BITS_8, \ + .stop_bits = ACPI_UART_STOP_BITS_1, \ + .endian = ACPI_UART_ENDIAN_LITTLE, \ + .parity = ACPI_UART_PARITY_NONE, \ + .flow_control = ACPI_UART_FLOW_NONE, \ + .rx_fifo_bytes = (fifo_bytes), \ + .tx_fifo_bytes = (fifo_bytes), \ + .shared = false } + +/* Write UARTSerialBusV2() descriptor to SSDT AML output */ +void acpi_device_write_uart(const struct acpi_uart *uart); + /* GPIO/timing information for the power on/off sequences */ struct acpi_power_res_params { /* GPIO used to take device out of reset or to put it into reset. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I671ce2a499d74717d8677528c46ab3fbc1d7faf5 Gerrit-Change-Number: 41792 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: mb/google/volteer: Create voxel variant
by David Wu (Code Review) 05 Jun '20

05 Jun '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41968 ) Change subject: mb/google/volteer: Create voxel variant ...................................................................... mb/google/volteer: Create voxel variant Create the voxel variant of the volteer reference board BUG=b:157879197 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_VOXEL Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I8ba5412be211730db84675927c500238cb20ff3d --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/voxel/Makefile.inc A src/mainboard/google/volteer/variants/voxel/gpio.c A src/mainboard/google/volteer/variants/voxel/include/variant/acpi/dptf.asl A src/mainboard/google/volteer/variants/voxel/include/variant/ec.h A src/mainboard/google/volteer/variants/voxel/include/variant/gpio.h A src/mainboard/google/volteer/variants/voxel/overridetree.cb 8 files changed, 74 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/41968/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 63e70c5..55056c4 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -69,6 +69,7 @@ default "Terrador" if BOARD_GOOGLE_TERRADOR default "Trondo" if BOARD_GOOGLE_TRONDO default "Volteer" if BOARD_GOOGLE_VOLTEER + default "Voxel" if BOARD_GOOGLE_VOXEL config MAX_CPUS int @@ -100,6 +101,7 @@ default "terrador" if BOARD_GOOGLE_TERRADOR default "trondo" if BOARD_GOOGLE_TRONDO default "volteer" if BOARD_GOOGLE_VOLTEER + default "voxel" if BOARD_GOOGLE_VOXEL config VARIANT_HAS_MIPI_CAMERA bool diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 479b118..6920aaf 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -25,3 +25,7 @@ bool "-> Volteer" select BOARD_GOOGLE_BASEBOARD_VOLTEER select VARIANT_HAS_MIPI_CAMERA + +config BOARD_GOOGLE_VOXEL + bool "-> Voxel" + select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/voxel/Makefile.inc b/src/mainboard/google/volteer/variants/voxel/Makefile.inc new file mode 100644 index 0000000..c9a128d --- /dev/null +++ b/src/mainboard/google/volteer/variants/voxel/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +SPD_SOURCES = + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/voxel/gpio.c b/src/mainboard/google/volteer/variants/voxel/gpio.c new file mode 100644 index 0000000..a54aeca --- /dev/null +++ b/src/mainboard/google/volteer/variants/voxel/gpio.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + +}; + +const struct pad_config *variant_base_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/volteer/variants/voxel/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/voxel/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..189cafe --- /dev/null +++ b/src/mainboard/google/volteer/variants/voxel/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/volteer/variants/voxel/include/variant/ec.h b/src/mainboard/google/volteer/variants/voxel/include/variant/ec.h new file mode 100644 index 0000000..4a9a461 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voxel/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/volteer/variants/voxel/include/variant/gpio.h b/src/mainboard/google/volteer/variants/voxel/include/variant/gpio.h new file mode 100644 index 0000000..0075826 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voxel/include/variant/gpio.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Copied from baseboard and may need to change for the new variant. */ + +#endif diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb new file mode 100644 index 0000000..75422d8 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/tigerlake + device domain 0 on + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/41968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ba5412be211730db84675927c500238cb20ff3d Gerrit-Change-Number: 41968 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: mb/google/zork: create new variant for Vilboz
by Peichao Li (Code Review) 05 Jun '20

05 Jun '20

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41801 ) Change subject: mb/google/zork: create new variant for Vilboz ...................................................................... mb/google/zork: create new variant for Vilboz BUG=b:157499341 BRANCH=NONE TEST=FW_NAME="vilboz" emerge-zork coreboot Signed-off-by: peichao.wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I28ab3edb130fc7bf8b786141bc088166052d4868 --- M src/mainboard/google/zork/Kconfig M src/mainboard/google/zork/Kconfig.name A src/mainboard/google/zork/variants/vilboz/Makefile.inc A src/mainboard/google/zork/variants/vilboz/include/variant/acpi/audio.asl A src/mainboard/google/zork/variants/vilboz/include/variant/acpi/mainboard.asl A src/mainboard/google/zork/variants/vilboz/include/variant/acpi/sleep.asl A src/mainboard/google/zork/variants/vilboz/include/variant/acpi/thermal.asl A src/mainboard/google/zork/variants/vilboz/include/variant/ec.h A src/mainboard/google/zork/variants/vilboz/include/variant/gpio.h A src/mainboard/google/zork/variants/vilboz/include/variant/thermal.h A src/mainboard/google/zork/variants/vilboz/overridetree.cb A src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc A src/mainboard/google/zork/variants/vilboz/variant.c 13 files changed, 185 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/41801/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 343b30b..9a2e373 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -50,6 +50,7 @@ default "trembyle" if BOARD_GOOGLE_TREMBYLE default "dalboz" if BOARD_GOOGLE_DALBOZ default "berknip" if BOARD_GOOGLE_BERKNIP + default "vilboz" if BOARD_GOOGLE_VILBOZ config MAINBOARD_PART_NUMBER string @@ -58,6 +59,7 @@ default "Trembyle" if BOARD_GOOGLE_TREMBYLE default "Dalboz" if BOARD_GOOGLE_DALBOZ default "Berknip" if BOARD_GOOGLE_BERKNIP + default "Vilboz" if BOARD_GOOGLE_VILBOZ config DEVICETREE string diff --git a/src/mainboard/google/zork/Kconfig.name b/src/mainboard/google/zork/Kconfig.name index 065f60c..2f721d4 100644 --- a/src/mainboard/google/zork/Kconfig.name +++ b/src/mainboard/google/zork/Kconfig.name @@ -4,6 +4,10 @@ bool "-> Dalboz" select BOARD_GOOGLE_BASEBOARD_DALBOZ +config BOARD_GOOGLE_VILBOZ + bool "-> Vilboz" + select BOARD_GOOGLE_BASEBOARD_DALBOZ + config BOARD_GOOGLE_EZKINIL bool "-> Ezkinil" select BOARD_GOOGLE_BASEBOARD_TREMBYLE diff --git a/src/mainboard/google/zork/variants/vilboz/Makefile.inc b/src/mainboard/google/zork/variants/vilboz/Makefile.inc new file mode 100644 index 0000000..dc1e411 --- /dev/null +++ b/src/mainboard/google/zork/variants/vilboz/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./spd + +ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/vilboz/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/vilboz/include/variant/acpi/audio.asl new file mode 100644 index 0000000..900e36f --- /dev/null +++ b/src/mainboard/google/zork/variants/vilboz/include/variant/acpi/audio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/audio.asl> diff --git a/src/mainboard/google/zork/variants/vilboz/include/variant/acpi/mainboard.asl b/src/mainboard/google/zork/variants/vilboz/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..a1161ed --- /dev/null +++ b/src/mainboard/google/zork/variants/vilboz/include/variant/acpi/mainboard.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/mainboard.asl> diff --git a/src/mainboard/google/zork/variants/vilboz/include/variant/acpi/sleep.asl b/src/mainboard/google/zork/variants/vilboz/include/variant/acpi/sleep.asl new file mode 100644 index 0000000..8177a9d --- /dev/null +++ b/src/mainboard/google/zork/variants/vilboz/include/variant/acpi/sleep.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/sleep.asl> diff --git a/src/mainboard/google/zork/variants/vilboz/include/variant/acpi/thermal.asl b/src/mainboard/google/zork/variants/vilboz/include/variant/acpi/thermal.asl new file mode 100644 index 0000000..7a793d8 --- /dev/null +++ b/src/mainboard/google/zork/variants/vilboz/include/variant/acpi/thermal.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/thermal.asl> diff --git a/src/mainboard/google/zork/variants/vilboz/include/variant/ec.h b/src/mainboard/google/zork/variants/vilboz/include/variant/ec.h new file mode 100644 index 0000000..9e61a44 --- /dev/null +++ b/src/mainboard/google/zork/variants/vilboz/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/ec.h> diff --git a/src/mainboard/google/zork/variants/vilboz/include/variant/gpio.h b/src/mainboard/google/zork/variants/vilboz/include/variant/gpio.h new file mode 100644 index 0000000..dfaeec3 --- /dev/null +++ b/src/mainboard/google/zork/variants/vilboz/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> diff --git a/src/mainboard/google/zork/variants/vilboz/include/variant/thermal.h b/src/mainboard/google/zork/variants/vilboz/include/variant/thermal.h new file mode 100644 index 0000000..2af6479 --- /dev/null +++ b/src/mainboard/google/zork/variants/vilboz/include/variant/thermal.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/thermal.h> diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb new file mode 100644 index 0000000..99e51ec --- /dev/null +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Start : OPN Performance Configuration + # See devhub #56670 Chapter 5 for documentation + # For the below fields, 0 indicates use SOC default + + # System config index + register "system_config" = "1" + + # Set STAPM confiuration. All of these fields must be set >0 to take affect + register "slow_ppt_limit" = "6000" #mw + register "fast_ppt_limit" = "9000" #mw + register "slow_ppt_time_constant" = "5" #second + register "stapm_time_constant" = "2500" #second + register "sustained_power_limit" = "4800" #mw + + # End : OPN Performance Configuration + + # I2C2 for touchscreen and trackpad + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 18, /* 0 to 2.31 (3.3 * .7) */ + .fall_time_ns = 57, /* 2.31 to 0 */ + }" + + # I2C3 for H1 + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 184, /* 0 to 1.26v (1.8 * .7) */ + .fall_time_ns = 42, /* 1.26v to 0 */ + .early_init = true, + }" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device pci 0.3 on end # USB 3.1 + end + device pci 14.3 on # - D14F3 bridge + chip ec/google/chromeec + device pnp 0c09.0 on + chip ec/google/chromeec/i2c_tunnel + register "uid" = "1" + register "remote_bus" = "8" + device generic 0.0 on + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""RT1015 Tweeter Left Speaker Amp"" + register "uid" = "0" + register "name" = ""TL"" + device i2c 28 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""RT1015 Tweeter Right Speaker Amp"" + register "uid" = "1" + register "name" = ""TR"" + device i2c 29 on end + end + end + end + end + end + end + end # domain + + device mmio 0xfedc4000 on # APU_I2C2_BASE + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "120" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "7" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.wake" = "7" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc new file mode 100644 index 0000000..4494b98 --- /dev/null +++ b/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Ordered List of APCB entries, up to 16. +# Entries should match this pattern {NAME}_x{1,2} +# There should be a matching SPD hex file in SPD_SOURCES_DIR +# matching the pattern {NAME}.spd.hex +# The _x{1,2} suffix denotes single or dual channel +# TODO: Remove channel suffix when b:141434940 is fixed +# Alternatively, generated APCBs stored at +# CONFIG_APCB_BLOB_DIR/APCB_{NAME}.bin can be included. +APCB_SOURCES = empty diff --git a/src/mainboard/google/zork/variants/vilboz/variant.c b/src/mainboard/google/zork/variants/vilboz/variant.c new file mode 100644 index 0000000..9a12413 --- /dev/null +++ b/src/mainboard/google/zork/variants/vilboz/variant.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <console/console.h> +#include <device/device.h> +#include <drivers/i2c/generic/chip.h> +#include <soc/pci_devs.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/i2c_tunnel/chip.h> +#include <string.h> + +#define EC_PNP_ID 0x0c09 + +extern struct chip_operations ec_google_chromeec_i2c_tunnel_ops; + +static const picasso_fsp_ddi_descriptor hdmi_ddi_descriptors[] = { + { // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub + .connector_type = HDMI, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { // DDI2, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +void variant_get_pcie_ddi_descriptors(const picasso_fsp_pcie_descriptor **pcie_descs, + size_t *pcie_num, + const picasso_fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + *pcie_descs = baseboard_get_pcie_descriptors(pcie_num); + + *ddi_descs = &hdmi_ddi_descriptors[0]; + *ddi_num = ARRAY_SIZE(hdmi_ddi_descriptors); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28ab3edb130fc7bf8b786141bc088166052d4868 Gerrit-Change-Number: 41801 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

9 30

Change in coreboot[master]: cpu/intel/slot_1: Select 16KiB bootblock if console is enabled
by Keith Hui (Code Review) 05 Jun '20

05 Jun '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41460 ) Change subject: cpu/intel/slot_1: Select 16KiB bootblock if console is enabled ...................................................................... cpu/intel/slot_1: Select 16KiB bootblock if console is enabled We previously confirmed [1] that bootblock will grow beyond current 8KiB size if console is enabled. Automatically change to 16KiB if user enabled it in menuconfig. [1] https://review.coreboot.org/c/coreboot/+/36775 Change-Id: Ic9988c77cf9677167a382aa4dc7dcfa2bc4cbe02 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/cpu/intel/slot_1/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/41460/1 diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 1ba71ad..a56208b 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -34,6 +34,7 @@ config C_ENV_BOOTBLOCK_SIZE hex + default 0x4000 if BOOTBLOCK_CONSOLE default 0x2000 endif -- To view, visit https://review.coreboot.org/c/coreboot/+/41460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9988c77cf9677167a382aa4dc7dcfa2bc4cbe02 Gerrit-Change-Number: 41460 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: soc/intel/jasperlake: Apply FiVR related settings
by Ronak Kanabar (Code Review) 05 Jun '20

05 Jun '20

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41062 ) Change subject: soc/intel/jasperlake: Apply FiVR related settings ...................................................................... Patch Set 14: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/41062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief81fe481c94abef9754881cf1f454699fafa52e Gerrit-Change-Number: 41062 Gerrit-PatchSet: 14 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 05 Jun 2020 04:49:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede: config spk_en gpio to low by default
by Karthik Ramasubramanian (Code Review) 05 Jun '20

05 Jun '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41853 ) Change subject: mb/google/dedede: config spk_en gpio to low by default ...................................................................... Patch Set 3: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/41853/2/src/mainboard/google/deded… File src/mainboard/google/dedede/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/41853/2/src/mainboard/google/deded… PS2, Line 178: GPP_D17 > I think Furquan was referring to register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" in […] As mentioned by Usha, audio support for waddledee is yet to be added. The GPIO will be exposed through ACPI when the audio support gets added in waddledee. Even though the amplifier is different, the GPIO purpose is still the same i.e to enable the speaker. -- To view, visit https://review.coreboot.org/c/coreboot/+/41853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I070679457b06cb82633c1197b893a5d89c8b2cf0 Gerrit-Change-Number: 41853 Gerrit-PatchSet: 3 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 05 Jun 2020 04:33:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Usha P <usha.p(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit June 2020