coreboot-gerrit June 2020

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Change in coreboot[master]: mb/google/volteer: Add firmware configuration probing for audio
by Duncan Laurie (Code Review) 02 Jun '20

02 Jun '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41216 ) Change subject: mb/google/volteer: Add firmware configuration probing for audio ...................................................................... mb/google/volteer: Add firmware configuration probing for audio For all of the audio devices in devicetree.cb add the probe matches that will determine if the device should be enabled or not based on the selected audio daughter board type. AUDIO=MAX98357_ALC5682I_I2S: enable max98357 and alc5628, disable others AUDIO=MAX98373_ALC5682I_I2S: enable max98373 and alc5682, disable others AUDIO=MAX98373_ALC5682_SNDW: enable soundwire devices, disable others BUG=b:147462631 TEST=test different device present in ACPI based on fw_config value: > AUDIO=NONE ectool cbi set 6 0x00000000 4 2 > AUDIO=MAX98357_ALC5682I_I2S ectool cbi set 6 0x00000100 4 2 > AUDIO=MAX98373_ALC5682I_I2S ectool cbi set 6 0x00000200 4 2 > AUDIO=MAX98373_ALC5682_SNDW ectool cbi set 6 0x00000300 4 2 Change-Id: I5492e8cddcff3ba01023b0daef02be3508d347b0 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/volteer/variants/volteer/overridetree.cb 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/41216/1 diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 13ee428..c2fc10b 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -11,6 +11,11 @@ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" + register "fw_config_probe" = "true" + register "fw_config" = "{ + FW_CONFIG_MATCH(AUDIO, MAX98357_ALC5682I_I2S), + FW_CONFIG_MATCH(AUDIO, MAX98373_ALC5682I_I2S) + }" device i2c 1a on end end chip drivers/i2c/max98373 @@ -19,6 +24,8 @@ register "uid" = "0" register "desc" = ""Right Speaker Amp"" register "name" = ""MAXR"" + register "fw_config_probe" = "true" + register "fw_config" = "{ FW_CONFIG_MATCH(AUDIO, MAX98373_ALC5682I_I2S) }" device i2c 31 on end end chip drivers/i2c/max98373 @@ -27,6 +34,8 @@ register "uid" = "1" register "desc" = ""Left Speaker Amp"" register "name" = ""MAXL"" + register "fw_config_probe" = "true" + register "fw_config" = "{ FW_CONFIG_MATCH(AUDIO, MAX98373_ALC5682I_I2S) }" device i2c 32 on end end end @@ -35,9 +44,13 @@ register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" register "sdmode_delay" = "5" + register "fw_config_probe" = "true" + register "fw_config" = "{ FW_CONFIG_MATCH(AUDIO, MAX98357_ALC5682I_I2S) }" device generic 0 on end end chip drivers/intel/soundwire + register "fw_config_probe" = "true" + register "fw_config" = "{ FW_CONFIG_MATCH(AUDIO, MAX98373_ALC5682_SNDW) }" device generic 0 on chip drivers/soundwire/alc5682 # SoundWire Link 0 ID 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/41216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5492e8cddcff3ba01023b0daef02be3508d347b0 Gerrit-Change-Number: 41216 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Add firmware configuration table
by Duncan Laurie (Code Review) 02 Jun '20

02 Jun '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41215 ) Change subject: mb/google/volteer: Add firmware configuration table ...................................................................... mb/google/volteer: Add firmware configuration table Add the current firmware configuration table for the volteer mainboard. This is not completely filled out for all fields yet but has the entries needed for audio. - When I2S options are selected disable the SoundWire GPIOs. - When SoundWire is enabled disable the I2S GPIOs. - When no audio is enabled disable all the GPIOs. The current mainboard configuration value is read from the Embedded Controller CBI field and provided to the firmware configuration interface for probing. BUG=b:147462631 TEST=Test that GPIOs are configured as expected based on the current value of the fw_config field in cbi. Change-Id: I179f8b6436be83a2b37911777764bd26a0d404b7 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Makefile.inc A src/mainboard/google/volteer/fw_config.c 3 files changed, 136 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/41215/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index e6c6ec7..3acc0ea 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -13,6 +13,7 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_LPC + select FW_CONFIG select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE diff --git a/src/mainboard/google/volteer/Makefile.inc b/src/mainboard/google/volteer/Makefile.inc index 9d1bb3f..2ddd508 100644 --- a/src/mainboard/google/volteer/Makefile.inc +++ b/src/mainboard/google/volteer/Makefile.inc @@ -13,6 +13,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c smm-y += smihandler.c diff --git a/src/mainboard/google/volteer/fw_config.c b/src/mainboard/google/volteer/fw_config.c new file mode 100644 index 0000000..64adfe9 --- /dev/null +++ b/src/mainboard/google/volteer/fw_config.c @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __MAINBOARD_FW_CONFIG__ +#define __MAINBOARD_FW_CONFIG__ + +#include <commonlib/helpers.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <fw_config.h> +#include <stdint.h> +#include <soc/gpio.h> + +static const struct pad_config dmic_enable_pads[] = { + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* DMIC_CLK1 */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* DMIC_DATA1 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC_CLK0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC_DATA0 */ +}; + +static const struct pad_config dmic_disable_pads[] = { + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), +}; + +static const struct pad_config sndw_enable_pads[] = { + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), /* SNDW0_CLK */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), /* SNDW0_DATA */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), /* SNDW1_CLK */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), /* SNDW1_DATA */ +}; + +static const struct pad_config sndw_disable_pads[] = { + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), +}; + +static const struct pad_config i2s_enable_pads[] = { + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* I2S1_SCLK */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* I2S_MCLK1 */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_SCLK */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_SFRM */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S0_TXD */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S0_RXD */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S1_RXD */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S1_TXD */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S1_SFRM */ +}; + +static const struct pad_config i2s_disable_pads[] = { + PAD_NC(GPP_A23, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_R0, NONE), + PAD_NC(GPP_R1, NONE), + PAD_NC(GPP_R2, DN_20K), + PAD_NC(GPP_R3, NONE), + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +static void audio_db_none_cb(const struct fw_config_option *option) +{ + printk(BIOS_INFO, "%s: Configure GPIOs for no audio.\n", __func__); + gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); + gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); + gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); +} + +static void audio_db_i2s_cb(const struct fw_config_option *option) +{ + printk(BIOS_INFO, "%s: Configure GPIOs for I2S audio.\n", __func__); + gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); +} + +static void audio_db_sndw_cb(const struct fw_config_option *option) +{ + printk(BIOS_INFO, "%s: Configure GPIOs for SoundWire audio.\n", __func__); + gpio_configure_pads(sndw_enable_pads, ARRAY_SIZE(sndw_enable_pads)); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); +} + +static const struct fw_config_field volteer_fw_config[] = { + { + FW_CONFIG_FIELD("DB", 0xf, 0), + }, + { + FW_CONFIG_FIELD("THERMAL", 0xf, 4), + }, + { + FW_CONFIG_FIELD("AUDIO", 0x7, 8), + .option = { + FW_CONFIG_OPTION_CB("NONE", 0, audio_db_none_cb), + FW_CONFIG_OPTION_CB("MAX98357_ALC5682I_I2S", 1, audio_db_i2s_cb), + FW_CONFIG_OPTION_CB("MAX98373_ALC5682I_I2S", 2, audio_db_i2s_cb), + FW_CONFIG_OPTION_CB("MAX98373_ALC5682_SNDW", 3, audio_db_sndw_cb) + }, + }, + { + FW_CONFIG_FIELD("TABLETMODE", 0x1, 11), + .option = { + FW_CONFIG_OPTION("DISABLED", 0), + FW_CONFIG_OPTION("ENABLED", 1) + }, + }, + { + FW_CONFIG_FIELD("LTE_DB", 0x3, 12), + .option = { + FW_CONFIG_OPTION("ABSENT", 0), + FW_CONFIG_OPTION("PRESENT", 1) + }, + }, + { } +}; + +size_t mainboard_get_fw_config(const struct fw_config_field **table, uint32_t *config) +{ + if (google_chromeec_cbi_get_fw_config(config) < 0) { + printk(BIOS_ERR, "Could not get fw_config from EC\n"); + return 0; + } + + *table = volteer_fw_config; + return ARRAY_SIZE(volteer_fw_config); +} + +#endif /* __MAINBOARD_FW_CONFIG__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I179f8b6436be83a2b37911777764bd26a0d404b7 Gerrit-Change-Number: 41215 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 15

Change in coreboot[master]: mb/google/volteer: Reorganize audio codecs
by Duncan Laurie (Code Review) 02 Jun '20

02 Jun '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41214 ) Change subject: mb/google/volteer: Reorganize audio codecs ...................................................................... mb/google/volteer: Reorganize audio codecs - Move all audio devices from baseboard to the volteer variant. - Add max98373 devices and enable the driver - Disable everything in FSP and let coreboot configure GPIOs. BUG=b:147462631 TEST=this change makes all audio devices show up in ACPI, so this was tested by ensuring that all audio devices are present in ACPI. Change-Id: Ic654ea52a549053622603aa8c81fb37577d4e011 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/volteer/overridetree.cb 3 files changed, 45 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/41214/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 952a0a1..e6c6ec7 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -4,6 +4,7 @@ select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID + select DRIVERS_I2C_MAX98373 select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_SPI_ACPI select DRIVERS_SOUNDWIRE_ALC5682 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index b689663..b676abc 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -118,10 +118,12 @@ # HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" - register "PchHdaAudioLinkDmicEnable[0]" = "1" - register "PchHdaAudioLinkDmicEnable[1]" = "1" - register "PchHdaAudioLinkSspEnable[0]" = "1" - register "PchHdaAudioLinkSspEnable[1]" = "1" + register "PchHdaAudioLinkDmicEnable[0]" = "0" + register "PchHdaAudioLinkDmicEnable[1]" = "0" + register "PchHdaAudioLinkSspEnable[0]" = "0" + register "PchHdaAudioLinkSspEnable[1]" = "0" + register "PchHdaAudioLinkSndwEnable[0]" = "0" + register "PchHdaAudioLinkSndwEnable[1]" = "0" # TCSS USB3 register "TcssXhciEn" = "1" @@ -238,20 +240,7 @@ device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 end - device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_F8_IRQ)" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_count" = "1" - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on end - end - end # I2C #0 0xA0E8 + device pci 15.0 on end # I2C #0 0xA0E8 device pci 15.1 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" @@ -379,14 +368,7 @@ end # eSPI 0xA080 - A09F device pci 1f.1 off end # P2SB 0xA0A0 device pci 1f.2 on end # PMC 0xA0A1 - device pci 1f.3 on - chip drivers/generic/max98357a - register "hid" = ""MX98357A"" - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end # Intel HD audio 0xA0C8-A0CF + device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF device pci 1f.4 off end # SMBus 0xA0A3 device pci 1f.5 on end # SPI 0xA0A4 device pci 1f.6 off end # GbE 0x15E1/0x15E2 diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index aa2c8fb..13ee428 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -1,6 +1,42 @@ chip soc/intel/tigerlake device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_F8_IRQ)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "4" + register "imon_slot_no" = "5" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "6" + register "imon_slot_no" = "7" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on end + end + end device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "sdmode_delay" = "5" + device generic 0 on end + end chip drivers/intel/soundwire device generic 0 on chip drivers/soundwire/alc5682 -- To view, visit https://review.coreboot.org/c/coreboot/+/41214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic654ea52a549053622603aa8c81fb37577d4e011 Gerrit-Change-Number: 41214 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cbfs: add cbfs_boot_locate_file_get_compression_info()
by Aaron Durbin (Code Review) 02 Jun '20

02 Jun '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41448 ) Change subject: cbfs: add cbfs_boot_locate_file_get_compression_info() ...................................................................... cbfs: add cbfs_boot_locate_file_get_compression_info() There's no current way to obtain the decompression information (algo and size) with the current API. Therefore, split cbfs_boot_load_file() up and add cbfs_boot_locate_file_get_compression_info() so other callers can obtain the same infromation. BUG=b:155322763,b:150746858,b:152909132 Change-Id: I605b036a50ed26ad6897b5b86a37897766169e6b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/include/cbfs.h M src/lib/cbfs.c 2 files changed, 21 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/41448/1 diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 29621c6..172b4b1 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -23,6 +23,11 @@ /* Locate file in a specific region of fmap. Return 0 on success. < 0 on error*/ int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, const char *name, uint32_t *type); +/* Locate file by name filling in the cbfs_type and compression information. + Returns 0 on success, < 0 on error. */ +int cbfs_boot_locate_file_get_compression_info(struct cbfsf *fh, + const char *name, uint32_t *cbfs_type, + uint32_t *compression_algo, size_t *decompressed_size); /* Load an arbitrary type file from CBFS into a buffer. Returns amount of * loaded bytes on success or 0 on error. File will get decompressed as * necessary. Same decompression requirements as diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index a3294de..c6767b0 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -189,6 +189,19 @@ return cbfs_boot_map_with_leak(name, CBFS_TYPE_OPTIONROM, NULL); } +int cbfs_boot_locate_file_get_compression_info(struct cbfsf *fh, + const char *name, uint32_t *cbfs_type, + uint32_t *compression_algo, size_t *decompressed_size) +{ + if (cbfs_boot_locate(fh, name, cbfs_type) < 0) + return -1; + + if (cbfsf_decompression_info(fh, compression_algo, decompressed_size) < 0) + return -1; + + return 0; +} + size_t cbfs_boot_load_file(const char *name, void *buf, size_t buf_size, uint32_t type) { @@ -196,13 +209,11 @@ uint32_t compression_algo; size_t decompressed_size; - if (cbfs_boot_locate(&fh, name, &type) < 0) + if (cbfs_boot_locate_file_get_compression_info(&fh, name, &type, + &compression_algo, &decompressed_size) < 0) return 0; - if (cbfsf_decompression_info(&fh, &compression_algo, - &decompressed_size) - < 0 - || decompressed_size > buf_size) + if (decompressed_size > buf_size) return 0; return cbfs_load_and_decompress(&fh.data, 0, region_device_sz(&fh.data), -- To view, visit https://review.coreboot.org/c/coreboot/+/41448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I605b036a50ed26ad6897b5b86a37897766169e6b Gerrit-Change-Number: 41448 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Update SMBIOS type 0 firmware version by VPD variable
by insomniac (Code Review) 02 Jun '20

02 Jun '20

insomniac has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41720 ) Change subject: mb/ocp/deltalake: Update SMBIOS type 0 firmware version by VPD variable ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/41720/11/src/mainboard/ocp/deltala… File src/mainboard/ocp/deltalake/ramstage.c: https://review.coreboot.org/c/coreboot/+/41720/11/src/mainboard/ocp/deltala… PS11, Line 79: const char *smbios_mainboard_bios_version(void) this feature would be useful beyond just DeltaLake. I am wondering whether we can generalize it in a way that: * doesn't change coreboot's default behaviour * allows more granular control (e.g. what is the fallback if the VPD variable is missing?) Some ideas to do that: 1. make this a global Kconfig tunable (e.g. CONFIG_VERSION_VPD, or any better name), whose value is the name of the VPD variable to read (instead of the hard-coded "version") 2. if this is set, override the default behaviour, otherwise use the normal versioning system 3. add a dependent config value for default value if the VPD var is missing (e.g. CONFIG_VERSION_VPD_DEFAULT_IF_MISSING), whose value would be used if VPD version is missing; and if not set, will return `coreboot_version` -- To view, visit https://review.coreboot.org/c/coreboot/+/41720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98a8fe1135728f31ec154d6340d19be8d8f980ba Gerrit-Change-Number: 41720 Gerrit-PatchSet: 11 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: insomniac <insomniac(a)slackware.it> Gerrit-Comment-Date: Tue, 02 Jun 2020 17:20:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: DO NOT MERGE: Increase the ACPIGEN stack size
by Raul Rangel (Code Review) 02 Jun '20

02 Jun '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41584 ) Change subject: DO NOT MERGE: Increase the ACPIGEN stack size ...................................................................... DO NOT MERGE: Increase the ACPIGEN stack size Picasso currently needs a larger limit. Need to figure out why. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I2aa1c4dadc4f0405e03d79df4eba8ce685a0e18b --- M src/acpi/acpigen.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/41584/1 diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 08f482d..089ce90 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* How much nesting do we support? */ -#define ACPIGEN_LENSTACK_SIZE 10 +#define ACPIGEN_LENSTACK_SIZE 15 /* * If you need to change this, change acpigen_write_len_f and -- To view, visit https://review.coreboot.org/c/coreboot/+/41584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aa1c4dadc4f0405e03d79df4eba8ce685a0e18b Gerrit-Change-Number: 41584 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/mtrr: add helper for setting multiple MTRRs
by Aaron Durbin (Code Review) 02 Jun '20

02 Jun '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41849 ) Change subject: cpu/x86/mtrr: add helper for setting multiple MTRRs ...................................................................... cpu/x86/mtrr: add helper for setting multiple MTRRs Introduce concept of var_mtrr_context object for tracking and assigning MTRR values. The algorithm is lifted from postcar_loader code, but it's generalized for different type of users: setting MSRs explicitly or deferring to a particular caller's desired actions. BUG=b:155426691,b:155322763 Change-Id: Ic03b4b617196f04071093bbba4cf28d23fa482d8 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/cpu/x86/mtrr/earlymtrr.c M src/include/cpu/x86/mtrr.h 2 files changed, 100 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/41849/1 diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 5a2ce55..008d9fd 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -65,3 +65,72 @@ wrmsr(MTRR_PHYS_BASE(i), mtrr); } } + +void var_mtrr_context_init(struct var_mtrr_context *ctx, void *arg) +{ + ctx->upper_mask = (1U << (cpu_phys_address_size() - 32)) - 1; + ctx->max_var_mtrrs = get_var_mtrr_count(); + ctx->used_var_mtrrs = 0; + ctx->arg = arg; +} + +int var_mtrr_set_with_cb(struct var_mtrr_context *ctx, uintptr_t addr, size_t size, + int type, void (*callback)(const struct var_mtrr_context *ctx, + uintptr_t base_addr, size_t size, + msr_t base, msr_t mask)) +{ + /* + * Utilize additional MTRRs if the specified size is greater than the + * base address alignment. + */ + while (size != 0) { + uint32_t addr_lsb; + uint32_t size_msb; + uint32_t mtrr_size; + msr_t base; + msr_t mask; + + if (ctx->used_var_mtrrs >= ctx->max_var_mtrrs) { + printk(BIOS_ERR, "No more variable MTRRs: %d\n", + ctx->max_var_mtrrs); + return -1; + } + + addr_lsb = fls(addr); + size_msb = fms(size); + + /* All MTRR entries need to have their base aligned to the mask + * size. The maximum size is calculated by a function of the + * min base bit set and maximum size bit set. */ + if (addr_lsb > size_msb) + mtrr_size = 1 << size_msb; + else + mtrr_size = 1 << addr_lsb; + + base.hi = (uint64_t)addr >> 32; + base.lo = addr | type; + mask.hi = ctx->upper_mask; + mask.lo = ~(mtrr_size - 1) | MTRR_PHYS_MASK_VALID; + callback(ctx, addr, mtrr_size, base, mask); + ctx->used_var_mtrrs++; + + size -= mtrr_size; + addr += mtrr_size; + } + + return 0; +} + +static void set_mtrr(const struct var_mtrr_context *ctx, uintptr_t base_addr, size_t size, + msr_t base, msr_t mask) +{ + int i = var_mtrr_context_current_mtrr(ctx); + + wrmsr(MTRR_PHYS_BASE(i), base); + wrmsr(MTRR_PHYS_MASK(i), mask); +} + +int var_mtrr_set(struct var_mtrr_context *ctx, uintptr_t addr, size_t size, int type) +{ + return var_mtrr_set_with_cb(ctx, addr, size, type, set_mtrr); +} diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 50148ff..552941e 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -111,6 +111,37 @@ asmlinkage void display_mtrrs(void); +/* Variable MTRR structure to help track and set MTRRs prior to ramstage. This + * and the following APIs can be used to set up more complex MTRR solutions + * instead of open coding get_free_var_mtrr() and set_var_mtrr() or for determining + * a future solution, such as postcar_loader. */ +struct var_mtrr_context { + uint32_t upper_mask; + int max_var_mtrrs; + int used_var_mtrrs; + void *arg; /* optional callback parameter */ +}; + +/* Returns 0-relative MTRR from context. Use MTRR_PHYS_BASE|MASK macros for calculating + MSR address value. */ +static inline int var_mtrr_context_current_mtrr(const struct var_mtrr_context *ctx) +{ + return ctx->used_var_mtrrs; +} + +/* Initialize var_mtrr_context object. Assumes all variable MTRRs are not yet used. */ +void var_mtrr_context_init(struct var_mtrr_context *ctx, void *arg); +/* Allocate a variable mtrr base and mask, calling the provided callback for each MTRR + * MSR base-mask pair needed to accommodate the address and size request. Returns < 0 + * on error and 0 on success. */ +int var_mtrr_set_with_cb(struct var_mtrr_context *ctx, + uintptr_t addr, size_t size, int type, + void (*callback)(const struct var_mtrr_context *ctx, + uintptr_t base_addr, size_t size, + msr_t base, msr_t mask)); +/* Same as var_mtrr_set_with_cb() but just write the MSRs directly. */ +int var_mtrr_set(struct var_mtrr_context *ctx, uintptr_t addr, size_t size, int type); + /* * Set the MTRRs using the data on the stack from setup_stack_and_mtrrs. * Return a new top_of_stack value which removes the setup_stack_and_mtrrs data. -- To view, visit https://review.coreboot.org/c/coreboot/+/41849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic03b4b617196f04071093bbba4cf28d23fa482d8 Gerrit-Change-Number: 41849 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: config spk_en gpio to low by default
by Tim Wawrzynczak (Code Review) 02 Jun '20

02 Jun '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41853 ) Change subject: mb/google/dedede: config spk_en gpio to low by default ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/41853/2/src/mainboard/google/deded… File src/mainboard/google/dedede/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/41853/2/src/mainboard/google/deded… PS2, Line 178: GPP_D17 > Hi Furquan, for waddledee audio support is not enabled yet. […] This is the baseboard GPIO file, so it should apply to all variants. -- To view, visit https://review.coreboot.org/c/coreboot/+/41853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I070679457b06cb82633c1197b893a5d89c8b2cf0 Gerrit-Change-Number: 41853 Gerrit-PatchSet: 3 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Jun 2020 16:53:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Usha P <usha.p(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/postcar_loader: utilize var_mtrr_context API
by Aaron Durbin (Code Review) 02 Jun '20

02 Jun '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41850 ) Change subject: arch/x86/postcar_loader: utilize var_mtrr_context API ...................................................................... arch/x86/postcar_loader: utilize var_mtrr_context API Now that there is a generic solution in mtrr subsystem utilize the API. BUG=b:155426691,b:155322763 Change-Id: Ie349d5669808928c7470c99d25c57c784174b4e9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/arch/x86/include/arch/romstage.h M src/arch/x86/postcar_loader.c 2 files changed, 21 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/41850/1 diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h index 8418366..28d29bf 100644 --- a/src/arch/x86/include/arch/romstage.h +++ b/src/arch/x86/include/arch/romstage.h @@ -5,6 +5,7 @@ #include <stddef.h> #include <stdint.h> +#include <cpu/x86/mtrr.h> void mainboard_romstage_entry(void); @@ -16,10 +17,8 @@ struct postcar_frame { uintptr_t stack; - uint32_t upper_mask; - int max_var_mtrrs; - int num_var_mtrrs; int skip_common_mtrr; + struct var_mtrr_context ctx; }; /* diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 58c6db9..084384e 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -26,12 +26,7 @@ static void postcar_frame_prepare(struct postcar_frame *pcf) { - msr_t msr; - msr = rdmsr(MTRR_CAP_MSR); - - pcf->upper_mask = (1 << (cpu_phys_address_size() - 32)) - 1; - pcf->max_var_mtrrs = msr.lo & MTRR_CAP_VCNT; - pcf->num_var_mtrrs = 0; + var_mtrr_context_init(&pcf->ctx, pcf); } int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size) @@ -60,47 +55,25 @@ return 0; } +static void postcar_var_mtrr_set(const struct var_mtrr_context *ctx, + uintptr_t addr, size_t size, + msr_t base, msr_t mask) +{ + struct postcar_frame *pcf = ctx->arg; + + printk(BIOS_DEBUG, "MTRR Range: Start=%lx End=%lx (Size %zx)\n", + addr, addr + size, size); + + stack_push(pcf, mask.hi); + stack_push(pcf, mask.lo); + stack_push(pcf, base.hi); + stack_push(pcf, base.lo); +} + void postcar_frame_add_mtrr(struct postcar_frame *pcf, uintptr_t addr, size_t size, int type) { - /* - * Utilize additional MTRRs if the specified size is greater than the - * base address alignment. - */ - while (size != 0) { - uint32_t addr_lsb; - uint32_t size_msb; - uint32_t mtrr_size; - - if (pcf->num_var_mtrrs >= pcf->max_var_mtrrs) { - printk(BIOS_ERR, "No more variable MTRRs: %d\n", - pcf->max_var_mtrrs); - return; - } - - addr_lsb = fls(addr); - size_msb = fms(size); - - /* All MTRR entries need to have their base aligned to the mask - * size. The maximum size is calculated by a function of the - * min base bit set and maximum size bit set. */ - if (addr_lsb > size_msb) - mtrr_size = 1 << size_msb; - else - mtrr_size = 1 << addr_lsb; - - printk(BIOS_DEBUG, "MTRR Range: Start=%lx End=%lx (Size %x)\n", - addr, addr + mtrr_size, mtrr_size); - - stack_push(pcf, pcf->upper_mask); - stack_push(pcf, ~(mtrr_size - 1) | MTRR_PHYS_MASK_VALID); - stack_push(pcf, 0); - stack_push(pcf, addr | type); - pcf->num_var_mtrrs++; - - size -= mtrr_size; - addr += mtrr_size; - } + var_mtrr_set_with_cb(&pcf->ctx, addr, size, type, postcar_var_mtrr_set); } void postcar_frame_add_romcache(struct postcar_frame *pcf, int type) @@ -140,8 +113,8 @@ * Place the number of used variable MTRRs on stack then max number * of variable MTRRs supported in the system. */ - stack_push(pcf, pcf->num_var_mtrrs); - stack_push(pcf, pcf->max_var_mtrrs); + stack_push(pcf, pcf->ctx.used_var_mtrrs); + stack_push(pcf, pcf->ctx.max_var_mtrrs); } static void finalize_load(uintptr_t *stack_top_ptr, uintptr_t stack_top) -- To view, visit https://review.coreboot.org/c/coreboot/+/41850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie349d5669808928c7470c99d25c57c784174b4e9 Gerrit-Change-Number: 41850 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: usb/xhci: Fix timeout logic
by Tim Wawrzynczak (Code Review) 02 Jun '20

02 Jun '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41854 ) Change subject: usb/xhci: Fix timeout logic ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/41854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81a888aa0a1544e55e6a680be8f3b7f6e0d87812 Gerrit-Change-Number: 41854 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jun 2020 16:48:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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