coreboot-gerrit June 2020

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Change in coreboot[master]: src: Add missing <types.h>
by HAOUAS Elyes (Code Review) 02 Jun '20

02 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42008 ) Change subject: src: Add missing <types.h> ...................................................................... src: Add missing <types.h> Remove remining unused <stddef> and replace <stdint.h> by <types.h> when <stddef.h> is missing. still missing <stddef>: diff <(git grep -l '#include <$types.h>\|<stddef.h>$' -- src/) <(git grep -l 'size_t\|wchar_t\|wint_t\|DEVTREE_EARLY\|DEVTREE_CONST\|MAYBE_STATIC_NONZERO\|zeroptr' -- src/) |grep -v vendorcode |grep '>' Change-Id: I82993b6955b615fdbe019ee4c470e19cbdb72943 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/armv7/cache.c M src/arch/arm64/armv8/cache.c M src/arch/arm64/armv8/mmu.c M src/arch/riscv/include/vm.h M src/arch/x86/exception.c M src/arch/x86/include/arch/bert_storage.h M src/arch/x86/include/arch/ebda.h M src/arch/x86/include/smm.h M src/arch/x86/memset.c M src/console/vtxprintf.c M src/cpu/amd/pi/00730F01/microcode_fam16h.c M src/device/i2c_bus.c M src/drivers/amd/agesa/state_machine.c M src/drivers/aspeed/common/aspeed_coreboot.h M src/drivers/elog/elog.c M src/drivers/i2c/designware/dw_i2c.h M src/drivers/i2c/tpm/tis.c M src/drivers/i2c/tpm/tpm.h M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h M src/drivers/secunet/dmi/smbios.c M src/drivers/spi/boot_device_rw_nommap.c M src/drivers/spi/cbfs_spi.c M src/drivers/spi/spi_sdcard.c M src/ec/google/chromeec/crosec_proto.c M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec_i2c.c M src/ec/google/chromeec/ec_lpc.c M src/ec/google/chromeec/vstore.c M src/ec/google/wilco/chip.c M src/ec/google/wilco/commands.c M src/ec/kontron/kempld/kempld_i2c.c M src/include/acpi/acpi_device.h M src/include/acpi/acpigen.h M src/include/crc_byte.h M src/include/device/i2c_bus.h M src/include/device/pci_rom.h M src/include/device/smbus_host.h M src/include/device/soundwire.h M src/include/device_tree.h M src/include/dimm_info_util.h M src/include/region_file.h M src/lib/fit.c M src/lib/gcov-glue.c M src/lib/reg_script.c M src/lib/rmodule.c M src/lib/selfboot.c M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/link/early_init.c M src/mainboard/google/octopus/mainboard.c M src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/reef/variants/coral/mainboard.c M src/mainboard/google/slippy/variants/leon/romstage.c M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/icelake_rvp/board_id.c M src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/jasperlake_rvp/board_id.c M src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/kunimitsu/spd/spd_util.c M src/mainboard/intel/tglrvp/board_id.c M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/lenovo/s230u/early_init.c M src/mainboard/lenovo/x1_carbon_gen1/early_init.c M src/mainboard/samsung/lumpy/early_init.c M src/mainboard/scaleway/tagada/bmcinfo.c M src/mainboard/supermicro/x9scl/early_init.c M src/northbridge/amd/agesa/agesa_helper.h M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/x4x/memmap.c M src/security/vboot/vboot_common.h M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/gpio.c M src/soc/amd/picasso/memmap.c M src/soc/amd/stoneyridge/gpio.c M src/soc/amd/stoneyridge/memmap.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/cavium/cn81xx/include/soc/cpu.h M src/soc/cavium/cn81xx/timer.c M src/soc/cavium/cn81xx/uart.c M src/soc/intel/apollolake/cse.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/cannonlake/elog.c M src/soc/intel/cannonlake/include/soc/gpio_defs.h M src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/common/block/include/intelblocks/lpss.h M src/soc/intel/common/block/include/intelblocks/pmc.h M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/common/mma.h M src/soc/intel/common/smbios.h M src/soc/intel/denverton_ns/gpio_dnv.c M src/soc/intel/denverton_ns/soc_util.c M src/soc/intel/icelake/include/soc/gpio_defs.h M src/soc/intel/jasperlake/include/soc/gpio_defs.h M src/soc/intel/skylake/elog.c M src/soc/intel/skylake/include/soc/gpio_defs.h M src/soc/intel/tigerlake/include/soc/gpio_defs.h M src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h M src/soc/mediatek/common/include/soc/gpio_common.h M src/soc/mediatek/common/include/soc/usb_common.h M src/soc/mediatek/mt8173/include/soc/addressmap.h M src/soc/mediatek/mt8173/include/soc/spm.h M src/soc/nvidia/tegra124/include/soc/addressmap.h M src/soc/nvidia/tegra124/include/soc/emc.h M src/soc/nvidia/tegra124/include/soc/mc.h M src/soc/nvidia/tegra124/include/soc/sdram_param.h M src/soc/nvidia/tegra124/include/soc/spi.h M src/soc/nvidia/tegra210/include/soc/clk_rst.h M src/soc/nvidia/tegra210/include/soc/emc.h M src/soc/nvidia/tegra210/include/soc/funitcfg.h M src/soc/nvidia/tegra210/include/soc/mc.h M src/soc/nvidia/tegra210/include/soc/padconfig.h M src/soc/nvidia/tegra210/include/soc/sdram_param.h M src/soc/nvidia/tegra210/include/soc/spi.h M src/soc/rockchip/common/include/soc/spi.h M src/soc/sifive/fu540/clock.c M src/southbridge/amd/agesa/hudson/spi.c M src/southbridge/intel/common/spi.c M src/superio/smsc/sch5545/sch5545_emi.h 134 files changed, 105 insertions(+), 134 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/42008/1 diff --git a/src/arch/arm/armv7/cache.c b/src/arch/arm/armv7/cache.c index 1c46e04..ae283f0 100644 --- a/src/arch/arm/armv7/cache.c +++ b/src/arch/arm/armv7/cache.c @@ -5,7 +5,7 @@ * Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition */ -#include <stdint.h> +#include <types.h> #include <arch/cache.h> #include <program_loading.h> diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index ae0729e..e30e878 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -5,7 +5,7 @@ * Reference: ARM Architecture Reference Manual, ARMv8-A edition */ -#include <stdint.h> +#include <types.h> #include <arch/cache.h> #include <arch/lib_helpers.h> diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c index 72e5cca..2f3bfef 100644 --- a/src/arch/arm64/armv8/mmu.c +++ b/src/arch/arm64/armv8/mmu.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause */ #include <assert.h> -#include <stdint.h> +#include <types.h> #include <string.h> #include <symbols.h> diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h index 5501a0c..012bc4d 100644 --- a/src/arch/riscv/include/vm.h +++ b/src/arch/riscv/include/vm.h @@ -4,7 +4,7 @@ #define _VM_H #include <string.h> -#include <stdint.h> +#include <types.h> #include <arch/encoding.h> #define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index 46ba370..0489665 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -7,7 +7,7 @@ #include <console/streams.h> #include <cpu/x86/cr.h> #include <cpu/x86/lapic.h> -#include <stdint.h> +#include <types.h> #include <string.h> #if CONFIG(GDB_STUB) diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h index c6a2f30..e055a83 100644 --- a/src/arch/x86/include/arch/bert_storage.h +++ b/src/arch/x86/include/arch/bert_storage.h @@ -3,7 +3,7 @@ #ifndef _BERT_STORAGE_H_ #define _BERT_STORAGE_H_ -#include <stdint.h> +#include <types.h> #include <acpi/acpi.h> /* Items in the BERT region diff --git a/src/arch/x86/include/arch/ebda.h b/src/arch/x86/include/arch/ebda.h index 71426b1..766db22 100644 --- a/src/arch/x86/include/arch/ebda.h +++ b/src/arch/x86/include/arch/ebda.h @@ -4,7 +4,6 @@ #define __ARCH_EBDA_H #include <stdint.h> -#include <stddef.h> #define X86_BDA_SIZE 0x200 #define X86_BDA_BASE ((void *)0x400) diff --git a/src/arch/x86/include/smm.h b/src/arch/x86/include/smm.h index 739b7158..e6db9dc 100644 --- a/src/arch/x86/include/smm.h +++ b/src/arch/x86/include/smm.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stddef.h> #include <stdint.h> #include <cpu/x86/smm.h> diff --git a/src/arch/x86/memset.c b/src/arch/x86/memset.c index 1796342..0cfa249 100644 --- a/src/arch/x86/memset.c +++ b/src/arch/x86/memset.c @@ -3,7 +3,7 @@ /* From glibc-2.14, sysdeps/i386/memset.c */ #include <string.h> -#include <stdint.h> +#include <types.h> typedef uint32_t op_t; diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 273bc7e..33e2f14 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -7,7 +7,7 @@ #include <console/vtxprintf.h> #include <ctype.h> #include <string.h> -#include <stdint.h> +#include <types.h> #define call_tx(x) tx_byte(x, data) diff --git a/src/cpu/amd/pi/00730F01/microcode_fam16h.c b/src/cpu/amd/pi/00730F01/microcode_fam16h.c index 496f2ec..29af710 100644 --- a/src/cpu/amd/pi/00730F01/microcode_fam16h.c +++ b/src/cpu/amd/pi/00730F01/microcode_fam16h.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/amd/microcode.h> diff --git a/src/device/i2c_bus.c b/src/device/i2c_bus.c index a65cdad..443c57b 100644 --- a/src/device/i2c_bus.c +++ b/src/device/i2c_bus.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <console/console.h> #include <device/smbus.h> #include <device/i2c_bus.h> diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 6ae7d99..889ddf5 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <string.h> #include <acpi/acpi.h> #include <bootstate.h> diff --git a/src/drivers/aspeed/common/aspeed_coreboot.h b/src/drivers/aspeed/common/aspeed_coreboot.h index 3f740b2..22a807c 100644 --- a/src/drivers/aspeed/common/aspeed_coreboot.h +++ b/src/drivers/aspeed/common/aspeed_coreboot.h @@ -5,7 +5,7 @@ #include <delay.h> #include <stdlib.h> -#include <stdint.h> +#include <types.h> #include <string.h> #include <arch/io.h> #include <device/mmio.h> diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 5e3409b..27573ed 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -14,7 +14,7 @@ #include <post.h> #include <rtc.h> #include <smbios.h> -#include <stdint.h> +#include <types.h> #include <string.h> #include <elog.h> #include "elog_internal.h" diff --git a/src/drivers/i2c/designware/dw_i2c.h b/src/drivers/i2c/designware/dw_i2c.h index 45f305e..5393d4e 100644 --- a/src/drivers/i2c/designware/dw_i2c.h +++ b/src/drivers/i2c/designware/dw_i2c.h @@ -5,7 +5,7 @@ #include <device/device.h> #include <device/i2c.h> -#include <stdint.h> +#include <types.h> #if CONFIG(DRIVERS_I2C_DESIGNWARE_DEBUG) #define DW_I2C_DEBUG BIOS_DEBUG diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c index 217d8c6..9905331 100644 --- a/src/drivers/i2c/tpm/tis.c +++ b/src/drivers/i2c/tpm/tis.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <stdint.h> +#include <types.h> #include <string.h> #include <assert.h> #include <commonlib/endian.h> diff --git a/src/drivers/i2c/tpm/tpm.h b/src/drivers/i2c/tpm/tpm.h index eb4fef1..da2271f 100644 --- a/src/drivers/i2c/tpm/tpm.h +++ b/src/drivers/i2c/tpm/tpm.h @@ -12,7 +12,7 @@ #ifndef __DRIVERS_TPM_SLB9635_I2C_TPM_H__ #define __DRIVERS_TPM_SLB9635_I2C_TPM_H__ -#include <stdint.h> +#include <types.h> enum tpm_timeout { TPM_TIMEOUT = 1, /* msecs */ diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index fdc92a7..c5fa202 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -6,7 +6,7 @@ #include <console/console.h> #include <fsp/api.h> #include <fsp/util.h> -#include <stdint.h> +#include <types.h> #include <string.h> #define HOB_HEADER_LEN 8 diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index c6c9179..76769ec 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -3,7 +3,6 @@ #ifndef _FSP2_0_API_H_ #define _FSP2_0_API_H_ -#include <stddef.h> #include <stdint.h> #include <fsp/soc_binding.h> #include <soc/intel/common/mma.h> diff --git a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h index 93e54b1..8ba8b3c 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h +++ b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h @@ -3,7 +3,6 @@ #ifndef _FSP2_0_SOC_BINDING_H_ #define _FSP2_0_SOC_BINDING_H_ -#include <stddef.h> #pragma pack(push) diff --git a/src/drivers/secunet/dmi/smbios.c b/src/drivers/secunet/dmi/smbios.c index f407b51..05df959 100644 --- a/src/drivers/secunet/dmi/smbios.c +++ b/src/drivers/secunet/dmi/smbios.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <string.h> #include <ctype.h> #include <commonlib/helpers.h> diff --git a/src/drivers/spi/boot_device_rw_nommap.c b/src/drivers/spi/boot_device_rw_nommap.c index a383f26..8059a14 100644 --- a/src/drivers/spi/boot_device_rw_nommap.c +++ b/src/drivers/spi/boot_device_rw_nommap.c @@ -3,7 +3,7 @@ #include <boot_device.h> #include <spi_flash.h> #include <spi-generic.h> -#include <stdint.h> +#include <types.h> static struct spi_flash sfg; static bool sfg_init_done; diff --git a/src/drivers/spi/cbfs_spi.c b/src/drivers/spi/cbfs_spi.c index 0034460..1ff2bcb 100644 --- a/src/drivers/spi/cbfs_spi.c +++ b/src/drivers/spi/cbfs_spi.c @@ -11,7 +11,7 @@ #include <spi_flash.h> #include <symbols.h> #include <cbmem.h> -#include <stdint.h> +#include <types.h> #include <timer.h> static struct spi_flash spi_flash_info; diff --git a/src/drivers/spi/spi_sdcard.c b/src/drivers/spi/spi_sdcard.c index 5d0a71b..f8faceb 100644 --- a/src/drivers/spi/spi_sdcard.c +++ b/src/drivers/spi/spi_sdcard.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <string.h> #include <spi-generic.h> #include <spi_sdcard.h> diff --git a/src/ec/google/chromeec/crosec_proto.c b/src/ec/google/chromeec/crosec_proto.c index e54ad7e..593c320 100644 --- a/src/ec/google/chromeec/crosec_proto.c +++ b/src/ec/google/chromeec/crosec_proto.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <stdint.h> +#include <types.h> #include <string.h> #include "ec.h" diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index a97dfb3..79b1b5c 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <string.h> #include <assert.h> #include <cbmem.h> diff --git a/src/ec/google/chromeec/ec_i2c.c b/src/ec/google/chromeec/ec_i2c.c index 68e3cf2..b79e09d 100644 --- a/src/ec/google/chromeec/ec_i2c.c +++ b/src/ec/google/chromeec/ec_i2c.c @@ -2,7 +2,7 @@ #include <console/console.h> #include <device/i2c_simple.h> -#include <stdint.h> +#include <types.h> #include <string.h> #include "ec.h" diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 5306dcc..9e4c0e6 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -6,7 +6,7 @@ #include <delay.h> #include <device/pnp.h> #include <ec/google/common/mec.h> -#include <stdint.h> +#include <types.h> #include "chip.h" #include "ec.h" diff --git a/src/ec/google/chromeec/vstore.c b/src/ec/google/chromeec/vstore.c index 2a33a3f..c5a68e2 100644 --- a/src/ec/google/chromeec/vstore.c +++ b/src/ec/google/chromeec/vstore.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <string.h> #include "ec.h" #include "ec_commands.h" diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index dccaa23..87aa0b9 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -11,7 +11,7 @@ #include <ec/acpi/ec.h> #include <intelblocks/cpulib.h> #include <pc80/keyboard.h> -#include <stdint.h> +#include <types.h> #include "commands.h" #include "ec.h" diff --git a/src/ec/google/wilco/commands.c b/src/ec/google/wilco/commands.c index 98b1efb..f6b1a21 100644 --- a/src/ec/google/wilco/commands.c +++ b/src/ec/google/wilco/commands.c @@ -2,7 +2,7 @@ #include <console/console.h> #include <ec/acpi/ec.h> -#include <stdint.h> +#include <types.h> #include <string.h> #include "ec.h" diff --git a/src/ec/kontron/kempld/kempld_i2c.c b/src/ec/kontron/kempld/kempld_i2c.c index 296cf76..78c6034 100644 --- a/src/ec/kontron/kempld/kempld_i2c.c +++ b/src/ec/kontron/kempld/kempld_i2c.c @@ -6,7 +6,7 @@ * Based on the similar driver in Linux. */ -#include <stdint.h> +#include <types.h> #include <console/console.h> #include <device/device.h> #include <device/i2c_bus.h> diff --git a/src/include/acpi/acpi_device.h b/src/include/acpi/acpi_device.h index 20dd8a4..21eb8db 100644 --- a/src/include/acpi/acpi_device.h +++ b/src/include/acpi/acpi_device.h @@ -4,7 +4,7 @@ #define __ACPI_ACPI_DEVICE_H__ #include <device/i2c.h> -#include <stdint.h> +#include <types.h> #include <spi-generic.h> enum acpi_dp_type { diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index a99489d..8611e1d 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -3,7 +3,7 @@ #ifndef __ACPI_ACPIGEN_H__ #define __ACPI_ACPIGEN_H__ -#include <stdint.h> +#include <types.h> #include <acpi/acpi.h> #include <acpi/acpi_device.h> #include <acpi/acpi_pld.h> diff --git a/src/include/crc_byte.h b/src/include/crc_byte.h index 2e93fe9..869c9c4 100644 --- a/src/include/crc_byte.h +++ b/src/include/crc_byte.h @@ -3,7 +3,7 @@ #ifndef CRC_BYTE_H #define CRC_BYTE_H -#include <stdint.h> +#include <types.h> /* This function is used to calculate crc7 byte by byte, with polynomial * x^7 + x^3 + 1. diff --git a/src/include/device/i2c_bus.h b/src/include/device/i2c_bus.h index 0e35a61..158cc93 100644 --- a/src/include/device/i2c_bus.h +++ b/src/include/device/i2c_bus.h @@ -3,7 +3,7 @@ #ifndef _DEVICE_I2C_BUS_H_ #define _DEVICE_I2C_BUS_H_ -#include <stdint.h> +#include <types.h> #include <device/i2c.h> #include <device/device.h> diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index c49389f..e6e6d53 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -1,7 +1,6 @@ #ifndef PCI_ROM_H #define PCI_ROM_H #include <endian.h> -#include <stddef.h> #include <acpi/acpi.h> #define PCI_ROM_HDR 0xAA55 diff --git a/src/include/device/smbus_host.h b/src/include/device/smbus_host.h index d9390ea..7ab3e9e 100644 --- a/src/include/device/smbus_host.h +++ b/src/include/device/smbus_host.h @@ -3,7 +3,7 @@ #ifndef __DEVICE_SMBUS_HOST_H__ #define __DEVICE_SMBUS_HOST_H__ -#include <stdint.h> +#include <types.h> #include <console/console.h> /* Low-level SMBUS host controller. */ diff --git a/src/include/device/soundwire.h b/src/include/device/soundwire.h index 85e3186..9e96bbf 100644 --- a/src/include/device/soundwire.h +++ b/src/include/device/soundwire.h @@ -17,7 +17,7 @@ #define __DEVICE_SOUNDWIRE_H__ #include <stdbool.h> -#include <stdint.h> +#include <types.h> /** * enum soundwire_limits - Limits on number of SoundWire devices in topology. diff --git a/src/include/device_tree.h b/src/include/device_tree.h index bd0d151..5f32196 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -4,7 +4,7 @@ #ifndef __DEVICE_TREE_H__ #define __DEVICE_TREE_H__ -#include <stdint.h> +#include <types.h> #include <list.h> /* diff --git a/src/include/dimm_info_util.h b/src/include/dimm_info_util.h index d20e8cd..3f491b2 100644 --- a/src/include/dimm_info_util.h +++ b/src/include/dimm_info_util.h @@ -4,7 +4,7 @@ #define _DIMM_INFO_UTIL_H_ #include <smbios.h> -#include <stdint.h> +#include <types.h> /** * Convert the SMBIOS bit widths into an SPD encoded width. diff --git a/src/include/region_file.h b/src/include/region_file.h index 0df64e5..5c36caf 100644 --- a/src/include/region_file.h +++ b/src/include/region_file.h @@ -4,7 +4,7 @@ #define REGION_FILE_H #include <commonlib/region.h> -#include <stdint.h> +#include <types.h> /* * A region file is an abstraction to allow appending updates in a diff --git a/src/lib/fit.c b/src/lib/fit.c index 748cd61..e038289 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -6,7 +6,7 @@ #include <console/console.h> #include <ctype.h> #include <endian.h> -#include <stdint.h> +#include <types.h> #include <bootmem.h> #include <stdlib.h> #include <string.h> diff --git a/src/lib/gcov-glue.c b/src/lib/gcov-glue.c index 101aec9..1cbe875 100644 --- a/src/lib/gcov-glue.c +++ b/src/lib/gcov-glue.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <bootstate.h> #include <cbmem.h> diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 73b781a..d8a0f31 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -8,7 +8,7 @@ #include <device/device.h> #include <device/resource.h> #include <device/pci.h> -#include <stdint.h> +#include <types.h> #include <reg_script.h> #if CONFIG(ARCH_X86) diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 7944535..f097a63 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -2,7 +2,7 @@ #include <assert.h> #include <cbmem.h> #include <cbfs.h> -#include <stdint.h> +#include <types.h> #include <stdlib.h> #include <string.h> #include <console/console.h> diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index c5ad525..4bb110d 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -3,7 +3,7 @@ #include <commonlib/bsd/compression.h> #include <commonlib/endian.h> #include <console/console.h> -#include <stdint.h> +#include <types.h> #include <stdlib.h> #include <string.h> #include <symbols.h> diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index 5d8355b..f4b6093 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -8,7 +8,7 @@ #define __BASEBOARD_VARIANTS_H__ #include <soc/gpio.h> -#include <stdint.h> +#include <types.h> /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ diff --git a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h index c72df8f..c46f757 100644 --- a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h @@ -4,7 +4,7 @@ #define __BASEBOARD_VARIANTS_H__ #include <soc/gpio.h> -#include <stdint.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h index 2f06a55..5c4a394 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h @@ -5,7 +5,7 @@ #include <soc/cnl_memcfg_init.h> #include <soc/gpio.h> -#include <stdint.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index 8360f2a..970bd82 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <string.h> #include <device/pci_ops.h> #include <acpi/acpi.h> diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index e6dbd03..18010ce 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -17,7 +17,7 @@ #include <soc/gpio.h> #include <soc/nhlt.h> #include <soc/pci_devs.h> -#include <stdint.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include <variant/ec.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h index 206ce8b..cab28a0 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h @@ -5,7 +5,7 @@ #include <soc/gpio.h> #include <soc/meminit.h> -#include <stdint.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* The next set of functions return the gpio table and fill in the number of diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h index 1fdc32f..47edcdf 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h @@ -4,7 +4,7 @@ #define __BASEBOARD_VARIANTS_H__ #include <soc/gpio.h> -#include <stdint.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h index 5b08c6a..ea79f13 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h @@ -5,7 +5,7 @@ #include <soc/gpio.h> #include <soc/meminit.h> -#include <stdint.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* Return the sku id based off the strapping resistors attached to SoC. */ diff --git a/src/mainboard/google/reef/variants/coral/mainboard.c b/src/mainboard/google/reef/variants/coral/mainboard.c index 683624c..581534d 100644 --- a/src/mainboard/google/reef/variants/coral/mainboard.c +++ b/src/mainboard/google/reef/variants/coral/mainboard.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <drivers/intel/gma/opregion.h> #include <ec/google/chromeec/ec.h> #include "baseboard/variants.h" diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index 4485c55..c0c4308 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <string.h> #include <cbfs.h> #include <console/console.h> diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 0f46a33..bf0c3ae9 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <string.h> #include <cbfs.h> #include <console/console.h> diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 7ebb7aa..c4d6d35 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <string.h> #include <cbfs.h> #include <console/console.h> diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h index af9ba07..bb9ca0d 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h @@ -4,7 +4,7 @@ #define __BASEBOARD_VARIANTS_H__ #include <soc/gpio.h> -#include <stdint.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* The next set of functions return the gpio table and fill in the number of diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h index 48abbfe..a492fcd 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h @@ -5,7 +5,7 @@ #include <soc/cnl_memcfg_init.h> #include <soc/gpio.h> -#include <stdint.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* The next set of functions return the gpio table and fill in the number of diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h index 178064f..4623ae6 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h @@ -5,7 +5,7 @@ #include <soc/gpio.h> #include <soc/meminit.h> -#include <stdint.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /** diff --git a/src/mainboard/intel/icelake_rvp/board_id.c b/src/mainboard/intel/icelake_rvp/board_id.c index 0ab7e6a..ea3d584 100644 --- a/src/mainboard/intel/icelake_rvp/board_id.c +++ b/src/mainboard/intel/icelake_rvp/board_id.c @@ -2,7 +2,7 @@ #include "board_id.h" #include <boardid.h> #include <ec/acpi/ec.h> -#include <stdint.h> +#include <types.h> #include <ec/google/chromeec/ec.h> static int get_board_id_via_ext_ec(void) diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h index 16a4cbc..562fb74 100644 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h @@ -4,7 +4,7 @@ #define __BASEBOARD_VARIANTS_H__ #include <soc/gpio.h> -#include <stdint.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* The next set of functions return the gpio table and fill in the number of diff --git a/src/mainboard/intel/jasperlake_rvp/board_id.c b/src/mainboard/intel/jasperlake_rvp/board_id.c index 90609ff..56d960b 100644 --- a/src/mainboard/intel/jasperlake_rvp/board_id.c +++ b/src/mainboard/intel/jasperlake_rvp/board_id.c @@ -3,7 +3,7 @@ #include <boardid.h> #include <ec/acpi/ec.h> #include <ec/google/chromeec/ec.h> -#include <stdint.h> +#include <types.h> #include "board_id.h" diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h index e2e331a..0736c1b 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h @@ -5,7 +5,7 @@ #include <soc/gpio.h> #include <soc/meminit.h> -#include <stdint.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> enum jsl_board_id { diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index a1faf7e..b0b4672 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cbfs.h> #include <console/console.h> -#include <stdint.h> +#include <types.h> #include <string.h> #include "boardid.h" #include "spd.h" diff --git a/src/mainboard/intel/tglrvp/board_id.c b/src/mainboard/intel/tglrvp/board_id.c index a6cad1c..2e07b80 100644 --- a/src/mainboard/intel/tglrvp/board_id.c +++ b/src/mainboard/intel/tglrvp/board_id.c @@ -3,7 +3,7 @@ #include <boardid.h> #include <ec/acpi/ec.h> #include <ec/google/chromeec/ec.h> -#include <stdint.h> +#include <types.h> #include "board_id.h" diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h index 0da97cd..ad87407 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h @@ -5,7 +5,7 @@ #include <soc/gpio.h> #include <soc/meminit.h> -#include <stdint.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* The next set of functions return the gpio table and fill in the number of diff --git a/src/mainboard/lenovo/s230u/early_init.c b/src/mainboard/lenovo/s230u/early_init.c index bbf0c2f..a96e7c3 100644 --- a/src/mainboard/lenovo/s230u/early_init.c +++ b/src/mainboard/lenovo/s230u/early_init.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <string.h> #include <cbfs.h> #include <device/pci_ops.h> diff --git a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c index f5299ea..784de46 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <string.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index 091cbc5..7966ac2 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <string.h> #include <arch/io.h> #include <bootblock_common.h> diff --git a/src/mainboard/scaleway/tagada/bmcinfo.c b/src/mainboard/scaleway/tagada/bmcinfo.c index 0be5532..e8e6eea 100644 --- a/src/mainboard/scaleway/tagada/bmcinfo.c +++ b/src/mainboard/scaleway/tagada/bmcinfo.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <console/console.h> #include <console/uart.h> diff --git a/src/mainboard/supermicro/x9scl/early_init.c b/src/mainboard/supermicro/x9scl/early_init.c index 4a31884..1f0a4e5 100644 --- a/src/mainboard/supermicro/x9scl/early_init.c +++ b/src/mainboard/supermicro/x9scl/early_init.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <device/pci_ops.h> #include <device/pnp_def.h> #include <device/pnp_ops.h> diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h index 8d229b1..389eba2 100644 --- a/src/northbridge/amd/agesa/agesa_helper.h +++ b/src/northbridge/amd/agesa/agesa_helper.h @@ -3,7 +3,6 @@ #ifndef _AGESA_HELPER_H_ #define _AGESA_HELPER_H_ -#include <stddef.h> #include <arch/romstage.h> enum { diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 4fe3998..d19d6d0 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -3,7 +3,7 @@ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ -#include <stdint.h> +#include <types.h> #include <arch/romstage.h> #include <device/pci_ops.h> #include <device/pci_def.h> diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index c282aea..476d240 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -3,7 +3,7 @@ #include <commonlib/helpers.h> #include <console/console.h> #include <acpi/acpi.h> -#include <stdint.h> +#include <types.h> #include <delay.h> #include <cpu/intel/haswell/haswell.h> #include <device/device.h> diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 07aea98..38dc490 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -12,7 +12,7 @@ #include <cpu/x86/smm.h> #include <program_loading.h> #include <cpu/intel/smm_reloc.h> -#include <stdint.h> +#include <types.h> /* Decodes TSEG region size to bytes. */ u32 decode_tseg_size(const u8 esmramc) diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index ad89aef..c8524ef 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -12,7 +12,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> -#include <stdint.h> +#include <types.h> u8 decode_pciebar(u32 *const base, u32 *const len) { diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index ee1ec5e..2a4796e 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -4,7 +4,7 @@ #include <cbmem.h> #include <commonlib/helpers.h> -#include <stdint.h> +#include <types.h> #include <arch/romstage.h> #include <device/pci_ops.h> #include <device/pci_def.h> diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index 66e96e4..0c07382 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -3,7 +3,7 @@ #define __VBOOT_VBOOT_COMMON_H__ #include <commonlib/region.h> -#include <stdint.h> +#include <types.h> #include <vb2_api.h> /* diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h index 764078f..6993b27 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h @@ -3,7 +3,7 @@ #ifndef __AMD_PCI_UTIL_H__ #define __AMD_PCI_UTIL_H__ -#include <stdint.h> +#include <types.h> #include <soc/amd_pci_int_defs.h> /* FCH index/data registers */ diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index e52751a..69eece9 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -3,7 +3,6 @@ #ifndef __PICASSO_CHIP_H__ #define __PICASSO_CHIP_H__ -#include <stddef.h> #include <stdint.h> #include <amdblocks/chip.h> #include <commonlib/helpers.h> diff --git a/src/soc/amd/picasso/gpio.c b/src/soc/amd/picasso/gpio.c index c402fb5..c794553 100644 --- a/src/soc/amd/picasso/gpio.c +++ b/src/soc/amd/picasso/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <amdblocks/gpio_banks.h> #include <amdblocks/acpimmio.h> #include <soc/gpio.h> diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index 5f4ba42..b7f6bfb 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -3,7 +3,7 @@ #define __SIMPLE_DEVICE__ #include <assert.h> -#include <stdint.h> +#include <types.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <cpu/amd/msr.h> diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index a595014..7c02c11 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <amdblocks/gpio_banks.h> #include <amdblocks/acpimmio.h> #include <soc/gpio.h> diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 9807905..faf3db9 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -3,7 +3,7 @@ #define __SIMPLE_DEVICE__ #include <assert.h> -#include <stdint.h> +#include <types.h> #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index c6fdc60..0a9dfdb 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -24,7 +24,7 @@ #include <soc/northbridge.h> #include <soc/pci_devs.h> #include <soc/iomap.h> -#include <stdint.h> +#include <types.h> #include <string.h> #include <arch/bert_storage.h> diff --git a/src/soc/cavium/cn81xx/include/soc/cpu.h b/src/soc/cavium/cn81xx/include/soc/cpu.h index ccbe82c..4d08a18 100644 --- a/src/soc/cavium/cn81xx/include/soc/cpu.h +++ b/src/soc/cavium/cn81xx/include/soc/cpu.h @@ -3,7 +3,7 @@ #ifndef __SOC_CAVIUM_CN81XX_CPU_H__ #define __SOC_CAVIUM_CN81XX_CPU_H__ -#include <stdint.h> +#include <types.h> #include <symbols.h> /** diff --git a/src/soc/cavium/cn81xx/timer.c b/src/soc/cavium/cn81xx/timer.c index 6ac85ef..fa13ba6 100644 --- a/src/soc/cavium/cn81xx/timer.c +++ b/src/soc/cavium/cn81xx/timer.c @@ -10,7 +10,7 @@ #include <console/console.h> #include <soc/clock.h> #include <soc/timer.h> -#include <stdint.h> +#include <types.h> #include <timer.h> #include <soc/addressmap.h> #include <assert.h> diff --git a/src/soc/cavium/cn81xx/uart.c b/src/soc/cavium/cn81xx/uart.c index 03f94d5..8e2ccd8 100644 --- a/src/soc/cavium/cn81xx/uart.c +++ b/src/soc/cavium/cn81xx/uart.c @@ -8,7 +8,7 @@ #include <console/uart.h> #include <delay.h> #include <endian.h> -#include <stdint.h> +#include <types.h> #include <soc/clock.h> #include <soc/uart.h> #include <assert.h> diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index fef98e3..82b0a9c 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -13,7 +13,7 @@ #include <soc/pcr_ids.h> #include <soc/pci_devs.h> #include <device/pci_ops.h> -#include <stdint.h> +#include <types.h> #define MKHI_GROUP_ID_MCA 0x0a diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index bada5fd..460cb07 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -8,7 +8,7 @@ #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> -#include <stdint.h> +#include <types.h> static uintptr_t dpr_region_start(void) { diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c index fb25472..6a19cb4 100644 --- a/src/soc/intel/cannonlake/elog.c +++ b/src/soc/intel/cannonlake/elog.c @@ -4,7 +4,7 @@ #include <cbmem.h> #include <console/console.h> #include <device/pci_ops.h> -#include <stdint.h> +#include <types.h> #include <elog.h> #include <intelblocks/pmclib.h> #include <intelblocks/xhci.h> diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h index 9b1690e..91e5d24 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h @@ -4,7 +4,6 @@ #define _SOC_CANNONLAKE_GPIO_DEFS_H_ #ifndef __ACPI__ -#include <stddef.h> #endif #include <soc/gpio_common.h> #include <soc/gpio_soc_defs.h> diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h index a1f51d1..0ecaeab 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h @@ -4,7 +4,6 @@ #define _SOC_CANNONLAKE_GPIO_DEFS_CNP_H_H_ #ifndef __ACPI__ -#include <stddef.h> #endif #include <soc/gpio_common.h> #include <soc/gpio_soc_defs_cnp_h.h> diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index dde06c0..33ed1ba 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -6,7 +6,7 @@ #include <acpi/acpi.h> #include <device/device.h> #include <intelblocks/cpulib.h> -#include <stdint.h> +#include <types.h> /* Forward declare the power state struct here */ struct chipset_power_state; diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h index 145857c..0556f63 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpss.h +++ b/src/soc/intel/common/block/include/intelblocks/lpss.h @@ -4,7 +4,7 @@ #define SOC_INTEL_COMMON_BLOCK_LPSS_H #include <device/device.h> -#include <stdint.h> +#include <types.h> /* D0 and D3 enable config */ enum lpss_pwr_state { diff --git a/src/soc/intel/common/block/include/intelblocks/pmc.h b/src/soc/intel/common/block/include/intelblocks/pmc.h index 75e2127..b0efe7b 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc.h @@ -4,7 +4,7 @@ #define SOC_INTEL_COMMON_BLOCK_PMC_H #include <device/device.h> -#include <stdint.h> +#include <types.h> /* PMC controller resource structure */ struct pmc_resource_config { diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index 2b06a50..a28b301 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -4,7 +4,7 @@ #define SOC_INTEL_COMMON_BLOCK_PMCLIB_H #include <device/pci_type.h> -#include <stdint.h> +#include <types.h> /* Forward declare the power state struct here */ struct chipset_power_state; diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index 87fdf68..3d041aa 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -6,7 +6,7 @@ #include <console/uart.h> #include <device/device.h> #include <intelblocks/gpio.h> -#include <stdint.h> +#include <types.h> #define MAX_GPIO_PAD_PER_UART 2 diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 12eb38e..4a293d9 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -13,7 +13,7 @@ #include <pc80/mc146818rtc.h> #include <security/vboot/vboot_common.h> #include <soc/pm.h> -#include <stdint.h> +#include <types.h> #include <string.h> #include <timer.h> diff --git a/src/soc/intel/common/mma.h b/src/soc/intel/common/mma.h index 2e01210..e8e7943 100644 --- a/src/soc/intel/common/mma.h +++ b/src/soc/intel/common/mma.h @@ -3,7 +3,7 @@ #ifndef _SOC_MMA_H_ #define _SOC_MMA_H_ -#include <stdint.h> +#include <types.h> #include <commonlib/region.h> struct mma_config_param { diff --git a/src/soc/intel/common/smbios.h b/src/soc/intel/common/smbios.h index c7da3b3..3ae4f1e 100644 --- a/src/soc/intel/common/smbios.h +++ b/src/soc/intel/common/smbios.h @@ -3,7 +3,7 @@ #ifndef _COMMON_SMBIOS_H_ #define _COMMON_SMBIOS_H_ -#include <stdint.h> +#include <types.h> #include <memory_info.h> /* Offset info DIMM_INFO SpdSave for start of serial number */ diff --git a/src/soc/intel/denverton_ns/gpio_dnv.c b/src/soc/intel/denverton_ns/gpio_dnv.c index 0999cce..0e7d4c9 100644 --- a/src/soc/intel/denverton_ns/gpio_dnv.c +++ b/src/soc/intel/denverton_ns/gpio_dnv.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <string.h> #include <device/mmio.h> #include <console/console.h> diff --git a/src/soc/intel/denverton_ns/soc_util.c b/src/soc/intel/denverton_ns/soc_util.c index d5b9b34..faa158b 100644 --- a/src/soc/intel/denverton_ns/soc_util.c +++ b/src/soc/intel/denverton_ns/soc_util.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <device/pci.h> diff --git a/src/soc/intel/icelake/include/soc/gpio_defs.h b/src/soc/intel/icelake/include/soc/gpio_defs.h index 31f83d6..16ab084 100644 --- a/src/soc/intel/icelake/include/soc/gpio_defs.h +++ b/src/soc/intel/icelake/include/soc/gpio_defs.h @@ -4,7 +4,6 @@ #define _SOC_ICELAKE_GPIO_DEFS_H_ #ifndef __ACPI__ -#include <stddef.h> #endif #include <soc/gpio_soc_defs.h> diff --git a/src/soc/intel/jasperlake/include/soc/gpio_defs.h b/src/soc/intel/jasperlake/include/soc/gpio_defs.h index 6e822c9..5a73ce9 100644 --- a/src/soc/intel/jasperlake/include/soc/gpio_defs.h +++ b/src/soc/intel/jasperlake/include/soc/gpio_defs.h @@ -4,7 +4,6 @@ #define _SOC_JASPERLAKE_GPIO_DEFS_H_ #ifndef __ACPI__ -#include <stddef.h> #endif #include <soc/gpio_soc_defs.h> diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 550ee41..8bc97b9 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -6,7 +6,7 @@ #include <console/console.h> #include <device/mmio.h> #include <device/pci_ops.h> -#include <stdint.h> +#include <types.h> #include <elog.h> #include <intelblocks/pmclib.h> #include <intelblocks/xhci.h> diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 2a5e788..2256256 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -3,7 +3,6 @@ #ifndef _SOC_GPIO_DEFS_H_ #define _SOC_GPIO_DEFS_H_ #ifndef __ACPI__ -#include <stddef.h> #endif #if CONFIG(SKYLAKE_SOC_PCH_H) # include <soc/gpio_pch_h_defs.h> diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_defs.h index dc1087c..81d0032 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_defs.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_defs.h @@ -4,7 +4,6 @@ #define _SOC_TIGERLAKE_GPIO_DEFS_H_ #ifndef __ACPI__ -#include <stddef.h> #endif #include <soc/gpio_soc_defs.h> diff --git a/src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h b/src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h index 93dcf20..91c95d4 100644 --- a/src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h +++ b/src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h @@ -4,7 +4,6 @@ #define LEWISBURG_GPIO_DEFS_H #ifndef __ACPI__ -#include <stddef.h> #endif /* GPIO Community 0 */ diff --git a/src/soc/mediatek/common/include/soc/gpio_common.h b/src/soc/mediatek/common/include/soc/gpio_common.h index 5348e05..68c9d3e 100644 --- a/src/soc/mediatek/common/include/soc/gpio_common.h +++ b/src/soc/mediatek/common/include/soc/gpio_common.h @@ -4,7 +4,6 @@ #define SOC_MEDIATEK_COMMON_GPIO_H #include <soc/gpio_base.h> -#include <stddef.h> #include <stdint.h> enum pull_enable { diff --git a/src/soc/mediatek/common/include/soc/usb_common.h b/src/soc/mediatek/common/include/soc/usb_common.h index 6fa050d..134b05e 100644 --- a/src/soc/mediatek/common/include/soc/usb_common.h +++ b/src/soc/mediatek/common/include/soc/usb_common.h @@ -3,7 +3,6 @@ #ifndef SOC_MEDIATEK_USB_COMMON_H #define SOC_MEDIATEK_USB_COMMON_H -#include <stddef.h> /* ip_pw_ctrl0 */ #define CTRL0_IP_SW_RST (0x1 << 0) diff --git a/src/soc/mediatek/mt8173/include/soc/addressmap.h b/src/soc/mediatek/mt8173/include/soc/addressmap.h index 4b2e150..16fa398 100644 --- a/src/soc/mediatek/mt8173/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8173/include/soc/addressmap.h @@ -3,7 +3,6 @@ #ifndef __SOC_MEDIATEK_MT8173_INCLUDE_SOC_ADDRESS_MAP_H__ #define __SOC_MEDIATEK_MT8173_INCLUDE_SOC_ADDRESS_MAP_H__ -#include <stddef.h> #include <stdint.h> enum { diff --git a/src/soc/mediatek/mt8173/include/soc/spm.h b/src/soc/mediatek/mt8173/include/soc/spm.h index 0d8e0d3..b66b798 100644 --- a/src/soc/mediatek/mt8173/include/soc/spm.h +++ b/src/soc/mediatek/mt8173/include/soc/spm.h @@ -4,7 +4,6 @@ #define __SOC_MEDIATEK_MT8173_SPM_H__ #include <soc/addressmap.h> -#include <stddef.h> enum { SPM_PROJECT_CODE = 0xb16 diff --git a/src/soc/nvidia/tegra124/include/soc/addressmap.h b/src/soc/nvidia/tegra124/include/soc/addressmap.h index bef4204..a54cee4 100644 --- a/src/soc/nvidia/tegra124/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra124/include/soc/addressmap.h @@ -3,7 +3,6 @@ #ifndef __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ #define __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ -#include <stddef.h> enum { TEGRA_SRAM_BASE = 0x40000000, diff --git a/src/soc/nvidia/tegra124/include/soc/emc.h b/src/soc/nvidia/tegra124/include/soc/emc.h index 2242f10..c3c91c0 100644 --- a/src/soc/nvidia/tegra124/include/soc/emc.h +++ b/src/soc/nvidia/tegra124/include/soc/emc.h @@ -3,7 +3,6 @@ #ifndef __SOC_NVIDIA_TEGRA124_EMC_H__ #define __SOC_NVIDIA_TEGRA124_EMC_H__ -#include <stddef.h> #include <stdint.h> enum { diff --git a/src/soc/nvidia/tegra124/include/soc/mc.h b/src/soc/nvidia/tegra124/include/soc/mc.h index b8c0a90..42dad67 100644 --- a/src/soc/nvidia/tegra124/include/soc/mc.h +++ b/src/soc/nvidia/tegra124/include/soc/mc.h @@ -3,7 +3,6 @@ #ifndef __SOC_NVIDIA_TEGRA124_MC_H__ #define __SOC_NVIDIA_TEGRA124_MC_H__ -#include <stddef.h> #include <stdint.h> // Memory Controller registers we need/care about diff --git a/src/soc/nvidia/tegra124/include/soc/sdram_param.h b/src/soc/nvidia/tegra124/include/soc/sdram_param.h index 45cd914..7acbd3c 100644 --- a/src/soc/nvidia/tegra124/include/soc/sdram_param.h +++ b/src/soc/nvidia/tegra124/include/soc/sdram_param.h @@ -10,7 +10,6 @@ #ifndef __SOC_NVIDIA_TEGRA124_SDRAM_PARAM_H__ #define __SOC_NVIDIA_TEGRA124_SDRAM_PARAM_H__ -#include <stddef.h> #include <stdint.h> enum { diff --git a/src/soc/nvidia/tegra124/include/soc/spi.h b/src/soc/nvidia/tegra124/include/soc/spi.h index 42214bc..a0846e1 100644 --- a/src/soc/nvidia/tegra124/include/soc/spi.h +++ b/src/soc/nvidia/tegra124/include/soc/spi.h @@ -5,7 +5,6 @@ #include <spi-generic.h> #include <soc/dma.h> -#include <stddef.h> struct tegra_spi_regs { u32 command1; /* 0x000: SPI_COMMAND1 */ diff --git a/src/soc/nvidia/tegra210/include/soc/clk_rst.h b/src/soc/nvidia/tegra210/include/soc/clk_rst.h index d4bddad..4d82466 100644 --- a/src/soc/nvidia/tegra210/include/soc/clk_rst.h +++ b/src/soc/nvidia/tegra210/include/soc/clk_rst.h @@ -3,7 +3,6 @@ #ifndef _TEGRA210_CLK_RST_H_ #define _TEGRA210_CLK_RST_H_ #include <stdint.h> -#include <stddef.h> /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ struct __packed clk_rst_ctlr { diff --git a/src/soc/nvidia/tegra210/include/soc/emc.h b/src/soc/nvidia/tegra210/include/soc/emc.h index 493f95f..0ebe97b 100644 --- a/src/soc/nvidia/tegra210/include/soc/emc.h +++ b/src/soc/nvidia/tegra210/include/soc/emc.h @@ -3,7 +3,6 @@ #ifndef __SOC_NVIDIA_TEGRA210_EMC_H__ #define __SOC_NVIDIA_TEGRA210_EMC_H__ -#include <stddef.h> #include <stdint.h> enum { diff --git a/src/soc/nvidia/tegra210/include/soc/funitcfg.h b/src/soc/nvidia/tegra210/include/soc/funitcfg.h index 493c9a0..404841c 100644 --- a/src/soc/nvidia/tegra210/include/soc/funitcfg.h +++ b/src/soc/nvidia/tegra210/include/soc/funitcfg.h @@ -6,7 +6,7 @@ #include <soc/clock.h> #include <soc/padconfig.h> #include <soc/pinmux.h> -#include <stdint.h> +#include <types.h> #define FUNIT_INDEX(_name) FUNIT_##_name diff --git a/src/soc/nvidia/tegra210/include/soc/mc.h b/src/soc/nvidia/tegra210/include/soc/mc.h index 0097575..54edcd6 100644 --- a/src/soc/nvidia/tegra210/include/soc/mc.h +++ b/src/soc/nvidia/tegra210/include/soc/mc.h @@ -3,7 +3,6 @@ #ifndef __SOC_NVIDIA_TEGRA210_MC_H__ #define __SOC_NVIDIA_TEGRA210_MC_H__ -#include <stddef.h> #include <stdint.h> // Memory Controller registers we need/care about diff --git a/src/soc/nvidia/tegra210/include/soc/padconfig.h b/src/soc/nvidia/tegra210/include/soc/padconfig.h index b6b0d75..020b42c 100644 --- a/src/soc/nvidia/tegra210/include/soc/padconfig.h +++ b/src/soc/nvidia/tegra210/include/soc/padconfig.h @@ -3,7 +3,7 @@ #ifndef __SOC_NVIDIA_TEGRA210_PAD_CFG_H #define __SOC_NVIDIA_TEGRA210_PAD_CFG_H -#include <stdint.h> +#include <types.h> #include <soc/pinmux.h> struct pad_config { diff --git a/src/soc/nvidia/tegra210/include/soc/sdram_param.h b/src/soc/nvidia/tegra210/include/soc/sdram_param.h index 7513302..d63dbc5 100644 --- a/src/soc/nvidia/tegra210/include/soc/sdram_param.h +++ b/src/soc/nvidia/tegra210/include/soc/sdram_param.h @@ -10,7 +10,6 @@ #ifndef __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ #define __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ -#include <stddef.h> #include <stdint.h> enum { diff --git a/src/soc/nvidia/tegra210/include/soc/spi.h b/src/soc/nvidia/tegra210/include/soc/spi.h index 53de7cf..598f364 100644 --- a/src/soc/nvidia/tegra210/include/soc/spi.h +++ b/src/soc/nvidia/tegra210/include/soc/spi.h @@ -5,7 +5,6 @@ #include <soc/dma.h> #include <spi-generic.h> -#include <stddef.h> struct tegra_spi_regs { u32 command1; /* 0x000: SPI_COMMAND1 */ diff --git a/src/soc/rockchip/common/include/soc/spi.h b/src/soc/rockchip/common/include/soc/spi.h index 0184fef..675ee8f 100644 --- a/src/soc/rockchip/common/include/soc/spi.h +++ b/src/soc/rockchip/common/include/soc/spi.h @@ -5,7 +5,6 @@ /* This driver serves as a CBFS media source. */ #include <spi-generic.h> -#include <stddef.h> struct rockchip_spi { u32 ctrlr0; diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index 9b21532..972ebb1 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -4,7 +4,7 @@ #include <console/console.h> #include <soc/clock.h> #include <soc/addressmap.h> -#include <stdint.h> +#include <types.h> // 33.33 Mhz after reset #define FU540_BASE_FQY 33330 diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index cce11dc..a61404a 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <types.h> #include <device/mmio.h> #include <console/console.h> #include <spi_flash.h> diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 380940c..3e0bd9c 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -4,7 +4,7 @@ /* This file is derived from the flashrom project. */ -#include <stdint.h> +#include <types.h> #include <string.h> #include <bootstate.h> #include <commonlib/helpers.h> diff --git a/src/superio/smsc/sch5545/sch5545_emi.h b/src/superio/smsc/sch5545/sch5545_emi.h index 2bf3a76..2d39982 100644 --- a/src/superio/smsc/sch5545/sch5545_emi.h +++ b/src/superio/smsc/sch5545/sch5545_emi.h @@ -4,7 +4,7 @@ #define SUPERIO_SCH_5545_EMI_H #include <stdlib.h> -#include <stdint.h> +#include <types.h> /* Embedded Memory Interface registers */ #define SCH5545_EMI_HOST_TO_EC_MAILBOX 0x0 -- To view, visit https://review.coreboot.org/c/coreboot/+/42008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82993b6955b615fdbe019ee4c470e19cbdb72943 Gerrit-Change-Number: 42008 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: fw_config: Add firmware configuration interface
by Duncan Laurie (Code Review) 02 Jun '20

02 Jun '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41209 ) Change subject: fw_config: Add firmware configuration interface ...................................................................... fw_config: Add firmware configuration interface This change introduces a new top-level interface for interacting with a bitmask providing firmware configuration information. This is motivated by Chromebook mainboards that need to support multiple different configurations at runtime with the same BIOS. In these devices the Embedded Controller provides a bitmask that can be broken down into different fields and each field can be broken down into different options. The firmware configuration interface is intended to be easily adapted by device drivers and mainboards and lead to less code duplication for new mainboards that make use of this feature by providing common functions and integration into devicetree.cb. BUG=b:147462631 TEST=this provides a new interface that is tested in subsequent commits Change-Id: I1e889c235a81545e2ec0e3a34dfa750ac828a330 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- A Documentation/lib/fw_config.md M Documentation/lib/index.md A src/include/fw_config.h M src/lib/Kconfig M src/lib/Makefile.inc A src/lib/fw_config.c 6 files changed, 742 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/41209/1 diff --git a/Documentation/lib/fw_config.md b/Documentation/lib/fw_config.md new file mode 100644 index 0000000..6f769d6 --- /dev/null +++ b/Documentation/lib/fw_config.md @@ -0,0 +1,406 @@ +# Firmware Configuration Interface in coreboot + +## Motivation + +The firmware configuration interface in coreboot is designed to support a wide variety of +configuration options in that are dictated by the hardware at runtime. This allows a single +BIOS image to be used across a wide variety of devices which may have key differences but are +otherwise similar enough to be a variant of the same baseboard. + +The initial implementation is designed to take advantage of a bitmask returned by the Embedded +Controller on Google Chrome OS devices which allows the manufacturer to use the same firmware +image across multiple devices by selecting various options at runtime. A different +implementation could use a file in CBFS or a hard coded value in Kconfig for different images +to make the selected configuration options static. + +This firmware configuration interface differs from the CMOS option interface in that this +bitmask value is not intended as a user-configurable setting as the configuration values must +match the actual hardware. In the case where a user was to swap their hardware this value +would need to be updated or overridden. + +## Device Presence + +One common example of why a firmware configuration interface is important is determining if a +device is present in the system. With some bus topologies and hardware mechanisms it is +possible to probe and enumerate this at runtime: + +- PCI is a self-discoverable bus and is very easy to handle. +- I2C devices can often be probed with a combination of bus and address. +- The use of GPIOs with external strap to ground or different voltages can be used to detect +presence of a device. + +However there are several cases where this is insufficient: + +- I2C peripherals that require different drivers but have the same bus address cannot be +uniquely identified at runtime. +- A mainboard may be designed with multiple daughter board combinations which contain devices +and configurations that cannot be detected. +- While presence detect GPIOs are a convenient way for a single device presence, they are +unable to distinguish between different devices so it can require a large number of GPIOs to +support relatively few options. + +This presence detection can impact different stages of boot: + +### ACPI + +Devices that are not present should not provide an ACPI device indicating that they are +present or the operating system may not be able to handle it correctly. + +The ACPI devices are largely driven by chips defined in the mainboard `devicetree.cb` and +the variant overridetree.cb. This means it is important to be able to specify when a device +is present or not directly in `devicetree.cb` itself. Otherwise each mainboard needs custom +code to parse the tree and disable unused devices. + +### GPIO + +GPIOs with multiple functions may need to be configured correctly depending on the attached +device. Given the wide variety of GPIO configuration possibilities it is not feasible to +specify all combinations directly in `devicetree.cb` and it is best left to code provided by +the mainboard. + +### FSP UPD + +Enabling and disabling devices may require altering FSP UPD values that are provided to the +various stages of FSP. These options are also not easy to specify multiple times for +different configurations in `devicetree.cb` and can be provided by the mainboard as code. + +## Firmware Configuration Interface + +The firmware configuration interface consists of two inputs: + +1. The table of fields and options that represent the board-specific bitmask. +2. The bitmask of selected options for a particular hardware combination. + +Both of these are provided by the mainboard itself because it is the source of truth for the +possible combinations of SoC and devices. + +### Mainboard Table + +To use the firmware configuration interface the mainboard provides a table defining the fields +within the bitmask and what each of the various options are within each field. + +The list of fields is terminated by an empty field where `field.name == NULL`. + +### Field List + +The table provides a `struct fw_config_field` for each field within the bitmask and contains +the name of that field as well as the starting offset and the mask of bits to be included. + +Each field also contains a list of `struct fw_config_option` which is terminated by an empty +entry where `option.name == NULL`. + +```c +/** + * struct fw_config_field - Descriptor for field within firmware configuration bitmask. + * @name: Name of this field. + * @mask: Mask value that indicates which bits are in this field. + * @shift: Offset within the 32-bit value where this field starts. + * @option: List of field options. + */ +struct fw_config_field { + const char *name; + uint32_t mask; + size_t shift; + struct fw_config_option option[FW_CONFIG_OPTION_MAX]; +}; +``` + +### Option List + +Each field can contain multiple `struct fw_config_option` definitions, and one should be +provided for each possible field option. Options must be unique and there is no provision in +this design for multiple options that have the same value or name. + +Each field option in the list consists of a name and the expected field value, as well as a +callback function. This callback will be executed at boot if the option matches the value of +the field returned by the mainboard. + +```c +/** + * struct fw_config_option - Descriptor for option within a field. + * @name: Name of this field option. + * @value: Value of this option. + * @callback: Function callback for when this option is selected. + */ +struct fw_config_option { + const char *name; + uint32_t value; + fw_config_option_cb *callback; +}; +``` + +Helper macros are provided which make it easier to write the firmware configuration table and +allow the fields to be specified on one line. + + FW_CONFIG_FIELD(name, mask, shift) + FW_CONFIG_OPTION(name, value) + FW_CONFIG_OPTION_CB(name, value, callback) + +### Probe List + +The probe list provides a set of field and option names to match against the mainboard table +and value. Each entry specifies the name of the field within the firmware configuration +bitmask and the name of the option within that field that should be checked. + +This list allows for a driver probe to check for multiple matches, either multiple options +from the same field or from different fields. + +An array of these structures is typically provided in a driver chip configuration structure +and filled out by the mainboard in `devicetree.cb`. + +```c +/** + * struct fw_config_probe - Descriptor for a firmware configuration probe match. + * @field: Name of the field to match. + * @option: Name of the option within the field to match. + */ +struct fw_config_probe { + const char *field; + const char *option; +}; +``` + +A helper macro is provided to make it easier to add matches for driver probing. Note that +with this macro the name strings should not be enclosed in quotes, in order to allow this to +be easily used in `devicetree.cb`: + + FW_CONFIG_MATCH(field_name, option_name) + +### Interface Library + +In addition to the structures there are some defined library functions that are intended for +use by drivers and mainboards. + +#### Match Field and Option + +This function searches the mainboard table for a matching field and option name. It takes +a single field and option name to search for and returns a boolean value that indicates +whether the field and option was found in the table. + +This is intended for mainboards that may need to to additional processing outside of the +automated probing and callback interface. For example during romstage it may be necessary +to check if a given field and option is enabled and adjust a parameter to FSP-M. + +```c +/** + * fw_config_match() - Check provided field and option name against mainboard table. + * @field_name: Name of the field that this option belongs to. + * @option_name: Name of the option within the field to find. + * + * Return %true if option is a match, %false if option does not match. + */ +bool fw_config_match(const char *field_name, const char *option_name); +``` + +#### Probe Device + +This interface is used by device drivers to probe a list of field and option names where any +match in the list is considered a successful probe. A device declared in `devicetree.cb` may +be considered present by more than one option, and any entry in the list is considered a +positive match. + +```c +/** + * fw_config_probe() - Check each field and option against match_list. + * @match_list: List of fw_config field and option names to check. + * + * Return %true if match is found, %false if match is not found. + */ +bool fw_config_probe(const struct fw_config_probe *match_list); +``` + +## Mainboard Integration + +There are several requirements that the mainboard is expected to provide for the firmware +configuration interface. + +### Configuration Table + +The mainboard must provide a function that returns the table of fields and options as well as +the current firmware configuration value. + +The table itself can be declared as a static structure in the mainboard code. Here we show a +boolean 1-bit field for `FEATURE` which is at bit offset 0 and can be set to either `ENABLE` +or `DISABLE`. + +```c +static const struct fw_config_field mainboard_fw_config[] = { + { + FW_CONFIG_FIELD("FEATURE", 0x1, 0), + .option = { + FW_CONFIG_OPTION("DISABLE", 0), + FW_CONFIG_OPTION("ENABLE", 1), + } + }, + { } +}; +``` + +### Configuration Value + +The actual selection of firmware configuration options is done based on a 32-bit mask that +is provided by the mainboard. This value can be read from a variety of different sources: + +- Chrome OS boards typically retrieve the firmware configuration value from the Embedded +Controller via a mailbox function. +- The value could be hard coded in Kconfig or in the source directly. +- The value could be provided in CBFS and added to the image after building. +- The value could be stored directly in flash or CMOS. + +In this example the value is read from the Chrome OS Embedded Controller and provided together +with the pointer to the mainboard firmware configuration table. + +```c +size_t mainboard_get_fw_config(const struct fw_config_field **table, uint32_t *config) +{ + if (google_chromeec_cbi_get_fw_config(config) < 0) { + printk(BIOS_ERR, "Could not get fw_config from EC\n"); + return 0; + } + + *table = mainboard_fw_config; + return ARRAY_SIZE(mainboard_fw_config); +} +``` + +### Option Callbacks + +The table of fields and values can optionally contain a callback function for each defined +option. This allows the mainboard to do special configuration to support the particular +selected option. + +During boot the table of fields is compared against the mainboard provided bitmask and +callbacks will be executed for the option that matches within each field. This happens before +the device driver enable stage to allow the mainboard to alter the device tree if needed. + +Continuing with the previous example if the value returned by the mainboard at boot has +`bit 0 == 0` then the `FEATURE` field option will be set to `DISABLE` and the provided callback +`feature_disable_cb()` will be executed. If the field value is 1 then the field option will +be set to `ENABLE` and the provided callback `feature_enable_cb()` will be executed. + +```c +static void feature_disable_cb(const struct fw_config_option *option) +{ + const struct pad_config disable_pads[] = { + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + }; + gpio_configure_pads(disable_pads, ARRAY_SIZE(disable_pads)); +} + +static void feature_enable_cb(const struct fw_config_option *option) +{ + const struct pad_config enable_pads[] = { + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + }; + gpio_configure_pads(enable_pads, ARRAY_SIZE(enable_pads)); +} + +static const struct fw_config_field mainboard_fw_config[] = { + { + FW_CONFIG_FIELD("FEATURE", 0x1, 0), + .option = { + FW_CONFIG_OPTION_CB("DISABLE", 0, feature_disable_cb), + FW_CONFIG_OPTION_CB("ENABLE", 1, feature_enable_cb), + } + }, + { } +}; +``` + +### Device Driver Probing + +When a device driver supports the firmware configuration interface the probe matches can be +specified directly in `devicetree.cb` together with the driver. This relies on an array of +`struct fw_config_probe` to allow multiple matches to be specified. This is a convenient +way to disable drivers for hardware that does not exist in the system, preventing the system +from allocating resources or generating ACPI code for that device. + +This `devicetree.cb` example is based on the table provided in previous examples. If the +`FEATURE` field is set to `ENABLE` then this match will be true and the device will be +considered present. If the field was set to `DISABLE` then the device would be disabled in +the driver by clearing the `enabled` flag in the device structure, and it would not execute +any callback. + +``` +device pci 15.0 on + chip drivers/i2c/generic + register "desc" = ""Example Probed Device"" + register "fw_config_probe" = "true" + register "fw_config" = "{ FW_CONFIG_MATCH(FEATURE, ENABLE) }" + device i2c ff on end + end +end +``` + +## Driver Integration + +Driver support for firmware configuration needs only a few changes: + +1) Add an array of `struct fw_config_probe` to the chip configuration in `chip.h`, along with +an enable flag to make it clear that this probing is expected. +2) Call `fw_config_probe()` from the drivers `chip.enable_dev()` function and supply the list +of matches to check from `devicetree.cb` as an argument. +3) Disable the device if the probe returns false. + +### Example: Driver Chip Configuration + +```c +struct drivers_example_config { + bool fw_config_probe; + struct fw_config_probe fw_config[FW_CONFIG_PROBE_MAX]; +}; +``` + +### Example: Driver Enable Function + +```c +static void drivers_example_enable(struct device *dev) +{ + struct drivers_example_config *config = dev->chip_info; + + if (config->fw_config_probe && !fw_config_probe(config->fw_config)) + dev->enabled = 0; +} +struct chip_operations drivers_example_ops = { + CHIP_NAME("Example Driver") + .enable_dev = drivers_example_enable +}; +``` + +## Other Uses + +The device driver probing and callback interface allow for seamless integration with the +mainboard, but both are designed for ramstage and there are other situations where code may +need to probe or check the value of a field in romstage or other points in ramstage. For +this reason it is also possible to use the firmware configuration interface directly. + +This example has a mainboard check if a feature is disabled and set an FSP UPD before memory +training. This example expects that the default value of this option is set to `true` in +`devicetree.cb` and this code is disabling that feature before FSP is executed. + +```c +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + if (fw_config_match("FEATURE", "DISABLE")) + mupd->ExampleFeature = false; +} +``` + +### Modifying the Firmware Configuration + +The actual implementation of retrieving the firmware configuration value is left up to the +individual mainboard. If the value comes from Kconfig it is easy to adjust in the local +config file. If it comes from CBFS it could be updated after building the image. + +Google Chrome OS devices support an Embedded Controller interface for reading and writing the +firmware configuration value, along with other board-specific information. It is not typically +necessary to adjust this value, but it is possible *(after disabling write protection)* by using +the `ectool` command in a Chrome OS environment. + +For more information on the firmware configuration field on Chrome OS devices see the Chromium +documentation for [Firmware Config][1] and [Board Info][2]. + +[1]: http://chromium.googlesource.com/chromiumos/docs/+/master/design_docs/firmw… +[2]: http://chromium.googlesource.com/chromiumos/docs/+/master/design_docs/cros_… diff --git a/Documentation/lib/index.md b/Documentation/lib/index.md index 99b8061..d64b4e9 100644 --- a/Documentation/lib/index.md +++ b/Documentation/lib/index.md @@ -3,7 +3,7 @@ This section contains documentation about coreboot internal technical information and libraries. -## Structure and layout - [Flashmap and Flashmap Descriptor](flashmap.md) - [ABI data consumption](abi-data-consumption.md) - [Timestamps](timestamp.md) +- [Firmware Configuration Interface](fw_config.md) diff --git a/src/include/fw_config.h b/src/include/fw_config.h new file mode 100644 index 0000000..a2780e5 --- /dev/null +++ b/src/include/fw_config.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __FW_CONFIG__ +#define __FW_CONFIG__ + +#include <stdint.h> +#include <types.h> + +/** + * enum fw_config_max - Limits on firmware configuration structures. + * @FW_CONFIG_PROBE_MAX: Default limit of probe entries for a driver. + * @FW_CONFIG_OPTION_MAX: Limit on the number of options within a field. + */ +enum fw_config_max { + FW_CONFIG_PROBE_MAX = 8, + FW_CONFIG_OPTION_MAX = 32 +}; + +/** + * fw_config_option_cb() - Callback for option to do extra work. + * @option: Option that was discovered. + */ +struct fw_config_option; +typedef void fw_config_option_cb(const struct fw_config_option *option); + +/** + * struct fw_config_option - Descriptor for option within a field. + * @name: Name of this field option. + * @value: Value of this option. + * @callback: Function callback for when this option is selected. + */ +struct fw_config_option { + const char *name; + uint32_t value; + fw_config_option_cb *callback; +}; + +/** + * struct fw_config_field - Descriptor for field within firmware configuration bitmask. + * @name: Name of this field. + * @mask: Mask value that indicates which bits are in this field. + * @shift: Offset within the 32-bit value where this field starts. + * @option: List of field options. + */ +struct fw_config_field { + const char *name; + uint32_t mask; + size_t shift; + struct fw_config_option option[FW_CONFIG_OPTION_MAX]; +}; + +/** + * struct fw_config_probe - Descriptor for a firmware configuration probe match. + * @field: Name of the field to match. + * @option: Name of the option within the field to match. + */ +struct fw_config_probe { + const char *field; + const char *option; +}; + +/** + * FW_CONFIG_FIELD() - Helper macro for defining a field. + * @__name: Name of this field. + * @__mask: Bitmask for extracting this field. + * @__shift: Bit offset where this field starts. + */ +#define FW_CONFIG_FIELD(__name, __mask, __shift) \ + .name = (__name), \ + .mask = (__mask), \ + .shift = (__shift) + +/** + * FW_CONFIG_OPTION_CB() - Helper macro for defining a field option with a callback. + * @__name; Name of the field option. + * @__value: Value for this option after field shift and mask are applied. + * @__callback: Function to be called if the field is set to this option. + */ +#define FW_CONFIG_OPTION_CB(__name, __value, __callback) { \ + .name = (__name), \ + .value = (__value), \ + .callback = (__callback) \ +} + +/** + * FW_CONFIG_OPTION() - Helper macro for defining a field option without a callback. + * @__name; Name of the field option. + * @__value: Value for this option after field shift and mask are applied. + */ +#define FW_CONFIG_OPTION(__name, __value) FW_CONFIG_OPTION_CB(__name, __value, NULL) + +/** + * FW_CONFIG_MATCH() - Helper macro for defining a field and option to match against. + * @__field: Name of the field to match. + * @__option: Name of the field option to match. + */ +#define FW_CONFIG_MATCH(__field, __option) { \ + .field = #__field, \ + .option = #__option, \ +} + +/** + * mainboard_get_fw_config() - Get table of fields and config value from mainboard. + * This is defined as a weak function in lib/fw_config.c + * and can be overridden by the mainboard. + * @table: Pointer to list of fields that is provided by the mainboard. The list is + * terminated by an empty entry where the field name is NULL. + * @config: Pointer to 32-bit integer of mainboard firmware configuration value. + * + * Return number of entries in mainboard_table, zero if table is not found. + */ +size_t mainboard_get_fw_config(const struct fw_config_field **table, uint32_t *config); + +#if CONFIG(FW_CONFIG) + +/** + * fw_config_match() - Check provided field and option name against mainboard table. + * @field_name: Name of the field that this option belongs to. + * @option_name: Name of the option within the field to find. + * + * Return %true if option is a match, %false if option does not match. + */ +bool fw_config_match(const char *field_name, const char *option_name); + +/** + * fw_config_probe() - Check each field and option against match_list. + * @match_list: List of fw_config field and option names to check. + * + * Return %true if match is found, %false if match is not found. + */ +bool fw_config_probe(const struct fw_config_probe *match_list); + +#else /* CONFIG(FW_CONFIG) */ + +static inline bool fw_config_match(const char *field_name, const char *option_name) +{ + /* Always return true when probing with disabled fw_config. */ + return true; +} +static inline bool fw_config_probe(const struct fw_config_probe *match_list) +{ + /* Always return true when probing with disabled fw_config. */ + return true; +} + +#endif /* CONFIG(FW_CONFIG) */ + +#endif /* __FW_CONFIG__ */ diff --git a/src/lib/Kconfig b/src/lib/Kconfig index dd9974a..78a1eb8 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -75,3 +75,11 @@ If your platform really doesn't want to use an FMAP cache (e.g. due to space constraints), you can select this to disable warnings and save a bit more code. + +config FW_CONFIG + bool + default n + help + Enable support for probing devices with fw_config. This is a simple + bitmask broken into fields and options which can be provided by an + Embedded Controller or CBFS. diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index c03aea1..126ad0d 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -67,6 +67,7 @@ $(eval rmodules_$(arch)-y += rmodule.ld)) romstage-y += fmap.c +romstage-$(CONFIG_FW_CONFIG) += fw_config.c romstage-y += delay.c romstage-y += cbfs.c romstage-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c lzmadecode.c @@ -106,6 +107,7 @@ ramstage-y += coreboot_table.c ramstage-y += bootmem.c ramstage-y += fmap.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += memchr.c ramstage-y += memcmp.c ramstage-y += malloc.c diff --git a/src/lib/fw_config.c b/src/lib/fw_config.c new file mode 100644 index 0000000..4364728 --- /dev/null +++ b/src/lib/fw_config.c @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <bootstate.h> +#include <commonlib/helpers.h> +#include <console/console.h> +#include <fw_config.h> +#include <stdint.h> +#include <string.h> +#include <types.h> + +MAYBE_STATIC_BSS const struct fw_config_field *mainboard_table; +MAYBE_STATIC_BSS uint32_t mainboard_config; + +__weak size_t mainboard_get_fw_config(const struct fw_config_field **table, uint32_t *config) +{ + return 0; +} + +/** + * fw_config_prepare() - Check and set up mainboard table and config value. + * + * Return %false if mainboard does not provide table, otherwise %true. + */ +static bool fw_config_prepare(void) +{ + if (!mainboard_table) { + /* Get mainboard table and config value. */ + if (!mainboard_get_fw_config(&mainboard_table, &mainboard_config)) { + printk(BIOS_WARNING, + "%s: Mainboard did not provide firmware configuration table.\n", + __func__); + return false; + } + } + return true; +} + +/** + * fw_config_check_option() - Check this option against the mainboard config. + * @field: Field that this option belongs to. + * @option: Option that should be checked. + * + * Return %true if option matches, %false if it does not. + */ +static inline bool fw_config_check_option(const struct fw_config_field *field, + const struct fw_config_option *option) +{ + return option->value == ((mainboard_config >> field->shift) & field->mask); +} + +/** + * fw_config_find_option() - Find matching option in the provided field. + * @field: The field to search. + * @option_name: The name of the option to look for. + * + * Return pointer to option that is found, NULL if no match is found. + */ +static const struct fw_config_option * +fw_config_find_option(const struct fw_config_field *field, const char *option_name) +{ + size_t entry; + + for (entry = 0; entry < FW_CONFIG_OPTION_MAX; entry++) { + const struct fw_config_option *option = &field->option[entry]; + + /* Stop at the first undefined option in the list. */ + if (!option || !option->name) + break; + + /* Check this option name to see if it matches. */ + if (strncmp(option->name, option_name, strlen(option->name)) == 0) + return option; + } + return NULL; +} + +/** + * fw_config_find_field() - Find matching field in the mainboard table. + * @field_name: The name of the field to look for. + * + * Return pointer to field that is found, NULL if no match is found or no table is defined. + */ +static const struct fw_config_field *fw_config_find_field(const char *field_name) +{ + const struct fw_config_field *field; + + if (!fw_config_prepare()) + return NULL; + + /* Look for matching field name first. */ + for (field = mainboard_table; field && field->name; field++) { + if (strncmp(field->name, field_name, strlen(field->name)) == 0) + return field; + } + return NULL; +} + +bool fw_config_match(const char *field_name, const char *option_name) +{ + const struct fw_config_field *field; + const struct fw_config_option *option; + + /* Always return true when probing with missing fw_config. */ + if (!fw_config_prepare()) + return true; + + /* Find the field that matches probed field name. */ + field = fw_config_find_field(field_name); + if (!field) + return false; + + /* Find the option in this field that matches probed option name. */ + option = fw_config_find_option(field, option_name); + if (option && fw_config_check_option(field, option)) { + printk(BIOS_INFO, "%s: match found for %s:%s\n", __func__, + field_name, option_name); + return true; + } + + return false; +} + +bool fw_config_probe(const struct fw_config_probe *match_list) +{ + size_t entry; + + /* Always return true when probing with missing fw_config. */ + if (!fw_config_prepare()) + return true; + + /* Check each entry in the probe list provided by the caller. */ + for (entry = 0; entry < FW_CONFIG_PROBE_MAX; entry++) { + const struct fw_config_probe *match = &match_list[entry]; + + /* Stop at the first undefined match in the list. */ + if (!match || !match->option) + break; + + /* Check for a match with this option. */ + if (fw_config_match(match->field, match->option)) + return true; + } + + return false; +} + +/** + * fw_config_run_callbacks() - Find matching options and execute provided callbacks. + * Callbacks are executed before device enable functions are called. + */ +static void fw_config_run_callbacks(void *unused) +{ + const struct fw_config_field *field; + + if (!fw_config_prepare()) + return; + + /* Go through each field and find which option is selected. */ + for (field = mainboard_table; field && field->name; field++) { + size_t entry; + + for (entry = 0; entry < FW_CONFIG_OPTION_MAX; entry++) { + const struct fw_config_option *option = &field->option[entry]; + + /* Stop at the first undefined option in the list. */ + if (!option || !option->name) + break; + + /* Call provided callback if option is selected. */ + if (option->callback && fw_config_check_option(field, option)) + option->callback(option); + } + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_run_callbacks, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/41209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e889c235a81545e2ec0e3a34dfa750ac828a330 Gerrit-Change-Number: 41209 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

8 48

Change in coreboot[master]: cpu/x86/mtrr: add x86_setup_mtrrs_with_detect_no_above_4gb()
by Aaron Durbin (Code Review) 02 Jun '20

02 Jun '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41897 ) Change subject: cpu/x86/mtrr: add x86_setup_mtrrs_with_detect_no_above_4gb() ...................................................................... cpu/x86/mtrr: add x86_setup_mtrrs_with_detect_no_above_4gb() There's not a function that is the equivalent to x86_setup_mtrrs_with_detect() but not solving for above 4GiB. Provide x86_setup_mtrrs_with_detect_no_above_4gb() which is the equivalent to x86_setup_mtrrs_with_detect() but instructs the MTRR solver to not take into account memory above 4GiB. BUG=b:155426691 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Ia1b5d67d6f139aaa929e03ddbc394d57dfb949e0 --- M src/cpu/x86/mtrr/mtrr.c M src/include/cpu/x86/mtrr.h 2 files changed, 16 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/41897/1 diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 6187578..f74cef3 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -775,7 +775,7 @@ commit_var_mtrrs(sol); } -void x86_setup_mtrrs(void) +static void _x86_setup_mtrrs(unsigned int above4gb) { int address_size; @@ -783,14 +783,26 @@ address_size = cpu_phys_address_size(); printk(BIOS_DEBUG, "CPU physical address size: %d bits\n", address_size); + x86_setup_var_mtrrs(address_size, above4gb); +} + +void x86_setup_mtrrs(void) +{ /* Always handle addresses above 4GiB. */ - x86_setup_var_mtrrs(address_size, 1); + _x86_setup_mtrrs(1); } void x86_setup_mtrrs_with_detect(void) { detect_var_mtrrs(); - x86_setup_mtrrs(); + /* Always handle addresses above 4GiB. */ + _x86_setup_mtrrs(1); +} + +void x86_setup_mtrrs_with_detect_no_above_4gb(void) +{ + detect_var_mtrrs(); + _x86_setup_mtrrs(0); } void x86_mtrr_check(void) diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 552941e..2d758d2 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -78,6 +78,7 @@ * it always dynamically detects the number of variable MTRRs available. */ void x86_setup_mtrrs_with_detect(void); +void x86_setup_mtrrs_with_detect_no_above_4gb(void); /* * x86_setup_var_mtrrs() parameters: * address_bits - number of physical address bits supported by cpu -- To view, visit https://review.coreboot.org/c/coreboot/+/41897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1b5d67d6f139aaa929e03ddbc394d57dfb949e0 Gerrit-Change-Number: 41897 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: drivers/intel/gma: drop gma_set_gnvs_aslb()
by Matt DeVillier (Code Review) 02 Jun '20

02 Jun '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40712 ) Change subject: drivers/intel/gma: drop gma_set_gnvs_aslb() ...................................................................... drivers/intel/gma: drop gma_set_gnvs_aslb() At one point this was called in opregion.c, but now only exists as duplicated code in several platforms/SoCs that for most turns a single line of code into a 4-line function, and for others is simply unused. Drop it and clean up the mess. Change-Id: Ida23ca5ecf1821e019ed850d1eec2a858bd2e50f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/drivers/intel/gma/opregion.h M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/ironlake/gma.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/x4x/gma.c M src/soc/intel/baytrail/gfx.c M src/soc/intel/braswell/gfx.c M src/soc/intel/broadwell/igd.c M src/soc/intel/skylake/graphics.c 12 files changed, 9 insertions(+), 87 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/40712/1 diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h index 4967691..d49424d 100644 --- a/src/drivers/intel/gma/opregion.h +++ b/src/drivers/intel/gma/opregion.h @@ -246,7 +246,6 @@ void intel_gma_opregion_register(uintptr_t opregion); void intel_gma_restore_opregion(void); uintptr_t gma_get_gnvs_aslb(const void *gnvs); -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb); enum cb_err intel_gma_init_igd_opregion(igd_opregion_t *opregion); /* diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 25f7518..4a6ea63 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -38,13 +38,6 @@ return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); } -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static u32 get_cdclk(struct device *const dev) { const u16 cdclk_sel = @@ -232,7 +225,7 @@ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (gnvs) { /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); + gnvs->aslb = (uintptr_t)opregion); } else { printk(BIOS_ERR, "Error: GNVS table not found.\n"); } diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index c6b8fab..f325109 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -216,13 +216,6 @@ return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); } -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void power_well_enable(void) { gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE); @@ -535,7 +528,7 @@ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (gnvs) { /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); + gnvs->aslb = (uintptr_t)opregion); } else { printk(BIOS_ERR, "Error: GNVS table not found.\n"); } diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 8a19b3e..c9105a1 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -50,13 +50,6 @@ return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); } -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static int gtt_setup(u8 *mmiobase) { unsigned long PGETBL_save; @@ -781,7 +774,7 @@ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (gnvs) { /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); + gnvs->aslb = (uintptr_t)opregion); } else { printk(BIOS_ERR, "Error: GNVS table not found.\n"); } diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index c8bbbfd..f2680a5 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -71,13 +71,6 @@ return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); } -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void gma_pm_init_post_vbios(struct device *dev) { struct northbridge_intel_ironlake_config *conf = dev->chip_info; @@ -227,7 +220,7 @@ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (gnvs) { /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); + gnvs->aslb = (uintptr_t)opregion); } else { printk(BIOS_ERR, "Error: GNVS table not found.\n"); } diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index d398b55..5e541c0 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -49,13 +49,6 @@ return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); } -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static int gtt_setup(u8 *mmiobase) { u32 gttbase; @@ -293,7 +286,7 @@ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (gnvs) { /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); + gnvs->aslb = (uintptr_t)opregion); } else { printk(BIOS_ERR, "Error: GNVS table not found.\n"); } diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 5c4f548..aafb193 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -309,13 +309,6 @@ return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); } -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void gma_pm_init_pre_vbios(struct device *dev) { u32 reg32; @@ -662,7 +655,7 @@ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (gnvs) { /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); + gnvs->aslb = (uintptr_t)opregion); } else { printk(BIOS_ERR, "Error: GNVS table not found.\n"); } diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index f5335ec..6496e0e 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -34,13 +34,6 @@ return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); } -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void gma_func0_init(struct device *dev) { u32 reg32; @@ -104,7 +97,7 @@ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (gnvs) { /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); + gnvs->aslb = (uintptr_t)opregion); } else { printk(BIOS_ERR, "Error: GNVS table not found.\n"); } diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 64c9061..e0f25bf 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -359,13 +359,6 @@ return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); } -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void gfx_init(struct device *dev) { /* Pre VBIOS Init */ @@ -410,7 +403,7 @@ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (gnvs) { /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); + gnvs->aslb = (uintptr_t)opregion); } else { printk(BIOS_ERR, "Error: GNVS table not found.\n"); } diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index d6671f6..046dad2 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -70,13 +70,6 @@ return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); } -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void gma_generate_ssdt(struct device *dev) { const struct soc_intel_braswell_config *chip = dev->chip_info; diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index dbb4205..b0ee605 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -498,13 +498,6 @@ return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); } -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void igd_init(struct device *dev) { int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT); @@ -607,7 +600,7 @@ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (gnvs) { /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); + gnvs->aslb = (uintptr_t)opregion); } else { printk(BIOS_ERR, "Error: GNVS table not found.\n"); } diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index c338a67..b7db45c 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -134,13 +134,6 @@ return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); } -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - /* Initialize IGD OpRegion, called from ACPI code */ static void update_igd_opregion(igd_opregion_t *opregion) { -- To view, visit https://review.coreboot.org/c/coreboot/+/40712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida23ca5ecf1821e019ed850d1eec2a858bd2e50f Gerrit-Change-Number: 40712 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/intel/apollolake: Save/restore GMA OpRegion address
by Matt DeVillier (Code Review) 02 Jun '20

02 Jun '20

Matt DeVillier has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/25416 ) Change subject: soc/intel/apollolake: Save/restore GMA OpRegion address ...................................................................... Abandoned superseded by approach in CB:40725 -- To view, visit https://review.coreboot.org/c/coreboot/+/25416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4123998b0ab3c263c6a9ff14084a0d8808e5f4cd Gerrit-Change-Number: 25416 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: soc/intel/apollolake: Save/restore GMA OpRegion address
by Matt DeVillier (Code Review) 02 Jun '20

02 Jun '20

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25416 ) Change subject: soc/intel/apollolake: Save/restore GMA OpRegion address ...................................................................... Patch Set 5: > Patch Set 5: > > CB:40724 has been merged. What needs to happen to this patch train? this specific patch is superseded by the (merged) change in CB:40725 so I'll abandon it. CB:40593 and CB:40594 need some adjustment to work under Linux, right now they just provide enough of an interface for Windows to make use of the vendor/driver backlight controls -- To view, visit https://review.coreboot.org/c/coreboot/+/25416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4123998b0ab3c263c6a9ff14084a0d8808e5f4cd Gerrit-Change-Number: 25416 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Tue, 02 Jun 2020 16:23:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Apply FiVR related settings
by Meera Ravindranath (Code Review) 02 Jun '20

02 Jun '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Maulik V Vaghela, Aamir Bohra, Ronak Kanabar, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41062 to look at the new patch set (#14). Change subject: soc/intel/jasperlake: Apply FiVR related settings ...................................................................... soc/intel/jasperlake: Apply FiVR related settings Set optimized values for FiVR to shut the VCCIN_AUX_SHUTDOWN power rails during SOix. BUG=None BRANCH=None TEST=Build and boot dedede and check VCCIN_AUX_SHUTDOWN rails are shut. Change-Id: Ief81fe481c94abef9754881cf1f454699fafa52e Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/41062/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/41062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief81fe481c94abef9754881cf1f454699fafa52e Gerrit-Change-Number: 41062 Gerrit-PatchSet: 14 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/jasperlake: Apply FiVR related settings
by Meera Ravindranath (Code Review) 02 Jun '20

02 Jun '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Maulik V Vaghela, Aamir Bohra, Ronak Kanabar, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41062 to look at the new patch set (#13). Change subject: soc/intel/jasperlake: Apply FiVR related settings ...................................................................... soc/intel/jasperlake: Apply FiVR related settings Set optimized values for FiVR to shut the VCCIN_AUX_SHUTDOWN power rails during SOix. BUG=None BRANCH=None TEST=Build and boot dedede and check VCCIN_AUX_SHUTDOWN rails are shut. Change-Id: Ief81fe481c94abef9754881cf1f454699fafa52e Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/41062/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/41062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief81fe481c94abef9754881cf1f454699fafa52e Gerrit-Change-Number: 41062 Gerrit-PatchSet: 13 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/amd/stoneyridge: Generate SPCR table
by Raul Rangel (Code Review) 02 Jun '20

02 Jun '20

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25345 ) Change subject: soc/amd/stoneyridge: Generate SPCR table ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/25345/6/src/soc/amd/stoneyridge/ua… File src/soc/amd/stoneyridge/uart.c: https://review.coreboot.org/c/coreboot/+/25345/6/src/soc/amd/stoneyridge/ua… PS6, Line 41: AMDCZ > Works for me, not that I will get to this any time soon... […] I think we can remove all the special AMDCZ handling. The AMD part uses DW IP. The driver supports reading the fixed clock rate: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/t… So if we pass that along then I think the kernel will configure the IP correctly so we can boot with console=ttyS0 even when coreboot hasn't setup the UART. I need to try this out on zork. -- To view, visit https://review.coreboot.org/c/coreboot/+/25345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc98bcf4f8c070b8002bcc795254b19f928c741b Gerrit-Change-Number: 25345 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Tue, 02 Jun 2020 15:25:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Daniel Kurtz <djkurtz(a)google.com> Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/picasso: Install AGESA ACPI tables
by Raul Rangel (Code Review) 02 Jun '20

02 Jun '20

Hello Matt Papageorge, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41804 to review the following change. Change subject: soc/amd/picasso: Install AGESA ACPI tables ...................................................................... soc/amd/picasso: Install AGESA ACPI tables AGESA FSP provides additional ACPI tables that are required. BUG=b:133337564, b:153675915 TEST=Boot trembyle to OS and dump ACPI tables. ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TPM2 TPM2 log created at 0xcc513000 ACPI: added table 4/32, length now 52 ACPI: * MADT ACPI: added table 5/32, length now 56 current = cc635af0 Searching for AGESA FSP ACPI Tables ACPI: * SSDT (AGESA). ACPI: added table 6/32, length now 60 ACPI: * CRAT (AGESA). ACPI: added table 7/32, length now 64 ACPI: * ALIB (AGESA). ACPI: added table 8/32, length now 68 ACPI: * IVRS (AGESA). ACPI: added table 9/32, length now 72 ACPI: * HPET ACPI: added table 10/32, length now 76 Copying initialized VBIOS image from 0x000c0000 ACPI: * VFCT at cc63ca30 ACPI: added table 11/32, length now 80 ACPI: done. ACPI tables: 102048 bytes. [ 0.042326] ACPI: Early table checksum verification disabled [ 0.048621] ACPI: RSDP 0x00000000000F0000 000024 (v02 COREv4) [ 0.055011] ACPI: XSDT 0x00000000CC6310E0 00007C (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.064506] ACPI: FACP 0x00000000CC634850 000114 (v06 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.073998] ACPI: DSDT 0x00000000CC631280 0035CF (v02 COREv4 COREBOOT 00010001 INTL 20200110) [ 0.083488] ACPI: FACS 0x00000000CC631240 000040 [ 0.088623] ACPI: SSDT 0x00000000CC634970 00103D (v02 COREv4 COREBOOT 0000002A CORE 20200110) [ 0.098114] ACPI: MCFG 0x00000000CC6359B0 00003C (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.107606] ACPI: TPM2 0x00000000CC6359F0 00004C (v04 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.117100] ACPI: APIC 0x00000000CC635A40 0000A6 (v03 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.126592] ACPI: SSDT 0x00000000CC635AF0 00119C (v01 AMD AMD CPU 00000001 AMD 00000001) [ 0.136082] ACPI: CRAT 0x00000000CC636C90 000810 (v01 AMD AMD CRAT 00000001 AMD 00000001) [ 0.145573] ACPI: SSDT 0x00000000CC6374A0 005419 (v02 AMD AmdTable 00000002 MSFT 02000002) [ 0.155064] ACPI: IVRS 0x00000000CC63C8C0 000126 (v02 AMD AMD IVRS 00000001 AMD 00000000) [ 0.164556] ACPI: HPET 0x00000000CC63C9F0 000038 (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.174047] ACPI: VFCT 0x00000000CC63CA30 00D469 (v01 COREv4 COREBOOT 00000000 CORE 20200110) Signed-off-by: Matt Papageorge <matt.papageorge(a)amd.corp-partner.google.com> Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ic1e87c0f7a7c736592dd8c5c6765ef9a37ed7a40 --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/agesa_acpi.c M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/include/soc/acpi.h M src/vendorcode/amd/fsp/picasso/FspGuids.h A src/vendorcode/amd/fsp/picasso/acpi_hob.h 6 files changed, 86 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/41804/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index d0046ea..2b7cf28 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -47,6 +47,7 @@ ramstage-y += root_complex.c ramstage-y += mca.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c ramstage-y += gpio.c ramstage-y += southbridge.c ramstage-y += pmutil.c diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c new file mode 100644 index 0000000..5aafd55 --- /dev/null +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <acpi_hob.h> +#include <console/console.h> +#include <fsp/util.h> +#include <FspGuids.h> +#include <lib.h> +#include <soc/acpi.h> + +static uintptr_t add_agesa_acpi_table(guid_t guid, const char *name, acpi_rsdp_t *rsdp, + uintptr_t current) +{ + const struct amd_fsp_acpi_hob_info *data; + void *table = (void *)current; + size_t hob_size; + + data = fsp_find_extension_hob_by_guid(guid.b, &hob_size); + if (!data) { + printk(BIOS_ERR, "AGESA %s ACPI table was not found.\n", name); + return current; + } + + printk(BIOS_INFO, "ACPI: * %s (AGESA).\n", name); + + memcpy(table, data->hob_payload, data->table_size_in_bytes); + + current += data->table_size_in_bytes; + acpi_add_table(rsdp, table); + current = acpi_align_current(current); + + return current; +} + +uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, + acpi_rsdp_t *rsdp) +{ + printk(BIOS_DEBUG, "Searching for AGESA FSP ACPI Tables\n"); + + current = add_agesa_acpi_table(AMD_FSP_ACPI_SSDT_HOB_GUID, "SSDT", rsdp, current); + current = add_agesa_acpi_table(AMD_FSP_ACPI_CRAT_HOB_GUID, "CRAT", rsdp, current); + current = add_agesa_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); + current = add_agesa_acpi_table(AMD_FSP_ACPI_IVRS_HOB_GUID, "IVRS", rsdp, current); + + /* Add SRAT, MSCT, SLIT if needed in the future */ + + return current; +} diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index f593664..61ba5e0 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -145,6 +145,8 @@ static void soc_init(void *chip_info) { + default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables; + fsp_silicon_init(acpi_is_wakeup_s3()); data_fabric_set_mmio_np(); diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index 6250f86..77f836c 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -14,6 +14,9 @@ void southbridge_inject_dsdt(const struct device *device); +uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, + acpi_rsdp_t *rsdp); + const char *soc_acpi_name(const struct device *dev); #endif /* __SOC_PICASSO_ACPI_H__ */ diff --git a/src/vendorcode/amd/fsp/picasso/FspGuids.h b/src/vendorcode/amd/fsp/picasso/FspGuids.h index 24b185d..64bf97c 100644 --- a/src/vendorcode/amd/fsp/picasso/FspGuids.h +++ b/src/vendorcode/amd/fsp/picasso/FspGuids.h @@ -9,6 +9,22 @@ GUID_INIT(0x5fc7897a, 0x5aff, 0x4c61, \ 0xaa, 0x7a, 0xdd, 0xcf, 0xa9, 0x18, 0x43, 0x0c) +#define AMD_FSP_ACPI_SSDT_HOB_GUID \ + GUID_INIT(0x54445353, 0x4002, 0x403b, \ + 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) + +#define AMD_FSP_ACPI_CRAT_HOB_GUID \ + GUID_INIT(0x54415243, 0x4002, 0x403b, \ + 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) + +#define AMD_FSP_ACPI_ALIB_HOB_GUID \ + GUID_INIT(0x42494c41, 0x4002, 0x403b, \ + 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) + +#define AMD_FSP_ACPI_IVRS_HOB_GUID \ + GUID_INIT(0x53525649, 0x4002, 0x403b, \ + 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) + #define PICASSO_MISC_DATA_HOB_GUID \ GUID_INIT(0xf2784616, 0xb9bf, 0x4e1e, \ 0x99, 0xe0, 0x96, 0x26, 0xda, 0x7e, 0xa5, 0xf5) diff --git a/src/vendorcode/amd/fsp/picasso/acpi_hob.h b/src/vendorcode/amd/fsp/picasso/acpi_hob.h new file mode 100644 index 0000000..b33ea50 --- /dev/null +++ b/src/vendorcode/amd/fsp/picasso/acpi_hob.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PI_PICASSO_ACPI_HOB_H__ +#define __PI_PICASSO_ACPI_HOB_H__ + +#include <stdint.h> + +struct amd_fsp_acpi_hob_info { + uint32_t table_size_in_bytes; + uint8_t total_hobs_for_table; + uint8_t sequence_number; + uint16_t reserved; + uint16_t hob_payload[0xffc8]; +} __packed; + +#endif /* __PI_PICASSO_ACPI_HOB_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e87c0f7a7c736592dd8c5c6765ef9a37ed7a40 Gerrit-Change-Number: 41804 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit June 2020