coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: drivers/intel/fsp2_0: Add FSP 2.2 specific support
by build bot (Jenkins) (Code Review) 02 Jun '20

02 Jun '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41728 ) Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/41728/5/src/drivers/intel/fsp2_0/s… File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/c/coreboot/+/41728/5/src/drivers/intel/fsp2_0/s… PS5, Line 82: FSPS_ARCH_UPD *arch_upd; need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/41728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Gerrit-Change-Number: 41728 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jun 2020 12:37:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Add FSP 2.2 specific support
by Subrata Banik (Code Review) 02 Jun '20

02 Jun '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41728 ) Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/41728/3/src/drivers/intel/fsp2_0/s… File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/c/coreboot/+/41728/3/src/drivers/intel/fsp2_0/s… PS3, Line 41: fsp_handle_reset(status); > FSP requests System reset through "status" (return value) is not an error scenario. If FSP insist system reset using Return value FSP_STATUS_RESET_REQUIRED_* then control won't come back to https://review.coreboot.org/c/coreboot/+/41728/3..4/src/drivers/intel/fsp2_…. Assume FSP didn't request reset but there are some failure during FSP-S execution which results !EFI_SUCCESS those been handled between line 42-69. As per FSP spec, upon returning call from FSP to bootloader, we need to check return status idea is to create a helper function rather duplicating things for 'n' number of times in coreboot code to check FSP-S all possible API return status. > It can be due to the modified register settings take effect only post-reset. So, I suggest triggering system reset should be handled in the outside of function. i don't understand how it might be helpful, i'm guessing you have been carried by function name. its been changed now :) > If FSP's reset request is considered as an error, then it should be handled differently like triggering system recovery to avoid back to back resets! function name changed now -- To view, visit https://review.coreboot.org/c/coreboot/+/41728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Gerrit-Change-Number: 41728 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jun 2020 12:37:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Add FSP 2.2 specific support
by Subrata Banik (Code Review) 02 Jun '20

02 Jun '20

Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Maulik V Vaghela, Duncan Laurie, Sridhar Siricilla, Aamir Bohra, Srinidhi N Kaushik, Andrey Petrov, Aaron Durbin, Patrick Rudolph, Nathaniel L Desimone, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41728 to look at the new patch set (#5). Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support ...................................................................... drivers/intel/fsp2_0: Add FSP 2.2 specific support • Based on FSP EAS v2.1 – Backward compatibility is retained. • Added multi-phase silicon initialization to increase the modularity of the FspSiliconInit() API. • Added FspMultiPhaseSiInit() API • FSP_INFO_HEADER changes o Added FspMultiPhaseSiInitEntryOffset • Added FSPS_ARCH_UPD o Added EnableMultiPhaseSiliconInit, bootloaders designed for FSP 2.0/2.1 can disable the FspMultiPhaseSiInit() API and continue to use FspSiliconInit() without change. FSP 2.2 Specification: https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-… Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/commonlib/include/commonlib/timestamp_serialized.h M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/intel/fsp2_0/include/fsp/upd.h M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/fsp2_0/util.c M src/include/console/post_codes.h 9 files changed, 199 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/41728/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/41728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Gerrit-Change-Number: 41728 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/jasperlake: Updat pch_hda.asl to ASL2.0 syntax
by V Sowmya (Code Review) 02 Jun '20

02 Jun '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41863 ) Change subject: soc/intel/jasperlake: Updat pch_hda.asl to ASL2.0 syntax ...................................................................... soc/intel/jasperlake: Updat pch_hda.asl to ASL2.0 syntax This change updates pch_hda.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for wdoo. Change-Id: I8e965560518decbfafabe9ac06066d28d59240d0 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/soc/intel/jasperlake/acpi/pch_hda.asl 1 file changed, 7 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/41863/1 diff --git a/src/soc/intel/jasperlake/acpi/pch_hda.asl b/src/soc/intel/jasperlake/acpi/pch_hda.asl index f292901..340c765 100644 --- a/src/soc/intel/jasperlake/acpi/pch_hda.asl +++ b/src/soc/intel/jasperlake/acpi/pch_hda.asl @@ -26,19 +26,17 @@ */ Method (_DSM, 4) { - If (LEqual (Arg0, ^UUID)) { + If (Arg0 == ^UUID) { /* * Function 0: Function Support Query * Returns a bitmask of functions supported. */ - If (LEqual (Arg2, Zero)) { + If (Arg2 == Zero) { /* * NHLT Query only supported for revision 1 and * if NHLT address and length are set in NVS. */ - If (LAnd (LEqual (Arg1, One), - LAnd (LNotEqual (NHLA, Zero), - LNotEqual (NHLL, Zero)))) { + If ((Arg1 == One) && ((NHLA != Zero) && (NHLL != Zero))) { Return (Buffer (One) { 0x03 }) } Else { Return (Buffer (One) { 0x01 }) @@ -52,14 +50,14 @@ * * Returns a pointer to NHLT table in memory. */ - If (LEqual (Arg2, One)) { + If (Arg2 == One) { CreateQWordField (NBUF, ^NHLT._MIN, NBAS) CreateQWordField (NBUF, ^NHLT._MAX, NMAS) CreateQWordField (NBUF, ^NHLT._LEN, NLEN) - Store (NHLA, NBAS) - Store (NHLA, NMAS) - Store (NHLL, NLEN) + NBAS = NHLA + NMAS = NHLA + NLEN = NHLL Return (NBUF) } -- To view, visit https://review.coreboot.org/c/coreboot/+/41863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e965560518decbfafabe9ac06066d28d59240d0 Gerrit-Change-Number: 41863 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Update camera_clock_ctl.asl to ASL2.0 syntax
by V Sowmya (Code Review) 02 Jun '20

02 Jun '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41954 ) Change subject: soc/intel/jasperlake: Update camera_clock_ctl.asl to ASL2.0 syntax ...................................................................... soc/intel/jasperlake: Update camera_clock_ctl.asl to ASL2.0 syntax This change updates camera_clock_ctl.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for wdoo. Change-Id: I76ec29210ecdde728ce55531d2b6657be87ce9da Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/41954/1 diff --git a/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl b/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl index 3d31502..d76cb5d 100644 --- a/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl +++ b/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl @@ -11,7 +11,7 @@ /* IsCLK PCH base register for clock settings */ Name (ICKB, 0) - Store (PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1, ICKB) + ICKB = PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1 /* * Arg0 : Clock Number -- To view, visit https://review.coreboot.org/c/coreboot/+/41954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76ec29210ecdde728ce55531d2b6657be87ce9da Gerrit-Change-Number: 41954 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Apply FiVR related settings
by Paul Menzel (Code Review) 02 Jun '20

02 Jun '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41062 ) Change subject: soc/intel/jasperlake: Apply FiVR related settings ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/c/coreboot/+/41062/12//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/41062/12//COMMIT_MSG@15 PS12, Line 15: are shut. Were you able to measure the power savings? -- To view, visit https://review.coreboot.org/c/coreboot/+/41062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief81fe481c94abef9754881cf1f454699fafa52e Gerrit-Change-Number: 41062 Gerrit-PatchSet: 12 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jun 2020 12:18:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Updat platform.asl to ASL2.0 syntax
by V Sowmya (Code Review) 02 Jun '20

02 Jun '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41861 ) Change subject: soc/intel/jasperlake: Updat platform.asl to ASL2.0 syntax ...................................................................... soc/intel/jasperlake: Updat platform.asl to ASL2.0 syntax This change updates platform.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for wdoo. Change-Id: Ie55bcd9ac2ca746c046ebe05140b2ac291fb0459 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/soc/intel/jasperlake/acpi/platform.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/41861/1 diff --git a/src/soc/intel/jasperlake/acpi/platform.asl b/src/soc/intel/jasperlake/acpi/platform.asl index 7345864..4b01aeb 100644 --- a/src/soc/intel/jasperlake/acpi/platform.asl +++ b/src/soc/intel/jasperlake/acpi/platform.asl @@ -16,5 +16,5 @@ Method (_PIC, 1) { /* Remember the OS' IRQ routing choice. */ - Store (Arg0, PICM) + PICM = Arg0 } -- To view, visit https://review.coreboot.org/c/coreboot/+/41861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie55bcd9ac2ca746c046ebe05140b2ac291fb0459 Gerrit-Change-Number: 41861 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Add FSP 2.2 specific support
by Sridhar Siricilla (Code Review) 02 Jun '20

02 Jun '20

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41728 ) Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/41728/3/src/drivers/intel/fsp2_0/s… File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/c/coreboot/+/41728/3/src/drivers/intel/fsp2_0/s… PS3, Line 41: fsp_handle_reset(status); > Ack FSP requests System reset through "status" (return value) is not an error scenario. It can be due to the modified register settings take effect only post-reset. So, I suggest triggering system reset should be handled in the outside of function. If FSP's reset request is considered as an error, then it should be handled differently like triggering system recovery to avoid back to back resets! -- To view, visit https://review.coreboot.org/c/coreboot/+/41728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Gerrit-Change-Number: 41728 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jun 2020 12:16:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Updat scs.asl to ASL2.0 syntax
by V Sowmya (Code Review) 02 Jun '20

02 Jun '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41862 ) Change subject: soc/intel/jasperlake: Updat scs.asl to ASL2.0 syntax ...................................................................... soc/intel/jasperlake: Updat scs.asl to ASL2.0 syntax This change updates scs.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for wdoo. Change-Id: Ic1b5f3395a1ea8a3dd2ac6b109f9a5abe65d137f Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/soc/intel/jasperlake/acpi/scs.asl 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/41862/1 diff --git a/src/soc/intel/jasperlake/acpi/scs.asl b/src/soc/intel/jasperlake/acpi/scs.asl index bee862d..508fb9b 100644 --- a/src/soc/intel/jasperlake/acpi/scs.asl +++ b/src/soc/intel/jasperlake/acpi/scs.asl @@ -37,22 +37,22 @@ Method(_PS0, 0, Serialized) { Stall (50) // Sleep 50 us - Store(0, PGEN) // Disable PG + PGEN = 0 // Disable PG /* Clear register 0x1C20/0x4820 */ SCSC (PID_EMMC) /* Set Power State to D0 */ - And (PMCR, 0xFFFC, PMCR) - Store (PMCR, TEMP) + PMCR = PMCR & 0xFFFC + TEMP = PMCR } Method(_PS3, 0, Serialized) { - Store(1, PGEN) // Enable PG + PGEN = 1 // Enable PG /* Set Power State to D3 */ - Or (PMCR, 0x0003, PMCR) - Store (PMCR, TEMP) + PMCR = PMCR | 0x0003 + TEMP = PMCR } Device (CARD) @@ -90,23 +90,23 @@ Method (_PS0, 0, Serialized) { - Store (0, PGEN) /* Disable PG */ + PGEN = 0 /* Disable PG */ /* Clear register 0x1C20/0x4820 */ SCSC (PID_SDX) /* Set Power State to D0 */ - And (PMCR, 0xFFFC, PMCR) - Store (PMCR, TEMP) + PMCR = PMCR & 0xFFFC + TEMP = PMCR } Method (_PS3, 0, Serialized) { - Store (1, PGEN) /* Enable PG */ + PGEN = 1 /* Enable PG */ /* Set Power State to D3 */ - Or (PMCR, 0x0003, PMCR) - Store (PMCR, TEMP) + PMCR = PMCR | 0x0003 + TEMP = PMCR } Device (CARD) -- To view, visit https://review.coreboot.org/c/coreboot/+/41862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1b5f3395a1ea8a3dd2ac6b109f9a5abe65d137f Gerrit-Change-Number: 41862 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Apply FiVR related settings
by Meera Ravindranath (Code Review) 02 Jun '20

02 Jun '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Maulik V Vaghela, Aamir Bohra, Ronak Kanabar, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41062 to look at the new patch set (#12). Change subject: soc/intel/jasperlake: Apply FiVR related settings ...................................................................... soc/intel/jasperlake: Apply FiVR related settings Set optimized values for FiVR to shut the VCCIN_AUX_SHUTDOWN power rails during SOix. BUG=None BRANCH=None TEST=Build and boot dedede and check VCCIN_AUX_SHUTDOWN rails are shut. Change-Id: Ief81fe481c94abef9754881cf1f454699fafa52e Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/41062/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/41062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief81fe481c94abef9754881cf1f454699fafa52e Gerrit-Change-Number: 41062 Gerrit-PatchSet: 12 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit June 2020