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Change in coreboot[master]: sb/intel/bd82x6x: Fix 16-bit read/write PCI_COMMAND register
by HAOUAS Elyes (Code Review) 02 Jun '20

02 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40807 ) Change subject: sb/intel/bd82x6x: Fix 16-bit read/write PCI_COMMAND register ...................................................................... sb/intel/bd82x6x: Fix 16-bit read/write PCI_COMMAND register Change-Id: I1589fd8df4ec0fcdcde283513734dfd8458df2f7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/early_usb_mrc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/bd82x6x/usb_ehci.c 8 files changed, 41 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/40807/1 diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 0466d31..2aa5863 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -282,8 +282,7 @@ } /* Set Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); pci_write_config8(dev, 0x3c, 0x0a); // unused? diff --git a/src/southbridge/intel/bd82x6x/early_usb_mrc.c b/src/southbridge/intel/bd82x6x/early_usb_mrc.c index 719f94b..77a243c 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_usb_mrc.c @@ -19,19 +19,19 @@ { pci_devfn_t usb0 = PCH_EHCI1_DEV; pci_devfn_t usb1 = PCH_EHCI2_DEV; - u32 cmd; + u16 cmd; /* USB Controller 1 */ pci_write_config32(usb0, PCI_BASE_ADDRESS_0, PCH_EHCI1_TEMP_BAR0); - cmd = pci_read_config32(usb0, PCI_COMMAND); + cmd = pci_read_config16(usb0, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(usb0, PCI_COMMAND, cmd); + pci_write_config16(usb0, PCI_COMMAND, cmd); /* USB Controller 2 */ pci_write_config32(usb1, PCI_BASE_ADDRESS_0, PCH_EHCI2_TEMP_BAR0); - cmd = pci_read_config32(usb1, PCI_COMMAND); + cmd = pci_read_config16(usb1, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(usb1, PCI_COMMAND, cmd); + pci_write_config16(usb1, PCI_COMMAND, cmd); } diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index b1f3bfe..88d669b 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -472,6 +472,7 @@ { struct me_hfs hfs; u32 reg32; + u16 reg16; mei_base_address = (u32 *) (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); @@ -494,10 +495,10 @@ mkhi_end_of_post(); /* Make sure IO is disabled */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); + pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); @@ -590,7 +591,7 @@ { struct resource *res; struct mei_csr host; - u32 reg32; + u16 reg16; /* Find the MMIO base for the ME interface */ res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -601,9 +602,9 @@ mei_base_address = (u32*)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config16(dev, PCI_COMMAND, reg16); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 054c29f..b072201 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -468,6 +468,7 @@ { struct me_hfs hfs; u32 reg32; + u16 reg16; mei_base_address = (void *) (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); @@ -490,10 +491,10 @@ mkhi_end_of_post(); /* Make sure IO is disabled */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); + pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); @@ -578,7 +579,7 @@ { struct resource *res; struct mei_csr host; - u32 reg32; + u16 reg16; /* Find the MMIO base for the ME interface */ res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -589,9 +590,9 @@ mei_base_address = (u32 *)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config16(dev, PCI_COMMAND, reg16); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index cb31880..9c06e21 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -302,7 +302,7 @@ static void pch_pcie_enable(struct device *dev) { struct southbridge_intel_bd82x6x_config *config = dev->chip_info; - u32 reg32; + u16 reg16; if (!config) return; @@ -359,10 +359,10 @@ } /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Do not claim downstream transactions for PCIe ports */ new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); @@ -389,9 +389,7 @@ } /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } /* @@ -411,7 +409,7 @@ void pch_enable(struct device *dev) { - u32 reg32; + u16 reg16; /* PCH PCIe Root Ports get special handling */ if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT) @@ -421,18 +419,16 @@ printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Hide this device if possible */ pch_hide_devfn(dev->path.pci.devfn); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } } diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 7baf67d..85941e1 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -212,9 +212,7 @@ printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); /* Enable Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 78ac08b..0aab47a 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -95,7 +95,7 @@ static void xhci_sleep(u8 slp_typ) { - u32 reg32, xhci_bar; + u32 xhci_bar; u16 reg16; switch (slp_typ) { @@ -105,9 +105,9 @@ reg16 &= ~0x03UL; pci_write_config32(PCH_XHCI_DEV, 0x74, reg16); - reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND); - reg32 |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); + reg16 = pci_read_config16(PCH_XHCI_DEV, PCI_COMMAND); + reg16 |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config16(PCH_XHCI_DEV, PCI_COMMAND, reg16); xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & ~0xFUL; @@ -121,9 +121,9 @@ if ((xhci_bar + 0x4F0) & 1) pch_iobp_update(0xEC000382, ~0UL, (3 << 2)); - reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); + reg16 = pci_read_config16(PCH_XHCI_DEV, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config16(PCH_XHCI_DEV, PCI_COMMAND, reg16); reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); reg16 |= 0x03; diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index b906937..b2363b5 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -31,10 +31,7 @@ pci_write_config32(dev, 0xfc, 0x205b1708); #endif - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - //reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* For others, done in MRC. */ #if CONFIG(USE_NATIVE_RAMINIT) -- To view, visit https://review.coreboot.org/c/coreboot/+/40807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1589fd8df4ec0fcdcde283513734dfd8458df2f7 Gerrit-Change-Number: 40807 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: src: Remove unused '#include <cbfs.h>'
by HAOUAS Elyes (Code Review) 02 Jun '20

02 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41682 ) Change subject: src: Remove unused '#include <cbfs.h>' ...................................................................... src: Remove unused '#include <cbfs.h>' Found using: diff <(git grep -l '#include <cbfs.h>' -- src/) <(git grep -l 'cbfs_boot_map_optionrom\|cbfs_boot_map_optionrom_revision\|cbfs_boot_locate\|cbfs_boot_map_with_leak\|cbfs_locate_file_in_region\|cbfs_boot_load_file\|cbfs_load_and_decompress\|cbfs_prog_stage_load\|cbfs_boot_region_device' -- src/) |grep '<' |grep -v vendorcode Change-Id: Icaecb5b910888f34cddedab7b2f64eaf6d01ad66 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm64/fit_payload.c M src/arch/riscv/boot.c M src/arch/riscv/fit_payload.c M src/drivers/pc80/rtc/mc146818rtc.c M src/lib/fit.c M src/lib/fit_payload.c M src/lib/selfboot.c M src/mainboard/facebook/fbg1701/romstage.c M src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c M src/mainboard/intel/kblrvp/romstage.c M src/mainboard/intel/tglrvp/romstage_fsp_params.c M src/mainboard/portwell/m107/romstage.c M src/mainboard/sifive/hifive-unleashed/media.c M src/soc/amd/common/block/psp/psp_smm.c M src/soc/intel/apollolake/mmap_boot.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/qualcomm/sc7180/aop_load_reset.c M src/soc/qualcomm/sc7180/include/soc/qupv3_config.h M src/soc/qualcomm/sdm845/aop_load_reset.c 19 files changed, 0 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/41682/1 diff --git a/src/arch/arm64/fit_payload.c b/src/arch/arm64/fit_payload.c index c8eba8d..760b48c 100644 --- a/src/arch/arm64/fit_payload.c +++ b/src/arch/arm64/fit_payload.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <cbfs.h> #include <commonlib/bsd/compression.h> #include <console/console.h> #include <bootmem.h> diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 7cb0a36..ab05f94 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -6,7 +6,6 @@ #include <arch/encoding.h> #include <arch/smp/smp.h> #include <mcall.h> -#include <cbfs.h> #include <console/console.h> struct arch_prog_run_args { diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c index 2e676c7..abce57e 100644 --- a/src/arch/riscv/fit_payload.c +++ b/src/arch/riscv/fit_payload.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <cbfs.h> #include <commonlib/bsd/compression.h> #include <console/console.h> #include <bootmem.h> diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 79bb5eb..3227510 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -9,7 +9,6 @@ #include <option.h> #include <pc80/mc146818rtc.h> #include <rtc.h> -#include <cbfs.h> #include <security/vboot/vbnv.h> #include <security/vboot/vbnv_layout.h> #include <types.h> diff --git a/src/lib/fit.c b/src/lib/fit.c index 90cbfca..d930c39 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -2,7 +2,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <assert.h> -#include <cbfs.h> #include <console/console.h> #include <ctype.h> #include <endian.h> diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c index b3a03a1..90948f9 100644 --- a/src/lib/fit_payload.c +++ b/src/lib/fit_payload.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbfs.h> #include <commonlib/bsd/compression.h> #include <console/console.h> #include <bootmem.h> diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index c5ad525..1af824f 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -7,7 +7,6 @@ #include <stdlib.h> #include <string.h> #include <symbols.h> -#include <cbfs.h> #include <lib.h> #include <bootmem.h> #include <program_loading.h> diff --git a/src/mainboard/facebook/fbg1701/romstage.c b/src/mainboard/facebook/fbg1701/romstage.c index 6dafd8a..f307f95 100644 --- a/src/mainboard/facebook/fbg1701/romstage.c +++ b/src/mainboard/facebook/fbg1701/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <build.h> -#include <cbfs.h> #include <console/console.h> #include <chip.h> #include <device/pci_ops.h> diff --git a/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c index 2cd8637..5b7445f 100644 --- a/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbfs.h> #include <console/console.h> #include <fsp/api.h> #include <soc/romstage.h> diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index 281a24f..a3fb285 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbfs.h> #include <console/console.h> #include <fsp/api.h> #include <gpio.h> diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c index d4433a1..47507f4 100644 --- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -6,7 +6,6 @@ #include <spd_bin.h> #include <soc/meminit.h> #include <baseboard/variants.h> -#include <cbfs.h> #include "board_id.h" #include "spd/spd.h" diff --git a/src/mainboard/portwell/m107/romstage.c b/src/mainboard/portwell/m107/romstage.c index 4f666e2..3ba12f3 100644 --- a/src/mainboard/portwell/m107/romstage.c +++ b/src/mainboard/portwell/m107/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbfs.h> #include <console/console.h> #include <chip.h> #include <device/pci_ops.h> diff --git a/src/mainboard/sifive/hifive-unleashed/media.c b/src/mainboard/sifive/hifive-unleashed/media.c index 9f91bcb..2ba6d2b 100644 --- a/src/mainboard/sifive/hifive-unleashed/media.c +++ b/src/mainboard/sifive/hifive-unleashed/media.c @@ -2,7 +2,6 @@ #include <boot_device.h> #include <symbols.h> -#include <cbfs.h> #include <device/mmio.h> #include <soc/addressmap.h> #include <soc/spi.h> diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c index b103b3e..61e0f2c 100644 --- a/src/soc/amd/common/block/psp/psp_smm.c +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -3,7 +3,6 @@ #include <device/mmio.h> #include <cpu/x86/msr.h> #include <cpu/amd/msr.h> -#include <cbfs.h> #include <region_file.h> #include <rules.h> #include <console/console.h> diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index b37d760..30c629e 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <boot_device.h> -#include <cbfs.h> #include <commonlib/region.h> #include <console/console.h> #include <fmap.h> diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 2125f0a..c19c0cf 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/ioapic.h> -#include <cbfs.h> #include <console/console.h> #include <cpu/x86/lapic.h> #include <device/pci.h> diff --git a/src/soc/qualcomm/sc7180/aop_load_reset.c b/src/soc/qualcomm/sc7180/aop_load_reset.c index 85ea67e..f080f52 100644 --- a/src/soc/qualcomm/sc7180/aop_load_reset.c +++ b/src/soc/qualcomm/sc7180/aop_load_reset.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbfs.h> #include <halt.h> #include <console/console.h> #include <timestamp.h> diff --git a/src/soc/qualcomm/sc7180/include/soc/qupv3_config.h b/src/soc/qualcomm/sc7180/include/soc/qupv3_config.h index d67c0b5..b595984 100644 --- a/src/soc/qualcomm/sc7180/include/soc/qupv3_config.h +++ b/src/soc/qualcomm/sc7180/include/soc/qupv3_config.h @@ -4,7 +4,6 @@ #define _SC7180_QUPV3_CONFIG_H_ #include <assert.h> -#include <cbfs.h> #include <soc/clock.h> #include <soc/qcom_qup_se.h> diff --git a/src/soc/qualcomm/sdm845/aop_load_reset.c b/src/soc/qualcomm/sdm845/aop_load_reset.c index eb90f86..8a479e5 100644 --- a/src/soc/qualcomm/sdm845/aop_load_reset.c +++ b/src/soc/qualcomm/sdm845/aop_load_reset.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbfs.h> #include <console/console.h> #include <soc/mmu.h> #include <soc/aop.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/41682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icaecb5b910888f34cddedab7b2f64eaf6d01ad66 Gerrit-Change-Number: 41682 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

6 12

Change in coreboot[master]: mb/google/{daisy,veyron{_mickey,_rialto}}: Remove unused 'include <vb...
by HAOUAS Elyes (Code Review) 02 Jun '20

02 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41684 ) Change subject: mb/google/{daisy,veyron{_mickey,_rialto}}: Remove unused 'include <vbe.h>' ...................................................................... mb/google/{daisy,veyron{_mickey,_rialto}}: Remove unused 'include <vbe.h>' Change-Id: I7c0be437e8cb49934913563c6d21056034a50095 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/daisy/mainboard.c M src/mainboard/google/veyron/mainboard.c M src/mainboard/google/veyron_mickey/mainboard.c M src/mainboard/google/veyron_rialto/mainboard.c 4 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/41684/1 diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index de60024..2f07937 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -18,7 +18,6 @@ #include <soc/tmu.h> #include <soc/usb.h> #include <symbols.h> -#include <vbe.h> #include "exynos5250.h" diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c index 60c9737..b270466 100644 --- a/src/mainboard/google/veyron/mainboard.c +++ b/src/mainboard/google/veyron/mainboard.c @@ -16,7 +16,6 @@ #include <soc/spi.h> #include <soc/i2c.h> #include <symbols.h> -#include <vbe.h> #include <vendorcode/google/chromeos/chromeos.h> #include "board.h" diff --git a/src/mainboard/google/veyron_mickey/mainboard.c b/src/mainboard/google/veyron_mickey/mainboard.c index f9feb2f..2567249 100644 --- a/src/mainboard/google/veyron_mickey/mainboard.c +++ b/src/mainboard/google/veyron_mickey/mainboard.c @@ -15,7 +15,6 @@ #include <soc/spi.h> #include <soc/i2c.h> #include <symbols.h> -#include <vbe.h> #include <vendorcode/google/chromeos/chromeos.h> #include "board.h" diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c index 1a5a944..9a9ce79 100644 --- a/src/mainboard/google/veyron_rialto/mainboard.c +++ b/src/mainboard/google/veyron_rialto/mainboard.c @@ -16,7 +16,6 @@ #include <soc/spi.h> #include <soc/i2c.h> #include <symbols.h> -#include <vbe.h> #include <vendorcode/google/chromeos/chromeos.h> #include <security/vboot/vboot_common.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/41684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c0be437e8cb49934913563c6d21056034a50095 Gerrit-Change-Number: 41684 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: src: Remove unused 'include <fmap.h>'
by HAOUAS Elyes (Code Review) 02 Jun '20

02 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41681 ) Change subject: src: Remove unused 'include <fmap.h>' ...................................................................... src: Remove unused 'include <fmap.h>' Change-Id: I79eea0a00c2de54f82b372229381534707a295bb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/vpd/vpd_cbmem.c M src/security/vboot/vboot_common.c 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/41681/1 diff --git a/src/drivers/vpd/vpd_cbmem.c b/src/drivers/vpd/vpd_cbmem.c index eadda52..a13fb01 100644 --- a/src/drivers/vpd/vpd_cbmem.c +++ b/src/drivers/vpd/vpd_cbmem.c @@ -2,7 +2,6 @@ #include <console/console.h> #include <cbmem.h> -#include <fmap.h> #include <string.h> #include <timestamp.h> diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index 30a2c2f..1cddeeb 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -3,7 +3,6 @@ #include <boot_device.h> #include <cbmem.h> #include <console/cbmem_console.h> -#include <fmap.h> #include <reset.h> #include <security/vboot/misc.h> #include <security/vboot/vboot_common.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/41681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79eea0a00c2de54f82b372229381534707a295bb Gerrit-Change-Number: 41681 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: src: Remove duplicated includes
by HAOUAS Elyes (Code Review) 02 Jun '20

02 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41676 ) Change subject: src: Remove duplicated includes ...................................................................... src: Remove duplicated includes Change-Id: If8c7e26ebd954b19bfb8766b26570c6865ad255e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/51nb/x210/romstage.c M src/mainboard/google/fizz/mainboard.c M src/soc/amd/common/block/acpi/acpi.c M src/soc/amd/common/block/lpc/lpc_util.c M src/soc/intel/braswell/northcluster.c M src/soc/mediatek/common/dsi.c M src/soc/mediatek/mt8173/i2c.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/pi/hudson/early_setup.c 9 files changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/41676/1 diff --git a/src/mainboard/51nb/x210/romstage.c b/src/mainboard/51nb/x210/romstage.c index caaa52d..60f008c 100644 --- a/src/mainboard/51nb/x210/romstage.c +++ b/src/mainboard/51nb/x210/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <string.h> #include <assert.h> #include <soc/romstage.h> #include <spd_bin.h> diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index c86be82..7b89058 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -10,7 +10,6 @@ #include <ec/google/chromeec/ec.h> #include <gpio.h> #include <intelblocks/power_limit.h> -#include <variant/gpio.h> #include <smbios.h> #include <soc/gpio.h> #include <soc/pci_devs.h> diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c index 964aef1..2be9b9e 100644 --- a/src/soc/amd/common/block/acpi/acpi.c +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -10,7 +10,6 @@ #include <halt.h> #include <security/vboot/vboot_common.h> #include <soc/southbridge.h> -#include <halt.h> void poweroff(void) { diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index d2a65c8..eb129dc 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -12,7 +12,6 @@ /* The LPC-ISA bridge is always at D14F3 */ #if !defined(__SIMPLE_DEVICE__) -#include <device/device.h> #define _LPCB_DEV pcidev_on_root(0x14, 0x3) #else #define _LPCB_DEV PCI_DEV(0, 0x14, 0x3) diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 67f8649..bf922c4 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -7,7 +7,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/lapic_def.h> -#include <cpu/x86/smm.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/iosf.h> diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 73dacef..2505bbc 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> -#include <device/mmio.h> #include <console/console.h> #include <device/mmio.h> #include <delay.h> diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index af2e029..f80fb97 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -7,9 +7,7 @@ #include <device/mmio.h> #include <soc/addressmap.h> #include <soc/i2c.h> -#include <device/mmio.h> #include <soc/pll.h> -#include <soc/i2c.h> #define I2C_CLK_HZ (AXI_HZ / 16) diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 63d2b81..4864945 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -7,7 +7,6 @@ #include <amdblocks/acpimmio.h> #include <device/pci_ops.h> #include <console/console.h> -#include <amdblocks/acpimmio.h> #include "hudson.h" diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 09a2750..8bca42b 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -9,7 +9,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <console/console.h> -#include <amdblocks/acpimmio.h> #include "hudson.h" #include "pci_devs.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/41676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8c7e26ebd954b19bfb8766b26570c6865ad255e Gerrit-Change-Number: 41676 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: src: Remove unused 'include <symbols.h>'
by HAOUAS Elyes (Code Review) 02 Jun '20

02 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41673 ) Change subject: src: Remove unused 'include <symbols.h>' ...................................................................... src: Remove unused 'include <symbols.h>' Change-Id: Ica355292eeda9c386b49db97f021566d52943d40 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm64/armv8/mmu.c M src/arch/x86/acpi_s3.c M src/arch/x86/boot.c M src/cpu/x86/lapic/lapic_cpu_init.c M src/cpu/x86/mp_init.c M src/lib/cbfs.c M src/lib/decompressor.c M src/lib/fmap.c M src/lib/prog_loaders.c M src/lib/ramdetect.c M src/lib/selfboot.c M src/mainboard/emulation/qemu-riscv/rom_media.c M src/mainboard/google/gale/bootblock.c M src/mainboard/google/storm/bootblock.c M src/security/tpm/tspi/log.c M src/soc/cavium/cn81xx/soc.c M src/soc/mediatek/common/i2c.c M src/soc/mediatek/mt8173/i2c.c M src/soc/nvidia/tegra124/clock.c M src/soc/nvidia/tegra124/spi.c M src/soc/nvidia/tegra210/arm_tf.c M src/soc/nvidia/tegra210/romstage.c M src/soc/nvidia/tegra210/spi.c M src/soc/qualcomm/sc7180/qspi.c M src/soc/qualcomm/sdm845/qspi.c M src/soc/rockchip/common/include/soc/soc.h 26 files changed, 0 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/41673/1 diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c index 72e5cca..82afb9d 100644 --- a/src/arch/arm64/armv8/mmu.c +++ b/src/arch/arm64/armv8/mmu.c @@ -3,7 +3,6 @@ #include <assert.h> #include <stdint.h> #include <string.h> -#include <symbols.h> #include <console/console.h> #include <arch/mmu.h> diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 5ef0f7a..d0f3eca 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -10,7 +10,6 @@ #include <timestamp.h> #include <program_loading.h> #include <romstage_handoff.h> -#include <symbols.h> #include <cpu/x86/smm.h> #if ENV_RAMSTAGE || ENV_POSTCAR diff --git a/src/arch/x86/boot.c b/src/arch/x86/boot.c index db9d69e..2866492 100644 --- a/src/arch/x86/boot.c +++ b/src/arch/x86/boot.c @@ -4,7 +4,6 @@ #include <console/console.h> #include <program_loading.h> #include <ip_checksum.h> -#include <symbols.h> int payload_arch_usable_ram_quirk(uint64_t start, uint64_t size) { diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 58a633b..a3198cf 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -9,7 +9,6 @@ #include <halt.h> #include <lib.h> #include <string.h> -#include <symbols.h> #include <console/console.h> #include <device/device.h> #include <device/path.h> diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index caed8f4..98efde6 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -22,7 +22,6 @@ #include <device/path.h> #include <smp/atomic.h> #include <smp/spinlock.h> -#include <symbols.h> #include <timer.h> #include <thread.h> diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index a3294de..17ce9b3 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -12,7 +12,6 @@ #include <security/vboot/vboot_common.h> #include <stdlib.h> #include <string.h> -#include <symbols.h> #include <timestamp.h> #define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) diff --git a/src/lib/decompressor.c b/src/lib/decompressor.c index 8ae9358..83b71b1 100644 --- a/src/lib/decompressor.c +++ b/src/lib/decompressor.c @@ -4,7 +4,6 @@ #include <commonlib/bsd/compression.h> #include <delay.h> #include <program_loading.h> -#include <symbols.h> #include <timestamp.h> extern u8 compressed_bootblock[]; diff --git a/src/lib/fmap.c b/src/lib/fmap.c index 671a962..8545e23 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -6,7 +6,6 @@ #include <fmap.h> #include <stddef.h> #include <string.h> -#include <symbols.h> #include "fmap_config.h" diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 7088d8d..cb8ac0b 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -13,7 +13,6 @@ #include <romstage_handoff.h> #include <rmodule.h> #include <stage_cache.h> -#include <symbols.h> #include <timestamp.h> #include <fit_payload.h> #include <security/vboot/vboot_common.h> diff --git a/src/lib/ramdetect.c b/src/lib/ramdetect.c index 328ca07..5ddacb1 100644 --- a/src/lib/ramdetect.c +++ b/src/lib/ramdetect.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <types.h> -#include <symbols.h> #include <device/mmio.h> #include <ramdetect.h> #include <console/console.h> diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index c5ad525..eccac69 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -6,7 +6,6 @@ #include <stdint.h> #include <stdlib.h> #include <string.h> -#include <symbols.h> #include <cbfs.h> #include <lib.h> #include <bootmem.h> diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c index 15989f2..a08aa89 100644 --- a/src/mainboard/emulation/qemu-riscv/rom_media.c +++ b/src/mainboard/emulation/qemu-riscv/rom_media.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <boot_device.h> -#include <symbols.h> /* This assumes that the CBFS resides at start of dram, which is true for the * default configuration. */ diff --git a/src/mainboard/google/gale/bootblock.c b/src/mainboard/google/gale/bootblock.c index 343fe65..109ff2b 100644 --- a/src/mainboard/google/gale/bootblock.c +++ b/src/mainboard/google/gale/bootblock.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <console/console.h> -#include <symbols.h> #include "mmu.h" #include <soc/usbl_if.h> diff --git a/src/mainboard/google/storm/bootblock.c b/src/mainboard/google/storm/bootblock.c index e7ff6a3..852acfe 100644 --- a/src/mainboard/google/storm/bootblock.c +++ b/src/mainboard/google/storm/bootblock.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <console/console.h> -#include <symbols.h> #include "mmu.h" #include <soc/usbl_if.h> diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 07623f7..0529b86 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -4,7 +4,6 @@ #include <security/tpm/tspi.h> #include <region_file.h> #include <string.h> -#include <symbols.h> #include <cbmem.h> #include <bootstate.h> #include <vb2_sha.h> diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 3545d55..b8b370c 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -14,7 +14,6 @@ #include <stddef.h> #include <stdlib.h> #include <string.h> -#include <symbols.h> #include <libbdk-boot/bdk-boot.h> #include <soc/ecam0.h> #include <console/uart.h> diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c index 87925ba..e576560 100644 --- a/src/soc/mediatek/common/i2c.c +++ b/src/soc/mediatek/common/i2c.c @@ -5,7 +5,6 @@ #include <console/console.h> #include <delay.h> #include <timer.h> -#include <symbols.h> #include <device/mmio.h> #include <soc/i2c.h> #include <device/i2c_simple.h> diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index 0adee22..af2e029 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -4,7 +4,6 @@ #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> -#include <symbols.h> #include <device/mmio.h> #include <soc/addressmap.h> #include <soc/i2c.h> diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index a2427fe..fb14c4e 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -12,7 +12,6 @@ #include <soc/maincpu.h> #include <soc/pmc.h> #include <soc/sysctr.h> -#include <symbols.h> static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; static struct flow_ctlr *flow = (void *)TEGRA_FLOW_BASE; diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 75cd9f7..6a25721 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -13,7 +13,6 @@ #include <soc/spi.h> #include <spi-generic.h> #include <spi_flash.h> -#include <symbols.h> #include <timer.h> #include <types.h> diff --git a/src/soc/nvidia/tegra210/arm_tf.c b/src/soc/nvidia/tegra210/arm_tf.c index e12b201..684a3c4 100644 --- a/src/soc/nvidia/tegra210/arm_tf.c +++ b/src/soc/nvidia/tegra210/arm_tf.c @@ -5,7 +5,6 @@ #include <bl31.h> #include <soc/addressmap.h> #include <soc/console_uart.h> -#include <symbols.h> #include <types.h> typedef struct bl31_plat_params { diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c index 4f92c5f..3e807dc 100644 --- a/src/soc/nvidia/tegra210/romstage.c +++ b/src/soc/nvidia/tegra210/romstage.c @@ -14,7 +14,6 @@ #include <soc/sdram_configs.h> #include <soc/romstage.h> #include <soc/nvidia/tegra/apbmisc.h> -#include <symbols.h> #include <vendorcode/google/chromeos/chromeos.h> void __weak romstage_mainboard_init(void) diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index eae8f39..4ccb926 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -13,7 +13,6 @@ #include <soc/addressmap.h> #include <soc/dma.h> #include <soc/spi.h> -#include <symbols.h> #include <types.h> #if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI diff --git a/src/soc/qualcomm/sc7180/qspi.c b/src/soc/qualcomm/sc7180/qspi.c index 675641b..ef2dbd3 100644 --- a/src/soc/qualcomm/sc7180/qspi.c +++ b/src/soc/qualcomm/sc7180/qspi.c @@ -8,7 +8,6 @@ #include <soc/qspi.h> #include <soc/gpio.h> #include <soc/clock.h> -#include <symbols.h> #include <assert.h> #include <gpio.h> #include <string.h> diff --git a/src/soc/qualcomm/sdm845/qspi.c b/src/soc/qualcomm/sdm845/qspi.c index 8c98316..a8e2dec 100644 --- a/src/soc/qualcomm/sdm845/qspi.c +++ b/src/soc/qualcomm/sdm845/qspi.c @@ -8,7 +8,6 @@ #include <soc/qspi.h> #include <soc/gpio.h> #include <soc/clock.h> -#include <symbols.h> #include <assert.h> #include <gpio.h> #include <string.h> diff --git a/src/soc/rockchip/common/include/soc/soc.h b/src/soc/rockchip/common/include/soc/soc.h index 67ee284..aaef606 100644 --- a/src/soc/rockchip/common/include/soc/soc.h +++ b/src/soc/rockchip/common/include/soc/soc.h @@ -3,8 +3,6 @@ #ifndef __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_SOC_H #define __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_SOC_H -#include <symbols.h> - #define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | set) #define RK_SETBITS(set) RK_CLRSETBITS(0, set) #define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/41673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica355292eeda9c386b49db97f021566d52943d40 Gerrit-Change-Number: 41673 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: soc/amd/picasso: Remove unused 'include <romstage_handoff.h>'
by HAOUAS Elyes (Code Review) 02 Jun '20

02 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41672 ) Change subject: soc/amd/picasso: Remove unused 'include <romstage_handoff.h>' ...................................................................... soc/amd/picasso: Remove unused 'include <romstage_handoff.h>' Change-Id: I07100361705ce421131b8a5d772cb5ba2d8722ff Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/romstage.c 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/41672/1 diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 9c26f35..4ea962f 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -5,7 +5,6 @@ #include <device/device.h> #include <device/pci.h> #include <drivers/i2c/designware/dw_i2c.h> -#include <romstage_handoff.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/data_fabric.h> diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index a2ca055..0bbceec 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -10,7 +10,6 @@ #include <commonlib/helpers.h> #include <console/console.h> #include <program_loading.h> -#include <romstage_handoff.h> #include <elog.h> #include <soc/romstage.h> #include <soc/mtrr.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/41672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07100361705ce421131b8a5d772cb5ba2d8722ff Gerrit-Change-Number: 41672 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: src: Remove unused 'includ </arch/smp/mpspec.h>'
by HAOUAS Elyes (Code Review) 02 Jun '20

02 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41669 ) Change subject: src: Remove unused 'includ </arch/smp/mpspec.h>' ...................................................................... src: Remove unused 'includ </arch/smp/mpspec.h>' Change-Id: If8048586e3693a8e6f63d9dc2800b073bab78628 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/beltino/acpi_tables.c M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/google/parrot/acpi_tables.c M src/mainboard/google/rambi/acpi_tables.c M src/mainboard/google/slippy/acpi_tables.c M src/mainboard/google/stout/acpi_tables.c M src/mainboard/google/stout/onboard.h M src/mainboard/intel/baskingridge/acpi_tables.c M src/mainboard/intel/emeraldlake2/acpi_tables.c M src/mainboard/intel/harcuvar/acpi_tables.c M src/mainboard/intel/strago/acpi_tables.c M src/mainboard/intel/wtm2/acpi_tables.c M src/mainboard/samsung/lumpy/acpi_tables.c M src/mainboard/samsung/stumpy/acpi_tables.c M src/mainboard/scaleway/tagada/acpi_tables.c M src/soc/intel/common/block/acpi/acpi.c M src/southbridge/intel/i82371eb/acpi_tables.c 17 files changed, 0 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/41669/1 diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c index b6a5606..d2f7f45 100644 --- a/src/mainboard/google/beltino/acpi_tables.c +++ b/src/mainboard/google/beltino/acpi_tables.c @@ -2,7 +2,6 @@ #include <types.h> #include <acpi/acpi.h> -#include <arch/smp/mpspec.h> #include <device/device.h> #include <ec/google/chromeec/ec.h> #include <southbridge/intel/lynxpoint/nvs.h> diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index 50bd1e0..3e8cc20 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -3,7 +3,6 @@ #include <types.h> #include <acpi/acpi.h> #include <arch/ioapic.h> -#include <arch/smp/mpspec.h> #include <device/device.h> #include <soc/acpi.h> #include <soc/nvs.h> diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index ce03c70..62722ec 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -2,7 +2,6 @@ #include <types.h> #include <acpi/acpi.h> -#include <arch/smp/mpspec.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> #include <ec/compal/ene932/ec.h> diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index 507da97..c4c1788 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -3,7 +3,6 @@ #include <types.h> #include <acpi/acpi.h> #include <arch/ioapic.h> -#include <arch/smp/mpspec.h> #include <device/device.h> #include <soc/acpi.h> #include <soc/nvs.h> diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index d091931..ba55647 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -2,7 +2,6 @@ #include <types.h> #include <acpi/acpi.h> -#include <arch/smp/mpspec.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 76342d4..08bd4cd 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -2,7 +2,6 @@ #include <types.h> #include <acpi/acpi.h> -#include <arch/smp/mpspec.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> #include <bootmode.h> diff --git a/src/mainboard/google/stout/onboard.h b/src/mainboard/google/stout/onboard.h index 6024ba8..a31dffd 100644 --- a/src/mainboard/google/stout/onboard.h +++ b/src/mainboard/google/stout/onboard.h @@ -3,8 +3,6 @@ #ifndef STOUT_ONBOARD_H #define STOUT_ONBOARD_H -#include <arch/smp/mpspec.h> - #define STOUT_NIC_VENDOR_ID 0x10EC #define STOUT_NIC_DEVICE_ID 0x8168 diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index ba6d9c0..24edfea 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -2,7 +2,6 @@ #include <types.h> #include <acpi/acpi.h> -#include <arch/smp/mpspec.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index 013487f..36d0d66 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -2,7 +2,6 @@ #include <types.h> #include <acpi/acpi.h> -#include <arch/smp/mpspec.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/intel/harcuvar/acpi_tables.c b/src/mainboard/intel/harcuvar/acpi_tables.c index 046d3ac..1351e62 100644 --- a/src/mainboard/intel/harcuvar/acpi_tables.c +++ b/src/mainboard/intel/harcuvar/acpi_tables.c @@ -2,7 +2,6 @@ #include <types.h> #include <acpi/acpi.h> -#include <arch/smp/mpspec.h> #include <device/device.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c index a3b9dd0..e97d9c1 100644 --- a/src/mainboard/intel/strago/acpi_tables.c +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <arch/ioapic.h> -#include <arch/smp/mpspec.h> #include <device/device.h> #include <soc/acpi.h> #include <soc/iomap.h> diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 960dbde..87cb965 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -3,7 +3,6 @@ #include <types.h> #include <acpi/acpi.h> #include <arch/ioapic.h> -#include <arch/smp/mpspec.h> #include <device/device.h> #include <soc/acpi.h> #include <soc/nvs.h> diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index 592ed50..aafbdb6 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -2,7 +2,6 @@ #include <types.h> #include <acpi/acpi.h> -#include <arch/smp/mpspec.h> #include <device/device.h> #include <ec/acpi/ec.h> #if CONFIG(CHROMEOS) diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index de2d51d..b66e4dd 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -2,7 +2,6 @@ #include <types.h> #include <acpi/acpi.h> -#include <arch/smp/mpspec.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c index 046d3ac..1351e62 100644 --- a/src/mainboard/scaleway/tagada/acpi_tables.c +++ b/src/mainboard/scaleway/tagada/acpi_tables.c @@ -2,7 +2,6 @@ #include <types.h> #include <acpi/acpi.h> -#include <arch/smp/mpspec.h> #include <device/device.h> #include <cpu/x86/msr.h> diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 70a9cac..02864b9 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -2,7 +2,6 @@ #include <acpi/acpigen.h> #include <arch/ioapic.h> -#include <arch/smp/mpspec.h> #include <bootstate.h> #include <cbmem.h> #include <cf9_reset.h> diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index ab28e76..7507cd5 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -3,7 +3,6 @@ #include <console/console.h> #include <acpi/acpi.h> #include <acpi/acpigen.h> -#include <arch/smp/mpspec.h> #include <device/device.h> #include "i82371eb.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/41669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8048586e3693a8e6f63d9dc2800b073bab78628 Gerrit-Change-Number: 41669 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: src: Remove unused 'include <bootmode.h>'
by HAOUAS Elyes (Code Review) 02 Jun '20

02 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41670 ) Change subject: src: Remove unused 'include <bootmode.h>' ...................................................................... src: Remove unused 'include <bootmode.h>' Change-Id: I658023f7c3535a2cddd8e11ca8bebe20ae53ffb0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/google/chromeec/ec.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/soc/cavium/cn81xx/soc.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/skylake/chip.c 7 files changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/41670/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index b964581..6465960 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -3,7 +3,6 @@ #include <stdint.h> #include <string.h> #include <assert.h> -#include <bootmode.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index a2b26ae..72c284f 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -2,7 +2,6 @@ #include <console/console.h> #include <commonlib/region.h> -#include <bootmode.h> #include <cf9_reset.h> #include <string.h> #include <arch/cpu.h> diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 43858f5..1ec54b3 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -2,7 +2,6 @@ #include <console/console.h> #include <console/usb.h> -#include <bootmode.h> #include <cf9_reset.h> #include <string.h> #include <device/device.h> diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 1077824..3545d55 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -4,7 +4,6 @@ * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. */ -#include <bootmode.h> #include <console/console.h> #include <device/device.h> #include <soc/addressmap.h> diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 2abeb3a..09537a1 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -4,7 +4,6 @@ #include <device/pci_ops.h> #include <arch/symbols.h> #include <assert.h> -#include <bootmode.h> #include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 54d6134..3b7aa40 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -2,7 +2,6 @@ #include <stdint.h> #include <arch/romstage.h> -#include <bootmode.h> #include <cbmem.h> #include <console/console.h> #include <cpu/x86/mtrr.h> diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index b14bb72..a1ef06e 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootmode.h> #include <bootstate.h> #include <cbmem.h> #include <fsp/api.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/41670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I658023f7c3535a2cddd8e11ca8bebe20ae53ffb0 Gerrit-Change-Number: 41670 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: src: Remove unused 'include <bootstate.h>'
by HAOUAS Elyes (Code Review) 02 Jun '20

02 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41671 ) Change subject: src: Remove unused 'include <bootstate.h>' ...................................................................... src: Remove unused 'include <bootstate.h>' Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/acpi_bert_storage.c M src/arch/x86/tables.c M src/drivers/intel/fsp1_1/hob.c M src/ec/google/chromeec/ec.c M src/lib/cbmem_common.c M src/lib/ext_stage_cache.c M src/lib/imd_cbmem.c M src/mainboard/google/hatch/variants/jinlon/mainboard.c M src/mainboard/intel/strago/mainboard.c M src/mainboard/protectli/vault_kbl/ramstage.c M src/mainboard/supermicro/x11-lga1151-series/ramstage.c M src/soc/amd/common/block/psp/psp_gen1.c M src/soc/amd/common/block/psp/psp_gen2.c M src/soc/amd/common/block/psp/psp_smm.c M src/soc/amd/picasso/chip.c M src/soc/intel/apollolake/elog.c M src/soc/intel/braswell/ramstage.c M src/soc/intel/common/block/smm/smm.c M src/soc/intel/common/vbt.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/pmc.c M src/southbridge/intel/lynxpoint/smi.c 23 files changed, 0 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/41671/1 diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index cde95f1..de56291 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootstate.h> #include <cbmem.h> #include <console/console.h> #include <cpu/x86/name.h> diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 3b1b76d..492674c 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -2,7 +2,6 @@ #include <console/console.h> #include <bootmem.h> -#include <bootstate.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> #include <arch/pirq_routing.h> diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c index d13939c..9a09cfd 100644 --- a/src/drivers/intel/fsp1_1/hob.c +++ b/src/drivers/intel/fsp1_1/hob.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/hlt.h> -#include <bootstate.h> #include <console/console.h> #include <fsp/util.h> #include <ip_checksum.h> diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 6465960..89f137c 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -3,7 +3,6 @@ #include <stdint.h> #include <string.h> #include <assert.h> -#include <bootstate.h> #include <cbmem.h> #include <console/console.h> #include <delay.h> diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index c24479d..bc3bfc9 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cbmem.h> -#include <bootstate.h> #include <symbols.h> void cbmem_run_init_hooks(int is_recovery) diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index afc0618..2fb1e9e 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootstate.h> #include <cbmem.h> #include <console/console.h> #include <imd.h> diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 2f065ff..c95753f 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -2,7 +2,6 @@ #include <assert.h> #include <boot/coreboot_tables.h> -#include <bootstate.h> #include <bootmem.h> #include <console/console.h> #include <cbmem.h> diff --git a/src/mainboard/google/hatch/variants/jinlon/mainboard.c b/src/mainboard/google/hatch/variants/jinlon/mainboard.c index 6e0315b..6fde602 100644 --- a/src/mainboard/google/hatch/variants/jinlon/mainboard.c +++ b/src/mainboard/google/hatch/variants/jinlon/mainboard.c @@ -4,7 +4,6 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> -#include <bootstate.h> #include <ec/google/chromeec/ec.h> #include <device/device.h> #include <drivers/gfx/generic/chip.h> diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c index 287623e..dd40848 100644 --- a/src/mainboard/intel/strago/mainboard.c +++ b/src/mainboard/intel/strago/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootstate.h> #include <device/device.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/protectli/vault_kbl/ramstage.c b/src/mainboard/protectli/vault_kbl/ramstage.c index 266094a4..962702f 100644 --- a/src/mainboard/protectli/vault_kbl/ramstage.c +++ b/src/mainboard/protectli/vault_kbl/ramstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <bootstate.h> #include <soc/ramstage.h> #include "gpio.h" diff --git a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c index 8c9daf7..5de606d 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c +++ b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootstate.h> #include <soc/ramstage.h> #include <variant/gpio.h> diff --git a/src/soc/amd/common/block/psp/psp_gen1.c b/src/soc/amd/common/block/psp/psp_gen1.c index 703af9d..5096dd3 100644 --- a/src/soc/amd/common/block/psp/psp_gen1.c +++ b/src/soc/amd/common/block/psp/psp_gen1.c @@ -4,7 +4,6 @@ #include <cbfs.h> #include <region_file.h> #include <timer.h> -#include <bootstate.h> #include <console/console.h> #include <amdblocks/psp.h> #include <soc/iomap.h> diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index cf9b532..59e6255 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -2,7 +2,6 @@ #include <device/mmio.h> #include <timer.h> -#include <bootstate.h> #include <amdblocks/psp.h> #include <soc/iomap.h> #include "psp_def.h" diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c index 024e952..b103b3e 100644 --- a/src/soc/amd/common/block/psp/psp_smm.c +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -5,7 +5,6 @@ #include <cpu/amd/msr.h> #include <cbfs.h> #include <region_file.h> -#include <bootstate.h> #include <rules.h> #include <console/console.h> #include <amdblocks/psp.h> diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index f593664..9c26f35 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootstate.h> #include <cpu/amd/mtrr.h> #include <console/console.h> #include <device/device.h> diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index 30d7b20..408017f 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootstate.h> #include <cbmem.h> #include <console/console.h> #include <elog.h> diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 101ab92..893a6b6 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -2,7 +2,6 @@ #include <arch/cpu.h> #include <acpi/acpi.h> -#include <bootstate.h> #include <cbmem.h> #include <console/console.h> #include <cpu/intel/microcode.h> diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index 2696777..93fcee2 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootstate.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c index 3d0ba1a..690fb5f 100644 --- a/src/soc/intel/common/vbt.c +++ b/src/soc/intel/common/vbt.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <bootmode.h> -#include <bootstate.h> #include "vbt.h" #include <drivers/intel/gma/opregion.h> diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index a1ef06e..6ef01d8 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootstate.h> #include <cbmem.h> #include <fsp/api.h> #include <acpi/acpi.h> diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 845becc..bfa59fe 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/cpu.h> -#include <bootstate.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 62e3711..bf3c77b 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -6,7 +6,6 @@ * Chapter number: 4 */ -#include <bootstate.h> #include <console/console.h> #include <device/mmio.h> #include <device/device.h> diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 9d57554..cddada1 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootstate.h> #include <device/device.h> #include <device/pci.h> #include <console/console.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/41671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1 Gerrit-Change-Number: 41671 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit June 2020