coreboot-gerrit June 2020

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Change in coreboot[master]: mb/google/hatch: Enable the CSE Lite SKU for Puff variants
by V Sowmya (Code Review) 02 Jun '20

02 Jun '20

Hello build bot (Jenkins), Furquan Shaikh, Jamie Chen, Rizwan Qureshi, Sridhar Siricilla, Balaji Manigandan, Kane Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41199 to look at the new patch set (#8). Change subject: mb/google/hatch: Enable the CSE Lite SKU for Puff variants ...................................................................... mb/google/hatch: Enable the CSE Lite SKU for Puff variants This patch enables enables the CSE Lite SKU for all the puff variant boards. BUG=b:143229683 TEST=Build and boot puff with CSE Lite SKU. Cq-Depend: chrome-internal:3046770 Change-Id: I0de6bca162b01870ca554ae97bc4a41cf66fef18 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/google/hatch/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/41199/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/41199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0de6bca162b01870ca554ae97bc4a41cf66fef18 Gerrit-Change-Number: 41199 Gerrit-PatchSet: 8 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/vpd: add function to find default boolean key value
by Jonathan Zhang (Code Review) 02 Jun '20

02 Jun '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41586 ) Change subject: drivers/vpd: add function to find default boolean key value ...................................................................... drivers/vpd: add function to find default boolean key value This change is based on the concept that system user's overwrite settings are held in VPD_RW region, while system owner's (default) settings are held in VPD_RO region. Add vpd_get_bool_ex() to find value of boolean type vpd key. VPD_RW is searched first; If not found in VPD_RW, then search VPD_RO. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I960688d1f6ab199768107ab73b8a7400a3fdf473 --- M src/drivers/vpd/vpd.c M src/drivers/vpd/vpd.h 2 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/41586/1 diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index 7ed1255..74ac700 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -227,3 +227,22 @@ } else return false; } + +/* + * This function finds value of boolean type vpd key with the + * concept of default value being held in VPD_RO, and overwrite + * value being held in VPD_RW. + * + * True is returned if key found in VPD_RW, otherwise VPD_RO + * is searched. The value is held in *val if true is returned. + */ +bool vpd_get_bool_ex(const char *key, uint8_t *val) +{ + if (vpd_get_bool(key, VPD_RW, val)) + return true; + + if (vpd_get_bool(key, VPD_RO, val)) + return true; + + return false; +} diff --git a/src/drivers/vpd/vpd.h b/src/drivers/vpd/vpd.h index 05b7db8..cfc339d 100644 --- a/src/drivers/vpd/vpd.h +++ b/src/drivers/vpd/vpd.h @@ -76,4 +76,14 @@ bool vpd_get_bool(const char *key, enum vpd_region region, uint8_t *val); +/* + * This function finds value of boolean type vpd key with the + * concept of default value being held in VPD_RO, and overwrite + * value being held in VPD_RW. + * + * True is returned if key found in VPD_RW, otherwise VPD_RO + * is searched. The value is held in *val if true is returned. + */ +bool vpd_get_bool_ex(const char *key, uint8_t *val) + #endif /* __VPD_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I960688d1f6ab199768107ab73b8a7400a3fdf473 Gerrit-Change-Number: 41586 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

6 18

Change in coreboot[master]: drivers/uart/util.c: Add missing 'include <commonlib/bsd/helpers.h>
by HAOUAS Elyes (Code Review) 02 Jun '20

02 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41678 ) Change subject: drivers/uart/util.c: Add missing 'include <commonlib/bsd/helpers.h> ...................................................................... drivers/uart/util.c: Add missing 'include <commonlib/bsd/helpers.h> Change-Id: If7d10036ab3047a9f2480e7ed04c6a6c7033ee27 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/uart/util.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/41678/1 diff --git a/src/drivers/uart/util.c b/src/drivers/uart/util.c index 1ac994e..f18a99d 100644 --- a/src/drivers/uart/util.c +++ b/src/drivers/uart/util.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/uart.h> -#include <types.h> +#include <commonlib/bsd/helpers.h> #include <timer.h> /* Calculate divisor. Do not floor but round to nearest integer. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7d10036ab3047a9f2480e7ed04c6a6c7033ee27 Gerrit-Change-Number: 41678 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: soc/intel/apollolake: Save/restore GMA OpRegion address
by Patrick Georgi (Code Review) 02 Jun '20

02 Jun '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25416 ) Change subject: soc/intel/apollolake: Save/restore GMA OpRegion address ...................................................................... Patch Set 5: CB:40724 has been merged. What needs to happen to this patch train? -- To view, visit https://review.coreboot.org/c/coreboot/+/25416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4123998b0ab3c263c6a9ff14084a0d8808e5f4cd Gerrit-Change-Number: 25416 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Tue, 02 Jun 2020 07:57:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mtrr.h: Get rid of commonlib/helpers.h dependency
by Nico Huber (Code Review) 02 Jun '20

02 Jun '20

Hello Kyösti Mälkki, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41785 to review the following change. Change subject: cpu/x86/mtrr.h: Get rid of commonlib/helpers.h dependency ...................................................................... cpu/x86/mtrr.h: Get rid of commonlib/helpers.h dependency We want to use the CACHE_ROM_* macros in linker scripts. Avoid `commonlib/helpers.h` as it contains an incompatible ALIGN() definition. Change-Id: I3bf20733418ca4135f364a3f6489e74d45e4f466 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/include/cpu/x86/mtrr.h 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/41785/1 diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 50148ff..301ea30 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -1,7 +1,6 @@ #ifndef CPU_X86_MTRR_H #define CPU_X86_MTRR_H -#include <commonlib/helpers.h> #ifndef __ASSEMBLER__ #include <cpu/x86/msr.h> #include <arch/cpu.h> @@ -187,8 +186,8 @@ /* Last but not least, most (if not all) chipsets have MMIO between 0xfe000000 and 0xff000000, so limit to 16MiB. */ -#if CAR_CACHE_ROM_SIZE >= 16 * MiB -# define CACHE_ROM_SIZE (16 * MiB) +#if CAR_CACHE_ROM_SIZE >= 16 << 20 +# define CACHE_ROM_SIZE (16 << 20) #else # define CACHE_ROM_SIZE CAR_CACHE_ROM_SIZE #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/41785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bf20733418ca4135f364a3f6489e74d45e4f466 Gerrit-Change-Number: 41785 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

7 12

Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/cpx_sp: update to FSP WW20 release
by Patrick Georgi (Code Review) 02 Jun '20

02 Jun '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40034 ) Change subject: vendorcode/intel/fsp/fsp2_0/cpx_sp: update to FSP WW20 release ...................................................................... vendorcode/intel/fsp/fsp2_0/cpx_sp: update to FSP WW20 release Update Cooperlake-SP (CPX-SP) FSP header files to WW20 release. As CPX-SP FSP engineering is on-going (the processor Mass Production is some time in this year). These header files will be adjusted when changes are necessary with newer FSP release. This commit corresponds to FSP release WW20 (tag WHITLEY.0.PRB.0016.D.65). Also update soc/xeon_sp code file and Skylake-SP header file accordingly to use FsptPort80RouteDisable instead of PcdPort80RouteDisable. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com> Change-Id: I8bc6882e47de23d83ba0f521bb12a10dace523ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/40034 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/soc/intel/xeon_sp/bootblock.c A src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h A src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/gpio_fsp.h A src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h A src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h 10 files changed, 1,540 insertions(+), 36 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 72d9742..f6653e2 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -25,7 +25,7 @@ .Reserved1 = {0}, }, .FsptConfig = { - .PcdFsptPort80RouteDisable = 0, + .FsptPort80RouteDisable = 0, .ReservedTempRamInitUpd = {0}, }, .UnusedUpdSpace0 = {0}, diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h new file mode 100644 index 0000000..98a16d7 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h @@ -0,0 +1,68 @@ +/** @file + Header file for Firmware Version Information + + @copyright + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved. + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License which accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ +#define _FIRMWARE_VERSION_INFO_HOB_H_ + +#include <Uefi/UefiMultiPhase.h> +#include <Pi/PiBootMode.h> +#include <Pi/PiHob.h> + +#pragma pack(1) +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} FIRMWARE_VERSION; + +/// +/// Firmware Version Information Structure +/// +typedef struct { + UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name + UINT8 VersionStringIndex; ///< Offset 1 Index of Version String + FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version +} FIRMWARE_VERSION_INFO; + +#ifndef __SMBIOS_STANDARD_H__ +/// +/// The Smbios structure header. +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Handle; +} SMBIOS_STRUCTURE; +#endif + +/// +/// Firmware Version Information HOB Structure +/// +typedef struct { + EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB + SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB + UINT8 Count; ///< Offset 28 Number of FVI elements included. +/// +/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer +/// +} FIRMWARE_VERSION_INFO_HOB; +#pragma pack() + +#endif // _FIRMWARE_VERSION_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h index 086c118..7491aca 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h @@ -1,18 +1,48 @@ -/* - * These are fake files which only contain padding and some known - * data structures from FSP2.x spec. - */ +/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ #ifndef __FSPUPD_H__ #define __FSPUPD_H__ -#include <stdint.h> #include <FspEas.h> -#define FSP_M_CONFIG FSPM_CONFIG +#pragma pack(1) -#define FSPT_UPD_SIGNATURE 0x545F445055434F53ULL /* 'SOCUPD_T' */ -#define FSPM_UPD_SIGNATURE 0x4D5F445055434F53ULL /* 'SOCUPD_M' */ -#define FSPS_UPD_SIGNATURE 0x535F445055434F53ULL /* 'SOCUPD_S' */ +#define FSPT_UPD_SIGNATURE 0x545F445055434F53 /* 'SOCUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F445055434F53 /* 'SOCUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F445055434F53 /* 'SOCUPD_S' */ + +#pragma pack() #endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index bdd80ec..c4c23df 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -1,22 +1,566 @@ +/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + #ifndef __FSPMUPD_H__ #define __FSPMUPD_H__ -#include <FspEas.h> #include <FspUpd.h> -#pragma pack (1) +#define SPEED_REC_96GT 0 +#define SPEED_REC_104GT 1 +#define ADAPTIVE_CTLE 0x3f -typedef struct { -uint8_t padding[208]; -} FSPM_CONFIG; +#define CPXSP_2S6KTI_EPARAM_TABLE \ + /* Socket 0 */ \ + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), 0x2C33383F, ADAPTIVE_CTLE}, \ + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), 0x2B35353F, ADAPTIVE_CTLE}, \ + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK2), 0x2D37353F, ADAPTIVE_CTLE}, \ + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK3), 0x2D37353F, ADAPTIVE_CTLE}, \ + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK4), 0x2D37353F, ADAPTIVE_CTLE}, \ + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), 0x2C35363F, ADAPTIVE_CTLE}, \ + /* Socket 1 */ \ + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), 0x2C33383F, ADAPTIVE_CTLE}, \ + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), 0x2B35353F, ADAPTIVE_CTLE}, \ + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK2), 0x2D35373F, ADAPTIVE_CTLE}, \ + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK3), 0x2D35373F, ADAPTIVE_CTLE}, \ + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK4), 0x2A2F3A3F, ADAPTIVE_CTLE}, \ + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), 0x2C35363F, ADAPTIVE_CTLE} -typedef struct { - FSP_UPD_HEADER FspUpdHeader; - FSPM_ARCH_UPD FspmArchUpd; - FSPM_CONFIG FspmConfig; - uint16_t UpdTerminator; -} FSPM_UPD; +#define CPXSP_2S6KTI_EPARAM_TABLE_COUNT 12 // NOTE - needs to match number of elements in CPXSP_2S6KTI_EPARAM_TABLE + #pragma pack(1) +typedef struct { + UINT8 SocketID; + UINT8 Freq; + UINT32 Link; + UINT32 AllLanesTXEQ; + UINT8 CTLEPEAK; +} ALL_LANES_EPARAM_LINK_INFO; + +typedef enum { + KTI_LINK0 = 0x0, + KTI_LINK1, + KTI_LINK2, + KTI_LINK3, + KTI_LINK4, + KTI_LINK5 +} KTI_LOGIC_LINK; + +#define IIO_BIFURCATE_xxxxxxxx 0xFE +#define IIO_BIFURCATE_x4x4x4x4 0x0 +#define IIO_BIFURCATE_x4x4xxx8 0x1 +#define IIO_BIFURCATE_xxx8x4x4 0x2 +#define IIO_BIFURCATE_xxx8xxx8 0x3 +#define IIO_BIFURCATE_xxxxxx16 0x4 +#define IIO_BIFURCATE_x2x2x4x8 0x5 +#define IIO_BIFURCATE_x4x2x2x8 0x6 +#define IIO_BIFURCATE_x8x2x2x4 0x7 +#define IIO_BIFURCATE_x8x4x2x2 0x8 +#define IIO_BIFURCATE_x2x2x4x4x4 0x9 +#define IIO_BIFURCATE_x4x2x2x4x4 0xA +#define IIO_BIFURCATE_x4x4x2x2x4 0xB +#define IIO_BIFURCATE_x4x4x4x2x2 0xC +#define IIO_BIFURCATE_x2x2x2x2x8 0xD +#define IIO_BIFURCATE_x8x2x2x2x2 0xE +#define IIO_BIFURCATE_x2x2x2x2x4x4 0xF +#define IIO_BIFURCATE_x2x2x4x2x2x4 0x10 +#define IIO_BIFURCATE_x2x2x4x4x2x2 0x11 +#define IIO_BIFURCATE_x4x2x2x2x2x4 0x12 +#define IIO_BIFURCATE_x4x2x2x4x2x2 0x13 +#define IIO_BIFURCATE_x4x4x2x2x2x2 0x14 +#define IIO_BIFURCATE_x2x2x2x2x2x2x4 0x15 +#define IIO_BIFURCATE_x2x2x2x2x4x2x2 0x16 +#define IIO_BIFURCATE_x2x2x4x2x2x2x2 0x17 +#define IIO_BIFURCATE_x4x2x2x2x2x2x2 0x18 +#define IIO_BIFURCATE_x2x2x2x2x2x2x2x2 0x19 +#define IIO_BIFURCATE_AUTO 0xFF + +typedef struct { + UINT8 Socket; + UINT8 IouNumber; + UINT8 Bifurcation; +} UPD_IIO_BIFURCATION_DATA_ENTRY; + +typedef enum { + Iio_Socket0 = 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 = 0, + Iio_Iou1, + Iio_Iou2, + Iio_Iou3, + Iio_Mcp0, + Iio_Mcp1, + Iio_IouMax +} IIO_IOUS; + +/** FSP-M Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Customer Revision + The Customer can set this revision string for their own purpose. +**/ + UINT8 CustomerRevision[32]; + +/** Offset 0x0060 - Bus Ratio + Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO +**/ + UINT8 BusRatio[8]; + +/** Offset 0x0068 - D2K Credit Config + Set the D2K Credit Config + 1:Min, 2:Med, 3:Max +**/ + UINT8 D2KCreditConfig; + +/** Offset 0x0069 - Snoop Throttle Config + Set the Snoop Throttle Config + 0:DIS, 1:Min, 2:Med, 3:Max +**/ + UINT8 SnoopThrottleConfig; + +/** Offset 0x006A - Legacy VGA Soc + Socket that claims the legacy VGA range +**/ + UINT8 LegacyVgaSoc; + +/** Offset 0x006B - Legacy VGA Stack + Stack that claims the legacy VGA range +**/ + UINT8 LegacyVgaStack; + +/** Offset 0x006C - Pcie P2P Performance Mode + Determine if to enable PCIe P2P Performance Mode + $EN_DIS +**/ + UINT8 P2pRelaxedOrdering; + +/** Offset 0x006D - Debug Print Level + Set Debug Print Level + 1:Fatal, 2:Warning, 4:Summary, 8:Detail, 0x0F:All +**/ + UINT8 DebugPrintLevel; + +/** Offset 0x006E - SNC + Enable or Disable SNC + $EN_DIS +**/ + UINT8 SncEn; + +/** Offset 0x006F - UMA Clustering + Set UMA Clusters + 0:Disable, 2:Two Clusters, 4:Four Clusters +**/ + UINT8 UmaClustering; + +/** Offset 0x0070 - IODC Mode + IODC Setup Option + 0:Disable, 1:Auto, 2:Push, 3:AllocFlow 4:NonAlloc, 5:WCILF +**/ + UINT8 IoDcMode; + +/** Offset 0x0071 - Degrade Precedence + Setup Degrade Precedence + 0:Topology, 1:Feature +**/ + UINT8 DegradePrecedence; + +/** Offset 0x0072 - Degrade 4 Socket Preference + Setup Degrade 4 Socket Preference + 0:Fully Connect, 1:Dual Link Ring +**/ + UINT8 Degrade4SPreference; + +/** Offset 0x0073 - Directory Mode + Enable or Disable Directory Mode + $EN_DIS +**/ + UINT8 DirectoryModeEn; + +/** Offset 0x0074 - XPT Prefetch Enable + Enable or Disable XPT Prefetch +**/ + UINT8 XptPrefetchEn; + +/** Offset 0x0075 - KTI Prefetch Enable + Enable or Disable KTI Prefetch + $EN_DIS +**/ + UINT8 KtiPrefetchEn; + +/** Offset 0x0076 - XPT Remote Prefetch Enable + Enable or Disable XPT Remote Prefetch Enable + $EN_DIS +**/ + UINT8 XptRemotePrefetchEn; + +/** Offset 0x0077 - KTI FPGA + Enable or Disable KTI FPGA + $EN_DIS +**/ + UINT8 KtiFpgaEnable[8]; + +/** Offset 0x007F - DDRT QoS Mode + Setup DDRT QoS +**/ + UINT8 DdrtQosMode; + +/** Offset 0x0080 - KTI Link Speed Mode + Choose KTI Link Speed Mode +**/ + UINT8 KtiLinkSpeedMode; + +/** Offset 0x0081 - KTI Link Speed + Setup KTI Link Speed +**/ + UINT8 KtiLinkSpeed; + +/** Offset 0x0082 - KTI Link L0p + Enable or Disable KTI Link L0p +**/ + UINT8 KtiLinkL0pEn; + +/** Offset 0x0083 - KTI Link L1 + Enable or Disable KTI Link L1 +**/ + UINT8 KtiLinkL1En; + +/** Offset 0x0084 - KTI Failover + Enable or Disable KTI Failover +**/ + UINT8 KtiFailoverEn; + +/** Offset 0x0085 - KTI LB Enable + Enable or Disable KTI LB + $EN_DIS +**/ + UINT8 KtiLbEn; + +/** Offset 0x0086 - KTI CRC Mode + Select KTI CRC Mode + 0:16bit, 1:32bit, 2:Auto +**/ + UINT8 KtiCrcMode; + +/** Offset 0x0087 - KTI CPU Socket Hotplug + Enable or Disable KTI CPU Socket Hotplug + $EN_DIS +**/ + UINT8 KtiCpuSktHotPlugEn; + +/** Offset 0x0088 - KTI CPU Socket HotPlug Topology + Select KTI CPU Socket HotPlug Topology + 0:4Socket, 1:8Socket +**/ + UINT8 KtiCpuSktHotPlugTopology; + +/** Offset 0x0089 - KTI SKU Mismatch Check + Enable or Disable KTI SKU Mismatch Check + $EN_DIS +**/ + UINT8 KtiSkuMismatchCheck; + +/** Offset 0x008A - IRQ Threshold + Select IRQ Threshold + 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High +**/ + UINT8 IrqThreshold; + +/** Offset 0x008B - IRQ Threshold + Enable or Disable + 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High +**/ + UINT8 TorThresLoctoremNorm; + +/** Offset 0x008C - TOR threshold - Loctorem threshold empty + Select TOR threshold - Loctorem threshold empty + 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High +**/ + UINT8 TorThresLoctoremEmpty; + +/** Offset 0x008D - TSC Sync in Sockets + Enable or Disable TSC Sync in Sockets +**/ + UINT8 TscSyncEn; + +/** Offset 0x008E - HA A to S directory optimization + Enable or Disable HA A to S directory optimization +**/ + UINT8 StaleAtoSOptEn; + +/** Offset 0x008F - LLC Deadline Allocation + Enable or Disable LLC Deadline Allocation + $EN_DIS +**/ + UINT8 LLCDeadLineAlloc; + +/** Offset 0x0090 - Split Lock + Enable or Disable Split Lock +**/ + UINT8 SplitLock; + +/** Offset 0x0091 - MMCFG Base Address + Setup MMCFG Base Address + 0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6:Auto +**/ + UINT8 mmCfgBase; + +/** Offset 0x0092 - MMCFG Size + Select MMCFG Size + 0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6: Auto +**/ + UINT8 mmCfgSize; + +/** Offset 0x0093 +**/ + UINT8 UnusedUpdSpace0; + +/** Offset 0x0094 - MMIO Low Base Address + Select MMIO Low Base Address + 0:, 1:, 2:, 3:, 4:, 5:, 6: +**/ + UINT32 mmiolBase; + +/** Offset 0x0098 - MMIO Low Size + Select MMIO Low Size + $EN_DIS +**/ + UINT32 mmiolSize; + +/** Offset 0x009C - MMIO High Base Address + Select MMIO High Base Address + 0:, 1:, 2:, 3:, 4:, 5:, 6: +**/ + UINT32 mmiohBase; + +/** Offset 0x00A0 - High Gap + Enable or Disable High Gap + $EN_DIS +**/ + UINT8 highGap; + +/** Offset 0x00A1 +**/ + UINT8 UnusedUpdSpace1; + +/** Offset 0x00A2 - MMIO High Size + Select MMIO High Size + 0:, 1:, 2:, 3:, 4:, 5:, 6: +**/ + UINT16 mmiohSize; + +/** Offset 0x00A4 - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT8 isocEn; + +/** Offset 0x00A5 - DCA + Enable or Disable DCA + $EN_DIS +**/ + UINT8 dcaEn; + +/** Offset 0x00A6 +**/ + UINT8 UnusedUpdSpace2[2]; + +/** Offset 0x00A8 - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT32 BoardTypeBitmask; + +/** Offset 0x00AC - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT32 AllLanesPtr; + +/** Offset 0x00B0 - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT32 PerLanePtr; + +/** Offset 0x00B4 - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT32 AllLanesSizeOfTable; + +/** Offset 0x00B8 - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT32 PerLaneSizeOfTable; + +/** Offset 0x00BC - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT32 WaitTimeForPSBP; + +/** Offset 0x00C0 - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT8 IsKtiNvramDataReady; + +/** Offset 0x00C1 +**/ + UINT8 UnusedUpdSpace3[3]; + +/** Offset 0x00C4 - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT32 OemHookPostTopologyDiscovery; + +/** Offset 0x00C8 - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT32 OemGetResourceMapUpdate; + +/** Offset 0x00CC - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT8 BoardId; + +/** Offset 0x00CD - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT8 WaSerializationEn; + +/** Offset 0x00CE - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT8 KtiInEnableMktme; + +/** Offset 0x00CF +**/ + UINT8 UnusedUpdSpace4; + +/** Offset 0x00D0 - Address of IIoBifurcationTable. + The address of the table of IIoBifurcation. + $EN_DIS +**/ + UINT32 IIoBifurcationTablePtr; + +/** Offset 0x00D4 - Number of IIoBifurcationTable Entry + Number of IIoBifurcationTable Entry. If this is not zero, the IIoBifurcationTablePtr + must not be NULL. +**/ + UINT8 NumOfIIoBifurcationTable; + +/** Offset 0x00D5 - PchAdrEn + Enable or Disable PchAdr +**/ + UINT8 PchAdrEn; + +/** Offset 0x00D6 - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT8 PchPcieRootPortFunctionSwap; + +/** Offset 0x00D7 - PCH PCIE PLL Ssc + Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC + of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF +**/ + UINT8 PchPciePllSsc; + +/** Offset 0x00D8 - Usage type for PCH PCIE Root Port Index + Index assigned to every PCH PCIE Root Port +**/ + UINT8 PchPciePortIndex[20]; + +/** Offset 0x00EC - Usage type for PCH PCIE Root Port Enable or Disable + 0-19: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use + (free running), 0xFF: not used +**/ + UINT8 PchPcieForceEnable[20]; + +/** Offset 0x0100 - Usage type for PCH PCIE Root Port Link Speed + 0-19: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use + (free running), 0xFF: not used +**/ + UINT8 PchPciePortLinkSpeed[20]; + +/** Offset 0x0114 +**/ + UINT8 ReservedMemoryInitUpd[16]; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSP_M_CONFIG FspmConfig; + +/** Offset 0x0124 +**/ + UINT8 UnusedUpdSpace5[2]; + +/** Offset 0x0126 +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + #endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h index 646c1e2..fc08084 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h @@ -1,20 +1,184 @@ +/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + #ifndef __FSPSUPD_H__ #define __FSPSUPD_H__ -#pragma pack(1) - #include <FspUpd.h> +#pragma pack(1) + + +/** FSP-S Configuration +**/ typedef struct { - uint8_t padding[54]; + +/** Offset 0x0020 - PCIe Controller 0 Bifurcation + Configure PCI Express controller 0 bifurcation. + 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 +**/ + UINT8 BifurcationPcie0; + +/** Offset 0x0021 - PCIe Controller 1 Bifurcation + Configure PCI Express controller 1 bifurcation. + 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 +**/ + UINT8 BifurcationPcie1; + +/** Offset 0x0022 - Active Core Count + Select # of Active Cores (Default: 0, 0:ALL, 1..15 = 1..15 Cores) + 0:ALL, 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, + 14:14, 15:15 +**/ + UINT8 ActiveCoreCount; + +/** Offset 0x0023 +**/ + UINT8 UnusedUpdSpace0; + +/** Offset 0x0024 +**/ + UINT32 CpuMicrocodePatchBase; + +/** Offset 0x0028 +**/ + UINT32 CpuMicrocodePatchSize; + +/** Offset 0x002C - PCIe Controller 0 + Enable / Disable PCI Express controller 0 + $EN_DIS +**/ + UINT8 EnablePcie0; + +/** Offset 0x002D - PCIe Controller 1 + Enable / Disable PCI Express controller 1 + $EN_DIS +**/ + UINT8 EnablePcie1; + +/** Offset 0x002E - Embedded Multi-Media Controller (eMMC) + Enable / Disable Embedded Multi-Media controller + $EN_DIS +**/ + UINT8 EnableEmmc; + +/** Offset 0x002F - LAN Controllers + Enable / Disable LAN controllers, refer to FSP Integration Guide for details. + 0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only +**/ + UINT8 EnableGbE; + +/** Offset 0x0030 +**/ + UINT32 FiaMuxConfigRequestPtr; + +/** Offset 0x0034 - PCIe Root Port 0 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcieRootPort0DeEmphasis; + +/** Offset 0x0035 - PCIe Root Port 1 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcieRootPort1DeEmphasis; + +/** Offset 0x0036 - PCIe Root Port 2 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcieRootPort2DeEmphasis; + +/** Offset 0x0037 - PCIe Root Port 3 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcieRootPort3DeEmphasis; + +/** Offset 0x0038 - PCIe Root Port 4 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcieRootPort4DeEmphasis; + +/** Offset 0x0039 - PCIe Root Port 5 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcieRootPort5DeEmphasis; + +/** Offset 0x003A - PCIe Root Port 6 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcieRootPort6DeEmphasis; + +/** Offset 0x003B - PCIe Root Port 7 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcieRootPort7DeEmphasis; + +/** Offset 0x003C +**/ + UINT32 EMMCDLLConfigPtr; + +/** Offset 0x0040 +**/ + UINT8 ReservedSiliconInitUpd[16]; } FSPS_CONFIG; +/** Fsp S UPD Configuration +**/ typedef struct { + +/** Offset 0x0000 +**/ FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ FSPS_CONFIG FspsConfig; - uint16_t UpdTerminator; + +/** Offset 0x0050 +**/ + UINT8 UnusedUpdSpace1[6]; + +/** Offset 0x0056 +**/ + UINT16 UpdTerminator; } FSPS_UPD; -#pragma pack(1) +#pragma pack() #endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h index a792e70..b3c9661 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h @@ -1,3 +1,35 @@ +/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + #ifndef __FSPTUPD_H__ #define __FSPTUPD_H__ @@ -5,25 +37,71 @@ #pragma pack(1) + +/** FSP-T Core UPD +**/ typedef struct { - uint32_t MicrocodeRegionBase; - uint32_t MicrocodeRegionLength; - uint32_t CodeRegionBase; - uint32_t CodeRegionLength; - uint8_t Reserved1[16]; + +/** Offset 0x0020 +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x0024 +**/ + UINT32 MicrocodeRegionLength; + +/** Offset 0x0028 +**/ + UINT32 CodeRegionBase; + +/** Offset 0x002C +**/ + UINT32 CodeRegionLength; + +/** Offset 0x0030 +**/ + UINT8 Reserved1[16]; } FSPT_CORE_UPD; +/** FSP-T Configuration +**/ typedef struct { - uint8_t PcdFsptPort80RouteDisable; - uint8_t ReservedTempRamInitUpd[31]; + +/** Offset 0x0040 - Disable Port80 output in FSP-T + Select Port80 Control in FSP-T (0:VPD-Style, 1:Enable Port80 Output, 2:Disable Port80 + Output, refer to FSP Integration Guide for details + 0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output +**/ + UINT8 FsptPort80RouteDisable; + +/** Offset 0x0041 +**/ + UINT8 ReservedTempRamInitUpd[31]; } FSPT_CONFIG; +/** Fsp T UPD Configuration +**/ typedef struct { + +/** Offset 0x0000 +**/ FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ FSPT_CORE_UPD FsptCoreUpd; + +/** Offset 0x0040 +**/ FSPT_CONFIG FsptConfig; - uint8_t UnusedUpdSpace0[6]; - uint16_t UpdTerminator; + +/** Offset 0x0060 +**/ + UINT8 UnusedUpdSpace0[6]; + +/** Offset 0x0066 +**/ + UINT16 UpdTerminator; } FSPT_UPD; #pragma pack() diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/gpio_fsp.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/gpio_fsp.h new file mode 100644 index 0000000..be9d33f --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/gpio_fsp.h @@ -0,0 +1,205 @@ +/** +Copyright (c) 2019-2020, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + + +#ifndef _GPIO_FSP_H_ +#define _GPIO_FSP_H_ + +// +// Below defines are based on GPIO_CONFIG structure fields +// +#define GPIO_CONF_PAD_MODE_MASK 0xF +#define GPIO_CONF_PAD_MODE_BIT_POS 0 +#define GPIO_CONF_HOST_OWN_MASK 0x3 +#define GPIO_CONF_HOST_OWN_BIT_POS 0 +#define GPIO_CONF_DIR_MASK 0x7 +#define GPIO_CONF_DIR_BIT_POS 0 +#define GPIO_CONF_INV_MASK 0x18 +#define GPIO_CONF_INV_BIT_POS 3 +#define GPIO_CONF_OUTPUT_MASK 0x3 +#define GPIO_CONF_OUTPUT_BIT_POS 0 +#define GPIO_CONF_INT_ROUTE_MASK 0x1F +#define GPIO_CONF_INT_ROUTE_BIT_POS 0 +#define GPIO_CONF_INT_TRIG_MASK 0xE0 +#define GPIO_CONF_INT_TRIG_BIT_POS 5 +#define GPIO_CONF_RESET_MASK 0x7 +#define GPIO_CONF_RESET_BIT_POS 0 +#define GPIO_CONF_TERM_MASK 0x1F +#define GPIO_CONF_TERM_BIT_POS 0 +#define GPIO_CONF_PADTOL_MASK 0x60 +#define GPIO_CONF_PADTOL_BIT_POS 5 +#define GPIO_CONF_LOCK_MASK 0x7 +#define GPIO_CONF_LOCK_BIT_POS 0 +#define GPIO_CONF_RXRAW_MASK 0x3 +#define GPIO_CONF_RXRAW_BIT_POS 0 + +typedef enum { GpioHardwareDefault = 0x0 } GPIO_HARDWARE_DEFAULT; + +/// +/// GPIO Pad Mode +/// +typedef enum { + GpioPadModeGpio = 0x1, + GpioPadModeNative1 = 0x3, + GpioPadModeNative2 = 0x5, + GpioPadModeNative3 = 0x7, + GpioPadModeNative4 = 0x9 +} GPIO_PAD_MODE; + +/// +/// Host Software Pad Ownership modes +/// +typedef enum { + GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified + GpioHostOwnAcpi = 0x1, ///< Set HOST ownership to ACPI + GpioHostOwnGpio = 0x3 ///< Set HOST ownership to GPIO +} GPIO_HOSTSW_OWN; + +/// +/// GPIO Direction +/// +typedef enum { + GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified + GpioDirInOut = + (0x1 | (0x1 << 3)), ///< Set pad for both output and input + GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and + ///input with inversion + GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only + GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion + GpioDirOut = 0x5, ///< Set pad for output only + GpioDirNone = 0x7 ///< Disable both output and input +} GPIO_DIRECTION; + +/// +/// GPIO Output State +/// +typedef enum { + GpioOutDefault = 0x0, ///< Leave output value unmodified + GpioOutLow = 0x1, ///< Set output to low + GpioOutHigh = 0x3 ///< Set output to high +} GPIO_OUTPUT_STATE; + +/// +/// GPIO interrupt configuration +/// This setting is applicable only if GPIO is in input mode. +/// GPIO_INT_CONFIG allows to choose which interrupt is generated +/// (IOxAPIC/SCI/SMI/NMI) +/// and how it is triggered (edge or level). +/// Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to +/// GpioIntBothEdgecan +/// to describe an interrupt e.g. GpioIntApic | GpioIntLevel +/// If GPIO is set to cause an SCI then also Gpe is enabled for this pad. +/// Not all GPIO are capable of generating an SMI or NMI interrupt +/// + +typedef enum { + GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified + GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation + GpioIntNmi = 0x3, ///< Enable NMI interrupt only + GpioIntSmi = 0x5, ///< Enable SMI interrupt only + GpioIntSci = 0x9, ///< Enable SCI interrupt only + GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only + GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered + GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of + ///edge depends on input inversion) + GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger + GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered +} GPIO_INT_CONFIG; + +/// +/// GPIO Power Configuration +/// GPIO_RESET_CONFIG allows to set GPIO Reset (used to reset the specified +/// Pad Register fields). +/// +typedef enum { + GpioResetDefault = 0x0, ///< Leave value of pad reset unmodified + GpioResetPwrGood = 0x1, ///< Powergood reset + GpioResetDeep = 0x3, ///< Deep GPIO Reset + GpioResetNormal = 0x5, ///< GPIO Reset + GpioResetResume = 0x7 ///< Resume Reset (applicable only for GPD group) +} GPIO_RESET_CONFIG; + +/// +/// GPIO Electrical Configuration +/// Set GPIO termination and Pad Tolerance (applicable only for some pads) +/// Field from GpioTermDefault to GpioTermNative can be OR'ed with +/// GpioTolerance1v8. +/// +typedef enum { + GpioTermDefault = 0x0, ///< Leave termination setting unmodified + GpioTermNone = 0x1, ///< none + GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down + GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down + GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up + GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up + GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up + GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up + GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up + GpioTermNative = 0x1F, ///< Native function controls pads termination + GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance + GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance +} GPIO_ELECTRICAL_CONFIG; + +/// +/// GPIO LockConfiguration +/// Set GPIO configuration lock and output state lock +/// GpioLockPadConfig and GpioLockOutputState can be OR'ed +/// +typedef enum { + GpioLockDefault = 0x0, ///< Leave lock setting unmodified + GpioPadConfigLock = 0x3, ///< Lock Pad Configuration + GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value +} GPIO_LOCK_CONFIG; + +/// +/// Other GPIO Configuration +/// GPIO_OTHER_CONFIG is used for less often settings and for future extensions +/// Supported settings: +/// - RX raw override to '1' - allows to override input value to '1' +/// This setting is applicable only if in input mode (both in GPIO and +/// native usage). +/// The override takes place at the internal pad state directly from buffer +/// and before the RXINV. +/// +typedef enum { + GpioRxRaw1Default = 0x0, ///< Use default input override value + GpioRxRaw1Dis = 0x1, ///< Don't override input + GpioRxRaw1En = 0x3 ///< Override input to '1' +} GPIO_OTHER_CONFIG; + +// +// Possible values of Pad Ownership +// +typedef enum { + GpioPadOwnHost = 0x0, + GpioPadOwnCsme = 0x1, + GpioPadOwnIsh = 0x2, +} GPIO_PAD_OWN; + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h new file mode 100644 index 0000000..1ce5d30 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -0,0 +1,306 @@ +/** +Copyright (c) 2019-2020, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + + +#ifndef _HOB_IIOUDS_H_ +#define _HOB_IIOUDS_H_ + +#include <fsp/util.h> + +#define FSP_HOB_IIO_UNIVERSAL_DATA_GUID { \ + 0xa1, 0x96, 0xf3, 0x7f, 0x7d, 0xee, 0x1e, 0x43, \ + 0xba, 0x53, 0x8f, 0xCa, 0x12, 0x7c, 0x44, 0xc0 \ +} + +#define NUMBER_PORTS_PER_SOCKET 21 +#define MAX_SOCKET 8 // CONFIG_MAX_SOCKET +#define MaxIIO MAX_SOCKET +#define MAX_IIO_STACK 6 +#define MAX_IMC 2 +#define MAX_CH 6 +#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) + +// Maximum KTI PORTS to be used in structure definition +#if (MAX_SOCKET == 1) + #define MAX_FW_KTI_PORTS 3 +#else + #define MAX_FW_KTI_PORTS 6 +#endif //(MAX_SOCKET == 1) + +#define MAX_LOGIC_IIO_STACK (MAX_IIO_STACK+2) + +#pragma pack(1) + +//--------------------------------------------------------------------------------------// +// Structure definitions for Universal Data Store (UDS) +//--------------------------------------------------------------------------------------// + +typedef enum { + TYPE_SCF_BAR = 0, + TYPE_PCU_BAR, + TYPE_MEM_BAR0, + TYPE_MEM_BAR1, + TYPE_MEM_BAR2, + TYPE_MEM_BAR3, + TYPE_MEM_BAR4, + TYPE_MEM_BAR5, + TYPE_MEM_BAR6, + TYPE_MEM_BAR7, + TYPE_SBREG_BAR, + TYPE_MAX_MMIO_BAR +} MMIO_BARS; + +/// +/// RC version number structure. +/// +typedef struct { + uint8_t Major; + uint8_t Minor; + uint8_t Revision; + uint16_t BuildNumber; +} RC_VERSION; + +/** + IIO PCIe Ports + **/ +typedef enum { + PORT_0 = 0, + // IOU0 + PORT_1A, + PORT_1B, + PORT_1C, + PORT_1D, + // IOU1 + PORT_2A, + PORT_2B, + PORT_2C, + PORT_2D, + // IOU2 + PORT_4A, + PORT_4B, + PORT_4C, + PORT_4D, + // MCP0 + PORT_5A, + PORT_5B, + PORT_5C, + PORT_5D, + // MCP1 + PORT_6A, + PORT_6B, + PORT_6C, + PORT_6D, + MAX_PORTS +} PCIE_PORTS; + +/** + IIO Stacks + **/ +typedef enum { + CSTACK = 0, + PSTACK0, + PSTACK1, + PSTACK2, + PSTACK3, + PSTACK4, + MAX_STACKS +} IIO_STACKS; + +typedef struct uint64_t_struct { + uint32_t lo; + uint32_t hi; +} UINT64_STRUCT; + +typedef struct { + uint8_t Device; + uint8_t Function; +} IIO_PORT_INFO; + +typedef struct { + uint8_t Valid; // TRUE, if the link is valid (i.e reached normal operation) + uint8_t PeerSocId; // Socket ID + uint8_t PeerSocType; // Socket Type (0 - CPU; 1 - IIO) + uint8_t PeerPort; // Port of the peer socket +} QPI_PEER_DATA; + +typedef struct { + uint8_t Valid; + uint32_t MmioBar[TYPE_MAX_MMIO_BAR]; + uint8_t PcieSegment; + UINT64_STRUCT SegMmcfgBase; + uint16_t stackPresentBitmap; + uint16_t M2PciePresentBitmap; + uint8_t TotM3Kti; + uint8_t TotCha; + uint32_t ChaList; + uint32_t SocId; + QPI_PEER_DATA PeerInfo[MAX_FW_KTI_PORTS]; // QPI LEP info +} QPI_CPU_DATA; + +typedef struct { + uint8_t Valid; + uint8_t SocId; + QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info +} QPI_IIO_DATA; + +typedef struct { + IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET]; +} IIO_DMI_PCIE_INFO; + +typedef enum { + TYPE_UBOX = 0, + TYPE_UBOX_IIO, + TYPE_MCP, + TYPE_FPGA, + TYPE_HFI, + TYPE_NAC, + TYPE_GRAPHICS, + TYPE_DINO, + TYPE_RESERVED, + TYPE_DISABLED, // This item must be prior to stack specific disable types + TYPE_UBOX_IIO_DIS, + TYPE_MCP_DIS, + TYPE_FPGA_DIS, + TYPE_HFI_DIS, + TYPE_NAC_DIS, + TYPE_GRAPHICS_DIS, + TYPE_DINO_DIS, + TYPE_RESERVED_DIS, + TYPE_NONE +} STACK_TYPE; + +typedef struct _STACK_RES { + uint8_t Personality; // see STACK_TYPE for details + uint8_t BusBase; + uint8_t BusLimit; + uint16_t PciResourceIoBase; + uint16_t PciResourceIoLimit; + uint32_t IoApicBase; + uint32_t IoApicLimit; + uint32_t PciResourceMem32Base; + uint32_t PciResourceMem32Limit; + uint64_t PciResourceMem64Base; + uint64_t PciResourceMem64Limit; + uint32_t VtdBarAddress; + uint32_t Slt2HfiBarAddress; // KNH Only +} STACK_RES; + +typedef struct { + uint8_t Valid; + uint8_t SocketID; // Socket ID of the IIO (0..3) + uint8_t BusBase; + uint8_t BusLimit; + uint16_t PciResourceIoBase; + uint16_t PciResourceIoLimit; + uint32_t IoApicBase; + uint32_t IoApicLimit; + uint32_t PciResourceMem32Base; + uint32_t PciResourceMem32Limit; + uint64_t PciResourceMem64Base; + uint64_t PciResourceMem64Limit; + STACK_RES StackRes[MAX_LOGIC_IIO_STACK]; + uint32_t RcBaseAddress; + IIO_DMI_PCIE_INFO PcieInfo; + uint8_t DmaDeviceCount; +} IIO_RESOURCE_INSTANCE; + +typedef struct { + uint16_t PlatGlobalIoBase; // Global IO Base + uint16_t PlatGlobalIoLimit; // Global IO Limit + uint32_t PlatGlobalMmiolBase; // Global Mmiol base + uint32_t PlatGlobalMmiolLimit; // Global Mmiol limit + uint64_t PlatGlobalMmiohBase; // Global Mmioh Base [43:0] + uint64_t PlatGlobalMmiohLimit; // Global Mmioh Limit [43:0] + QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU + QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO + uint32_t MemTsegSize; + uint32_t MemIedSize; + uint64_t PciExpressBase; + uint32_t PciExpressSize; + uint32_t MemTolm; + IIO_RESOURCE_INSTANCE IIO_resource[MAX_SOCKET]; + uint8_t numofIIO; + uint8_t MaxBusNumber; + uint32_t packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. + uint8_t EVMode; + uint8_t Pci64BitResourceAllocation; + uint8_t SkuPersonality[MAX_SOCKET]; + uint8_t VMDStackEnable[MaxIIO][MAX_IIO_STACK]; + uint16_t IoGranularity; + uint32_t MmiolGranularity; + UINT64_STRUCT MmiohGranularity; + uint8_t RemoteRequestThreshold; //5370389 + uint64_t softskuSocketPresentBitMap; // bitmap of Softsku sockets with CPUs present detected + uint32_t UboxMmioSize; + uint32_t MaxAddressBits; + uint32_t DmiReservedMmiolSize[MAX_SOCKET]; +} PLATFORM_DATA; + +typedef struct { + uint8_t CurrentUpiiLinkSpeed; // Current programmed UPI Link speed (Slow/Full speed mode) + uint8_t CurrentUpiLinkFrequency; // Current requested UPI Link frequency (in GT) + uint8_t OutKtiCpuSktHotPlugEn; // 0 - Disabled, 1 - Enabled for PM X2APIC + uint32_t OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM + uint8_t IsocEnable; + uint32_t meRequestedSize; // Size of the memory range requested by ME FW, in MB + uint32_t ieRequestedSize; // Size of the memory range requested by IE FW, in MB + uint8_t DmiVc1; + uint8_t DmiVcm; + uint32_t CpuPCPSInfo; + uint8_t LtsxEnable; + uint8_t MctpEn; + uint8_t cpuSubType; + uint8_t SystemRasType; + uint8_t numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC + uint16_t tolmLimit; + uint32_t tohmLimit; + RC_VERSION RcVersion; + BOOLEAN MsrTraceEnable; + uint8_t DdrXoverMode; // DDR 2.2 Mode + // For RAS + uint8_t bootMode; + uint8_t OutClusterOnDieEn; // Whether RC enabled COD support + uint8_t OutSncEn; + uint8_t OutNumOfCluster; + uint8_t imcEnabled[MAX_SOCKET][MAX_IMC]; + uint16_t LlcSizeReg; + uint8_t chEnabled[MAX_SOCKET][MAX_CH]; + uint8_t memNode[MC_MAX_NODE]; + uint8_t IoDcMode; + uint8_t DfxRstCplBitsEn; +} SYSTEM_STATUS; + +typedef struct { + PLATFORM_DATA PlatformData; + SYSTEM_STATUS SystemStatus; + uint32_t OemValue; +} IIO_UDS; +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h new file mode 100644 index 0000000..6b0823c --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -0,0 +1,109 @@ +/** +Copyright (c) 2019-2020, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + + +#ifndef _MEMORY_MAP_GUID_H_ +#define _MEMORY_MAP_GUID_H_ + +#define FSP_SYSTEM_MEMORYMAP_HOB_GUID { \ + 0x15, 0x00, 0x87, 0xf8, 0x94, 0x69, 0x98, 0x4b, 0x95, 0xa2, \ + 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f \ + } + +#define MEMTYPE_1LM_MASK (1 << 0) +#define MEMTYPE_2LM_MASK (1 << 1) +#define MEMTYPE_VOLATILE_MASK (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK) + +#define MAX_SAD_RULES 24 +#define MAX_DRAM_CLUSTERS 1 +#define MAX_IMC_PER_SOCKET 2 +#define MAX_SRAT_MEM_ENTRIES_PER_IMC 8 +#define MAX_ACPI_MEMORY_AFFINITY_COUNT ( \ + MAX_SOCKET * MAX_IMC_PER_SOCKET * MAX_SRAT_MEM_ENTRIES_PER_IMC \ + ) + +/* ACPI SRAT Memory Flags */ +#define SRAT_ACPI_MEMORY_ENABLED (1 << 0) +#define SRAT_ACPI_MEMORY_HOT_REMOVE_SUPPORTED (1 << 1) +#define SRAT_ACPI_MEMORY_NONVOLATILE (1 << 2) + +#define MEM_TYPE_RESERVED (1 << 8) +#define MEM_ADDR_64MB_SHIFT_BITS 26 + +// +// System Memory Map HOB information +// + +#pragma pack(1) + +typedef struct SystemMemoryMapElement { + // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache + // Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region + UINT16 Type; + // Node ID of the HA Owning the memory + UINT8 NodeId; + // Socket Id of socket that has his memory - ONLY IN NUMA + UINT8 SocketId; + // Socket interleave bitmap, if more that on socket then ImcInterBitmap and ChInterBitmap are identical in all sockets + UINT8 SktInterBitmap; + // IMC interleave bitmap for this memory + UINT8 ImcInterBitmap; + // Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; + // 011b denotes Ch1 & 0 are interleaved + UINT8 ChInterBitmap[MAX_IMC]; + // Base Address of the element in 64MB chunks + UINT32 BaseAddress; + // Size of this memory element in 64MB chunks + UINT32 ElementSize; +} SYSTEM_MEMORY_MAP_ELEMENT; + +/* NOTE - Reserved sizes need to be calibrated if any of the above #define values change */ +typedef struct SystemMemoryMapHob { + UINT8 reserved1[61]; + + UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem. + UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem. + UINT32 highMemBase; // Mem base in 64MB units for above 4GB mem. + UINT32 highMemSize; // Mem size in 64MB units for above 4GB mem. + UINT32 memSize; // Total physical memory size + UINT16 memFreq; // Mem Frequency + + UINT8 reserved2[61]; + + UINT8 numberEntries; // Number of Memory Map Elements + SYSTEM_MEMORY_MAP_ELEMENT Element[MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; + + UINT8 reserved3[24409]; +} SYSTEM_MEMORY_MAP_HOB; + +#pragma pack() + +void soc_display_memmap_hob(void); + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h index 23b4a04..1568f2b 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h @@ -71,7 +71,7 @@ Output, refer to FSP Integration Guide for details 0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output **/ - UINT8 PcdFsptPort80RouteDisable; + UINT8 FsptPort80RouteDisable; /** Offset 0x0041 **/ -- To view, visit https://review.coreboot.org/c/coreboot/+/40034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8bc6882e47de23d83ba0f521bb12a10dace523ce Gerrit-Change-Number: 40034 Gerrit-PatchSet: 14 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: acpi: Add definitions for device sleep states
by Duncan Laurie (Code Review) 02 Jun '20

02 Jun '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41791 ) Change subject: acpi: Add definitions for device sleep states ...................................................................... acpi: Add definitions for device sleep states The ACPI device sleep states are different from system sleep states and many places hardcode to specific values that are difficult to decode without referring to the spec. Change-Id: If5e732725b775742fd2a9fd0df697e312aa7bf20 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/include/acpi/acpi.h 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/41791/1 diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index ea80e3b..34cb6ea 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -31,6 +31,14 @@ #define SLP_TYP_S5 5 #endif +/* ACPI Device Sleep States */ +#define ACPI_DEVICE_SLEEP_D0 0 +#define ACPI_DEVICE_SLEEP_D1 1 +#define ACPI_DEVICE_SLEEP_D2 2 +#define ACPI_DEVICE_SLEEP_D3 3 +#define ACPI_DEVICE_SLEEP_D3_HOT ACPI_DEVICE_SLEEP_D3 +#define ACPI_DEVICE_SLEEP_D3_COLD 4 + #define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ #define OEM_ID "COREv4" /* Must be exactly 6 bytes long! */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5e732725b775742fd2a9fd0df697e312aa7bf20 Gerrit-Change-Number: 41791 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/xeon_sp: Read PPIN MSR and save to an array for each CPU
by Johnny Lin (Code Review) 02 Jun '20

02 Jun '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40523 ) Change subject: soc/xeon_sp: Read PPIN MSR and save to an array for each CPU ...................................................................... soc/xeon_sp: Read PPIN MSR and save to an array for each CPU PPIN (Protected Processor Inventory Number) MSR is read and saved to an array during xeon_sp_core_init() for each CPU for later use, such as SMBIOS type 11 OEM string population. Tested on OCP Tioga Pass. Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Change-Id: I5e1de8bcb651fb8ae8b106db1978235b0dd84c47 --- M src/soc/intel/xeon_sp/skx/cpu.c M src/soc/intel/xeon_sp/skx/include/soc/msr.h 2 files changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/40523/1 diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index fcee02f..7072285 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -25,8 +25,21 @@ #include <assert.h> #include "chip.h" +msr_t xeon_sp_ppin[MAX_SOCKET] = {0}; +static uint32_t core_bits, thread_bits; +static uint32_t socket_index = (1 << MAX_SOCKET) - 1; static const config_t *chip_config = NULL; +static void save_ppin(msr_t ppin, unsigned int apic_id) +{ + uint8_t package; + + get_cpu_info_from_apicid(apic_id, core_bits, thread_bits, &package, NULL, NULL); + /* Save to the corresponding CPU PPIN. */ + xeon_sp_ppin[package] = ppin; + socket_index &= ~(1UL << package); +} + static void xeon_configure_mca(void) { msr_t msr; @@ -59,6 +72,10 @@ __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); assert(chip_config != NULL); + /* If socket_index is 0 then all PPIN have been saved. */ + if (socket_index) + save_ppin(rdmsr(MSR_PPIN), cpu->path.apic.apic_id); + /* set MSR_PKG_CST_CONFIG_CONTROL - scope per core*/ msr.hi = 0; msr.lo = (PKG_CSTATE_NO_LIMIT | IO_MWAIT_REDIRECTION_ENABLE | CFG_LOCK_ENABLE); @@ -246,7 +263,7 @@ chip_config = dev->chip_info; config_reset_cpl3_csrs(); - + get_core_thread_bits(&core_bits, &thread_bits); /* calls src/cpu/x86/mp_init.c */ if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/soc/intel/xeon_sp/skx/include/soc/msr.h b/src/soc/intel/xeon_sp/skx/include/soc/msr.h index 9505776..4f569e1 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/msr.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/msr.h @@ -17,6 +17,7 @@ #define _SOC_MSR_H_ #include <intelblocks/msr.h> +#include <cpu/x86/msr.h> #define IA32_MCG_CAP 0x179 #define IA32_MCG_CAP_COUNT_MASK 0xff @@ -109,4 +110,7 @@ #define EPB_ENERGY_POLICY_SHIFT 3 #define EPB_ENERGY_POLICY_MASK (0xf << EPB_ENERGY_POLICY_SHIFT) +/* MSR Protected Processor Inventory Number */ +#define MSR_PPIN 0x04F +extern msr_t xeon_sp_ppin[]; #endif /* _SOC_MSR_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e1de8bcb651fb8ae8b106db1978235b0dd84c47 Gerrit-Change-Number: 40523 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Mask lower 20 bits of TOLUD and TOLM in systemag...
by Furquan Shaikh (Code Review) 02 Jun '20

02 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41471 ) Change subject: soc/intel/broadwell: Mask lower 20 bits of TOLUD and TOLM in systemagent.asl ...................................................................... soc/intel/broadwell: Mask lower 20 bits of TOLUD and TOLM in systemagent.asl Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and 1 lock bit. If lock bit is set, then systemagent.asl would end up reporting the base address of low MMIO incorrectly i.e. off by 1. This change masks the lower 20 bits of TOLUD and TOM registers when exposing it in the ACPI tables to ensure that the base address of low MMIO region is reported correctly. Change-Id: I11b3ef8deda21930998471ab6e712da4c62f5b02 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/broadwell/acpi/systemagent.asl 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/41471/1 diff --git a/src/soc/intel/broadwell/acpi/systemagent.asl b/src/soc/intel/broadwell/acpi/systemagent.asl index c73322f..f37af41 100644 --- a/src/soc/intel/broadwell/acpi/systemagent.asl +++ b/src/soc/intel/broadwell/acpi/systemagent.asl @@ -147,13 +147,19 @@ // Fix up PCI memory region // Start with Top of Lower Usable DRAM + // Lower 20 bits of TOLUD register need to be masked since they contain lock and + // reserved bits. Store (^MCHC.TLUD, Local0) + And (Local0, ShiftLeft(0xfff, 20), Local0) Store (^MCHC.MEBA, Local1) // Check if ME base is equal If (LEqual (Local0, Local1)) { // Use Top Of Memory instead Store (^MCHC.TOM, Local0) + // Lower 20 bits of TOM register need to be masked since they contain lock and + // reserved bits. + And (Local0, ShiftLeft(0x7ffff, 20), Local0) } Store (Local0, PMIN) -- To view, visit https://review.coreboot.org/c/coreboot/+/41471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11b3ef8deda21930998471ab6e712da4c62f5b02 Gerrit-Change-Number: 41471 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Early programming of ACPI bar
by Rocky Phagura (Code Review) 02 Jun '20

02 Jun '20

Rocky Phagura has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41680 ) Change subject: soc/intel/xeon_sp: Early programming of ACPI bar ...................................................................... soc/intel/xeon_sp: Early programming of ACPI bar ACPI bar was not programmed previously for which is needed to enable SMI's and to check SMI status registers. TEST=build for Tiogapass and checked ACPI base, able to enable SMIs and check status registers Change-Id: If5a0c4daabf5c35dc2852434fe46712ac9b06379 Signed-off-by: Rocky Phagura <rphagura(a)fb.com> --- M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/bootblock.c A src/soc/intel/xeon_sp/include/soc/bootblock.h A src/soc/intel/xeon_sp/include/soc/pch.h M src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/pch.c 6 files changed, 123 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/41680/1 diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 7950b81..9589e5a 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -5,7 +5,7 @@ subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx -bootblock-y += bootblock.c spi.c lpc.c gpio.c +bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c romstage-y += romstage.c reset.c util.c spi.c gpio.c ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 7f14be6..72d9742 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -9,6 +9,7 @@ #include <cpu/x86/mtrr.h> #include <intelblocks/lpc_lib.h> #include <soc/pci_devs.h> +#include <soc/bootblock.h> const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { @@ -53,4 +54,5 @@ { if (CONFIG(BOOTBLOCK_CONSOLE)) printk(BIOS_DEBUG, "FSP TempRamInit successful...\n"); + bootblock_pch_init(); } diff --git a/src/soc/intel/xeon_sp/include/soc/bootblock.h b/src/soc/intel/xeon_sp/include/soc/bootblock.h new file mode 100644 index 0000000..4b1bae8 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/bootblock.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef _SOC_SKYLAKE_BOOTBLOCK_H_ +#define _SOC_SKYLAKE_BOOTBLOCK_H_ + +#include <intelblocks/systemagent.h> + +/* Bootblock pre console init programming */ +void bootblock_cpu_init(void); +void bootblock_pch_early_init(void); + +/* Bootblock post console init programming */ +void i2c_early_init(void); +void bootblock_pch_init(void); +void pch_early_iorange_init(void); +void report_platform_info(void); +void report_memory_config(void); + +#endif diff --git a/src/soc/intel/xeon_sp/include/soc/pch.h b/src/soc/intel/xeon_sp/include/soc/pch.h new file mode 100644 index 0000000..72150f8 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/pch.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef _SOC_PCH_H_ +#define _SOC_PCH_H_ + +#include <device/device.h> + +#if ENV_RAMSTAGE +void pch_disable_devfn(struct device *dev); +#endif + +#endif /* _SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h index 74343f8..d3bad1b 100644 --- a/src/soc/intel/xeon_sp/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/include/soc/pmc.h @@ -3,18 +3,28 @@ #ifndef _SOC_PMC_H_ #define _SOC_PMC_H_ -/* PCI Configuration Space (D31:F2): PMC */ -#define PMC_ACPI_CNT 0x44 + /* PCI Configuration Space (D31:F2): PMC */ +#define ABASE 0x40 +#define ACTL 0x44 +#define PMC_ACPI_CNT 0x44 +#define PWRM_EN (1 << 8) +#define ACPI_EN (1 << 7) +#define SCI_IRQ_SEL (7 << 0) +#define SCI_IRQ_ADJUST 0 -#define SCI_IRQ_SEL (7 << 0) -#define SCIS_IRQ9 0 -#define SCIS_IRQ10 1 -#define SCIS_IRQ11 2 -#define SCIS_IRQ20 4 -#define SCIS_IRQ21 5 -#define SCIS_IRQ22 6 -#define SCIS_IRQ23 7 +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 +#define PWRMBASE 0x48 +#define GEN_PMCON_A 0xa0 +#define SMI_LOCK (1 << 4) +#define GEN_PMCON_B 0xa4 +#define SLP_STR_POL_LOCK (1 << 18) +#define ACPI_BASE_LOCK (1 << 17) -#define SCI_IRQ_ADJUST 0 #endif diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c new file mode 100644 index 0000000..d6c1c4b --- /dev/null +++ b/src/soc/intel/xeon_sp/pch.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <device/pci_ops.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <intelblocks/cse.h> +#include <intelblocks/fast_spi.h> +#include <intelblocks/itss.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/p2sb.h> +#include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> +#include <intelblocks/rtc.h> +#include <soc/bootblock.h> +#include <soc/iomap.h> +#include <soc/p2sb.h> +#include <soc/pch.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <soc/pm.h> +#include <soc/pmc.h> +#include "../chip.h" +#include <console/console.h> + +#define PCR_DMI_DMICTL 0x2234 +#define PCR_DMI_DMICTL_SRLOCK (1 << 31) +#define PCR_DMI_ACPIBA 0x27B4 +#define PCR_DMI_ACPIBDID 0x27B8 +#define PCR_DMI_PMBASEA 0x27AC +#define PCR_DMI_PMBASEC 0x27B0 + +static void soc_config_acpibase(void) +{ + uint32_t reg32; + + /* Disable ABASE in PMC Device first before changing Base Address */ + reg32 = pci_read_config32(PCH_DEV_PMC, ACTL); + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN); + + /* Program ACPI Base */ + pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS); + + /* Enable ACPI in PMC */ + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN); + + uint32_t data = pci_read_config32(PCH_DEV_PMC, ABASE); + printk(BIOS_INFO, "%s : pmbase = %x\n", __func__, (int)data); + /* + * Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] + * to [0x3F, PMC PCI Offset 40h bit[15:2], 1] + */ + reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1); + pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32); + pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8); +} + +void bootblock_pch_init(void) +{ + /* + * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT + */ + soc_config_acpibase(); + + enable_rtc_upper_bank(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5a0c4daabf5c35dc2852434fe46712ac9b06379 Gerrit-Change-Number: 41680 Gerrit-PatchSet: 1 Gerrit-Owner: Rocky Phagura Gerrit-MessageType: newchange

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