coreboot-gerrit June 2020

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Change in coreboot[master]: mb/google/dedede: config spk_en gpio to low by default
by Furquan Shaikh (Code Review) 02 Jun '20

02 Jun '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41853 ) Change subject: mb/google/dedede: config spk_en gpio to low by default ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/41853/2/src/mainboard/google/deded… File src/mainboard/google/dedede/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/41853/2/src/mainboard/google/deded… PS2, Line 178: GPP_D17 This is exposed in ACPI tables only for waddledoo. I believe you will have to add it to other variants as well to ensure the kernel can control its state? -- To view, visit https://review.coreboot.org/c/coreboot/+/41853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I070679457b06cb82633c1197b893a5d89c8b2cf0 Gerrit-Change-Number: 41853 Gerrit-PatchSet: 2 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 02 Jun 2020 04:41:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Add SD card support
by Varshit B Pandya (Code Review) 02 Jun '20

02 Jun '20

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39237 ) Change subject: mb/google/dedede: Add SD card support ...................................................................... mb/google/dedede: Add SD card support 1. Configure SD card GPIOs. 2. Set SD card power polarity and card detect configs. Change-Id: I90c8ceb85ada23718ff7b6fd7013317c818dd532 Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c 2 files changed, 13 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/39237/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index d82dfc7..69899ac 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -106,6 +106,10 @@ # Enable EMMC HS400 mode register "ScsEmmcHs400Enabled" = "1" + # SD card configuration + register "sdcard_cd_gpio" = "VGPIO_39" + register "SdCardPowerEnableActiveHigh" = "1" + # Display related UPDs # Select eDP for port A register "DdiPortAConfig" = "1" @@ -167,7 +171,7 @@ register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi wifi end - device pci 14.5 off end # SDCard + device pci 14.5 on end # SDCard device pci 15.0 on end # I2C 0 device pci 15.1 on end # I2C 1 device pci 15.2 on end # I2C 2 diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 2b93159..753f7ba 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -272,21 +272,19 @@ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), /* G0 : SD_CMD */ - PAD_NC(GPP_G0, NONE), + PAD_CFG_NF(GPP_G0, NATIVE, DEEP, NF1), /* G1 : SD_DATA0 */ - PAD_NC(GPP_G1, NONE), + PAD_CFG_NF(GPP_G1, NATIVE, DEEP, NF1), /* G2 : SD_DATA1 */ - PAD_NC(GPP_G2, NONE), + PAD_CFG_NF(GPP_G2, NATIVE, DEEP, NF1), /* G3 : SD_DATA2 */ - PAD_NC(GPP_G3, NONE), + PAD_CFG_NF(GPP_G3, NATIVE, DEEP, NF1), /* G4 : SD_DATA3 */ - PAD_NC(GPP_G4, NONE), - /* G5 : SD_CD_ODL */ - PAD_NC(GPP_G5, NONE), + PAD_CFG_NF(GPP_G4, NATIVE, DEEP, NF1), + /* G5 : SD_CD# */ + PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1), /* G6 : SD_CLK */ - PAD_NC(GPP_G6, NONE), - /* G7 : SD_SDIO_WP */ - PAD_NC(GPP_G7, NONE), + PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* H0 : WWAN_PERST */ PAD_NC(GPP_H0, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/39237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90c8ceb85ada23718ff7b6fd7013317c818dd532 Gerrit-Change-Number: 39237 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/mb/google: add templates for dedede boards
by Paul Fagerburg (Code Review) 02 Jun '20

02 Jun '20

Paul Fagerburg has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41640 ) Change subject: util/mb/google: add templates for dedede boards ...................................................................... util/mb/google: add templates for dedede boards Add template directories for the Waddledee and Waddledoo reference boards of the Dedede baseboard. BUG=b:157183582 BRANCH=None TEST=N/A Signed-off-by: Paul Fagerburg <pfagerburg(a)chromium.org> Change-Id: Ida70a44097334991a93fec8f4933d7f6e39a187b --- A util/mainboard/google/waddledee/template/Makefile.inc A util/mainboard/google/waddledee/template/include/variant/ec.h A util/mainboard/google/waddledee/template/include/variant/gpio.h A util/mainboard/google/waddledee/template/memory.c A util/mainboard/google/waddledee/template/overridetree.cb A util/mainboard/google/waddledoo/template/Makefile.inc A util/mainboard/google/waddledoo/template/include/variant/acpi/camera.asl A util/mainboard/google/waddledoo/template/include/variant/ec.h A util/mainboard/google/waddledoo/template/include/variant/gpio.h A util/mainboard/google/waddledoo/template/memory.c A util/mainboard/google/waddledoo/template/overridetree.cb 11 files changed, 195 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/41640/1 diff --git a/util/mainboard/google/waddledee/template/Makefile.inc b/util/mainboard/google/waddledee/template/Makefile.inc new file mode 100644 index 0000000..4643cb2 --- /dev/null +++ b/util/mainboard/google/waddledee/template/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +SPD_SOURCES += empty #0b0000 + +romstage-y += memory.c diff --git a/util/mainboard/google/waddledee/template/include/variant/ec.h b/util/mainboard/google/waddledee/template/include/variant/ec.h new file mode 100644 index 0000000..6e12175 --- /dev/null +++ b/util/mainboard/google/waddledee/template/include/variant/ec.h @@ -0,0 +1,12 @@ +/* + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/util/mainboard/google/waddledee/template/include/variant/gpio.h b/util/mainboard/google/waddledee/template/include/variant/gpio.h new file mode 100644 index 0000000..c7e4605 --- /dev/null +++ b/util/mainboard/google/waddledee/template/include/variant/gpio.h @@ -0,0 +1,12 @@ +/* + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/util/mainboard/google/waddledee/template/memory.c b/util/mainboard/google/waddledee/template/memory.c new file mode 100644 index 0000000..2c81650 --- /dev/null +++ b/util/mainboard/google/waddledee/template/memory.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <baseboard/gpio.h> +#include <ec/google/chromeec/ec.h> +#include <gpio.h> + +bool variant_mem_is_half_populated(void) +{ + uint32_t board_ver; + + /* On boards where board version is populated, ram strap is also populated */ + if (!google_chromeec_get_board_version(&board_ver)) + return !gpio_get(GPIO_MEM_CH_SEL); + + return false; +} diff --git a/util/mainboard/google/waddledee/template/overridetree.cb b/util/mainboard/google/waddledee/template/overridetree.cb new file mode 100644 index 0000000..404024b --- /dev/null +++ b/util/mainboard/google/waddledee/template/overridetree.cb @@ -0,0 +1,42 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 15.0 on end + end +end diff --git a/util/mainboard/google/waddledoo/template/Makefile.inc b/util/mainboard/google/waddledoo/template/Makefile.inc new file mode 100644 index 0000000..c1e68ce --- /dev/null +++ b/util/mainboard/google/waddledoo/template/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +SPD_SOURCES = empty #0b0000 + +romstage-y += memory.c diff --git a/util/mainboard/google/waddledoo/template/include/variant/acpi/camera.asl b/util/mainboard/google/waddledoo/template/include/variant/acpi/camera.asl new file mode 100644 index 0000000..318b0de --- /dev/null +++ b/util/mainboard/google/waddledoo/template/include/variant/acpi/camera.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/acpi/camera.asl> diff --git a/util/mainboard/google/waddledoo/template/include/variant/ec.h b/util/mainboard/google/waddledoo/template/include/variant/ec.h new file mode 100644 index 0000000..6e12175 --- /dev/null +++ b/util/mainboard/google/waddledoo/template/include/variant/ec.h @@ -0,0 +1,12 @@ +/* + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/util/mainboard/google/waddledoo/template/include/variant/gpio.h b/util/mainboard/google/waddledoo/template/include/variant/gpio.h new file mode 100644 index 0000000..c7e4605 --- /dev/null +++ b/util/mainboard/google/waddledoo/template/include/variant/gpio.h @@ -0,0 +1,12 @@ +/* + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/util/mainboard/google/waddledoo/template/memory.c b/util/mainboard/google/waddledoo/template/memory.c new file mode 100644 index 0000000..2c81650 --- /dev/null +++ b/util/mainboard/google/waddledoo/template/memory.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <baseboard/gpio.h> +#include <ec/google/chromeec/ec.h> +#include <gpio.h> + +bool variant_mem_is_half_populated(void) +{ + uint32_t board_ver; + + /* On boards where board version is populated, ram strap is also populated */ + if (!google_chromeec_get_board_version(&board_ver)) + return !gpio_get(GPIO_MEM_CH_SEL); + + return false; +} diff --git a/util/mainboard/google/waddledoo/template/overridetree.cb b/util/mainboard/google/waddledoo/template/overridetree.cb new file mode 100644 index 0000000..69ea1e1 --- /dev/null +++ b/util/mainboard/google/waddledoo/template/overridetree.cb @@ -0,0 +1,58 @@ +chip soc/intel/jasperlake + + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 176, + .scl_hcnt = 95, + .sda_hold = 36, + } + }, + }" + device domain 0 on + device pci 14.0 on end + device pci 15.0 on end + device pci 15.2 on end + device pci 1c.7 on end + device pci 19.0 on end + device pci 1f.3 on end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/41640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida70a44097334991a93fec8f4933d7f6e39a187b Gerrit-Change-Number: 41640 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: config spk_en gpio to low by default
by Aamir Bohra (Code Review) 02 Jun '20

02 Jun '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41853 ) Change subject: mb/google/dedede: config spk_en gpio to low by default ...................................................................... Patch Set 2: (4 comments) https://review.coreboot.org/c/coreboot/+/41853/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/41853/2//COMMIT_MSG@9 PS2, Line 9: gpio speaker enable gpio https://review.coreboot.org/c/coreboot/+/41853/2//COMMIT_MSG@10 PS2, Line 10: so defaults it to 0 configure it low? https://review.coreboot.org/c/coreboot/+/41853/2//COMMIT_MSG@12 PS2, Line 12: BRANCH=None not needed https://review.coreboot.org/c/coreboot/+/41853/2//COMMIT_MSG@14 PS2, Line 14: tested tested speaker playback works fine? -- To view, visit https://review.coreboot.org/c/coreboot/+/41853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I070679457b06cb82633c1197b893a5d89c8b2cf0 Gerrit-Change-Number: 41853 Gerrit-PatchSet: 2 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 02 Jun 2020 04:03:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Enable GBB configs for dedede
by Usha P (Code Review) 02 Jun '20

02 Jun '20

Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41405 ) Change subject: mb/google/dedede: Enable GBB configs for dedede ...................................................................... mb/google/dedede: Enable GBB configs for dedede This patch enables the necessary GBB configs for dedede BUG=none BRANCH=none TEST=GBB Flag value was 0x39 before enabling the required flags and now it is updated to 0x40b9. Verfied from CPU log. Change-Id: Ica07c65d6cf23ea859de6aa8413377661547e47a Signed-off-by: Usha P <usha.p(a)intel.com> --- M src/mainboard/google/dedede/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/41405/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 91aeb93..af7a0a4 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -28,6 +28,10 @@ bool default y select EC_GOOGLE_CHROMEEC_SWITCHES + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_BOOT_LEGACY + select GBB_FLAG_FORCE_MANUAL_RECOVERY select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH -- To view, visit https://review.coreboot.org/c/coreboot/+/41405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica07c65d6cf23ea859de6aa8413377661547e47a Gerrit-Change-Number: 41405 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Enable coreboot lock down config
by Aamir Bohra (Code Review) 02 Jun '20

02 Jun '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41535 ) Change subject: mb/google/dedede: Enable coreboot lock down config ...................................................................... mb/google/dedede: Enable coreboot lock down config TEST=Build and boot waddledoo board Change-Id: Ic10af9a0d50946a98a5c4a77b492d242cef171ca Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41535/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index c891e6e..806b0e3 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -137,6 +137,7 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI0 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | @@ -148,6 +149,7 @@ #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .gspi[0] = { .speed_mhz = 1, .early_init = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/41535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic10af9a0d50946a98a5c4a77b492d242cef171ca Gerrit-Change-Number: 41535 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ocp/tiogapass/bootblock.c: Port 80h direct to GPIO for LED display
by Bryant Ou (Code Review) 02 Jun '20

02 Jun '20

Bryant Ou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40008 ) Change subject: ocp/tiogapass/bootblock.c: Port 80h direct to GPIO for LED display ...................................................................... ocp/tiogapass/bootblock.c: Port 80h direct to GPIO for LED display Change-Id: Ie0366a5f645b503068c29e35b33c1d087174c83b --- M src/mainboard/ocp/tiogapass/bootblock.c 1 file changed, 154 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/40008/1 diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c index d9a86e9..af75819 100644 --- a/src/mainboard/ocp/tiogapass/bootblock.c +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -4,6 +4,7 @@ #include <bootblock_common.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <device/pnp_ops.h> #include <intelblocks/pcr.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> @@ -13,6 +14,155 @@ /* these are defined in intelblocks/lpc_lib.h but we can't use them yet */ #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 +#define ASPEED_CONFIG_INDEX 0x2E +#define ASPEED_CONFIG_DATA 0x2F +#define ASPEDD_SCU_BASE 0x1E6E2000 + +static void lpc_read(uint32_t addr, uint32_t *value) +{ + uint32_t data = 0; + uint8_t tmp; + pnp_devfn_t dev = PNP_DEV(ASPEED_CONFIG_INDEX, AST2400_ILPC2AHB); + + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); + + /* Write Address */ + pnp_write_config(dev, 0xF0, ((addr & 0xFF000000) >> 24)); + pnp_write_config(dev, 0xF1, ((addr & 0x00FF0000) >> 16)); + pnp_write_config(dev, 0xF2, ((addr & 0x0000FF00) >> 8)); + pnp_write_config(dev, 0xF3, (addr & 0x000000FF)); + + /* Write Mode */ + tmp = pnp_read_config(dev, 0xF8); + pnp_write_config(dev, 0xF8, (tmp & 0xFC) | 0x02); + + /* Fire */ + outb(0xFE, ASPEED_CONFIG_INDEX); + tmp = inb(ASPEED_CONFIG_DATA); + + /* Get Data */ + data |= (pnp_read_config(dev, 0xF4) << 24); + data |= (pnp_read_config(dev, 0xF5) << 16); + data |= (pnp_read_config(dev, 0xF6) << 8); + data |= pnp_read_config(dev, 0xF7); + *value= data; + + pnp_set_enable(dev, 0); + pnp_exit_conf_state(dev); +} + +static void lpc_write(uint32_t addr, uint32_t data) +{ + uint8_t tmp; + pnp_devfn_t dev = PNP_DEV(ASPEED_CONFIG_INDEX, AST2400_ILPC2AHB); + + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); + + /* Write Address */ + pnp_write_config(dev, 0xF0, ((addr & 0xFF000000) >> 24)); + pnp_write_config(dev, 0xF1, ((addr & 0x00FF0000) >> 16)); + pnp_write_config(dev, 0xF2, ((addr & 0x0000FF00) >> 8)); + pnp_write_config(dev, 0xF3, (addr & 0x000000FF)); + + /* Write Data */ + pnp_write_config(dev, 0xF4, ((data & 0xFF000000) >> 24)); + pnp_write_config(dev, 0xF5, ((data & 0x00FF0000) >> 16)); + pnp_write_config(dev, 0xF6, ((data & 0x0000FF00) >> 8)); + pnp_write_config(dev, 0xF7, (data & 0x000000FF)); + + /* Write Mode */ + tmp = pnp_read_config(dev, 0xF8); + pnp_write_config(dev, 0xF8, (tmp & 0xFC) | 0x02); + + /* Fire */ + pnp_write_config(dev, 0xFE, 0xCF); + + pnp_set_enable(dev, 0); + pnp_exit_conf_state(dev); +} + +static void aspeed_direct_port_80(void) +{ + uint32_t address, value; + uint8_t data; + pnp_devfn_t dev = PNP_DEV(ASPEED_CONFIG_INDEX, AST2400_GPIO); + + /* Set command source of GPIOH to LPC + (GPIO068) Set 0x1e780068[24] = 1b */ + lpc_read(0x1e780068 , &value); + value &= 0xFEFFFFFF; + value |= 0x01000000; + lpc_write(0x1e780068, value); + + /* (GPIO06C) Set 0x1e78006C[24] = 0b */ + lpc_read(0x1e78006C, &value); + value &= 0xFEFFFFFF; + lpc_write(0x1e78006C, value); + + /* Unlock SCU Registers */ + address = (uint32_t)(ASPEDD_SCU_BASE); + lpc_read(address , &value); + value &= (0x00000000); + value |= (0x1688A8A8); + lpc_write(address, value); + + /* Program GPIOH multi-function to GPIO + (SCU90) Set 0x1e6e2090[7:6] = 00b */ + lpc_read(0x1e6e2090 , &value); + value &= 0xFFFFFF3F; + lpc_write(0x1e6e2090, value); + + /* Program GPIOH as output + (GPIO024) Set 0x1e780024[31:24] = FFh */ + lpc_read(0x1e780024, &value); + value &= 0x00FFFFFF; + value |= 0xFF000000; + lpc_write(0x1e780024, value); + + /* Set snooping address#0 as 80h + (SNPWADR) Set 0x1e789090[15:0] = 80h */ + lpc_read(0x1e789090, &value); + value &= 0xFFFF0000; + value |= 0x00000080; + lpc_write(0x1e789090, value); + + /* Enable snooping address#0 + (HICR5) Set 0x1e789080[0] = 1b */ + lpc_read(0x1e789080, &value); + value &= 0xFFFFFFFE; + value |= 0x00000001; + lpc_write(0x1e789080, value); + + /* Enable GPIO device */ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + data = pnp_read_config(dev, 0x30); + pnp_write_config(dev, 0x30, data | 0x1); + + /* Select GPIO[X] for port80 GPIO and enable inverse polarity of port80 GPIO */ + data = pnp_read_config(dev, 0x38); + data &= 0x60; + /* Select GPIOH for port80 GPIO: Set SIOR7_38[4:0] = 7h + Enable inverse polarity of port80 GPIO: Set SIOR7_38[7] = 1b */ + data |= 0x07; + pnp_write_config(dev, 0x38, data); + + /* Enable port80 GPIO: Set SIOR7_30[7] = 1b */ + data = pnp_read_config(dev, 0x30); + data &= 0x7F; + data |= 0x80; + pnp_write_config(dev, 0x30, data); + + /* Disable GPIO Device */ + pnp_set_logical_device(dev); + data = pnp_read_config(dev, 0x30); + pnp_write_config(dev, 0x30, data & 0xFE); + pnp_exit_conf_state(dev); +} static void enable_espi_lpc_io_windows(void) { @@ -54,6 +204,9 @@ enable_espi_lpc_io_windows(); /* Configure appropriate physical port of SuperIO chip off BMC */ - const pnp_devfn_t serial_dev = PNP_DEV(0x2e, com_to_ast_sio(CONFIG_UART_FOR_CONSOLE)); + const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_CONFIG_INDEX, com_to_ast_sio(CONFIG_UART_FOR_CONSOLE)); aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + + /* Port 80h direct to GPIO for LED display*/ + aspeed_direct_port_80(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/40008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0366a5f645b503068c29e35b33c1d087174c83b Gerrit-Change-Number: 40008 Gerrit-PatchSet: 1 Gerrit-Owner: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-MessageType: newchange

6 34

Change in coreboot[master]: drivers/intel/mipi_camera: camera SSDT generation
by Matt Delco (Code Review) 01 Jun '20

01 Jun '20

Matt Delco has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41607 ) Change subject: drivers/intel/mipi_camera: camera SSDT generation ...................................................................... Patch Set 10: (3 comments) https://review.coreboot.org/c/coreboot/+/41607/4/src/drivers/intel/mipi_cam… File src/drivers/intel/mipi_camera/camera.c: https://review.coreboot.org/c/coreboot/+/41607/4/src/drivers/intel/mipi_cam… PS4, Line 444: a > Adding a space leads to following warning by checkpatch.pl […] Ack https://review.coreboot.org/c/coreboot/+/41607/6/src/drivers/intel/mipi_cam… File src/drivers/intel/mipi_camera/camera.c: https://review.coreboot.org/c/coreboot/+/41607/6/src/drivers/intel/mipi_cam… PS6, Line 159: config->ssdb.platform = 9; : if (!config->ssdb.flash_support) : config->ssdb.flash_support = 2; : if (!config->ssdb.privacy_led) : config->ssdb.privacy_led = 1; : if (!config->ssdb.mipi_define) : config->ssdb.mipi_define = 1; : if (!config->ssdb.mclk_speed) : config->ssdb.mclk_speed = 19200000; > Thanks Matt, Sugnan could you add those in? Done https://review.coreboot.org/c/coreboot/+/41607/6/src/drivers/intel/mipi_cam… PS6, Line 188: /* Method (_DSM, 4, NotSerialized) */ : acpigen_write_method("_DSM", 0x4); : : /* ToBuffer (Arg0, Local0) */ : acpigen_write_to_buffer(ARG0_OP, LOCAL0_OP); : : /* If (LEqual (Local0, ToUUID(uuid))) */ : acpigen_write_if(); : acpigen_emit_byte(LEQUAL_OP); : acpigen_emit_byte(LOCAL0_OP); : acpigen_write_uuid("822ace8f-2814-4174-a56b-5f029fe079ee"); : acpigen_write_return_string(config->sensor_name ? config->sensor_name : "UNKNOWN"); : acpigen_pop_len(); /* If */ : : /* If (LEqual (Local0, ToUUID(uuid))) */ : acpigen_write_if(); : acpigen_emit_byte(LEQUAL_OP); : acpigen_emit_byte(LOCAL0_OP); : acpigen_write_uuid("26257549-9271-4ca4-bb43-c4899d5a4881"); : /* ToInteger (Arg2, Local1) */ : acpigen_write_to_integer(ARG2_OP, LOCAL1_OP); : : /* If (LEqual (Local1, 1)) */ : acpigen_write_if_lequal_op_int(LOCAL1_OP, 1); : acpigen_write_return_integer((config->ssdb.vcm_type ? 1 : 0) + : (config->ssdb.rom_type ? 1 : 0) + 1); : acpigen_pop_len(); /* If Arg2=1 */ : : /* If (LEqual (Local1, 2)) */ : acpigen_write_if_lequal_op_int(LOCAL1_OP, 2); : acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 | : ((uint32_t)i2c_addr) << 8 | 0x0); /* type 0 for sensor */ : acpigen_pop_len(); /* If Arg2=2 */ : : if (config->ssdb.vcm_type) { : /* If (LEqual (Local1, 3)) */ : acpigen_write_if_lequal_op_int(LOCAL1_OP, 3); : acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 | /* type 1 for vcm */ : ((uint32_t)config->vcm_address) << 8 | 0x01); : acpigen_pop_len(); /* If Arg2=3 */ : } : if (config->ssdb.rom_type) { : /* If (LEqual (Local1, 3 or 4)) */ : acpigen_write_if_lequal_op_int(LOCAL1_OP, 3 + (config->ssdb.vcm_type ? 1 : 0)); : acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 | /* type 2 for rom */ : ((uint32_t)config->rom_address) << 8 | 0x02); : acpigen_pop_len(); /* If Arg2=3 or 4 */ : } : : acpigen_pop_len(); /* If uuid */ : : /* Return (Buffer (One) { 0x0 }) */ : acpigen_write_return_singleton_buffer(0x0); : : acpigen_pop_len(); /* Method _DSM */ > You should be able to use acpigen_write_dsm. […] acpigen_write_dsm_uuid_arr() could be used for "26257549-9271-4ca4-bb43-c4899d5a4881", though "822ace8f-2814-4174-a56b-5f029fe079ee" seems to ignore the Arg2 ("Function index") so I'm not sure whether it's safe to assume this is zero or instead preserve the runtime behavior (e.g., using some hack like count==0 means do an unconditional call): acpigen_write_dsm_uuid() { // ... acpigen_write_to_integer(ARG2_OP, LOCAL1_OP); + if (!id->count) { + if (id->callbacks[0]) id->callbacks[0](id->arg); + } else { for (i = 0; i < id->count; i++) { acpigen_write_if_lequal_op_int(LOCAL1_OP, i); if (id->callbacks[i]) id->callbacks[i](id->arg); acpigen_pop_len(); } + } // ... } -- To view, visit https://review.coreboot.org/c/coreboot/+/41607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15979f345fb823df2560db269e902a1ea650b69e Gerrit-Change-Number: 41607 Gerrit-PatchSet: 10 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 01 Jun 2020 21:04:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt Delco <delco(a)chromium.org> Comment-In-Reply-To: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Enable Xdci for devicce role swap
by Brandon Breitenstein (Code Review) 01 Jun '20

01 Jun '20

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41975 ) Change subject: mb/google/volteer: Enable Xdci for devicce role swap ...................................................................... mb/google/volteer: Enable Xdci for devicce role swap For Device Role swap Xdci is needed to allow the swap to occur **WORK IN PROGRESS DO NOT MERGE** Change-Id: Ie6372f8522a33ea58a43ff29bfd4a23e26f5ca05 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/41975/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index c6a2e8b..82b3a88 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -122,6 +122,7 @@ # TCSS USB3 register "TcssXhciEn" = "1" + register "TcssXdciEn" = "1" register "TcssAuxOri" = "1" register "IomTypeCPortPadCfg[0]" = "0x090E000A" register "IomTypeCPortPadCfg[1]" = "0x090E000D" -- To view, visit https://review.coreboot.org/c/coreboot/+/41975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6372f8522a33ea58a43ff29bfd4a23e26f5ca05 Gerrit-Change-Number: 41975 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: drivers/intel/fsp2_0: Add FSP 2.2 specific support
by build bot (Jenkins) (Code Review) 01 Jun '20

01 Jun '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41728 ) Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/41728/3/src/drivers/intel/fsp2_0/s… File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/c/coreboot/+/41728/3/src/drivers/intel/fsp2_0/s… PS3, Line 81: FSPS_ARCH_UPD *arch_upd; need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/41728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Gerrit-Change-Number: 41728 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 01 Jun 2020 19:39:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit June 2020